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O3: Update stats for fetch and bp changes.

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This commit is contained in:
Ali Saidi 2011-07-10 12:56:09 -05:00
parent 3396fd9e84
commit 3ebfe2eb01
137 changed files with 16783 additions and 16739 deletions
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5
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -199,12 +200,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:12:22
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:09:24
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 279017416500 because target called exit()
Exiting @ tick 274500333500 because target called exit()

376
tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.279017 # Number of seconds simulated
sim_ticks 279017416500 # Number of ticks simulated
sim_seconds 0.274500 # Number of seconds simulated
sim_ticks 274500333500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 128000 # Simulator instruction rate (inst/s)
host_tick_rate 59339940 # Simulator tick rate (ticks/s)
host_mem_usage 192984 # Number of bytes of host memory used
host_seconds 4702.02 # Real time elapsed on the host
host_inst_rate 56944 # Simulator instruction rate (inst/s)
host_tick_rate 25971361 # Simulator tick rate (ticks/s)
host_mem_usage 245756 # Number of bytes of host memory used
host_seconds 10569.35 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517555 # DTB read hits
system.cpu.dtb.read_hits 114517568 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520186 # DTB read accesses
system.cpu.dtb.write_hits 39666604 # DTB write hits
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
system.cpu.dtb.write_hits 39666597 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39668906 # DTB write accesses
system.cpu.dtb.data_hits 154184159 # DTB hits
system.cpu.dtb.write_accesses 39668899 # DTB write accesses
system.cpu.dtb.data_hits 154184165 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154189092 # DTB accesses
system.cpu.itb.fetch_hits 29078095 # ITB hits
system.cpu.dtb.data_accesses 154189098 # DTB accesses
system.cpu.itb.fetch_hits 27986226 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 29078117 # ITB accesses
system.cpu.itb.fetch_accesses 27986248 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 558034834 # number of cpu cycles simulated
system.cpu.numCycles 549000668 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed.
system.cpu.activity 89.024000 # Percentage of cycles cpu is active
system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed.
system.cpu.activity 89.164571 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -61,79 +61,79 @@ system.cpu.comFloats 24 # Nu
system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total)
system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads
system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads
system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits
system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154627572 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed.
system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154582342 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use
system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use
system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits
system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits
system.cpu.icache.overall_hits 29077078 # number of overall hits
system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses
system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1015 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency
system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits
system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits
system.cpu.icache.overall_hits 27985205 # number of overall hits
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1019 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -143,159 +143,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets 21750
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use
system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use
system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits
system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 152394384 # number of overall hits
system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses
system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1570979 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles
system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits
system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 152394244 # number of overall hits
system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses
system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1571119 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 408187 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits
system.cpu.dcache.writebacks 408188 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73794 # number of replacements
system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use
system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 73797 # number of replacements
system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use
system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits
system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 364155 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses
system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 364156 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 92092 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 92094 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked
system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 59344 # number of writebacks
system.cpu.l2cache.writebacks 59345 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:20:02
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:09:24
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 162342217500 because target called exit()
Exiting @ tick 145300717500 because target called exit()

776
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.162342 # Number of seconds simulated
sim_ticks 162342217500 # Number of ticks simulated
sim_seconds 0.145301 # Number of seconds simulated
sim_ticks 145300717500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 248957 # Simulator instruction rate (inst/s)
host_tick_rate 71463217 # Simulator tick rate (ticks/s)
host_mem_usage 193608 # Number of bytes of host memory used
host_seconds 2271.69 # Real time elapsed on the host
host_inst_rate 109615 # Simulator instruction rate (inst/s)
host_tick_rate 28162171 # Simulator tick rate (ticks/s)
host_mem_usage 246532 # Number of bytes of host memory used
host_seconds 5159.43 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 122220880 # DTB read hits
system.cpu.dtb.read_misses 24742 # DTB read misses
system.cpu.dtb.read_hits 125840781 # DTB read hits
system.cpu.dtb.read_misses 26740 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 122245622 # DTB read accesses
system.cpu.dtb.write_hits 40876425 # DTB write hits
system.cpu.dtb.write_misses 28211 # DTB write misses
system.cpu.dtb.read_accesses 125867521 # DTB read accesses
system.cpu.dtb.write_hits 41455603 # DTB write hits
system.cpu.dtb.write_misses 32148 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 40904636 # DTB write accesses
system.cpu.dtb.data_hits 163097305 # DTB hits
system.cpu.dtb.data_misses 52953 # DTB misses
system.cpu.dtb.write_accesses 41487751 # DTB write accesses
system.cpu.dtb.data_hits 167296384 # DTB hits
system.cpu.dtb.data_misses 58888 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 163150258 # DTB accesses
system.cpu.itb.fetch_hits 65447834 # ITB hits
system.cpu.itb.fetch_misses 37 # ITB misses
system.cpu.dtb.data_accesses 167355272 # DTB accesses
system.cpu.itb.fetch_hits 71694847 # ITB hits
system.cpu.itb.fetch_misses 40 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 65447871 # ITB accesses
system.cpu.itb.fetch_accesses 71694887 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 324684436 # number of cpu cycles simulated
system.cpu.numCycles 290601436 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits
system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed
system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 36 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued
system.cpu.iq.rate 1.865224 # Inst issue rate
system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued
system.cpu.iq.rate 2.139184 # Inst issue rate
system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 43212719 # number of nop insts executed
system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed
system.cpu.iew.exec_branches 67449018 # Number of branches executed
system.cpu.iew.exec_stores 40932468 # Number of stores executed
system.cpu.iew.exec_rate 1.845435 # Inst execution rate
system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back
system.cpu.iew.wb_producers 395837342 # num instructions producing a value
system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value
system.cpu.iew.exec_nop 45600120 # number of nop insts executed
system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed
system.cpu.iew.exec_branches 68499674 # Number of branches executed
system.cpu.iew.exec_stores 41507202 # Number of stores executed
system.cpu.iew.exec_rate 2.112616 # Inst execution rate
system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back
system.cpu.iew.wb_producers 419952220 # num instructions producing a value
system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back
system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle
system.cpu.commit.count 601856963 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 153965363 # Number of memory references committed
@ -288,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 956313792 # The number of ROB reads
system.cpu.rob.rob_writes 1333072216 # The number of ROB writes
system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 938663770 # The number of ROB reads
system.cpu.rob.rob_writes 1394275800 # The number of ROB writes
system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads
system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 844972523 # number of integer regfile reads
system.cpu.int_regfile_writes 489243634 # number of integer regfile writes
system.cpu.fp_regfile_reads 253 # number of floating regfile reads
system.cpu.fp_regfile_writes 50 # number of floating regfile writes
system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads
system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 864545189 # number of integer regfile reads
system.cpu.int_regfile_writes 501712619 # number of integer regfile writes
system.cpu.fp_regfile_reads 277 # number of floating regfile reads
system.cpu.fp_regfile_writes 57 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 32 # number of replacements
system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use
system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks.
system.cpu.icache.replacements 36 # number of replacements
system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use
system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits
system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits
system.cpu.icache.overall_hits 65446683 # number of overall hits
system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses
system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1151 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits
system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits
system.cpu.icache.overall_hits 71693570 # number of overall hits
system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses
system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1277 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 471038 # number of replacements
system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use
system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits
system.cpu.dcache.replacements 470805 # number of replacements
system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use
system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 149582203 # number of overall hits
system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses
system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2073649 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 151630546 # number of overall hits
system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses
system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2034372 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked
system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 423176 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses
system.cpu.dcache.writebacks 423137 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 74455 # number of replacements
system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use
system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 74456 # number of replacements
system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use
system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 383286 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 92757 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 383086 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 92755 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 59322 # number of writebacks
system.cpu.l2cache.writebacks 59325 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

1
tests/long/00.gzip/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 16:32:58
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 00:29:29
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -44,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 189745250000 because target called exit()
Exiting @ tick 182546630500 because target called exit()

778
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.189745 # Number of seconds simulated
sim_ticks 189745250000 # Number of ticks simulated
sim_seconds 0.182547 # Number of seconds simulated
sim_ticks 182546630500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 57706 # Simulator instruction rate (inst/s)
host_tick_rate 18177630 # Simulator tick rate (ticks/s)
host_mem_usage 255472 # Number of bytes of host memory used
host_seconds 10438.39 # Real time elapsed on the host
sim_insts 602359840 # Number of instructions simulated
host_inst_rate 66837 # Simulator instruction rate (inst/s)
host_tick_rate 20255145 # Simulator tick rate (ticks/s)
host_mem_usage 257744 # Number of bytes of host memory used
host_seconds 9012.36 # Real time elapsed on the host
sim_insts 602359825 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 379490501 # number of cpu cycles simulated
system.cpu.numCycles 365093262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits
system.cpu.BPredUnit.lookups 94055134 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 86414920 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3979081 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 88956702 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 82512166 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 1838122 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1832 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 80667890 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 724099412 # Number of instructions fetch has processed
system.cpu.fetch.Branches 94055134 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 84350288 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 163986224 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 21484785 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 102787887 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 614 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 78002853 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1602878 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 364227401 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.127111 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.977166 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 200241339 54.98% 54.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25976483 7.13% 62.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 20067114 5.51% 67.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 25160816 6.91% 74.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 12370660 3.40% 77.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13978922 3.84% 81.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4846811 1.33% 83.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7981089 2.19% 85.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 53604167 14.72% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups
system.cpu.fetch.rateDist::total 364227401 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.257619 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.983327 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 103328819 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 82990379 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 141956916 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19169051 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 16782236 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6955768 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 2559 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 762233872 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 7095 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 16782236 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 116716310 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10162193 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 109463 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 147645122 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 72812077 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 747464015 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 176 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 58909213 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10051058 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 590 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 771173910 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3477020106 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3477019978 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle
system.cpu.rename.CommittedMaps 627417426 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 143756479 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6432 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6428 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 129949589 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 185066010 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 85818254 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 23013256 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 30486769 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 718960040 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7404 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 670280843 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 854799 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 116155760 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 288576013 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1102 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 364227401 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.840281 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.715695 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 91766913 25.19% 25.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 93871528 25.77% 50.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 74118513 20.35% 71.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 44924126 12.33% 83.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 26194132 7.19% 90.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19078510 5.24% 96.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7890026 2.17% 98.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 5178547 1.42% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1205106 0.33% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 364227401 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 168001 4.86% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2622016 75.82% 80.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 668303 19.32% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 415768758 62.03% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.03% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 175425484 26.17% 88.20% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 79080039 11.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued
system.cpu.iq.rate 1.710069 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 670280843 # Type of FU issued
system.cpu.iq.rate 1.835917 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3458320 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005160 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1709102170 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 835787693 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 655814402 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 673739143 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 28975081 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 36113410 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 129451 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 665732 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 15597236 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 16028 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12631 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 524844 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3752039 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 638545 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4390584 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 642328929 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 165615332 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6625907 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 16782236 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 788804 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 51690 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 719036936 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2011497 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 185066010 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 85818254 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6071 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13145 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5072 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 665732 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4120759 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 486329 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4607088 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 662401467 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 171983852 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7879376 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 61035 # number of nop insts executed
system.cpu.iew.exec_refs 240294143 # number of memory reference insts executed
system.cpu.iew.exec_branches 74636278 # Number of branches executed
system.cpu.iew.exec_stores 74678811 # Number of stores executed
system.cpu.iew.exec_rate 1.692609 # Inst execution rate
system.cpu.iew.wb_sent 637663585 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 636613604 # cumulative count of insts written-back
system.cpu.iew.wb_producers 410591202 # num instructions producing a value
system.cpu.iew.wb_consumers 620919251 # num instructions consuming a value
system.cpu.iew.exec_nop 69492 # number of nop insts executed
system.cpu.iew.exec_refs 249361026 # number of memory reference insts executed
system.cpu.iew.exec_branches 77022435 # Number of branches executed
system.cpu.iew.exec_stores 77377174 # Number of stores executed
system.cpu.iew.exec_rate 1.814335 # Inst execution rate
system.cpu.iew.wb_sent 657949131 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 655814418 # cumulative count of insts written-back
system.cpu.iew.wb_producers 425644511 # num instructions producing a value
system.cpu.iew.wb_consumers 661906658 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.677548 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.661263 # average fanout of values written-back
system.cpu.iew.wb_rate 1.796293 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.643058 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 602359891 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 75781554 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6305 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3943142 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 366940135 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.641575 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.021399 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 602359876 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 116686609 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6302 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4038424 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 347445166 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.733683 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.123903 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 118738354 32.36% 32.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 123466865 33.65% 66.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 52180899 14.22% 80.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12560554 3.42% 83.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 20975428 5.72% 89.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13806386 3.76% 93.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7633759 2.08% 95.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2509750 0.68% 95.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15068140 4.11% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 113764130 32.74% 32.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 109130175 31.41% 64.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 49680788 14.30% 78.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 10344875 2.98% 81.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 23361064 6.72% 88.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14153772 4.07% 92.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8154815 2.35% 94.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1152882 0.33% 94.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 17702665 5.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 366940135 # Number of insts commited each cycle
system.cpu.commit.count 602359891 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 347445166 # Number of insts commited each cycle
system.cpu.commit.count 602359876 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219173623 # Number of memory references committed
system.cpu.commit.loads 148952602 # Number of loads committed
system.cpu.commit.refs 219173617 # Number of memory references committed
system.cpu.commit.loads 148952599 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.branches 70828609 # Number of branches committed
system.cpu.commit.branches 70828606 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522671 # Number of committed integer instructions.
system.cpu.commit.int_insts 533522659 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15068140 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 17702665 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1030012828 # The number of ROB reads
system.cpu.rob.rob_writes 1367937117 # The number of ROB writes
system.cpu.timesIdled 36799 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 904900 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 602359840 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359840 # Number of Instructions Simulated
system.cpu.cpi 0.630006 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.630006 # CPI: Total CPI of All Threads
system.cpu.ipc 1.587286 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.587286 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3206207435 # number of integer regfile reads
system.cpu.int_regfile_writes 661050575 # number of integer regfile writes
system.cpu.rob.rob_reads 1048788374 # The number of ROB reads
system.cpu.rob.rob_writes 1454922610 # The number of ROB writes
system.cpu.timesIdled 36904 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 865861 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 602359825 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359825 # Number of Instructions Simulated
system.cpu.cpi 0.606105 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.606105 # CPI: Total CPI of All Threads
system.cpu.ipc 1.649879 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.649879 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3307885763 # number of integer regfile reads
system.cpu.int_regfile_writes 680907350 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 912573919 # number of misc regfile reads
system.cpu.misc_regfile_writes 2672 # number of misc regfile writes
system.cpu.icache.replacements 41 # number of replacements
system.cpu.icache.tagsinuse 627.011637 # Cycle average of tags in use
system.cpu.icache.total_refs 70198409 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 96294.113855 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 966917605 # number of misc regfile reads
system.cpu.misc_regfile_writes 2666 # number of misc regfile writes
system.cpu.icache.replacements 48 # number of replacements
system.cpu.icache.tagsinuse 654.116997 # Cycle average of tags in use
system.cpu.icache.total_refs 78001834 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 767 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 101697.306389 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 627.011637 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.306158 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 70198409 # number of ReadReq hits
system.cpu.icache.demand_hits 70198409 # number of demand (read+write) hits
system.cpu.icache.overall_hits 70198409 # number of overall hits
system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses
system.cpu.icache.demand_misses 920 # number of demand (read+write) misses
system.cpu.icache.overall_misses 920 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32585000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32585000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32585000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 70199329 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 70199329 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 70199329 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 654.116997 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.319393 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 78001834 # number of ReadReq hits
system.cpu.icache.demand_hits 78001834 # number of demand (read+write) hits
system.cpu.icache.overall_hits 78001834 # number of overall hits
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1019 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 35576500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 35576500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 35576500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 78002853 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 78002853 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 78002853 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35418.478261 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35418.478261 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35418.478261 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 34913.150147 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34913.150147 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34913.150147 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -351,143 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 731 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 731 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 731 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 252 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 252 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 767 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 767 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 767 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 25045500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25045500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25045500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 26271000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 26271000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 26271000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34251.629726 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 440236 # number of replacements
system.cpu.dcache.tagsinuse 4094.816019 # Cycle average of tags in use
system.cpu.dcache.total_refs 206409236 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 444332 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 464.538309 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 88952000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.816019 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 138485254 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 67921309 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1329 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1335 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 206406563 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 206406563 # number of overall hits
system.cpu.dcache.ReadReq_misses 243961 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1496222 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1740183 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1740183 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3253587000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 26715936018 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 29969523018 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 29969523018 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 138729215 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 440983 # number of replacements
system.cpu.dcache.tagsinuse 4094.790768 # Cycle average of tags in use
system.cpu.dcache.total_refs 209375241 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 445079 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 470.422646 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 87857000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.790768 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 141476381 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 67896188 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1340 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1332 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 209372569 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 209372569 # number of overall hits
system.cpu.dcache.ReadReq_misses 248779 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1521343 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 10 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1770122 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1770122 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3280245000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 26835404025 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 198500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 30115649025 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 30115649025 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 141725160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1335 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 208146746 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 208146746 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.001759 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.021554 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.011161 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 17222.052519 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 17222.052519 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked
system.cpu.dcache.LoadLockedReq_accesses 1350 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1332 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 211142691 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 211142691 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.001755 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.021916 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.007407 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.008384 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.008384 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 13185.377383 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17639.285832 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 19850 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 17013.318305 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 17013.318305 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 394716 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 46944 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1248905 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1295849 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1295849 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 197017 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 247317 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 444334 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 444334 # number of overall MSHR misses
system.cpu.dcache.writebacks 395060 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 51069 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1273974 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 10 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1325043 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1325043 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 197710 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 247369 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 445079 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 445079 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1620169000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2562065527 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4182234527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4182234527 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1624301000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2561171527 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4185472527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4185472527 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001395 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8223.498480 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8215.573314 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.647898 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 72895 # number of replacements
system.cpu.l2cache.tagsinuse 17837.050931 # Cycle average of tags in use
system.cpu.l2cache.total_refs 420745 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88410 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.759020 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 72980 # number of replacements
system.cpu.l2cache.tagsinuse 17828.973663 # Cycle average of tags in use
system.cpu.l2cache.total_refs 421802 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88512 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.765478 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1909.078024 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15927.972907 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058260 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486083 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 165017 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 394716 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 188953 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 353970 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 353970 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32728 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91091 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91091 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1124545500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2003459500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3128005000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3128005000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 197745 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 394716 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 247316 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 445061 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 445061 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.165506 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235986 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.204671 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.204671 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34339.341977 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34339.341977 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 1911.988295 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15916.985368 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058349 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.485748 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 165669 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 395060 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 188996 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 354665 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 354665 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32802 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58379 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91181 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91181 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1126009000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2004629500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3130638500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3130638500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 198471 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 395060 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 247375 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 445846 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 445846 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.165274 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235994 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.204512 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.204512 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34327.449546 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34338.195241 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34334.329520 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34334.329520 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
@ -496,32 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 58107 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32722 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses
system.cpu.l2cache.writebacks 58140 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32793 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58379 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91172 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91172 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1018131500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823239000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2841370500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2841370500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019413500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823005500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2842419000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2842419000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235986 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.204657 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.204657 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165228 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235994 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.204492 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.204492 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31086.314152 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31227.076517 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -498,7 +499,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:18:15
gem5 executing on zizzer
gem5 compiled Jul 8 2011 15:08:13
gem5 started Jul 8 2011 18:26:23
gem5 executing on u200439-lin.austin.arm.com
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -40,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 573907140000 because target called exit()
Exiting @ tick 563588156500 because target called exit()

736
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,250 +1,252 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.573907 # Number of seconds simulated
sim_ticks 573907140000 # Number of ticks simulated
sim_seconds 0.563588 # Number of seconds simulated
sim_ticks 563588156500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 108575 # Simulator instruction rate (inst/s)
host_tick_rate 44331146 # Simulator tick rate (ticks/s)
host_mem_usage 230156 # Number of bytes of host memory used
host_seconds 12945.91 # Real time elapsed on the host
host_inst_rate 64765 # Simulator instruction rate (inst/s)
host_tick_rate 25968064 # Simulator tick rate (ticks/s)
host_mem_usage 251156 # Number of bytes of host memory used
host_seconds 21703.13 # Real time elapsed on the host
sim_insts 1405604152 # Number of instructions simulated
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1147814281 # number of cpu cycles simulated
system.cpu.numCycles 1127176314 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 103831607 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 92935748 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 5327690 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 99212201 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 97835702 # Number of BTB hits
system.cpu.BPredUnit.lookups 108002078 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 96458356 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 5419443 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 104845979 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 103526655 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1143 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.usedRAS 1233 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 171000623 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1733021012 # Number of instructions fetch has processed
system.cpu.fetch.Branches 103831607 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 97836845 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 371038275 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5780781 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 171000623 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1213723 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1147443356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.514308 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.728632 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 182291160 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1787208152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 108002078 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 103527888 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 384452467 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 39306331 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 526780202 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 13 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1622 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 177554256 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1007248 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1126809005 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.590132 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.768689 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 776405081 67.66% 67.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 82050380 7.15% 74.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 44983062 3.92% 78.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23090909 2.01% 80.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 33504477 2.92% 83.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 33278378 2.90% 86.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 14847881 1.29% 87.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7468781 0.65% 88.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 131814407 11.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 742356538 65.88% 65.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 85341479 7.57% 73.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 46929286 4.16% 77.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 24554385 2.18% 79.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 34670829 3.08% 82.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 34912206 3.10% 85.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 15372705 1.36% 87.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7941055 0.70% 88.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 134730522 11.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1147443356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.090460 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.509844 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 395037433 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 355619175 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 349843694 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 18917144 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 28025910 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1728452454 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 28025910 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 431217240 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 109925159 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 53352046 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 328971918 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 195951083 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1711590764 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 114289761 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 41137293 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 28197975 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1428307054 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2890539960 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2856856842 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 33683118 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 1126809005 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.095816 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.585562 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 243483307 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 469211226 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 329903735 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 50927196 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 33283541 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 1773785354 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 33283541 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 303199519 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 121005551 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 66378557 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 319425533 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 283516304 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1755376544 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 158155356 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 64460520 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 40367810 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1464774447 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2963679380 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2929648556 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34030824 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 183536602 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3097987 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3097933 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 355739263 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 461589654 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 187242454 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 391441071 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 159185807 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1587145158 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3113475 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1482560203 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 270761 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 184202886 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 243216207 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 869804 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1147443356 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.292055 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.157896 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 220003995 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3335169 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3335909 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 507197291 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 473956598 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 190918944 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 402921595 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 162419763 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1626020867 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3211854 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1494042135 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 206172 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 223169277 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 302404283 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 968183 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1126809005 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.325905 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.154571 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 300845237 26.22% 26.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 453630203 39.53% 65.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 228516175 19.92% 85.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 106998909 9.32% 94.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 42740064 3.72% 98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 8913516 0.78% 99.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5375020 0.47% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 270889 0.02% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 153343 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 292007700 25.91% 25.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 411780858 36.54% 62.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 263168713 23.36% 85.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 101528512 9.01% 94.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 43990451 3.90% 98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 11374555 1.01% 99.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2356617 0.21% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 448758 0.04% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 152841 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1147443356 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1126809005 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 201164 6.38% 6.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 172993 5.49% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2493416 79.12% 90.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 283893 9.01% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 276548 8.36% 8.36% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 8.36% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 151088 4.56% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2447279 73.94% 86.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 434986 13.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 884414368 59.65% 59.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2630713 0.18% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 423843345 28.59% 88.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171671777 11.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 893364457 59.80% 59.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2623126 0.18% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 426278234 28.53% 88.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 171776318 11.50% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1482560203 # Type of FU issued
system.cpu.iq.rate 1.291638 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3151466 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002126 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4098230852 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1765766096 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1465086286 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17755137 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9173728 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8521133 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1476573323 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9138346 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 135220708 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 1494042135 # Type of FU issued
system.cpu.iq.rate 1.325473 # Inst issue rate
system.cpu.iq.fu_busy_cnt 3309901 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002215 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4100596899 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1843738328 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1474876541 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 17812449 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 9274219 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 8514769 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1488163197 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 9188839 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 140932048 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 59076810 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 33855 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 480180 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 20394312 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 71443754 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20242 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 695476 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 24070802 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 40283 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 267 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39866 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 28025910 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2504854 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 128582 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1690773630 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4528845 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 461589654 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 187242454 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3013900 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 66564 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 8476 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 480180 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5013682 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 651351 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 5665033 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1476197681 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 421021999 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6362522 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 33283541 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2642816 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 166342 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1732819113 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 4184603 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 473956598 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 190918944 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3110022 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 73740 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 9229 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 695476 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5255230 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 461002 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 5716232 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1486789752 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 422968775 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7252383 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 100514997 # number of nop insts executed
system.cpu.iew.exec_refs 591171698 # number of memory reference insts executed
system.cpu.iew.exec_branches 89599986 # Number of branches executed
system.cpu.iew.exec_stores 170149699 # Number of stores executed
system.cpu.iew.exec_rate 1.286095 # Inst execution rate
system.cpu.iew.wb_sent 1474639839 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1473607419 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1163432060 # num instructions producing a value
system.cpu.iew.wb_consumers 1211671971 # num instructions consuming a value
system.cpu.iew.exec_nop 103586392 # number of nop insts executed
system.cpu.iew.exec_refs 593427321 # number of memory reference insts executed
system.cpu.iew.exec_branches 90250072 # Number of branches executed
system.cpu.iew.exec_stores 170458546 # Number of stores executed
system.cpu.iew.exec_rate 1.319039 # Inst execution rate
system.cpu.iew.wb_sent 1484841678 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1483391310 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1170940676 # num instructions producing a value
system.cpu.iew.wb_consumers 1222219030 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.283838 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.960187 # average fanout of values written-back
system.cpu.iew.wb_rate 1.316024 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.958045 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 201157053 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 243200723 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 5327690 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1119418057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.330623 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.777335 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 5419443 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1093526075 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.362129 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.820328 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 396150099 35.39% 35.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 467476114 41.76% 77.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 53942653 4.82% 81.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 96590276 8.63% 90.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 32582647 2.91% 93.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8533715 0.76% 94.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 26013211 2.32% 96.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9722118 0.87% 97.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 28407224 2.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 386645364 35.36% 35.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 450467032 41.19% 76.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 52266567 4.78% 81.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 95504499 8.73% 90.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 32424023 2.97% 93.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8856558 0.81% 93.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 27482733 2.51% 96.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9900040 0.91% 97.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 29979259 2.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1119418057 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1093526075 # Number of insts commited each cycle
system.cpu.commit.count 1489523295 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 569360986 # Number of memory references committed
@ -254,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
system.cpu.commit.bw_lim_events 28407224 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 29979259 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2781626311 # The number of ROB reads
system.cpu.rob.rob_writes 3409421269 # The number of ROB writes
system.cpu.timesIdled 11496 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 370925 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 2796205964 # The number of ROB reads
system.cpu.rob.rob_writes 3498772696 # The number of ROB writes
system.cpu.timesIdled 11331 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 367309 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
system.cpu.cpi 0.816599 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.816599 # CPI: Total CPI of All Threads
system.cpu.ipc 1.224592 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.224592 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1997677714 # number of integer regfile reads
system.cpu.int_regfile_writes 1296953173 # number of integer regfile writes
system.cpu.fp_regfile_reads 16960308 # number of floating regfile reads
system.cpu.fp_regfile_writes 10460736 # number of floating regfile writes
system.cpu.misc_regfile_reads 596972028 # number of misc regfile reads
system.cpu.cpi 0.801916 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.801916 # CPI: Total CPI of All Threads
system.cpu.ipc 1.247014 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.247014 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2006108330 # number of integer regfile reads
system.cpu.int_regfile_writes 1306606440 # number of integer regfile writes
system.cpu.fp_regfile_reads 16974388 # number of floating regfile reads
system.cpu.fp_regfile_writes 10441040 # number of floating regfile writes
system.cpu.misc_regfile_reads 599300610 # number of misc regfile reads
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
system.cpu.icache.replacements 152 # number of replacements
system.cpu.icache.tagsinuse 1026.516875 # Cycle average of tags in use
system.cpu.icache.total_refs 170998889 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1268 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 134857.167981 # Average number of references to valid blocks.
system.cpu.icache.replacements 162 # number of replacements
system.cpu.icache.tagsinuse 1043.489653 # Cycle average of tags in use
system.cpu.icache.total_refs 177552476 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 136894.738628 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1026.516875 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.501229 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 170998889 # number of ReadReq hits
system.cpu.icache.demand_hits 170998889 # number of demand (read+write) hits
system.cpu.icache.overall_hits 170998889 # number of overall hits
system.cpu.icache.ReadReq_misses 1734 # number of ReadReq misses
system.cpu.icache.demand_misses 1734 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1734 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 61087500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 61087500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 61087500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 171000623 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 171000623 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 171000623 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 1043.489653 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.509516 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 177552476 # number of ReadReq hits
system.cpu.icache.demand_hits 177552476 # number of demand (read+write) hits
system.cpu.icache.overall_hits 177552476 # number of overall hits
system.cpu.icache.ReadReq_misses 1780 # number of ReadReq misses
system.cpu.icache.demand_misses 1780 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1780 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 62084000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 62084000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 62084000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 177554256 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 177554256 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 177554256 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35229.238754 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35229.238754 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35229.238754 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 34878.651685 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34878.651685 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34878.651685 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -307,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 465 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 465 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1269 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1269 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1269 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 482 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 482 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 44480000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 44480000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 44480000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 45208500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45208500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45208500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35051.221434 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34829.352851 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 477525 # number of replacements
system.cpu.dcache.tagsinuse 4095.396718 # Cycle average of tags in use
system.cpu.dcache.total_refs 449986913 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 481621 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 934.317467 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 132284000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.396718 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999853 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 284949611 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 165035983 # number of WriteReq hits
system.cpu.dcache.replacements 475456 # number of replacements
system.cpu.dcache.tagsinuse 4095.394464 # Cycle average of tags in use
system.cpu.dcache.total_refs 446158150 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 479552 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 930.364486 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 131008000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.394464 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999852 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 281189388 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 164967443 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits 449985594 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 449985594 # number of overall hits
system.cpu.dcache.ReadReq_misses 816129 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1810833 # number of WriteReq misses
system.cpu.dcache.demand_hits 446156831 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 446156831 # number of overall hits
system.cpu.dcache.ReadReq_misses 816269 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1879373 # number of WriteReq misses
system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
system.cpu.dcache.demand_misses 2626962 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2626962 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11967941500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 27822628145 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 2695642 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2695642 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11972698500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28858348258 # number of WriteReq miss cycles
system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles
system.cpu.dcache.demand_miss_latency 39790569645 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39790569645 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 285765740 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 40831046758 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 40831046758 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 282005657 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 452612556 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 452612556 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002856 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010853 # miss rate for WriteReq accesses
system.cpu.dcache.demand_accesses 448852473 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 448852473 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002895 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.011264 # miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
system.cpu.dcache.demand_miss_rate 0.005804 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.005804 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 14664.276726 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 15364.546673 # average WriteReq miss latency
system.cpu.dcache.demand_miss_rate 0.006006 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.006006 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 14667.589361 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 15355.306402 # average WriteReq miss latency
system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency
system.cpu.dcache.demand_avg_miss_latency 15146.990952 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 15146.990952 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_avg_miss_latency 15147.058385 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 15147.058385 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 428389 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 602603 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1542745 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 2145348 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 2145348 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 213526 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 268088 # number of WriteReq MSHR misses
system.cpu.dcache.writebacks 426829 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 604140 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1611957 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 2216097 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 2216097 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 212129 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 267416 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
system.cpu.dcache.demand_mshr_misses 481614 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 481614 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_misses 479545 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 479545 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1594631500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3466876734 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1590330500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3553768773 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5061508234 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5061508234 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5144099273 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5144099273 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000752 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7468.090537 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12931.860934 # average WriteReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.001068 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001068 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.997110 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13289.289994 # average WriteReq mshr miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 75907 # number of replacements
system.cpu.l2cache.tagsinuse 17672.498181 # Cycle average of tags in use
system.cpu.l2cache.total_refs 467533 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 91416 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.114345 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 75860 # number of replacements
system.cpu.l2cache.tagsinuse 17695.918496 # Cycle average of tags in use
system.cpu.l2cache.total_refs 464712 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 91372 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.085934 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1962.738670 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15709.759511 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.059898 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.479424 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 181118 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 428389 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 207636 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 388754 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 388754 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33668 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 60468 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 94136 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 94136 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1145944000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2080516000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3226460000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3226460000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 214786 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 428389 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 268104 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 482890 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 482890 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.156751 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.225539 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.194943 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.194943 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.592610 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34406.892902 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34274.453981 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34274.453981 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 1941.337449 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15754.581047 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.059245 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.480792 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 179775 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 426829 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 206986 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 386761 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 386761 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33652 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 60437 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 94089 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 94089 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1145407000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2080656500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3226063500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3226063500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 213427 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 426829 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 267423 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 480850 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 480850 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.157675 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.225998 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.195672 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.195672 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.818020 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34426.865993 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34287.360903 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34287.360903 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -449,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 59288 # number of writebacks
system.cpu.l2cache.writebacks 59276 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 33668 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 60468 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 94136 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 94136 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 33652 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 60437 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 94089 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 94089 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1043871500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893875000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2937746500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2937746500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1043368500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893759500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2937128000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2937128000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156751 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225539 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.194943 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.194943 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.856243 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.285109 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157675 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225998 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.195672 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.195672 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.650541 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31334.439168 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 27 2011 02:06:34
gem5 started Jun 27 2011 02:06:35
gem5 executing on burrito
command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:15
gem5 started Jul 8 2011 19:12:13
gem5 executing on u200439-lin.austin.arm.com
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -1062,4 +1062,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 750278436000 because target called exit()
Exiting @ tick 746999805000 because target called exit()

728
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,249 +1,251 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.750278 # Number of seconds simulated
sim_ticks 750278436000 # Number of ticks simulated
sim_seconds 0.747000 # Number of seconds simulated
sim_ticks 746999805000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 214715 # Simulator instruction rate (inst/s)
host_tick_rate 99350353 # Simulator tick rate (ticks/s)
host_mem_usage 230596 # Number of bytes of host memory used
host_seconds 7551.84 # Real time elapsed on the host
host_inst_rate 52755 # Simulator instruction rate (inst/s)
host_tick_rate 24303440 # Simulator tick rate (ticks/s)
host_mem_usage 253604 # Number of bytes of host memory used
host_seconds 30736.38 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1500556873 # number of cpu cycles simulated
system.cpu.numCycles 1493999611 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 179206646 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 179206646 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 8463551 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 169776881 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 168588435 # Number of BTB hits
system.cpu.BPredUnit.lookups 183981284 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 183981284 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 7273832 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 175979129 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 174823422 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 168643185 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1398775423 # Number of instructions fetch has processed
system.cpu.fetch.Branches 179206646 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 168588435 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 401459368 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 14868125 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 168643185 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 821564 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1500265844 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.692515 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.050179 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 199101325 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1418187336 # Number of instructions fetch has processed
system.cpu.fetch.Branches 183981284 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174823422 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 411931747 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 120581871 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 775842898 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 439 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 187933146 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1412014 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1493732032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.734289 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.070436 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1101846908 73.44% 73.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25629201 1.71% 75.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 17503252 1.17% 76.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 17259352 1.15% 77.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 30203070 2.01% 79.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 16882652 1.13% 80.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 34105222 2.27% 82.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37737433 2.52% 85.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 219098754 14.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1084944891 72.63% 72.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 27695152 1.85% 74.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18612240 1.25% 75.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 16931022 1.13% 76.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 30747713 2.06% 78.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 17254642 1.16% 80.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38005540 2.54% 82.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 38774045 2.60% 85.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 220766787 14.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1500265844 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.119427 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.932171 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 426619882 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 588582259 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 331774062 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 54890410 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 98399231 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2463603655 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 98399231 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 490140995 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 167797271 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3037 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 309381141 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 434544169 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2390094348 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 298397694 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 109374277 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2388910462 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5790943512 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5790943448 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 1493732032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123147 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.949255 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 299784199 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 683008972 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 314849688 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 89233622 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 106855551 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2563435147 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 106855551 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 360599256 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 188215169 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3353 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 328972953 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 509085750 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2506842740 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 353300714 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 135977984 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2507364398 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6062894034 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6062889786 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4248 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 770915812 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 713558954 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 613723437 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 250366407 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 539421468 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 206415389 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2337617045 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1854722734 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 196953 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 715983429 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1505792864 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1500265844 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.236263 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.216770 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 889369748 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 162 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 162 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 860776772 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 644217579 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 260359160 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 564219162 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 219825369 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2437807916 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 95 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1879814445 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 473311 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 816283522 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1731057121 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1493732032 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.258468 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.208875 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 461494018 30.76% 30.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 582014055 38.79% 69.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 214930558 14.33% 83.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 153972669 10.26% 94.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 64799231 4.32% 98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 17691341 1.18% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4397619 0.29% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 840611 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 125742 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 432191127 28.93% 28.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 591005322 39.57% 68.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 246823296 16.52% 85.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 135579868 9.08% 94.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 59328852 3.97% 98.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 22913004 1.53% 99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4862881 0.33% 99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 856243 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 171439 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1500265844 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1493732032 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 159647 3.75% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 3486871 81.91% 85.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 610438 14.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 145103 3.04% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 3853337 80.69% 83.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 777052 16.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 27575645 1.49% 1.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1184540758 63.87% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 450487645 24.29% 89.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192118686 10.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::No_OpClass 26397138 1.40% 1.40% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1212079345 64.48% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 449002654 23.89% 89.77% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192335308 10.23% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1854722734 # Type of FU issued
system.cpu.iq.rate 1.236023 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4256956 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002295 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5214165186 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3059990835 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1837811563 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 1879814445 # Type of FU issued
system.cpu.iq.rate 1.258243 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4775492 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002540 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5258609690 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3260533161 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1853774167 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_writes 1274 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1831404026 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 1858192780 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 117971084 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 120571651 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 194681312 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 16091 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 6391116 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 62180350 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 225175454 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6636 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 6448917 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 72173103 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30252 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 67 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30868 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 98399231 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1363305 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 110880 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2337617123 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 338195 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 613723437 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 250366407 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 56702 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 6391116 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4450206 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4153743 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8603949 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1842187665 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 444314021 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 12535069 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 106855551 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4276997 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 154006 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2437808011 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3809571 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 644217579 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 260359160 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 92996 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 6448917 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4522013 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2931532 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 7453545 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1858657499 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 444749829 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 21156946 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 636013673 # number of memory reference insts executed
system.cpu.iew.exec_branches 111427506 # Number of branches executed
system.cpu.iew.exec_stores 191699652 # Number of stores executed
system.cpu.iew.exec_rate 1.227669 # Inst execution rate
system.cpu.iew.wb_sent 1840965230 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1837811575 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1424401809 # num instructions producing a value
system.cpu.iew.wb_consumers 2083960582 # num instructions consuming a value
system.cpu.iew.exec_refs 636612361 # number of memory reference insts executed
system.cpu.iew.exec_branches 111987428 # Number of branches executed
system.cpu.iew.exec_stores 191862532 # Number of stores executed
system.cpu.iew.exec_rate 1.244082 # Inst execution rate
system.cpu.iew.wb_sent 1856615108 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1853774179 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1441885120 # num instructions producing a value
system.cpu.iew.wb_consumers 2107634936 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.224753 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.683507 # average fanout of values written-back
system.cpu.iew.wb_rate 1.240813 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.684125 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 716132515 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 816323432 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8463578 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1401866613 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.156668 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.378442 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 7273892 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1386876481 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.169170 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.394530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 520031376 37.10% 37.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 533018726 38.02% 75.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 125308330 8.94% 84.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 139235246 9.93% 93.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 43288203 3.09% 97.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23453801 1.67% 98.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 4331063 0.31% 99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1854281 0.13% 99.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11345587 0.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 510181205 36.79% 36.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 529583219 38.19% 74.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 122943422 8.86% 83.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 138376651 9.98% 93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 42654329 3.08% 96.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24144434 1.74% 98.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5177613 0.37% 99.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2036062 0.15% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11779546 0.85% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1401866613 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1386876481 # Number of insts commited each cycle
system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
@ -253,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 11345587 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 11779546 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3728147523 # The number of ROB reads
system.cpu.rob.rob_writes 4773653528 # The number of ROB writes
system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 291029 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 3812914349 # The number of ROB reads
system.cpu.rob.rob_writes 4982493999 # The number of ROB writes
system.cpu.timesIdled 44138 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 267579 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.cpi 0.925416 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.925416 # CPI: Total CPI of All Threads
system.cpu.ipc 1.080595 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.080595 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3235784294 # number of integer regfile reads
system.cpu.int_regfile_writes 1830729236 # number of integer regfile writes
system.cpu.cpi 0.921372 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.921372 # CPI: Total CPI of All Threads
system.cpu.ipc 1.085338 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.085338 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3240601354 # number of integer regfile reads
system.cpu.int_regfile_writes 1846777221 # number of integer regfile writes
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
system.cpu.misc_regfile_reads 930213220 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 793.330591 # Cycle average of tags in use
system.cpu.icache.total_refs 168641986 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 875 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 192733.698286 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 936479302 # number of misc regfile reads
system.cpu.icache.replacements 14 # number of replacements
system.cpu.icache.tagsinuse 820.004984 # Cycle average of tags in use
system.cpu.icache.total_refs 187931883 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 908 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 206973.439427 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 793.330591 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.387368 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 168641986 # number of ReadReq hits
system.cpu.icache.demand_hits 168641986 # number of demand (read+write) hits
system.cpu.icache.overall_hits 168641986 # number of overall hits
system.cpu.icache.ReadReq_misses 1199 # number of ReadReq misses
system.cpu.icache.demand_misses 1199 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1199 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 42201000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 42201000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 42201000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 168643185 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 168643185 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 168643185 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 820.004984 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.400393 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 187931883 # number of ReadReq hits
system.cpu.icache.demand_hits 187931883 # number of demand (read+write) hits
system.cpu.icache.overall_hits 187931883 # number of overall hits
system.cpu.icache.ReadReq_misses 1263 # number of ReadReq misses
system.cpu.icache.demand_misses 1263 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1263 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 44191500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 44191500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 44191500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 187933146 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 187933146 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 187933146 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35196.830692 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35196.830692 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35196.830692 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 34989.311164 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34989.311164 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34989.311164 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -304,159 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 324 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 324 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 875 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 875 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 875 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 355 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 355 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 355 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 30921000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 30921000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 30921000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 32070500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 32070500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 32070500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 460957 # number of replacements
system.cpu.dcache.tagsinuse 4095.145869 # Cycle average of tags in use
system.cpu.dcache.total_refs 513034277 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 465053 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1103.173782 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317696000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.145869 # Average occupied blocks per context
system.cpu.dcache.replacements 459464 # number of replacements
system.cpu.dcache.tagsinuse 4095.142322 # Cycle average of tags in use
system.cpu.dcache.total_refs 510865684 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 463560 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1102.048675 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317747000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.142322 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 326108931 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 186925346 # number of WriteReq hits
system.cpu.dcache.demand_hits 513034277 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 513034277 # number of overall hits
system.cpu.dcache.ReadReq_misses 218266 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1260711 # number of WriteReq misses
system.cpu.dcache.demand_misses 1478977 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1478977 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2205272500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24390827496 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 26596099996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 26596099996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 326327197 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 323944700 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 186920984 # number of WriteReq hits
system.cpu.dcache.demand_hits 510865684 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 510865684 # number of overall hits
system.cpu.dcache.ReadReq_misses 217118 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1265073 # number of WriteReq misses
system.cpu.dcache.demand_misses 1482191 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1482191 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2201155000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24662905498 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 26864060498 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 26864060498 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 324161818 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 514513254 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 514513254 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000669 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.006699 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.002875 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002875 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 17982.767816 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 17982.767816 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 474736000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29560 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191 # average number of cycles each access was blocked
system.cpu.dcache.demand_accesses 512347875 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 512347875 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000670 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.006722 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.002893 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002893 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18124.560531 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18124.560531 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1608500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 471924500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 447 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29514 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3598.434004 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 411400 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 3331 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1010593 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1013924 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1013924 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 214935 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 250118 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 465053 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 465053 # number of overall MSHR misses
system.cpu.dcache.writebacks 410359 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 3236 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1015395 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1018631 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1018631 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 213882 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 249678 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 463560 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 463560 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1536673000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2518183497 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4054856497 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4054856497 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1535369000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2499634500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4035003500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4035003500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7149.477749 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.579778 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73679 # number of replacements
system.cpu.l2cache.tagsinuse 18021.980204 # Cycle average of tags in use
system.cpu.l2cache.total_refs 455469 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.101465 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 73641 # number of replacements
system.cpu.l2cache.tagsinuse 18052.437933 # Cycle average of tags in use
system.cpu.l2cache.total_refs 453217 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89251 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.078005 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1918.737195 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16103.243009 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058555 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.491432 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 182682 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 411400 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 191297 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 373979 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 373979 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33118 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58831 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91949 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91949 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1130130500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2026415500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3156546000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3156546000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 215800 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 411400 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 250128 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 465928 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 465928 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.153466 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235204 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.197346 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.197346 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34329.312989 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34329.312989 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked
system.cpu.l2cache.occ_blocks::0 1921.052649 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16131.385284 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058626 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.492291 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 181658 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 410359 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 190902 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 372560 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 372560 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33126 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58782 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91908 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91908 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1130437500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2022399000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3152836500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3152836500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 214784 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 410359 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 249684 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 464468 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 464468 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.154229 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235426 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.197878 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.197878 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34304.266223 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34304.266223 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1076.388889 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 58539 # number of writebacks
system.cpu.l2cache.writebacks 58527 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 33118 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58831 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91949 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91949 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 33126 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58782 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91908 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91908 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1026873000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832918500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2859791500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2859791500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1027129500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1831638000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2858767500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2858767500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153466 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235204 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.197346 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.197346 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154229 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235426 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.197878 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.197878 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

33
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -10,12 +10,13 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
memories=system.physmem
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -930,7 +931,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -950,7 +951,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -1046,6 +1047,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.
[system.membus.badaddr_responder]
type=IsaFake
fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@ -1078,7 +1080,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -1197,6 +1199,7 @@ pio=system.iobus.port[27]
[system.tsunami.fake_OROM]
type=IsaFake
fake_mem=false
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
@ -1213,6 +1216,7 @@ pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
fake_mem=false
pio_addr=8804615848432
pio_latency=1000
pio_size=8
@ -1229,6 +1233,7 @@ pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
fake_mem=false
pio_addr=8804615848304
pio_latency=1000
pio_size=8
@ -1245,6 +1250,7 @@ pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
fake_mem=false
pio_addr=8804615848569
pio_latency=1000
pio_size=8
@ -1261,6 +1267,7 @@ pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
fake_mem=false
pio_addr=8804615848451
pio_latency=1000
pio_size=8
@ -1277,6 +1284,7 @@ pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
fake_mem=false
pio_addr=8804615848515
pio_latency=1000
pio_size=8
@ -1293,6 +1301,7 @@ pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
fake_mem=false
pio_addr=8804615848579
pio_latency=1000
pio_size=8
@ -1309,6 +1318,7 @@ pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
fake_mem=false
pio_addr=8804615848643
pio_latency=1000
pio_size=8
@ -1325,6 +1335,7 @@ pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
fake_mem=false
pio_addr=8804615848707
pio_latency=1000
pio_size=8
@ -1341,6 +1352,7 @@ pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
fake_mem=false
pio_addr=8804615848771
pio_latency=1000
pio_size=8
@ -1357,6 +1369,7 @@ pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
fake_mem=false
pio_addr=8804615848835
pio_latency=1000
pio_size=8
@ -1373,6 +1386,7 @@ pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
fake_mem=false
pio_addr=8804615848899
pio_latency=1000
pio_size=8
@ -1389,6 +1403,7 @@ pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
fake_mem=false
pio_addr=8804615850617
pio_latency=1000
pio_size=8
@ -1405,6 +1420,7 @@ pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
fake_mem=false
pio_addr=8804615848891
pio_latency=1000
pio_size=8
@ -1421,6 +1437,7 @@ pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
fake_mem=false
pio_addr=8804615848816
pio_latency=1000
pio_size=8
@ -1437,6 +1454,7 @@ pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
fake_mem=false
pio_addr=8804615848696
pio_latency=1000
pio_size=8
@ -1453,6 +1471,7 @@ pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
fake_mem=false
pio_addr=8804615848936
pio_latency=1000
pio_size=8
@ -1469,6 +1488,7 @@ pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
fake_mem=false
pio_addr=8804615848680
pio_latency=1000
pio_size=8
@ -1485,6 +1505,7 @@ pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
fake_mem=false
pio_addr=8804615848944
pio_latency=1000
pio_size=8

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
View file

@ -1,9 +1,5 @@
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
hack: be nice to actually delete the event here

22
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,17 +1,13 @@
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 12:02:59
M5 started Apr 21 2011 13:21:52
M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
gem5 compiled Jul 8 2011 15:02:59
gem5 started Jul 8 2011 18:23:45
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 109002500
Exiting @ tick 1901725056500 because m5_exit instruction encountered
info: Launching CPU 1 @ 107915000
Exiting @ tick 1898652239500 because m5_exit instruction encountered

3082
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

33
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -10,12 +10,13 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/chips/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
pal=/dist/m5/system/binaries/ts_osfpal
memories=system.physmem
pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -495,7 +496,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -515,7 +516,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -611,6 +612,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.
[system.membus.badaddr_responder]
type=IsaFake
fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@ -643,7 +645,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -762,6 +764,7 @@ pio=system.iobus.port[27]
[system.tsunami.fake_OROM]
type=IsaFake
fake_mem=false
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
@ -778,6 +781,7 @@ pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
fake_mem=false
pio_addr=8804615848432
pio_latency=1000
pio_size=8
@ -794,6 +798,7 @@ pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
fake_mem=false
pio_addr=8804615848304
pio_latency=1000
pio_size=8
@ -810,6 +815,7 @@ pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
fake_mem=false
pio_addr=8804615848569
pio_latency=1000
pio_size=8
@ -826,6 +832,7 @@ pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
fake_mem=false
pio_addr=8804615848451
pio_latency=1000
pio_size=8
@ -842,6 +849,7 @@ pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
fake_mem=false
pio_addr=8804615848515
pio_latency=1000
pio_size=8
@ -858,6 +866,7 @@ pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
fake_mem=false
pio_addr=8804615848579
pio_latency=1000
pio_size=8
@ -874,6 +883,7 @@ pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
fake_mem=false
pio_addr=8804615848643
pio_latency=1000
pio_size=8
@ -890,6 +900,7 @@ pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
fake_mem=false
pio_addr=8804615848707
pio_latency=1000
pio_size=8
@ -906,6 +917,7 @@ pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
fake_mem=false
pio_addr=8804615848771
pio_latency=1000
pio_size=8
@ -922,6 +934,7 @@ pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
fake_mem=false
pio_addr=8804615848835
pio_latency=1000
pio_size=8
@ -938,6 +951,7 @@ pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
fake_mem=false
pio_addr=8804615848899
pio_latency=1000
pio_size=8
@ -954,6 +968,7 @@ pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
fake_mem=false
pio_addr=8804615850617
pio_latency=1000
pio_size=8
@ -970,6 +985,7 @@ pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
fake_mem=false
pio_addr=8804615848891
pio_latency=1000
pio_size=8
@ -986,6 +1002,7 @@ pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
fake_mem=false
pio_addr=8804615848816
pio_latency=1000
pio_size=8
@ -1002,6 +1019,7 @@ pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
fake_mem=false
pio_addr=8804615848696
pio_latency=1000
pio_size=8
@ -1018,6 +1036,7 @@ pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
fake_mem=false
pio_addr=8804615848936
pio_latency=1000
pio_size=8
@ -1034,6 +1053,7 @@ pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
fake_mem=false
pio_addr=8804615848680
pio_latency=1000
pio_size=8
@ -1050,6 +1070,7 @@ pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
fake_mem=false
pio_addr=8804615848944
pio_latency=1000
pio_size=8

8
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
View file

@ -1,9 +1,5 @@
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
hack: be nice to actually delete the event here

20
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,16 +1,12 @@
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 12:02:59
M5 started Apr 21 2011 13:21:52
M5 executing on maize
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
gem5 compiled Jul 8 2011 15:02:59
gem5 started Jul 8 2011 18:21:28
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1863702170500 because m5_exit instruction encountered
Exiting @ tick 1860642398500 because m5_exit instruction encountered

1714
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -19,6 +19,7 @@ kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.diskmem
midr_regval=890236928
physmem=system.physmem
readfile=tests/halt.sh
@ -600,6 +601,7 @@ port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.r
[system.membus.badaddr_responder]
type=IsaFake
fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
@ -732,6 +734,7 @@ pio=system.iobus.port[9]
[system.realview.flash_fake]
type=IsaFake
fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
@ -818,6 +821,7 @@ pio=system.iobus.port[7]
[system.realview.l2x0_fake]
type=IsaFake
fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095

20
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
View file

@ -1,35 +1,19 @@
warn: Sockets disabled, not accepting vnc client connections
For more information see: http://www.m5sim.org/warn/af6a84f6
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: The clidr register always reports 0 caches.
For more information see: http://www.m5sim.org/warn/23a3c326
warn: The csselr register isn't implemented.
For more information see: http://www.m5sim.org/warn/c0c486b8
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: The ccsidr register isn't implemented and always reads as 0.
For more information see: http://www.m5sim.org/warn/2c4acb9c
warn: instruction 'mcr dccimvac' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr dccmvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr icimvau' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
For more information see: http://www.m5sim.org/warn/7998f2ea
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr bpiall' unimplemented
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
warn: instruction 'mcr bpiall' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here

22
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,17 +1,11 @@
Redirecting stdout to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simout
Redirecting stderr to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 21:41:16
M5 started May 16 2011 21:43:01
M5 executing on nadc-0271
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3
gem5 compiled Jul 8 2011 15:21:58
gem5 started Jul 9 2011 04:29:24
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 81956970500 because m5_exit instruction encountered
Exiting @ tick 80755049500 because m5_exit instruction encountered

1012
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
View file

@ -1 +1 @@
build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED!
build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 passed.

BIN
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
View file

Binary file not shown.

7
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,14 +494,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

1
tests/long/10.mcf/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 18:02:55
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 01:04:44
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -29,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 38330782000 because target called exit()
Exiting @ tick 33955329500 because target called exit()

782
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.038331 # Number of seconds simulated
sim_ticks 38330782000 # Number of ticks simulated
sim_seconds 0.033955 # Number of seconds simulated
sim_ticks 33955329500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50765 # Simulator instruction rate (inst/s)
host_tick_rate 21324746 # Simulator tick rate (ticks/s)
host_mem_usage 388132 # Number of bytes of host memory used
host_seconds 1797.48 # Real time elapsed on the host
sim_insts 91249905 # Number of instructions simulated
host_inst_rate 64380 # Simulator instruction rate (inst/s)
host_tick_rate 23956859 # Simulator tick rate (ticks/s)
host_mem_usage 390580 # Number of bytes of host memory used
host_seconds 1417.35 # Real time elapsed on the host
sim_insts 91249680 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,298 +51,300 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 76661565 # number of cpu cycles simulated
system.cpu.numCycles 67910660 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 27657644 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 22240511 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1744604 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24744282 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 23393916 # Number of BTB hits
system.cpu.BPredUnit.lookups 28244508 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 22629080 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1414299 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 25112752 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 24086234 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 124718 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 12906 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14552899 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 133105183 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27657644 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23518634 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 32520380 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1878354 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 14552899 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 370142 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 76631921 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.753228 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.654795 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 121674 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 12927 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 16032012 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 135606393 # Number of instructions fetch has processed
system.cpu.fetch.Branches 28244508 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24207908 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 33529641 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6010411 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 13862842 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 15326942 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 412294 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 67880028 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.019137 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.751435 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 44169594 57.64% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6017071 7.85% 65.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6194245 8.08% 73.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4415007 5.76% 79.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3274566 4.27% 83.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1452193 1.90% 85.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1693941 2.21% 87.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3142647 4.10% 91.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6272657 8.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 34404593 50.68% 50.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6761573 9.96% 60.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5940167 8.75% 69.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4952932 7.30% 76.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2875416 4.24% 80.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1738729 2.56% 83.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1585314 2.34% 85.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3119241 4.60% 90.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6502063 9.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 76631921 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.360776 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.736270 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 30588008 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 10266300 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 31174404 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 260454 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4342755 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4341355 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 41083 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 130094148 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 33304 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4342755 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 31960440 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 537193 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8162537 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 30023248 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1605748 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 125609145 # Number of instructions processed by rename
system.cpu.fetch.rateDist::total 67880028 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.415907 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.996835 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 18687820 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12370381 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 31414917 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 983964 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4422946 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4499724 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 32863 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 133147735 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 31368 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4422946 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 20483676 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 968140 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8316666 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 30556439 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3132161 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 128513000 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 50871 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 833181 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 20 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 146281053 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 547382815 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 547382254 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 561 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 38851577 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 673626 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 677053 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 5163872 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29426504 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6065519 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 977286 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 410445 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 117966564 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 652219 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107299468 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 25775 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 24675448 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 62409285 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 97813 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 76631921 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.400193 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.609861 # Number of insts issued each cycle
system.cpu.rename.IQFullEvents 288426 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1795950 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 149798068 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 559931036 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 559926436 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4600 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429111 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 42368952 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 668763 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 669407 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 7564309 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 30008124 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6129267 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1456420 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 516652 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 120184129 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 637684 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107766890 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 87998 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 29120799 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 70180475 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 83323 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 67880028 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.587608 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.759573 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 31086016 40.57% 40.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 16895448 22.05% 62.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 11625629 15.17% 77.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7628942 9.96% 87.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5191089 6.77% 94.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2275199 2.97% 97.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1510567 1.97% 99.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 290065 0.38% 99.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 128966 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 25488891 37.55% 37.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14322408 21.10% 58.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10131350 14.93% 73.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 8118242 11.96% 85.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4318324 6.36% 91.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2337223 3.44% 95.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2482658 3.66% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 475759 0.70% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 205173 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 76631921 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 67880028 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 155894 31.11% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 83070 16.58% 47.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 262134 52.31% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 57394 10.75% 10.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 196663 36.84% 47.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 279761 52.40% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 75289326 70.17% 70.17% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10516 0.01% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 12 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26536591 24.73% 94.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5462996 5.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 75833735 70.37% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 110 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26490777 24.58% 94.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5431101 5.04% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107299468 # Type of FU issued
system.cpu.iq.rate 1.399651 # Inst issue rate
system.cpu.iq.fu_busy_cnt 501125 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004670 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 291757623 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 143406422 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102963471 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 134 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 92 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 107800524 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 69 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 260883 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 107766890 # Type of FU issued
system.cpu.iq.rate 1.586892 # Inst issue rate
system.cpu.iq.fu_busy_cnt 533845 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004954 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 284035005 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 150060826 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 103585232 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 646 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 916 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 298 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 108300410 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 325 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 363305 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 6850627 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7190 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 117769 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1318766 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 7432292 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 39631 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 124361 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1382559 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30512 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4342755 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 92075 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 26289 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 118657452 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 642589 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29426504 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6065519 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 647367 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 20754 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 246 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 117769 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1576147 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 244055 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1820202 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104961161 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25966774 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2338307 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 4422946 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 101110 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 18559 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 120860696 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 802315 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 30008124 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6129267 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 632825 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 10731 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 124361 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1290705 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 209600 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1500305 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 105816782 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 26069680 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1950108 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 38669 # number of nop insts executed
system.cpu.iew.exec_refs 31256963 # number of memory reference insts executed
system.cpu.iew.exec_branches 21029204 # Number of branches executed
system.cpu.iew.exec_stores 5290189 # Number of stores executed
system.cpu.iew.exec_rate 1.369150 # Inst execution rate
system.cpu.iew.wb_sent 103386173 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102963532 # cumulative count of insts written-back
system.cpu.iew.wb_producers 59509513 # num instructions producing a value
system.cpu.iew.wb_consumers 95068105 # num instructions consuming a value
system.cpu.iew.exec_nop 38883 # number of nop insts executed
system.cpu.iew.exec_refs 31358457 # number of memory reference insts executed
system.cpu.iew.exec_branches 21276544 # Number of branches executed
system.cpu.iew.exec_stores 5288777 # Number of stores executed
system.cpu.iew.exec_rate 1.558176 # Inst execution rate
system.cpu.iew.wb_sent 104017986 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 103585530 # cumulative count of insts written-back
system.cpu.iew.wb_producers 60888984 # num instructions producing a value
system.cpu.iew.wb_consumers 97986900 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.343092 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.625967 # average fanout of values written-back
system.cpu.iew.wb_rate 1.525321 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.621399 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 27394736 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1716455 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 72289167 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.262465 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.025163 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 91262289 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 29597995 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554361 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1394652 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 63457083 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.438173 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.204542 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 36212335 50.09% 50.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18072720 25.00% 75.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 6165923 8.53% 83.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4479757 6.20% 89.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2050310 2.84% 92.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 555022 0.77% 93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 748999 1.04% 94.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 84475 0.12% 94.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3919626 5.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 29495808 46.48% 46.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 16759375 26.41% 72.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5313552 8.37% 81.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4030004 6.35% 87.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1955590 3.08% 90.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 709900 1.12% 91.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 461456 0.73% 92.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 205982 0.32% 92.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4525416 7.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 72289167 # Number of insts commited each cycle
system.cpu.commit.count 91262514 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 63457083 # Number of insts commited each cycle
system.cpu.commit.count 91262289 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27322629 # Number of memory references committed
system.cpu.commit.loads 22575876 # Number of loads committed
system.cpu.commit.refs 27322539 # Number of memory references committed
system.cpu.commit.loads 22575831 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18722470 # Number of branches committed
system.cpu.commit.branches 18722425 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72533318 # Number of committed integer instructions.
system.cpu.commit.int_insts 72533138 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.bw_lim_events 3919626 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 4525416 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 187021057 # The number of ROB reads
system.cpu.rob.rob_writes 241665246 # The number of ROB writes
system.cpu.timesIdled 1537 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 29644 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 91249905 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated
system.cpu.cpi 0.840128 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.840128 # CPI: Total CPI of All Threads
system.cpu.ipc 1.190295 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.190295 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 499502252 # number of integer regfile reads
system.cpu.int_regfile_writes 121448309 # number of integer regfile writes
system.cpu.fp_regfile_reads 60 # number of floating regfile reads
system.cpu.fp_regfile_writes 46 # number of floating regfile writes
system.cpu.misc_regfile_reads 187007485 # number of misc regfile reads
system.cpu.misc_regfile_writes 11602 # number of misc regfile writes
system.cpu.rob.rob_reads 179786217 # The number of ROB reads
system.cpu.rob.rob_writes 246157217 # The number of ROB writes
system.cpu.timesIdled 1527 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30632 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 91249680 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249680 # Number of Instructions Simulated
system.cpu.cpi 0.744229 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.744229 # CPI: Total CPI of All Threads
system.cpu.ipc 1.343672 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.343672 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 502577811 # number of integer regfile reads
system.cpu.int_regfile_writes 122258624 # number of integer regfile writes
system.cpu.fp_regfile_reads 150 # number of floating regfile reads
system.cpu.fp_regfile_writes 373 # number of floating regfile writes
system.cpu.misc_regfile_reads 189862426 # number of misc regfile reads
system.cpu.misc_regfile_writes 11512 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 569.362196 # Cycle average of tags in use
system.cpu.icache.total_refs 14552080 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21463.244838 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 615.328313 # Cycle average of tags in use
system.cpu.icache.total_refs 15326008 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 726 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21110.203857 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 569.362196 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.278009 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 14552080 # number of ReadReq hits
system.cpu.icache.demand_hits 14552080 # number of demand (read+write) hits
system.cpu.icache.overall_hits 14552080 # number of overall hits
system.cpu.icache.ReadReq_misses 819 # number of ReadReq misses
system.cpu.icache.demand_misses 819 # number of demand (read+write) misses
system.cpu.icache.overall_misses 819 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 29501500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 29501500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 29501500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 14552899 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 14552899 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 14552899 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000056 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000056 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000056 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36021.367521 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36021.367521 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36021.367521 # average overall miss latency
system.cpu.icache.occ_blocks::0 615.328313 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.300453 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 15326008 # number of ReadReq hits
system.cpu.icache.demand_hits 15326008 # number of demand (read+write) hits
system.cpu.icache.overall_hits 15326008 # number of overall hits
system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses
system.cpu.icache.demand_misses 934 # number of demand (read+write) misses
system.cpu.icache.overall_misses 934 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32832500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32832500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32832500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 15326942 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 15326942 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 15326942 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35152.569593 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35152.569593 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35152.569593 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -352,142 +354,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 679 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 679 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 679 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 207 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 207 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 207 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 727 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 727 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 23405500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 23405500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 23405500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 25012500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25012500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25012500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34470.544919 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.089409 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943332 # number of replacements
system.cpu.dcache.tagsinuse 3485.983944 # Cycle average of tags in use
system.cpu.dcache.total_refs 29091101 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947428 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.705342 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 16303802000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3485.983944 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.851070 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24496946 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4581580 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6778 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 29078526 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 29078526 # number of overall hits
system.cpu.dcache.ReadReq_misses 1032002 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 153401 # number of WriteReq misses
system.cpu.dcache.replacements 943475 # number of replacements
system.cpu.dcache.tagsinuse 3548.617037 # Cycle average of tags in use
system.cpu.dcache.total_refs 29160006 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.773426 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12936791000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3548.617037 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.866362 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24566182 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4581344 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6728 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5751 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 29147526 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 29147526 # number of overall hits
system.cpu.dcache.ReadReq_misses 998551 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 153637 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1185403 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1185403 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5774861500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4244831902 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 10019693402 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 10019693402 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25528948 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses 1152188 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1152188 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5569139000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4384723397 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 9953862397 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 9953862397 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25564733 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 6785 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 30263929 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 30263929 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.040425 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.032397 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001032 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.039169 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.039169 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5595.785183 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27671.474775 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 8452.562885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8452.562885 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23297488 # number of cycles access was blocked
system.cpu.dcache.LoadLockedReq_accesses 6735 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5751 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 30299714 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 30299714 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.039060 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.032447 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001039 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.038026 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.038026 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5577.220392 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 28539.501533 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 8639.095701 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8639.095701 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23292477 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8138 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8136 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.802654 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.890487 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 942849 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 119201 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 118773 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 942916 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 85616 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 119000 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 237974 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 237974 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 912801 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 34628 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947429 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947429 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 204616 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 204616 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 912935 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 34637 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947572 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947572 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2307886000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1057417534 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3365303534 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3365303534 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2294888500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1057301024 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3352189524 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3352189524 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035756 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007313 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031306 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031306 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2528.356126 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30536.488795 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035711 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.007315 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031273 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031273 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2513.747967 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30525.190519 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 702 # number of replacements
system.cpu.l2cache.tagsinuse 8532.679465 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1625371 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15516 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 104.754511 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 747 # number of replacements
system.cpu.l2cache.tagsinuse 9154.979721 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1625557 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15570 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 104.403147 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 402.391901 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8130.287564 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.012280 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.248117 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 912439 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942849 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 20125 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 932564 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 932564 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1003 # number of ReadReq misses
system.cpu.l2cache.occ_blocks::0 397.893639 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8757.086082 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.012143 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.267245 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 912568 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942916 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 20133 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 932701 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 932701 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1056 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 15542 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 15542 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 34422500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 499217500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 533640000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 533640000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 913442 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 942849 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 15596 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 15596 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 36204000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 498983500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 535187500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 535187500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 913624 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 942916 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 34664 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948106 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948106 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001098 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_accesses 34673 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948297 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948297 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001156 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.419426 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016393 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016393 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34319.541376 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.439920 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34335.349376 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34335.349376 # average overall miss latency
system.cpu.l2cache.ReadExReq_miss_rate 0.419346 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34284.090909 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34317.984869 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34315.689920 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34315.689920 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -500,28 +502,28 @@ system.cpu.l2cache.writebacks 32 # nu
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 993 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 1046 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 15532 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 15532 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 15586 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 15586 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 30896000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451520000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 482416000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 482416000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 32557500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451767000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 484324500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 484324500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001145 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419426 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016382 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.016382 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.796576 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.781003 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419346 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016436 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.016436 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31125.717017 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31070.632737 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

7
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,14 +494,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

11
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 27 2011 02:06:34
gem5 started Jun 27 2011 02:06:35
gem5 executing on burrito
command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:15
gem5 started Jul 8 2011 19:53:01
gem5 executing on u200439-lin.austin.arm.com
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -19,8 +19,9 @@ simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
info: Increasing stack size by one page.
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 81353358500 because target called exit()
Exiting @ tick 72726971500 because target called exit()

746
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,249 +1,251 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.081353 # Number of seconds simulated
sim_ticks 81353358500 # Number of ticks simulated
sim_seconds 0.072727 # Number of seconds simulated
sim_ticks 72726971500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 205113 # Simulator instruction rate (inst/s)
host_tick_rate 59982451 # Simulator tick rate (ticks/s)
host_mem_usage 365084 # Number of bytes of host memory used
host_seconds 1356.29 # Real time elapsed on the host
host_inst_rate 68290 # Simulator instruction rate (inst/s)
host_tick_rate 17852786 # Simulator tick rate (ticks/s)
host_mem_usage 388028 # Number of bytes of host memory used
host_seconds 4073.70 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 162706718 # number of cpu cycles simulated
system.cpu.numCycles 145453944 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 43478033 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 43478033 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2457578 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 38773202 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 38222212 # Number of BTB hits
system.cpu.BPredUnit.lookups 39128056 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 39128056 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1285795 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 34407152 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 33889591 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 30836194 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 225319864 # Number of instructions fetch has processed
system.cpu.fetch.Branches 43478033 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 38222212 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 71185003 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2631314 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 30836194 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 310702 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 161537602 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.462501 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.241161 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 29588069 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 209386921 # Number of instructions fetch has processed
system.cpu.fetch.Branches 39128056 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33889591 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 65111619 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 11621082 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 39294448 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 28796477 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 238037 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 144111677 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.561755 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.288092 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 92871455 57.49% 57.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4826864 2.99% 60.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3003358 1.86% 62.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6248204 3.87% 66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7317456 4.53% 70.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5554189 3.44% 74.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 8050336 4.98% 79.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 6460332 4.00% 83.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 27205408 16.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 81461032 56.53% 56.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3926007 2.72% 59.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2843085 1.97% 61.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4618863 3.21% 64.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 6929331 4.81% 69.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5578828 3.87% 73.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7691595 5.34% 78.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4554481 3.16% 81.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 26508455 18.39% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 161537602 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.267217 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.384822 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 68100520 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 13645788 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 66107585 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1213655 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 12470054 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 390299102 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 12470054 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 72027632 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 3012062 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6445 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 63003531 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 11017878 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 382954672 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 129805 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 9724942 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 343637650 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 940851472 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 940850893 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 579 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 144111677 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.269006 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.439541 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 42334644 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 29762063 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 54385999 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 7511580 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10117391 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 364671921 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 10117391 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 49398641 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4827860 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6920 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 54606982 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 25153883 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 359809940 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 255433 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20983622 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 323256675 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 885580834 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 885576522 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4312 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 95293458 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 468 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 25876087 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 121481389 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 39633547 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 49140895 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 10609784 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 366915906 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 331721300 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 173691 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 88480232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 124860059 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 161537602 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.053524 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.792236 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 74912483 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 57974009 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 116578971 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 38504515 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 58165962 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 12487625 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 352625128 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 468 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 320274168 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 148663 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 74313113 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 111731092 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 144111677 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.222403 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.776502 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 44404154 27.49% 27.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 26523670 16.42% 43.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 27554042 17.06% 60.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 26722697 16.54% 77.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 19519009 12.08% 89.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 11121773 6.88% 96.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3849891 2.38% 98.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1601720 0.99% 99.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 240646 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 34558203 23.98% 23.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 19108427 13.26% 37.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 27976000 19.41% 56.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 28361257 19.68% 76.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 18381125 12.75% 89.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 10394236 7.21% 96.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2736273 1.90% 98.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2552596 1.77% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 43560 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 161537602 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 144111677 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 20533 1.17% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1580184 90.40% 91.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 147351 8.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 26349 1.28% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1847389 89.85% 91.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 182278 8.87% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 188283743 56.76% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 108606815 32.74% 89.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34814023 10.49% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 182479275 56.98% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 71 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 103720585 32.38% 89.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34057526 10.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 331721300 # Type of FU issued
system.cpu.iq.rate 2.038768 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1748068 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005270 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 826901753 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 455618803 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 324135014 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 333452564 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 43811715 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 320274168 # Type of FU issued
system.cpu.iq.rate 2.201894 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2056016 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006420 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 786864122 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 427256918 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 315787747 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 570 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2776 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 224 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 322313191 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 45099386 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 30702001 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 37170 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 238201 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 8193796 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 25799583 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7450 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 343486 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 7064764 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3292 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 14215 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 3530 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 14483 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 12470054 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 739464 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 101352 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 366916371 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 440258 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 121481389 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 39633547 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4279 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 66728 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 238201 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2276962 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 580211 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2857173 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 327057192 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 107334804 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4664108 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 10117391 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 811347 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 102359 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 352625596 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 16735 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 116578971 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 38504515 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 471 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 58728 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 343486 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1207902 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 198656 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1406558 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 317936612 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 103056411 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2337556 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 141680841 # number of memory reference insts executed
system.cpu.iew.exec_branches 32801587 # Number of branches executed
system.cpu.iew.exec_stores 34346037 # Number of stores executed
system.cpu.iew.exec_rate 2.010103 # Inst execution rate
system.cpu.iew.wb_sent 325338225 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 324135094 # cumulative count of insts written-back
system.cpu.iew.wb_producers 242967410 # num instructions producing a value
system.cpu.iew.wb_consumers 330454956 # num instructions consuming a value
system.cpu.iew.exec_refs 136663121 # number of memory reference insts executed
system.cpu.iew.exec_branches 31969004 # Number of branches executed
system.cpu.iew.exec_stores 33606710 # Number of stores executed
system.cpu.iew.exec_rate 2.185823 # Inst execution rate
system.cpu.iew.wb_sent 316589546 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 315787971 # cumulative count of insts written-back
system.cpu.iew.wb_producers 236874431 # num instructions producing a value
system.cpu.iew.wb_consumers 330545022 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.992143 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.735251 # average fanout of values written-back
system.cpu.iew.wb_rate 2.171051 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.716618 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 88730028 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 74441748 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2457587 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 149067548 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.866218 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.482505 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 1285812 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 133994286 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.076152 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.625929 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63468061 42.58% 42.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 26994600 18.11% 60.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19490262 13.07% 73.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13117480 8.80% 82.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4245570 2.85% 85.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3438248 2.31% 87.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3061065 2.05% 89.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1693051 1.14% 90.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13559211 9.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 52509499 39.19% 39.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 24995000 18.65% 57.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 17512781 13.07% 70.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12345203 9.21% 80.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3532539 2.64% 82.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3553321 2.65% 85.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3000350 2.24% 87.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1127257 0.84% 88.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15418336 11.51% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 149067548 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 133994286 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed
@ -253,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 13559211 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 15418336 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 502430884 # The number of ROB reads
system.cpu.rob.rob_writes 746329282 # The number of ROB writes
system.cpu.timesIdled 40054 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1169116 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 471210217 # The number of ROB reads
system.cpu.rob.rob_writes 715407828 # The number of ROB writes
system.cpu.timesIdled 40427 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1342267 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 0.584871 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.584871 # CPI: Total CPI of All Threads
system.cpu.ipc 1.709779 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.709779 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 572576247 # number of integer regfile reads
system.cpu.int_regfile_writes 291474006 # number of integer regfile writes
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 41 # number of floating regfile writes
system.cpu.misc_regfile_reads 211119046 # number of misc regfile reads
system.cpu.icache.replacements 60 # number of replacements
system.cpu.icache.tagsinuse 811.599985 # Cycle average of tags in use
system.cpu.icache.total_refs 30834919 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1009 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 30559.880079 # Average number of references to valid blocks.
system.cpu.cpi 0.522854 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.522854 # CPI: Total CPI of All Threads
system.cpu.ipc 1.912581 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.912581 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 557964995 # number of integer regfile reads
system.cpu.int_regfile_writes 283520691 # number of integer regfile writes
system.cpu.fp_regfile_reads 186 # number of floating regfile reads
system.cpu.fp_regfile_writes 177 # number of floating regfile writes
system.cpu.misc_regfile_reads 204022079 # number of misc regfile reads
system.cpu.icache.replacements 65 # number of replacements
system.cpu.icache.tagsinuse 828.162739 # Cycle average of tags in use
system.cpu.icache.total_refs 28795146 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 27983.620991 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 811.599985 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.396289 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 30834919 # number of ReadReq hits
system.cpu.icache.demand_hits 30834919 # number of demand (read+write) hits
system.cpu.icache.overall_hits 30834919 # number of overall hits
system.cpu.icache.ReadReq_misses 1275 # number of ReadReq misses
system.cpu.icache.demand_misses 1275 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1275 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 46105500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 46105500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 46105500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 30836194 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 30836194 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 30836194 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36161.176471 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36161.176471 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36161.176471 # average overall miss latency
system.cpu.icache.occ_blocks::0 828.162739 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.404376 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 28795146 # number of ReadReq hits
system.cpu.icache.demand_hits 28795146 # number of demand (read+write) hits
system.cpu.icache.overall_hits 28795146 # number of overall hits
system.cpu.icache.ReadReq_misses 1331 # number of ReadReq misses
system.cpu.icache.demand_misses 1331 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1331 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 47629500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 47629500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 47629500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 28796477 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 28796477 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 28796477 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35784.748310 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35784.748310 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35784.748310 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -305,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 265 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 265 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 265 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1010 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1010 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1010 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1030 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1030 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1030 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 35558500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 35558500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 35558500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 36247000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 36247000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 36247000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35206.435644 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.262136 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35191.262136 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35191.262136 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2073960 # number of replacements
system.cpu.dcache.tagsinuse 4075.298640 # Cycle average of tags in use
system.cpu.dcache.total_refs 92302253 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2078056 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 44.417597 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 30307591000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4075.298640 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994946 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 61099794 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 31202450 # number of WriteReq hits
system.cpu.dcache.demand_hits 92302244 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 92302244 # number of overall hits
system.cpu.dcache.ReadReq_misses 2219212 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 237301 # number of WriteReq misses
system.cpu.dcache.demand_misses 2456513 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2456513 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14180205500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4209484208 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18389689708 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18389689708 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 63319006 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 2072723 # number of replacements
system.cpu.dcache.tagsinuse 4076.250938 # Cycle average of tags in use
system.cpu.dcache.total_refs 86852791 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2076819 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 41.820106 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 24787226000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4076.250938 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995178 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 55654749 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 31198033 # number of WriteReq hits
system.cpu.dcache.demand_hits 86852782 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 86852782 # number of overall hits
system.cpu.dcache.ReadReq_misses 2230129 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 241718 # number of WriteReq misses
system.cpu.dcache.demand_misses 2471847 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2471847 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14270225000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4343136672 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18613361672 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18613361672 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 57884878 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 94758757 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 94758757 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.035048 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.007548 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.025924 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.025924 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 6389.748028 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17739.007455 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 7486.095009 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 7486.095009 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 290000 # number of cycles access was blocked
system.cpu.dcache.demand_accesses 89324629 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 89324629 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.038527 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.007688 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.027673 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.027673 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 6398.833879 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17967.783417 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 7530.143116 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 7530.143116 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 275500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 82 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 3411.764706 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3359.756098 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.writebacks 1448049 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 247154 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 131299 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 378453 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 378453 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1972058 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106002 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2078060 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2078060 # number of overall MSHR misses
system.cpu.dcache.writebacks 1446764 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 259013 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 136012 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 395025 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 395025 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1971116 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 105706 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2076822 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2076822 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 5532610500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1870145708 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7402756208 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 7402756208 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 5556895000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1872300172 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7429195172 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 7429195172 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.031145 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003372 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.021930 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.021930 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.500903 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17642.551159 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.034052 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003362 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.023250 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.023250 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2819.161835 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17712.335837 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3577.193988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3577.193988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 49058 # number of replacements
system.cpu.l2cache.tagsinuse 18069.203236 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3319340 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 43.073070 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 49102 # number of replacements
system.cpu.l2cache.tagsinuse 18807.221207 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3317038 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 77109 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 43.017521 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 6443.195976 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11626.007260 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.196631 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.354798 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1938598 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1448049 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 63959 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2002557 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2002557 # number of overall hits
system.cpu.l2cache.ReadReq_misses 34456 # number of ReadReq misses
system.cpu.l2cache.occ_blocks::0 6724.342247 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12082.878960 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.205211 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.368740 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1937588 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1446764 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 63709 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2001297 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2001297 # number of overall hits
system.cpu.l2cache.ReadReq_misses 34500 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 42055 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 76511 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 76511 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1178964000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1437688500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 2616652500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 2616652500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1973054 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1448049 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_misses 42053 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 76553 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 76553 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1179515000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1442921000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 2622436000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 2622436000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1972088 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1446764 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2079068 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2079068 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.017463 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_accesses 105762 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2077850 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2077850 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.017494 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.396693 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.036801 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.036801 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34216.508010 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34185.911307 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34199.690241 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34199.690241 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
system.cpu.l2cache.ReadExReq_miss_rate 0.397619 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.036842 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.036842 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34188.840580 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34311.963475 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34256.475906 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34256.475906 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2461.538462 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.writebacks 29183 # number of writebacks
system.cpu.l2cache.writebacks 29195 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 34456 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 34500 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 42055 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 76511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 76511 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 42053 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 76553 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 76553 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1068941000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1070219000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308447000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2377388000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2377388000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1309892500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2380111500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2380111500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017463 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017494 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396693 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.036801 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.036801 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.363130 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.397619 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.036842 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.036842 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.840580 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31112.757104 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31148.610087 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.028438 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.028438 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

7
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,14 +494,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

1
tests/long/20.parser/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 15:29:17
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 01:33:51
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -73,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 320953109000 because target called exit()
Exiting @ tick 302517583000 because target called exit()

818
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.320953 # Number of seconds simulated
sim_ticks 320953109000 # Number of ticks simulated
sim_seconds 0.302518 # Number of seconds simulated
sim_ticks 302517583000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 40042 # Simulator instruction rate (inst/s)
host_tick_rate 22415184 # Simulator tick rate (ticks/s)
host_mem_usage 260460 # Number of bytes of host memory used
host_seconds 14318.56 # Real time elapsed on the host
sim_insts 573342262 # Number of instructions simulated
host_inst_rate 48998 # Simulator instruction rate (inst/s)
host_tick_rate 25853029 # Simulator tick rate (ticks/s)
host_mem_usage 270368 # Number of bytes of host memory used
host_seconds 11701.44 # Real time elapsed on the host
sim_insts 573342442 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 641906219 # number of cpu cycles simulated
system.cpu.numCycles 605035167 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 223949599 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 179054613 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 19156129 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 184229626 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 147971030 # Number of BTB hits
system.cpu.BPredUnit.lookups 237948628 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 189643896 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18525471 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 200558633 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 165003293 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 11972868 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2532941 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 130565917 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 973113322 # Number of instructions fetch has processed
system.cpu.fetch.Branches 223949599 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 159943898 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 241546376 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 21862580 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 2406 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 130565917 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3998860 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 637850640 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.791502 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.743865 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 12776963 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2655849 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 165318082 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1053599180 # Number of instructions fetch has processed
system.cpu.fetch.Branches 237948628 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 177780256 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 271034430 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 85133152 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 100456864 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 3051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 121417 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 151931838 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4658920 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 600617430 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.083903 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.829133 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 396316059 62.13% 62.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 20357816 3.19% 65.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 35705192 5.60% 70.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 35959525 5.64% 76.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 37219035 5.84% 82.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 17602838 2.76% 85.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 18536216 2.91% 88.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 14275483 2.24% 90.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 61878476 9.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 329595233 54.88% 54.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24765043 4.12% 59.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 43080599 7.17% 66.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 41413060 6.90% 73.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 43530596 7.25% 80.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 16033141 2.67% 82.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 19523127 3.25% 86.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 16376620 2.73% 88.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 66300011 11.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 637850640 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.348882 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.515974 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 274650627 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 79437827 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 227463937 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 2944119 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 53354130 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 31952595 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 76091 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1091620209 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 217331 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 53354130 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 289506174 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 9893108 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 49317817 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 215240896 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 20538515 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1036732054 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 236 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6072390 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 9974912 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1156982067 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4582431546 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4582430193 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1353 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672201056 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 484781006 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2811540 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2811485 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 54423240 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 192516932 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 113728531 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 52019514 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 56045106 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 898220409 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4649392 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 742085900 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4028217 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 325034737 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 902951971 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 771526 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 637850640 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.163416 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.451606 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 600617430 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.393281 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.741385 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 185610198 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 93209648 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 249465251 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 8754516 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 63577817 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 34830541 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 109065 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1190327461 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 219958 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 63577817 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 203483134 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 12711979 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52382429 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 240021493 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 28440578 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1124560978 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 631 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 9752153 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 15058133 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1694 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1243412483 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4977837521 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4977834393 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672201344 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 571211134 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2776537 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2776073 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 72944066 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 210041655 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 130199534 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 69466757 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 73938650 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 989222584 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4552609 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 764881922 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1674381 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 418150078 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1236634953 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 674707 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 600617430 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.273493 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.529486 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 296239264 46.44% 46.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 133409185 20.92% 67.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 102098632 16.01% 83.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 53722534 8.42% 91.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 32322089 5.07% 96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 11168911 1.75% 98.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5441714 0.85% 99.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2057834 0.32% 99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1390477 0.22% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 269133638 44.81% 44.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 116546536 19.40% 64.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 93441125 15.56% 79.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 61796479 10.29% 90.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 37339082 6.22% 96.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 12656566 2.11% 98.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5425017 0.90% 99.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3357457 0.56% 99.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 921530 0.15% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 637850640 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 600617430 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 95830 1.04% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5443662 59.10% 60.15% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3670689 39.85% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 286700 3.30% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5674602 65.33% 68.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2725077 31.37% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 503818075 67.89% 67.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 366199 0.05% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 82 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 163695097 22.06% 90.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 74206444 10.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 522376749 68.30% 68.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 381409 0.05% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 80 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 170546214 22.30% 90.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 71577467 9.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 742085900 # Type of FU issued
system.cpu.iq.rate 1.156066 # Inst issue rate
system.cpu.iq.fu_busy_cnt 9210181 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012411 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2135260638 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1228450518 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 694522935 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 200 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes
system.cpu.iq.FU_type_0::total 764881922 # Type of FU issued
system.cpu.iq.rate 1.264194 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8686379 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011356 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2140741838 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1412472990 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 713443043 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 472 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 751295979 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5771553 # Number of loads that had data forwarded from stores
system.cpu.iq.int_alu_accesses 773568201 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 6159543 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 65743781 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 15629 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 596063 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 56124460 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 83268468 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 32978 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 628275 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 72595427 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 24980 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 27007 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 156 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 53354130 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2618576 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 142825 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 912051296 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 21556193 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 192516932 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 113728531 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2788498 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 84227 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 8711 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 596063 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 17931306 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6522754 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 24454060 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 711877956 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 154430876 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30207944 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 63577817 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2968769 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 160563 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1003649799 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12343350 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 210041655 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 130199534 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2755333 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 81778 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 10213 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 628275 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18784960 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6284429 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 25069389 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 737887948 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 162551175 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 26993974 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9181495 # number of nop insts executed
system.cpu.iew.exec_refs 222561224 # number of memory reference insts executed
system.cpu.iew.exec_branches 143781551 # Number of branches executed
system.cpu.iew.exec_stores 68130348 # Number of stores executed
system.cpu.iew.exec_rate 1.109006 # Inst execution rate
system.cpu.iew.wb_sent 704134955 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 694522951 # cumulative count of insts written-back
system.cpu.iew.wb_producers 388125156 # num instructions producing a value
system.cpu.iew.wb_consumers 688020690 # num instructions consuming a value
system.cpu.iew.exec_nop 9874606 # number of nop insts executed
system.cpu.iew.exec_refs 230127290 # number of memory reference insts executed
system.cpu.iew.exec_branches 150192140 # Number of branches executed
system.cpu.iew.exec_stores 67576115 # Number of stores executed
system.cpu.iew.exec_rate 1.219579 # Inst execution rate
system.cpu.iew.wb_sent 726019609 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 713443059 # cumulative count of insts written-back
system.cpu.iew.wb_producers 405782893 # num instructions producing a value
system.cpu.iew.wb_consumers 732949927 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.081970 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.564118 # average fanout of values written-back
system.cpu.iew.wb_rate 1.179176 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.553630 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 574686146 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 337368429 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3877866 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 21251956 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 584496511 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.983216 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.594536 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 574686326 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 428980158 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3877902 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 20816789 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 537039614 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.070100 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.725106 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 311654164 53.32% 53.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 150316632 25.72% 79.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 55227209 9.45% 88.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 24753339 4.23% 92.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 15848741 2.71% 95.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6546524 1.12% 96.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7691194 1.32% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2289333 0.39% 98.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10169375 1.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 281877385 52.49% 52.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 136335503 25.39% 77.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 48132590 8.96% 86.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 21242728 3.96% 90.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19119215 3.56% 94.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6739612 1.25% 95.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8597333 1.60% 97.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3363443 0.63% 97.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11631805 2.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 584496511 # Number of insts commited each cycle
system.cpu.commit.count 574686146 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 537039614 # Number of insts commited each cycle
system.cpu.commit.count 574686326 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 184377221 # Number of memory references committed
system.cpu.commit.loads 126773150 # Number of loads committed
system.cpu.commit.refs 184377293 # Number of memory references committed
system.cpu.commit.loads 126773186 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 120192335 # Number of branches committed
system.cpu.commit.branches 120192371 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 473702077 # Number of committed integer instructions.
system.cpu.commit.int_insts 473702221 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.bw_lim_events 10169375 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 11631805 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1486374573 # The number of ROB reads
system.cpu.rob.rob_writes 1877592139 # The number of ROB writes
system.cpu.timesIdled 93100 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 4055579 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 573342262 # Number of Instructions Simulated
system.cpu.committedInsts_total 573342262 # Number of Instructions Simulated
system.cpu.cpi 1.119586 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.119586 # CPI: Total CPI of All Threads
system.cpu.ipc 0.893187 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.893187 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3288876394 # number of integer regfile reads
system.cpu.int_regfile_writes 807633235 # number of integer regfile writes
system.cpu.rob.rob_reads 1529067155 # The number of ROB reads
system.cpu.rob.rob_writes 2071246317 # The number of ROB writes
system.cpu.timesIdled 105999 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 4417737 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 573342442 # Number of Instructions Simulated
system.cpu.committedInsts_total 573342442 # Number of Instructions Simulated
system.cpu.cpi 1.055277 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.055277 # CPI: Total CPI of All Threads
system.cpu.ipc 0.947618 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.947618 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3393544591 # number of integer regfile reads
system.cpu.int_regfile_writes 828738212 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 1209708694 # number of misc regfile reads
system.cpu.misc_regfile_writes 4464272 # number of misc regfile writes
system.cpu.icache.replacements 11767 # number of replacements
system.cpu.icache.tagsinuse 1053.166926 # Cycle average of tags in use
system.cpu.icache.total_refs 130550979 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 13545 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9638.315172 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 1294615924 # number of misc regfile reads
system.cpu.misc_regfile_writes 4464344 # number of misc regfile writes
system.cpu.icache.replacements 14868 # number of replacements
system.cpu.icache.tagsinuse 1047.725210 # Cycle average of tags in use
system.cpu.icache.total_refs 151911457 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 16514 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9198.949800 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1053.166926 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.514242 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 130550990 # number of ReadReq hits
system.cpu.icache.demand_hits 130550990 # number of demand (read+write) hits
system.cpu.icache.overall_hits 130550990 # number of overall hits
system.cpu.icache.ReadReq_misses 14927 # number of ReadReq misses
system.cpu.icache.demand_misses 14927 # number of demand (read+write) misses
system.cpu.icache.overall_misses 14927 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 215353500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 215353500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 215353500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 130565917 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 130565917 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 130565917 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 14427.111945 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 14427.111945 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 14427.111945 # average overall miss latency
system.cpu.icache.occ_blocks::0 1047.725210 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.511585 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 151911844 # number of ReadReq hits
system.cpu.icache.demand_hits 151911844 # number of demand (read+write) hits
system.cpu.icache.overall_hits 151911844 # number of overall hits
system.cpu.icache.ReadReq_misses 19994 # number of ReadReq misses
system.cpu.icache.demand_misses 19994 # number of demand (read+write) misses
system.cpu.icache.overall_misses 19994 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 277167000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 277167000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 277167000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 151931838 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 151931838 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 151931838 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000132 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000132 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000132 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 13862.508753 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 13862.508753 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 13862.508753 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -350,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 2 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1072 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1072 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1072 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 13855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 13855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 13855 # number of overall MSHR misses
system.cpu.icache.writebacks 29 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1670 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1670 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1670 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 18324 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 18324 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 18324 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 147833000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 147833000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 147833000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 184845500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 184845500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 184845500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000106 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000106 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000106 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000121 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000121 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000121 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10087.617332 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1189612 # number of replacements
system.cpu.dcache.tagsinuse 4060.806862 # Cycle average of tags in use
system.cpu.dcache.total_refs 200134121 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1193708 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.657518 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6159317000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4060.806862 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.991408 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 142442366 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 52854608 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2604415 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 2232135 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 195296974 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 195296974 # number of overall hits
system.cpu.dcache.ReadReq_misses 1102250 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1384698 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2486948 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2486948 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 11846428500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 20406027500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 313000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 32252456000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 32252456000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 143544616 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 1208536 # number of replacements
system.cpu.dcache.tagsinuse 4059.803539 # Cycle average of tags in use
system.cpu.dcache.total_refs 207709608 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1212632 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 171.288246 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5997963000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4059.803539 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.991163 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 150052810 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 52876507 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2544785 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 2232171 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 202929317 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 202929317 # number of overall hits
system.cpu.dcache.ReadReq_misses 1147618 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1362799 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 51 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2510417 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2510417 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 12147896500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 20751705500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 582000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 32899602000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 32899602000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 151200428 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 2604451 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 2232135 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 197783922 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 197783922 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.007679 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.025529 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.012574 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.012574 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 8694.444444 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 12968.689333 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 12968.689333 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 2544836 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 2232171 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 205439734 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 205439734 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.007590 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.025126 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000020 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.012220 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.012220 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10585.313667 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 15227.267924 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 11411.764706 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 13105.233911 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 13105.233911 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 98500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 20 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 4925 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1065401 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 244002 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1048961 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1292963 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1292963 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 858248 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 335737 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1193985 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1193985 # number of overall MSHR misses
system.cpu.dcache.writebacks 1079332 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 271534 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1024501 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 51 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1296035 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1296035 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 876084 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 338298 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1214382 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1214382 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 6157877500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4228090500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 10385968000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 10385968000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 6267336500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4269582000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 10536918500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 10536918500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005979 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006190 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.006037 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.006037 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7174.939528 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005794 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005911 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005911 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.807740 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12620.772219 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 214616 # number of replacements
system.cpu.l2cache.tagsinuse 21258.843371 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1538764 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 234845 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.552254 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 231195370000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7817.837138 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13441.006233 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.238581 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.410187 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 742273 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1065403 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 160 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 231247 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 973520 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 973520 # number of overall hits
system.cpu.l2cache.ReadReq_misses 129152 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 104568 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 233720 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 233720 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 4416243000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 547000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3581590000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 7997833000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 7997833000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 871425 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1065403 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 272 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 335815 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1207240 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1207240 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.148208 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.411765 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.311386 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.193599 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.193599 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4883.928571 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34219.720178 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34219.720178 # average overall miss latency
system.cpu.l2cache.replacements 217502 # number of replacements
system.cpu.l2cache.tagsinuse 21268.774974 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1567233 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 237739 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.592242 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7619.579259 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13649.195715 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.232531 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.416540 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 761070 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1079361 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1189 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 231140 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 992210 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 992210 # number of overall hits
system.cpu.l2cache.ReadReq_misses 130897 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 521 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 105763 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 236660 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 236660 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 4476495000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 5061500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3624223500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 8100718500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 8100718500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 891967 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1079361 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 1710 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 336903 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1228870 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1228870 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.146751 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.304678 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.313927 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.192583 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.192583 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34198.606538 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 9714.971209 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.404480 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34229.352235 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34229.352235 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -498,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 169760 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 129137 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 104568 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 233705 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 233705 # number of overall MSHR misses
system.cpu.l2cache.writebacks 170191 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 130875 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 521 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 105763 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 236638 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 236638 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4006675000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3473000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3242222500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 7248897500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 7248897500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 4061689500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 16157000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3279601500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 7341291000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 7341291000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148191 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.411765 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311386 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.193586 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.193586 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146726 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.304678 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313927 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.192566 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.192566 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.876791 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31011.516315 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.968165 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

7
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,14 +494,14 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

12
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 27 2011 02:06:34
gem5 started Jun 27 2011 02:06:35
gem5 executing on burrito
command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:15
gem5 started Jul 8 2011 20:37:07
gem5 executing on u200439-lin.austin.arm.com
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -21,6 +21,7 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
@ -32,7 +33,6 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@ -77,4 +77,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 584042944000 because target called exit()
Exiting @ tick 589091030500 because target called exit()

760
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,249 +1,252 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.584043 # Number of seconds simulated
sim_ticks 584042944000 # Number of ticks simulated
sim_seconds 0.589091 # Number of seconds simulated
sim_ticks 589091030500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 221280 # Simulator instruction rate (inst/s)
host_tick_rate 84524523 # Simulator tick rate (ticks/s)
host_mem_usage 274300 # Number of bytes of host memory used
host_seconds 6909.75 # Real time elapsed on the host
host_inst_rate 58676 # Simulator instruction rate (inst/s)
host_tick_rate 22606879 # Simulator tick rate (ticks/s)
host_mem_usage 302632 # Number of bytes of host memory used
host_seconds 26058.04 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1168085889 # number of cpu cycles simulated
system.cpu.numCycles 1178182062 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 253398223 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 253398223 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16660589 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 238496117 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 219579135 # Number of BTB hits
system.cpu.BPredUnit.lookups 273761240 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 273761240 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16674451 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 263536261 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 242767527 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 188493207 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1362528555 # Number of instructions fetch has processed
system.cpu.fetch.Branches 253398223 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 219579135 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 442066407 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 19282041 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 77357 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 188493207 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3791136 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1143941897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.224075 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.207990 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 225401733 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1479491232 # Number of instructions fetch has processed
system.cpu.fetch.Branches 273761240 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 242767527 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 481293494 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 151906633 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 310358472 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 81567 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 542630 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 210837280 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 3978525 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1150020801 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.401549 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.263992 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 706029092 61.72% 61.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32745689 2.86% 64.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38225778 3.34% 67.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34592742 3.02% 70.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 20873132 1.82% 72.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 39592075 3.46% 76.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44500061 3.89% 80.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36282476 3.17% 83.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 191100852 16.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 673309594 58.55% 58.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 35910144 3.12% 61.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 42110719 3.66% 65.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 37429485 3.25% 68.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 23065552 2.01% 70.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 42484626 3.69% 74.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 50557962 4.40% 78.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 39843815 3.46% 82.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 205308904 17.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1143941897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.216935 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.166463 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 421359771 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 186435003 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 405946069 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21628019 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 108573035 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2494021022 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 108573035 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 460289272 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50662445 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15855 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 387005567 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 137395723 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2428811074 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 8205 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 53921903 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 70830357 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2267152647 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5703018907 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5703000611 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 18296 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 1150020801 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.232359 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.255741 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 295424105 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 258223017 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 403450338 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 60580436 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 132342905 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2687346589 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 53 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 132342905 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 338937810 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 65386701 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 28780 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 418304086 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 195020519 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2631430094 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 26828 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 78975062 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 100019003 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2450674662 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6174029113 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6173774259 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 254854 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 839853620 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2555 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2515 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 298765601 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 586920489 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222789217 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 352764399 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 138805015 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2327145816 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 9782 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1903699652 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 745209 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 795395556 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1355118976 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 9229 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1143941897 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.664158 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.649963 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 1023375635 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3023 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3014 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 414859898 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 629524584 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 242192886 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 419436220 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 160455315 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2509631726 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 14401 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1981481069 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1143998 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 979086329 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1684803071 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13848 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1150020801 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.722996 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.682483 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 364171044 31.83% 31.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 265972258 23.25% 55.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 191418370 16.73% 71.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 151056709 13.20% 85.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 94863070 8.29% 93.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 46725885 4.08% 97.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 20369113 1.78% 99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 8499440 0.74% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 866008 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 371533820 32.31% 32.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 234816386 20.42% 52.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 195375199 16.99% 69.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 160336940 13.94% 83.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 104083103 9.05% 92.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 52438845 4.56% 97.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 24322326 2.11% 99.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6470584 0.56% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 643598 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1143941897 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1150020801 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1290505 11.43% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7282962 64.50% 75.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2717631 24.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2000225 14.58% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9217501 67.18% 81.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2502434 18.24% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2277009 0.12% 0.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1273302138 66.89% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 457949055 24.06% 91.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170171450 8.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::No_OpClass 2582215 0.13% 0.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1339393426 67.60% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 465725544 23.50% 91.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 173779884 8.77% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1903699652 # Type of FU issued
system.cpu.iq.rate 1.629760 # Inst issue rate
system.cpu.iq.fu_busy_cnt 11291098 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005931 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4963377358 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3125135181 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1859937909 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 150 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 7364 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 35 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1912713667 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 121955986 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 1981481069 # Type of FU issued
system.cpu.iq.rate 1.681812 # Inst issue rate
system.cpu.iq.fu_busy_cnt 13720160 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006924 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5127845391 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3491473273 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1932208550 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1706 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 91974 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1992618257 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 757 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 130432763 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 202818329 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 145118 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2595412 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 73631154 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 245422424 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 85551 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2844514 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 93035934 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1267 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 2121 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 108573035 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9607775 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1579187 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2327155598 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2263253 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 586920489 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222791339 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 9782 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1056355 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 44992 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2595412 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15396927 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2702189 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18099116 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1873386406 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 447925301 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 30313246 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 132342905 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 11594389 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3099842 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2509646127 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 554822 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 629524584 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 242196119 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 14401 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2636094 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 28755 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2844514 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15750968 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2390539 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18141507 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1946393180 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 456989279 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 35087889 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 613922207 # number of memory reference insts executed
system.cpu.iew.exec_branches 173516320 # Number of branches executed
system.cpu.iew.exec_stores 165996906 # Number of stores executed
system.cpu.iew.exec_rate 1.603809 # Inst execution rate
system.cpu.iew.wb_sent 1866315288 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1859937944 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1434930162 # num instructions producing a value
system.cpu.iew.wb_consumers 2113232937 # num instructions consuming a value
system.cpu.iew.exec_refs 625199049 # number of memory reference insts executed
system.cpu.iew.exec_branches 178040376 # Number of branches executed
system.cpu.iew.exec_stores 168209770 # Number of stores executed
system.cpu.iew.exec_rate 1.652031 # Inst execution rate
system.cpu.iew.wb_sent 1940174748 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1932208590 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1494691214 # num instructions producing a value
system.cpu.iew.wb_consumers 2239401377 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.592296 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.679021 # average fanout of values written-back
system.cpu.iew.wb_rate 1.639992 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.667451 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 798170363 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 980665483 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16691926 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1035368862 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.476758 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.996244 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 16734282 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1017677896 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.502429 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.032638 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 433054636 41.83% 41.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 271974415 26.27% 68.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 102879563 9.94% 78.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 102354239 9.89% 87.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37870792 3.66% 91.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24412946 2.36% 93.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10660961 1.03% 94.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10611646 1.02% 95.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 41549664 4.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 426781992 41.94% 41.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 262838337 25.83% 67.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 100636861 9.89% 77.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 98086664 9.64% 87.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37562129 3.69% 90.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27349053 2.69% 93.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 11151176 1.10% 94.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9457604 0.93% 95.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 43814080 4.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1035368862 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1017677896 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed
@ -253,48 +256,48 @@ system.cpu.commit.branches 149758588 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 41549664 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 43814080 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3320978317 # The number of ROB reads
system.cpu.rob.rob_writes 4762953278 # The number of ROB writes
system.cpu.timesIdled 612203 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24143992 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 3483518055 # The number of ROB reads
system.cpu.rob.rob_writes 5151797430 # The number of ROB writes
system.cpu.timesIdled 664618 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 28161261 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.763960 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.763960 # CPI: Total CPI of All Threads
system.cpu.ipc 1.308969 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.308969 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3113988878 # number of integer regfile reads
system.cpu.int_regfile_writes 1735338379 # number of integer regfile writes
system.cpu.fp_regfile_reads 35 # number of floating regfile reads
system.cpu.misc_regfile_reads 1026178630 # number of misc regfile reads
system.cpu.icache.replacements 9690 # number of replacements
system.cpu.icache.tagsinuse 963.166837 # Cycle average of tags in use
system.cpu.icache.total_refs 188230465 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11136 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 16902.879400 # Average number of references to valid blocks.
system.cpu.cpi 0.770563 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.770563 # CPI: Total CPI of All Threads
system.cpu.ipc 1.297753 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.297753 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3171957706 # number of integer regfile reads
system.cpu.int_regfile_writes 1803005697 # number of integer regfile writes
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
system.cpu.misc_regfile_reads 1059979955 # number of misc regfile reads
system.cpu.icache.replacements 11725 # number of replacements
system.cpu.icache.tagsinuse 992.230576 # Cycle average of tags in use
system.cpu.icache.total_refs 210562203 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 13217 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 15931.164636 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 963.166837 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.470296 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 188237743 # number of ReadReq hits
system.cpu.icache.demand_hits 188237743 # number of demand (read+write) hits
system.cpu.icache.overall_hits 188237743 # number of overall hits
system.cpu.icache.ReadReq_misses 255464 # number of ReadReq misses
system.cpu.icache.demand_misses 255464 # number of demand (read+write) misses
system.cpu.icache.overall_misses 255464 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 1671443500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 1671443500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 1671443500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 188493207 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 188493207 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 188493207 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001355 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001355 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001355 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 6542.775107 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 6542.775107 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 6542.775107 # average overall miss latency
system.cpu.icache.occ_blocks::0 992.230576 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.484488 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 210569051 # number of ReadReq hits
system.cpu.icache.demand_hits 210569051 # number of demand (read+write) hits
system.cpu.icache.overall_hits 210569051 # number of overall hits
system.cpu.icache.ReadReq_misses 268229 # number of ReadReq misses
system.cpu.icache.demand_misses 268229 # number of demand (read+write) misses
system.cpu.icache.overall_misses 268229 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 1801320500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 1801320500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 1801320500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 210837280 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 210837280 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 210837280 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001272 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001272 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001272 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 6715.606814 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 6715.606814 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 6715.606814 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -303,60 +306,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 7 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 254036 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 254036 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 254036 # number of overall MSHR misses
system.cpu.icache.writebacks 8 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1476 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1476 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1476 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 266753 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 266753 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 266753 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 873542000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 873542000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 873542000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 963323500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 963323500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 963323500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001348 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.001348 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.001348 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3438.654364 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.001265 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.001265 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.001265 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3611.293969 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2526737 # number of replacements
system.cpu.dcache.tagsinuse 4088.695382 # Cycle average of tags in use
system.cpu.dcache.total_refs 470726270 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2530833 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 185.996575 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2167120000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4088.695382 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998217 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 321866059 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 147543837 # number of WriteReq hits
system.cpu.dcache.demand_hits 469409896 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 469409896 # number of overall hits
system.cpu.dcache.ReadReq_misses 3006715 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1616364 # number of WriteReq misses
system.cpu.dcache.demand_misses 4623079 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4623079 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 47957140000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 38289086000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 86246226000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 86246226000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 324872774 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 2529482 # number of replacements
system.cpu.dcache.tagsinuse 4088.837997 # Cycle average of tags in use
system.cpu.dcache.total_refs 471282230 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2533578 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 186.014494 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2156497000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4088.837997 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998251 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 322424417 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 147507556 # number of WriteReq hits
system.cpu.dcache.demand_hits 469931973 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 469931973 # number of overall hits
system.cpu.dcache.ReadReq_misses 3022528 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1652645 # number of WriteReq misses
system.cpu.dcache.demand_misses 4675173 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4675173 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 48854800500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 39692092500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 88546893000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 88546893000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 325446945 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 474032975 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 474032975 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.009255 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010836 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.009753 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.009753 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 15950.011890 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 23688.405582 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18655.581270 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18655.581270 # average overall miss latency
system.cpu.dcache.demand_accesses 474607146 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 474607146 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.009287 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.011080 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.009851 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.009851 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16163.555970 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24017.313156 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18939.810997 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18939.810997 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -365,75 +368,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 2229867 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1247117 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 605322 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1852439 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1852439 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1759598 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1011042 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2770640 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2770640 # number of overall MSHR misses
system.cpu.dcache.writebacks 2230911 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1260687 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 634109 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1894796 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1894796 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1761841 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1018536 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2780377 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2780377 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14841801000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 18214921000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 33056722000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 33056722000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 14865117000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 18574591000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 33439708000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 33439708000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005416 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006778 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005845 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005845 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8434.768055 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18015.988455 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005414 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006828 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005858 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005858 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8437.263635 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18236.558158 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 574893 # number of replacements
system.cpu.l2cache.tagsinuse 21475.591540 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3187531 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 594020 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.366033 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 306954721000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7759.826991 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13715.764549 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236811 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.418572 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1427752 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 2229874 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1226 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 528421 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1956173 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1956173 # number of overall hits
system.cpu.l2cache.ReadReq_misses 338145 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 241551 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 247520 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 585665 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 585665 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11551149000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 10207000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 8480925000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 20032074000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 20032074000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1765897 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2229874 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 242777 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 775941 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2541838 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2541838 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.191486 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.994950 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.318993 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.230410 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.230410 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34160.342457 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.256087 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.594861 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34203.980091 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34203.980091 # average overall miss latency
system.cpu.l2cache.replacements 576328 # number of replacements
system.cpu.l2cache.tagsinuse 21485.488039 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3192646 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 595469 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.361565 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 312361641000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7744.786330 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13740.701709 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.236352 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.419333 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1431746 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 2230919 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1301 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 527734 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1959480 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1959480 # number of overall hits
system.cpu.l2cache.ReadReq_misses 339175 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 252088 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 248002 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 587177 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 587177 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11584401000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 11543000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 8495722000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 20080123000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 20080123000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1770921 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2230919 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 253389 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 775736 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2546657 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2546657 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.191525 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.994866 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.319699 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.230568 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.230568 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34154.642883 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 45.789566 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.667285 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34197.734244 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34197.734244 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -442,32 +445,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 412030 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 1 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 338144 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 241551 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 247520 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 585664 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 585664 # number of overall MSHR misses
system.cpu.l2cache.writebacks 412300 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 339175 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 252088 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 248002 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 587177 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 587177 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10484231000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7489077000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673754000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18157985000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18157985000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 10515780500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7815593500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7689085500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18204866000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18204866000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191486 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994950 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318993 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.230410 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.230410 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.225584 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.123353 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.561409 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191525 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994866 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319699 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.230568 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.230568 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.996462 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.433325 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.126983 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -199,12 +200,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/y/ksewell/cpu2000/binaries/alpha/tru64/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

10
tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,14 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 09:22:03
gem5 started Jun 19 2011 12:35:06
gem5 executing on zooks
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:09:26
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 140230347500 because target called exit()
Exiting @ tick 139995113500 because target called exit()

310
tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,12 +1,12 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.140230 # Number of seconds simulated
sim_ticks 140230347500 # Number of ticks simulated
sim_seconds 0.139995 # Number of seconds simulated
sim_ticks 139995113500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 92522 # Simulator instruction rate (inst/s)
host_tick_rate 32544608 # Simulator tick rate (ticks/s)
host_mem_usage 159896 # Number of bytes of host memory used
host_seconds 4308.87 # Real time elapsed on the host
host_inst_rate 56567 # Simulator instruction rate (inst/s)
host_tick_rate 19864025 # Simulator tick rate (ticks/s)
host_mem_usage 252292 # Number of bytes of host memory used
host_seconds 7047.67 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 168277058 # DT
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277114 # DTB accesses
system.cpu.itb.fetch_hits 48911022 # ITB hits
system.cpu.itb.fetch_misses 44512 # ITB misses
system.cpu.itb.fetch_hits 48859849 # ITB hits
system.cpu.itb.fetch_misses 44521 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 48955534 # ITB accesses
system.cpu.itb.fetch_accesses 48904370 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 280460696 # number of cpu cycles simulated
system.cpu.numCycles 279990228 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 280031759 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 6816 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13555694 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 266905002 # Number of cycles cpu stages are processed.
system.cpu.activity 95.166633 # Percentage of cycles cpu is active
system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed.
system.cpu.activity 95.173539 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -61,79 +61,79 @@ system.cpu.comFloats 50439198 # Nu
system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total)
system.cpu.cpi 0.703500 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.703500 # CPI: Total CPI of All Threads
system.cpu.ipc 1.421463 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads
system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.421463 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 53559776 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30675983 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 15431294 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 36114910 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15774675 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007515 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 43.679120 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29804615 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 23755161 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280315566 # Number of Reads from Int. Register File
system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 439651425 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119618904 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 219815385 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100663476 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168393095 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14667100 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 763535 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 15430635 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 29156916 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 34.607496 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205476801 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168369236 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 78228073 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 202232623 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.107296 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 107968598 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 172492098 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.503127 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 103201194 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177259502 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.202974 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 181732278 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98728418 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.202230 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 90865904 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189594792 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.601199 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1967 # number of replacements
system.cpu.icache.tagsinuse 1829.231960 # Cycle average of tags in use
system.cpu.icache.total_refs 48906646 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3894 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12559.487930 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1970 # number of replacements
system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use
system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1829.231960 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.893180 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 48906646 # number of ReadReq hits
system.cpu.icache.demand_hits 48906646 # number of demand (read+write) hits
system.cpu.icache.overall_hits 48906646 # number of overall hits
system.cpu.icache.ReadReq_misses 4375 # number of ReadReq misses
system.cpu.icache.demand_misses 4375 # number of demand (read+write) misses
system.cpu.icache.overall_misses 4375 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 214226000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 214226000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 214226000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 48911021 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 48911021 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 48911021 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 48965.942857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 48965.942857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 48965.942857 # average overall miss latency
system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits
system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits
system.cpu.icache.overall_hits 48855472 # number of overall hits
system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses
system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses
system.cpu.icache.overall_misses 4376 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -143,35 +143,35 @@ system.cpu.icache.avg_blocked_cycles::no_targets 45000
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 481 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 481 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 3894 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 3894 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 3894 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 185204000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 185204000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 185204000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 47561.376477 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3284.909965 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3284.909965 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.801980 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits
system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits
@ -180,10 +180,10 @@ system.cpu.dcache.ReadReq_misses 1224 # nu
system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses
system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 13259 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 63822000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 626725500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 690547500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 690547500 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses
@ -192,16 +192,16 @@ system.cpu.dcache.ReadReq_miss_rate 0.000013 # mi
system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 52142.156863 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 52075.238887 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 52081.416396 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 52081.416396 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82468000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44625.541126 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 649 # number of writebacks
@ -214,59 +214,59 @@ system.cpu.dcache.WriteReq_mshr_misses 3202 # nu
system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 46179500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 169543500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 215723000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 215723000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48610 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52949.250468 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 13 # number of replacements
system.cpu.l2cache.tagsinuse 3899.405791 # Cycle average of tags in use
system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4719 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.154058 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use
system.cpu.l2cache.total_refs 729 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3528.869361 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 370.536429 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.107693 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 656 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 716 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 716 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4185 # number of ReadReq misses
system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 718 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7330 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7330 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 219146000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 164975000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 384121000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 384121000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 4841 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7331 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 8046 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8046 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.864491 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.911012 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.911012 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52364.635603 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52456.279809 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52403.956344 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52403.956344 # average overall miss latency
system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4185 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 7330 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7330 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 168185500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 126767000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 294952500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 294952500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864491 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.911012 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.911012 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.694146 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40307.472178 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,11 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instrutions is Alpha do not do anything
For more information see: http://www.m5sim.org/warn/3e0eccba
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
@ -53,5 +49,4 @@ Writing to chair.cook.ppm
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
hack: be nice to actually delete the event here

20
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,18 +1,14 @@
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 12:29:56
M5 started Apr 21 2011 13:02:51
M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:09:26
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.100000
Exiting @ tick 113012733500 because target called exit()
OO-style eon Time= 0.083333
Exiting @ tick 90884909500 because target called exit()

974
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,504 +1,506 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 199356 # Simulator instruction rate (inst/s)
host_mem_usage 214136 # Number of bytes of host memory used
host_seconds 1883.94 # Real time elapsed on the host
host_tick_rate 59987309 # Simulator tick rate (ticks/s)
sim_seconds 0.090885 # Number of seconds simulated
sim_ticks 90884909500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574812 # Number of instructions simulated
sim_seconds 0.113013 # Number of seconds simulated
sim_ticks 113012733500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 30270394 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 39807126 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 1409 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5223677 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted
system.cpu.commit.branches 44587533 # Number of branches committed
system.cpu.commit.bw_lim_events 16035403 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 216073988 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.845037 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 216073988 # Number of insts commited each cycle
system.cpu.commit.count 398664587 # Number of instructions committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
system.cpu.commit.int_insts 316365844 # Number of committed integer instructions.
system.cpu.commit.loads 94754489 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 168275218 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 375574812 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated
system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.601812 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses 93199835 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33131.956912 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31878.172589 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 93198164 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 55363500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1671 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 686 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 31400000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30218.957186 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.663747 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 73502931 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 537837000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 17798 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 14601 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 113412500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 3197 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 39861.573171 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 166720564 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30468.976321 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency
system.cpu.dcache.demand_hits 166701095 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 593200500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
system.cpu.dcache.demand_misses 19469 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 15287 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 144812500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.803985 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 166701095 # number of overall hits
system.cpu.dcache.overall_miss_latency 593200500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
system.cpu.dcache.overall_misses 19469 # number of overall misses
system.cpu.dcache.overall_mshr_hits 15287 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 144812500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 786 # number of replacements
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 3293.121210 # Cycle average of tags in use
system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 664 # number of writebacks
system.cpu.decode.BlockedCycles 5613634 # Number of cycles decode is blocked
system.cpu.decode.BranchMispred 4438 # Number of times decode detected a branch misprediction
system.cpu.decode.BranchResolved 10679460 # Number of times decode resolved a branch
system.cpu.decode.DecodedInsts 490538381 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 118863884 # Number of cycles decode is idle
system.cpu.decode.RunCycles 90994213 # Number of cycles decode is running
system.cpu.decode.SquashCycles 9813191 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 13275 # Number of squashed instructions handled by decode
system.cpu.decode.UnblockCycles 602257 # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses 183645342 # DTB accesses
system.cpu.dtb.data_acv 48603 # DTB access violations
system.cpu.dtb.data_hits 183566296 # DTB hits
system.cpu.dtb.data_misses 79046 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
host_inst_rate 96810 # Simulator instruction rate (inst/s)
host_tick_rate 23426991 # Simulator tick rate (ticks/s)
host_mem_usage 252820 # Number of bytes of host memory used
host_seconds 3879.50 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 103678274 # DTB read accesses
system.cpu.dtb.read_acv 48603 # DTB read access violations
system.cpu.dtb.read_hits 103600815 # DTB read hits
system.cpu.dtb.read_misses 77459 # DTB read misses
system.cpu.dtb.write_accesses 79967068 # DTB write accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 105630800 # DTB read hits
system.cpu.dtb.read_misses 100510 # DTB read misses
system.cpu.dtb.read_acv 48612 # DTB read access violations
system.cpu.dtb.read_accesses 105731310 # DTB read accesses
system.cpu.dtb.write_hits 79936147 # DTB write hits
system.cpu.dtb.write_misses 1547 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_hits 79965481 # DTB write hits
system.cpu.dtb.write_misses 1587 # DTB write misses
system.cpu.fetch.Branches 56786170 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 58423687 # Number of cache lines fetched
system.cpu.fetch.Cycles 93710532 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1318185 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 502037270 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 5229387 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.251238 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 58423687 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 41692920 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 2.221154 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 225887179 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.222513 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.113255 # Number of instructions fetched each cycle (Total)
system.cpu.dtb.write_accesses 79937694 # DTB write accesses
system.cpu.dtb.data_hits 185566947 # DTB hits
system.cpu.dtb.data_misses 102057 # DTB misses
system.cpu.dtb.data_acv 48612 # DTB access violations
system.cpu.dtb.data_accesses 185669004 # DTB accesses
system.cpu.itb.fetch_hits 58326026 # ITB hits
system.cpu.itb.fetch_misses 337 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 58326363 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 181769821 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 57225452 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 33446848 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3610875 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 40879451 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 32187006 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 10725194 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 60337386 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 506200677 # Number of instructions fetch has processed
system.cpu.fetch.Branches 57225452 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 42912200 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 94142068 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 13173843 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 17624322 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 7572 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 58326026 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1118192 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 181648006 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.786712 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.242035 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 132176647 58.51% 58.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9507177 4.21% 62.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 8947595 3.96% 66.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6461834 2.86% 69.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 13588400 6.02% 75.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 8169586 3.62% 79.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6674990 2.96% 82.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2889669 1.28% 83.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 37471281 16.59% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 87505938 48.17% 48.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 8084169 4.45% 52.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 9812284 5.40% 58.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6556715 3.61% 61.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 13799395 7.60% 69.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 9400037 5.17% 74.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5907170 3.25% 77.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3477374 1.91% 79.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 37104924 20.43% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 225887179 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 159270832 # number of floating regfile reads
system.cpu.fp_regfile_writes 104392422 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 58423687 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32309.424084 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30830.816483 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 58418912 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 154277500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000082 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 4775 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 868 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120456000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3907 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 14952.370617 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 58423687 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32309.424084 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency
system.cpu.icache.demand_hits 58418912 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 154277500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000082 # miss rate for demand accesses
system.cpu.icache.demand_misses 4775 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 868 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120456000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3907 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.890605 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 58418912 # number of overall hits
system.cpu.icache.overall_miss_latency 154277500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000082 # miss rate for overall accesses
system.cpu.icache.overall_misses 4775 # number of overall misses
system.cpu.icache.overall_mshr_hits 868 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120456000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3907 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1986 # number of replacements
system.cpu.icache.sampled_refs 3907 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1823.959859 # Cycle average of tags in use
system.cpu.icache.total_refs 58418912 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 48687009 # Number of branches executed
system.cpu.iew.exec_nop 26082950 # number of nop insts executed
system.cpu.iew.exec_rate 1.805331 # Inst execution rate
system.cpu.iew.exec_refs 183693980 # number of memory reference insts executed
system.cpu.iew.exec_stores 79967080 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 6012421 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 86376940 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 454930236 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 103726900 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 9802128 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 408050842 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 63 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 10208559 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 5629 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 192417 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 12228157 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 12856211 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 258989364 # num instructions consuming a value
system.cpu.iew.wb_count 404042671 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.726642 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 188192474 # num instructions producing a value
system.cpu.iew.wb_rate 1.787598 # insts written-back per cycle
system.cpu.iew.wb_sent 405020447 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 406883956 # number of integer regfile reads
system.cpu.int_regfile_writes 173490032 # number of integer regfile writes
system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 417852970 # Type of FU issued
system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 10358398 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 283872417 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 428847047 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 417852970 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 47599271 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 225887179 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.849830 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 181648006 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.314824 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.784844 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 66587043 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 13622871 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 88021771 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3884112 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9532209 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 10337474 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4322 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 494122650 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 12073 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9532209 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 71008708 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4690007 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 394366 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 87374252 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 8648464 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 480990212 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 42769 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 7153610 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 312500874 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 630714726 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 332574792 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 298139934 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 52968555 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 38325 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 292 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 23912108 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 111095455 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 85873017 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 14526105 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8463039 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 435543273 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 257 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 420425800 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1773859 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 58536245 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 32877731 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 181648006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.314508 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.994579 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 45216412 24.89% 24.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 30232996 16.64% 41.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 28617209 15.75% 57.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 25676408 14.14% 71.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 23156698 12.75% 84.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15699012 8.64% 92.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7807681 4.30% 97.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3971496 2.19% 99.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1270094 0.70% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 225887179 # Number of insts issued each cycle
system.cpu.iq.rate 1.848699 # Inst issue rate
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.fetch_accesses 58423991 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_hits 58423687 # ITB hits
system.cpu.itb.fetch_misses 304 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 3201 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.558495 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.559133 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 64 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 108554500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.980006 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98685500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980006 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34349.065531 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31163.354625 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 145193500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 131727500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 664 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 664 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 8089 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34457.903313 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 725 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 253748000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.910372 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 230413000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.910372 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.108576 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011590 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 725 # number of overall hits
system.cpu.l2cache.overall_miss_latency 253748000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.910372 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 7364 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 230413000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.910372 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 14 # number of replacements
system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 3937.604676 # Cycle average of tags in use
system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 7819910 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6085624 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 106982646 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 86376940 # Number of stores inserted to the mem dependence unit.
system.cpu.iq.issued_per_cycle::total 181648006 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 135221 1.15% 1.15% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 39442 0.34% 1.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 7017 0.06% 1.55% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 13904 0.12% 1.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 2001949 17.09% 18.77% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 880826 7.52% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.29% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5776712 49.33% 75.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2855706 24.39% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 164795138 39.20% 39.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2124451 0.51% 39.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.71% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 34088388 8.11% 47.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 8064196 1.92% 49.74% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 3086941 0.73% 50.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16853454 4.01% 54.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 1579988 0.38% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 108302425 25.76% 80.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 81497238 19.38% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 420425800 # Type of FU issued
system.cpu.iq.rate 2.312957 # Inst issue rate
system.cpu.iq.fu_busy_cnt 11710777 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.027855 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 685991050 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 291244200 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 242469849 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 349993192 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 202862270 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 165589366 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 253586541 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 178516455 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 13913922 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 16340969 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 171857 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26790 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12352289 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 176199 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 9532209 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2220194 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 306578 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 461167180 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2274758 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 111095455 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 85873017 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 257 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 130 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 26790 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3503569 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 569738 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4073307 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 411738121 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 105779948 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8687679 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 25623650 # number of nop insts executed
system.cpu.iew.exec_refs 185717662 # number of memory reference insts executed
system.cpu.iew.exec_branches 48391334 # Number of branches executed
system.cpu.iew.exec_stores 79937714 # Number of stores executed
system.cpu.iew.exec_rate 2.265162 # Inst execution rate
system.cpu.iew.wb_sent 409282340 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 408059215 # cumulative count of insts written-back
system.cpu.iew.wb_producers 198971045 # num instructions producing a value
system.cpu.iew.wb_consumers 279819296 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.244923 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.711070 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 62502516 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3606605 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 172115797 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.316258 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.838436 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 71294232 41.42% 41.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 26334848 15.30% 56.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15061233 8.75% 65.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13435550 7.81% 73.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8560921 4.97% 78.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6120977 3.56% 81.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 5034670 2.93% 84.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3342912 1.94% 86.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 22930454 13.32% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 172115797 # Number of insts commited each cycle
system.cpu.commit.count 398664569 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 168275214 # Number of memory references committed
system.cpu.commit.loads 94754486 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 44587530 # Number of branches committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
system.cpu.commit.bw_lim_events 22930454 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 610349451 # The number of ROB reads
system.cpu.rob.rob_writes 931879411 # The number of ROB writes
system.cpu.timesIdled 2704 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 121815 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
system.cpu.cpi 0.483978 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.483978 # CPI: Total CPI of All Threads
system.cpu.ipc 2.066211 # IPC: Instructions Per Cycle
system.cpu.ipc_total 2.066211 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 410939724 # number of integer regfile reads
system.cpu.int_regfile_writes 176360806 # number of integer regfile writes
system.cpu.fp_regfile_reads 160541736 # number of floating regfile reads
system.cpu.fp_regfile_writes 106688075 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 226025470 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 3360184 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 259532333 # Number of HB maps that are committed
system.cpu.rename.IQFullEvents 311 # Number of times rename has blocked due to IQ full
system.cpu.rename.IdleCycles 122116498 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.RenameLookups 625408393 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 477751875 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 306658733 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 88296359 # Number of cycles rename is running
system.cpu.rename.SquashCycles 9813191 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 1960754 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 47126400 # Number of HB maps that are undone due to squashing
system.cpu.rename.fp_rename_lookups 292973848 # Number of floating rename lookups
system.cpu.rename.int_rename_lookups 332434545 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 340193 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 36156 # count of serializing insts renamed
system.cpu.rename.skidInsts 5383709 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 253 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 654965356 # The number of ROB reads
system.cpu.rob.rob_writes 919674888 # The number of ROB writes
system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.icache.replacements 2140 # number of replacements
system.cpu.icache.tagsinuse 1834.625402 # Cycle average of tags in use
system.cpu.icache.total_refs 58320710 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4067 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14339.982788 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1834.625402 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.895813 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 58320710 # number of ReadReq hits
system.cpu.icache.demand_hits 58320710 # number of demand (read+write) hits
system.cpu.icache.overall_hits 58320710 # number of overall hits
system.cpu.icache.ReadReq_misses 5316 # number of ReadReq misses
system.cpu.icache.demand_misses 5316 # number of demand (read+write) misses
system.cpu.icache.overall_misses 5316 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 168223000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 168223000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 168223000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 58326026 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 58326026 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 58326026 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 31644.657637 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 31644.657637 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 31644.657637 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1249 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1249 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1249 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 4067 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 4067 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 4067 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 123582000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 123582000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 123582000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30386.525695 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 788 # number of replacements
system.cpu.dcache.tagsinuse 3295.374104 # Cycle average of tags in use
system.cpu.dcache.total_refs 165040256 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4187 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 39417.304992 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3295.374104 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.804535 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 91538987 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 73501262 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 165040249 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 165040249 # number of overall hits
system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 19466 # number of WriteReq misses
system.cpu.dcache.demand_misses 21149 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 21149 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 56075000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 568706500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 624781500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 624781500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 91540670 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 165061398 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 165061398 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33318.478907 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 29215.375527 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 29541.893234 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 29541.893234 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 662 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 689 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16273 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 16962 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 16962 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 994 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 31676000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 113165000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 144841000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 144841000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31867.203219 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35441.590980 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 10 # number of replacements
system.cpu.l2cache.tagsinuse 4007.918811 # Cycle average of tags in use
system.cpu.l2cache.total_refs 828 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.170827 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3630.264414 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 377.654397 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.110787 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 755 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 817 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 817 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4306 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7437 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 148211500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 108422000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 256633500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 256633500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 5061 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 8254 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8254 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.850820 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.901018 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.901018 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34419.763121 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34628.553178 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34507.664381 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34507.664381 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4306 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 7437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 134349000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98553500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 232902500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 232902500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.850820 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.901018 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.901018 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.418021 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31476.684765 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

5
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

1
tests/long/30.eon/ref/arm/linux/o3-timing/simerr
View file

@ -1,5 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera

22
tests/long/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 19:29:23
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 02:03:43
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -18,5 +12,5 @@ Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.110000
Exiting @ tick 117852123500 because target called exit()
OO-style eon Time= 0.100000
Exiting @ tick 108112565000 because target called exit()

745
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.117852 # Number of seconds simulated
sim_ticks 117852123500 # Number of ticks simulated
sim_seconds 0.108113 # Number of seconds simulated
sim_ticks 108112565000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 49475 # Simulator instruction rate (inst/s)
host_tick_rate 16703679 # Simulator tick rate (ticks/s)
host_mem_usage 264264 # Number of bytes of host memory used
host_seconds 7055.46 # Real time elapsed on the host
sim_insts 349066258 # Number of instructions simulated
host_inst_rate 68175 # Simulator instruction rate (inst/s)
host_tick_rate 21114970 # Simulator tick rate (ticks/s)
host_mem_usage 266872 # Number of bytes of host memory used
host_seconds 5120.19 # Real time elapsed on the host
sim_insts 349066124 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,103 +51,106 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 235704248 # number of cpu cycles simulated
system.cpu.numCycles 216225131 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 37732885 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 20795463 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3471100 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 27302215 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 21001151 # Number of BTB hits
system.cpu.BPredUnit.lookups 38871530 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21265030 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3261176 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 27909151 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 21653043 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 7420100 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 72463 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39991725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 328152707 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37732885 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 28421251 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 76800425 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3608252 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 39991725 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 624732 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 235576888 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.817631 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.040837 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 7689864 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 61658 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 44557213 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 344579360 # Number of instructions fetch has processed
system.cpu.fetch.Branches 38871530 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 29342907 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 80636459 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 11681756 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 82619379 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 42088076 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 916191 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 216112788 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.095569 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.185948 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 159366483 67.65% 67.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9270231 3.94% 71.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5914286 2.51% 74.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6643493 2.82% 76.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5462624 2.32% 79.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4799627 2.04% 81.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3754754 1.59% 82.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4137731 1.76% 84.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 36227659 15.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 136175266 63.01% 63.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9565429 4.43% 67.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6238703 2.89% 70.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6748883 3.12% 73.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5364932 2.48% 75.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4989535 2.31% 78.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3875216 1.79% 80.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4307528 1.99% 82.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 38847296 17.98% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 235576888 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.160086 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.392222 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 84492760 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 69387883 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 73181829 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1548924 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6965492 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7488186 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 73175 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 420043685 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 215754 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6965492 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 90152933 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 976284 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 57875196 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 69216447 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 10390536 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 409431138 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 10006 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5114847 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 449313195 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2409887049 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1322854173 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1087032876 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384568949 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 64744241 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3898927 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 3897858 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 35694607 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 106772052 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 90018438 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11281294 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21363407 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 384862513 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3813526 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 372770888 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1408906 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 37984896 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 125485450 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 258042 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 235576888 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.582375 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.822791 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 216112788 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.179773 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.593614 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 53033788 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 77116773 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 73749422 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3985890 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 8226915 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7647714 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 72935 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 439814331 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 207402 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 8226915 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 61196526 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1203573 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 59638529 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 69748798 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 16098447 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 424223689 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 22825 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 9278494 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 99 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 462213475 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2492907388 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1378161419 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1114745969 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384568743 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 77644727 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3986897 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4043470 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 51924156 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 109846529 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 95332472 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 14399866 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 29809960 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 399729408 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3865767 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 378419662 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1473555 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 54144389 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 177169340 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 310299 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 216112788 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.751029 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.895618 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 95699423 40.62% 40.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 48065676 20.40% 61.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 27569248 11.70% 72.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20762200 8.81% 81.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21955543 9.32% 90.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 12942689 5.49% 96.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 5977724 2.54% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1956925 0.83% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 647460 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 82036681 37.96% 37.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 39071702 18.08% 56.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 28236809 13.07% 69.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20423013 9.45% 78.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 23529038 10.89% 89.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 13145418 6.08% 95.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 6683366 3.09% 98.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2232223 1.03% 99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 754538 0.35% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 235576888 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 216112788 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2414 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2198 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available
@ -167,181 +170,181 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # at
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 11301 0.09% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 9996 0.08% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 197 0.00% 0.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 1510 0.01% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 142649 1.07% 1.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 1224 0.01% 1.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.28% 3.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7115466 53.58% 57.10% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5697057 42.90% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 2604 0.02% 0.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 194 0.00% 0.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 114242 0.95% 1.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 418 0.00% 1.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 276715 2.30% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7458735 61.87% 65.28% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4186007 34.72% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 126467737 33.93% 33.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147032 0.58% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6836061 1.83% 36.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.34% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8620472 2.31% 38.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3526603 0.95% 39.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1580695 0.42% 40.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21030277 5.64% 45.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7283358 1.95% 47.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262499 1.95% 49.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 102234129 27.43% 77.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85606734 22.96% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 130620873 34.52% 34.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147251 0.57% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6800768 1.80% 36.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8475274 2.24% 39.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3501119 0.93% 40.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1584837 0.42% 40.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21128819 5.58% 46.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7289356 1.93% 47.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7313976 1.93% 49.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.95% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 102741469 27.15% 77.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 86640612 22.90% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 372770888 # Type of FU issued
system.cpu.iq.rate 1.581520 # Inst issue rate
system.cpu.iq.fu_busy_cnt 13280227 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.035626 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 746488455 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 293551634 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 247041034 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 249319342 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 133204458 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 118172579 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 258240891 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 127810224 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4605348 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 378419662 # Type of FU issued
system.cpu.iq.rate 1.750119 # Inst issue rate
system.cpu.iq.fu_busy_cnt 12056154 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.031859 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 736575285 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 322046718 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 251010826 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 249906536 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 135772025 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 118653498 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 262435143 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 128040673 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5198793 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 12123008 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 25231 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 199737 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 7642570 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 15197510 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2287 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 168315 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12956623 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 309 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6965492 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 10869 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 480 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 388723243 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 6854795 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 106772052 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 90018438 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3802280 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 199737 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3305937 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 361135 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3667072 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 368528754 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 101011008 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4242134 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 8226915 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 19822 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 465 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 403642432 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2591477 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 109846529 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 95332472 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3854525 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 168315 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3199953 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 312751 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3512704 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 372398400 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 101298405 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6021262 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 47204 # number of nop insts executed
system.cpu.iew.exec_refs 185554303 # number of memory reference insts executed
system.cpu.iew.exec_branches 31933479 # Number of branches executed
system.cpu.iew.exec_stores 84543295 # Number of stores executed
system.cpu.iew.exec_rate 1.563522 # Inst execution rate
system.cpu.iew.wb_sent 365991200 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 365213613 # cumulative count of insts written-back
system.cpu.iew.wb_producers 165367337 # num instructions producing a value
system.cpu.iew.wb_consumers 317313225 # num instructions consuming a value
system.cpu.iew.exec_nop 47257 # number of nop insts executed
system.cpu.iew.exec_refs 186410418 # number of memory reference insts executed
system.cpu.iew.exec_branches 32413413 # Number of branches executed
system.cpu.iew.exec_stores 85112013 # Number of stores executed
system.cpu.iew.exec_rate 1.722272 # Inst execution rate
system.cpu.iew.wb_sent 370241650 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 369664324 # cumulative count of insts written-back
system.cpu.iew.wb_producers 175377527 # num instructions producing a value
system.cpu.iew.wb_consumers 344318453 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.549457 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.521149 # average fanout of values written-back
system.cpu.iew.wb_rate 1.709627 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.509347 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 349066870 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 39653224 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555484 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3440231 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 228611397 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.526901 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.127678 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 349066736 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 54571176 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555468 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3230397 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 207885874 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.679127 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.249386 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 102653839 44.90% 44.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 52967573 23.17% 68.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 21494828 9.40% 77.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 16426131 7.19% 84.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11610822 5.08% 89.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 6946497 3.04% 92.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3261718 1.43% 94.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2914745 1.27% 95.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10335244 4.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 88802662 42.72% 42.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 47260336 22.73% 65.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 19727320 9.49% 74.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 15331284 7.37% 82.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11254360 5.41% 87.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7570851 3.64% 91.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3388756 1.63% 93.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3248763 1.56% 94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11301542 5.44% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 228611397 # Number of insts commited each cycle
system.cpu.commit.count 349066870 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 207885874 # Number of insts commited each cycle
system.cpu.commit.count 349066736 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 177024911 # Number of memory references committed
system.cpu.commit.loads 94649043 # Number of loads committed
system.cpu.commit.refs 177024867 # Number of memory references committed
system.cpu.commit.loads 94649018 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.branches 30521922 # Number of branches committed
system.cpu.commit.branches 30521897 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279586109 # Number of committed integer instructions.
system.cpu.commit.int_insts 279586001 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.bw_lim_events 10335244 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 11301542 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 606993724 # The number of ROB reads
system.cpu.rob.rob_writes 784416922 # The number of ROB writes
system.cpu.timesIdled 2785 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 127360 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 349066258 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066258 # Number of Instructions Simulated
system.cpu.cpi 0.675242 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.675242 # CPI: Total CPI of All Threads
system.cpu.ipc 1.480950 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.480950 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1759160975 # number of integer regfile reads
system.cpu.int_regfile_writes 232094825 # number of integer regfile writes
system.cpu.fp_regfile_reads 189729002 # number of floating regfile reads
system.cpu.fp_regfile_writes 134274190 # number of floating regfile writes
system.cpu.misc_regfile_reads 986066945 # number of misc regfile reads
system.cpu.misc_regfile_writes 34422257 # number of misc regfile writes
system.cpu.icache.replacements 13781 # number of replacements
system.cpu.icache.tagsinuse 1824.800983 # Cycle average of tags in use
system.cpu.icache.total_refs 39975644 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2555.497283 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 600219721 # The number of ROB reads
system.cpu.rob.rob_writes 815506085 # The number of ROB writes
system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 112343 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 349066124 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066124 # Number of Instructions Simulated
system.cpu.cpi 0.619439 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.619439 # CPI: Total CPI of All Threads
system.cpu.ipc 1.614364 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.614364 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1775936880 # number of integer regfile reads
system.cpu.int_regfile_writes 235580324 # number of integer regfile writes
system.cpu.fp_regfile_reads 189945628 # number of floating regfile reads
system.cpu.fp_regfile_writes 134544688 # number of floating regfile writes
system.cpu.misc_regfile_reads 1009447373 # number of misc regfile reads
system.cpu.misc_regfile_writes 34422229 # number of misc regfile writes
system.cpu.icache.replacements 14157 # number of replacements
system.cpu.icache.tagsinuse 1842.318723 # Cycle average of tags in use
system.cpu.icache.total_refs 42071371 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 16032 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2624.212263 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1824.800983 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.891016 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 39975644 # number of ReadReq hits
system.cpu.icache.demand_hits 39975644 # number of demand (read+write) hits
system.cpu.icache.overall_hits 39975644 # number of overall hits
system.cpu.icache.ReadReq_misses 16081 # number of ReadReq misses
system.cpu.icache.demand_misses 16081 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16081 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 189840000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 189840000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 189840000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 39991725 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 39991725 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 39991725 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 11805.235993 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 11805.235993 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 11805.235993 # average overall miss latency
system.cpu.icache.occ_blocks::0 1842.318723 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.899570 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 42071371 # number of ReadReq hits
system.cpu.icache.demand_hits 42071371 # number of demand (read+write) hits
system.cpu.icache.overall_hits 42071371 # number of overall hits
system.cpu.icache.ReadReq_misses 16705 # number of ReadReq misses
system.cpu.icache.demand_misses 16705 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16705 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 202344500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 202344500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 202344500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 42088076 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 42088076 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 42088076 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000397 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000397 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000397 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12112.810536 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12112.810536 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12112.810536 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -351,142 +354,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 15646 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 15646 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 15646 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 669 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 669 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 669 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 16036 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 16036 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 16036 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 131146500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 131146500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 131146500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 136366000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 136366000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 136366000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8382.110444 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000381 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000381 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000381 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8503.741581 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1396 # number of replacements
system.cpu.dcache.tagsinuse 3097.520126 # Cycle average of tags in use
system.cpu.dcache.total_refs 178371323 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4582 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38928.704278 # Average number of references to valid blocks.
system.cpu.dcache.replacements 1406 # number of replacements
system.cpu.dcache.tagsinuse 3100.332801 # Cycle average of tags in use
system.cpu.dcache.total_refs 178043182 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4595 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38747.156039 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3097.520126 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.756230 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 96315033 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82033723 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 11410 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 178348756 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 178348756 # number of overall hits
system.cpu.dcache.ReadReq_misses 3256 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 18976 # number of WriteReq misses
system.cpu.dcache.occ_blocks::0 3100.332801 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.756917 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 95986293 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82033252 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 12491 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11132 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 178019545 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 178019545 # number of overall hits
system.cpu.dcache.ReadReq_misses 3385 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 19442 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 22232 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 22232 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 108888000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 618616000 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 22827 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 22827 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 112128500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 646930500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 727504000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 727504000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 96318289 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 11412 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 178370988 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 178370988 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33442.260442 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 32599.915683 # average WriteReq miss latency
system.cpu.dcache.demand_miss_latency 759059000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 759059000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 95989678 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 12493 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11132 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 178042372 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 178042372 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000160 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33125.110783 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33274.894558 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 32723.281756 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 32723.281756 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency 33252.683226 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33252.683226 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 308500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 28045.454545 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1019 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1507 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16140 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 1025 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16598 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 17647 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 17647 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1749 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2836 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4585 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4585 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 18228 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 18228 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1755 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2844 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4599 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4599 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 54106000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 100544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 154650000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 154650000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 53650500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 101058500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 154709000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 154709000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30935.391652 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35452.750353 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30570.085470 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35533.931083 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 54 # number of replacements
system.cpu.l2cache.tagsinuse 3793.062863 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13102 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5236 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.502292 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 59 # number of replacements
system.cpu.l2cache.tagsinuse 3910.187993 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13367 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.490591 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3424.878969 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 368.183894 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.104519 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011236 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13017 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1019 # number of Writeback hits
system.cpu.l2cache.occ_blocks::0 3537.549748 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 372.638245 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.107957 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011372 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13284 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1025 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 13034 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 13034 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4374 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 2816 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7190 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 150210000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 96886500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 247096500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 247096500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 17391 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1019 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 2833 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 20224 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 20224 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.251509 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_hits 13301 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 13301 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4501 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 2824 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7325 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7325 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 154458500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 97367500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 251826000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 251826000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 17785 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1025 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 2841 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 20626 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 20626 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.253078 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.993999 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.355518 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.355518 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34341.563786 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.717330 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34366.689847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34366.689847 # average overall miss latency
system.cpu.l2cache.ReadExReq_miss_rate 0.994016 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.355134 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.355134 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.485226 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.576487 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34378.976109 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34378.976109 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -496,31 +499,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4323 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 2816 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 7139 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7139 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 54 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4447 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 2824 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 7271 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7271 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 134686000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88056000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 222742000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 222742000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 138555000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88338500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 226893500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 226893500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248577 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250042 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993999 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.352996 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.352996 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.678927 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994016 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.352516 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.352516 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.959748 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.886364 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31281.338527 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864

10
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 10:33:23
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:14:22
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 689104583500 because target called exit()
Exiting @ tick 643278327500 because target called exit()

791
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.689105 # Number of seconds simulated
sim_ticks 689104583500 # Number of ticks simulated
sim_seconds 0.643278 # Number of seconds simulated
sim_ticks 643278327500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 190198 # Simulator instruction rate (inst/s)
host_tick_rate 71894197 # Simulator tick rate (ticks/s)
host_mem_usage 200384 # Number of bytes of host memory used
host_seconds 9584.98 # Real time elapsed on the host
host_inst_rate 72554 # Simulator instruction rate (inst/s)
host_tick_rate 25601460 # Simulator tick rate (ticks/s)
host_mem_usage 253232 # Number of bytes of host memory used
host_seconds 25126.63 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 514070459 # DTB read hits
system.cpu.dtb.read_misses 615925 # DTB read misses
system.cpu.dtb.read_hits 519966765 # DTB read hits
system.cpu.dtb.read_misses 661962 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 514686384 # DTB read accesses
system.cpu.dtb.write_hits 251680293 # DTB write hits
system.cpu.dtb.write_misses 42864 # DTB write misses
system.cpu.dtb.read_accesses 520628727 # DTB read accesses
system.cpu.dtb.write_hits 283803273 # DTB write hits
system.cpu.dtb.write_misses 53019 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 251723157 # DTB write accesses
system.cpu.dtb.data_hits 765750752 # DTB hits
system.cpu.dtb.data_misses 658789 # DTB misses
system.cpu.dtb.write_accesses 283856292 # DTB write accesses
system.cpu.dtb.data_hits 803770038 # DTB hits
system.cpu.dtb.data_misses 714981 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 766409541 # DTB accesses
system.cpu.itb.fetch_hits 343698672 # ITB hits
system.cpu.itb.fetch_misses 197 # ITB misses
system.cpu.dtb.data_accesses 804485019 # DTB accesses
system.cpu.itb.fetch_hits 398172437 # ITB hits
system.cpu.itb.fetch_misses 227 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 343698869 # ITB accesses
system.cpu.itb.fetch_accesses 398172664 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
system.cpu.numCycles 1378209168 # number of cpu cycles simulated
system.cpu.numCycles 1286556656 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 28355376 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 286093994 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 234435463 # Number of BTB hits
system.cpu.BPredUnit.lookups 402336394 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 266883320 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 28923526 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 333487818 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 271623617 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 847 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 343698672 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2972544545 # Number of instructions fetch has processed
system.cpu.fetch.Branches 342127414 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 283762997 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 569144710 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 28790520 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 343698672 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4322809 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1378074830 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.157027 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.030206 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 61006515 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1123 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 414972341 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3352664907 # Number of instructions fetch has processed
system.cpu.fetch.Branches 402336394 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 332630132 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 645381442 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 165705235 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 89720860 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 4171 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 398172437 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11167265 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1286425438 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.606187 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.132190 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 808930120 58.70% 58.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 53203120 3.86% 62.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38710034 2.81% 65.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 60833254 4.41% 69.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 120527197 8.75% 78.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 36009747 2.61% 81.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 37301448 2.71% 83.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7023896 0.51% 84.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 215536014 15.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 641043996 49.83% 49.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 57060222 4.44% 54.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 45200815 3.51% 57.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 74446189 5.79% 63.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 134854552 10.48% 74.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 43347618 3.37% 77.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44933428 3.49% 80.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8201322 0.64% 81.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 237337296 18.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1378074830 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.248241 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.156817 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 1286425438 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.312723 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.605921 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 450744873 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 71473924 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 619092915 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 8779214 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 136334512 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 30672233 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12086 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3254497888 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 45897 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 136334512 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 481076883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 28014325 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 24661 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 596193290 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 44781767 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3152490171 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 251 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 750331 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 37577847 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2105819344 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3700266531 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3588526705 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 111739826 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 641174032 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 294900052 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 45514192 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5837090 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2345716556 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2067604433 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 522645709 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 720850274 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2943 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 124041279 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 733340932 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 346031420 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 95137569 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 27633179 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2644257175 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2155824179 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 16126742 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 820828364 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 783816601 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1286425438 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.675825 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.770169 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 467246309 36.32% 36.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 226022267 17.57% 53.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 245197843 19.06% 72.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131574377 10.23% 83.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 102243605 7.95% 91.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 70385882 5.47% 96.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 25434522 1.98% 98.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 15392931 1.20% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2927702 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1286425438 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 16153 0.06% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 21369886 75.29% 75.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 6999064 24.66% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1238199555 57.44% 57.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 16604 0.00% 57.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 27850923 1.29% 58.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 8254691 0.38% 59.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 584881936 27.13% 86.58% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 289413066 13.42% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued
system.cpu.iq.rate 1.500211 # Inst issue rate
system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2793381779 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 51921347 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2155824179 # Type of FU issued
system.cpu.iq.rate 1.675654 # Inst issue rate
system.cpu.iq.fu_busy_cnt 28385103 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5494149121 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3387002536 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1990375209 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 148436520 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 78085554 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 72618270 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2108584760 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 75621770 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 67562501 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 130104006 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1647 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 84105156 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 222270906 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2427 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2537 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 135236524 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4160 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 5770 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2668815228 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3006027 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 294900052 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 131680 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1990177336 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 514686474 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 77427097 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 136334512 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 3822943 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 203706 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3007852435 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2742591 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 733340932 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 346031420 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 131030 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2537 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 30744167 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 897447 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 31641614 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2065462954 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 520628814 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 90361225 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 323098610 # number of nop insts executed
system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed
system.cpu.iew.exec_branches 273848647 # Number of branches executed
system.cpu.iew.exec_stores 251723816 # Number of stores executed
system.cpu.iew.exec_rate 1.444031 # Inst execution rate
system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1118735591 # num instructions producing a value
system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value
system.cpu.iew.exec_nop 363595182 # number of nop insts executed
system.cpu.iew.exec_refs 804485830 # number of memory reference insts executed
system.cpu.iew.exec_branches 279503743 # Number of branches executed
system.cpu.iew.exec_stores 283857016 # Number of stores executed
system.cpu.iew.exec_rate 1.605419 # Inst execution rate
system.cpu.iew.wb_sent 2064970542 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2062993479 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1176781433 # num instructions producing a value
system.cpu.iew.wb_consumers 1743261069 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back
system.cpu.iew.wb_rate 1.603500 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.675046 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 982155641 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 28911563 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1150090926 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.746808 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.513435 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 542926028 47.21% 47.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 216885753 18.86% 66.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 119710361 10.41% 76.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 61150951 5.32% 81.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 44124600 3.84% 85.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 24943285 2.17% 87.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19289585 1.68% 89.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 16206963 1.41% 90.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 104853400 9.12% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1150090926 # Number of insts commited each cycle
system.cpu.commit.count 2008987604 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 721864922 # Number of memory references committed
@ -288,50 +290,50 @@ system.cpu.commit.branches 266706457 # Nu
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 104853400 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3864626779 # The number of ROB reads
system.cpu.rob.rob_writes 5411636382 # The number of ROB writes
system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 4030744361 # The number of ROB reads
system.cpu.rob.rob_writes 6118806810 # The number of ROB writes
system.cpu.timesIdled 3658 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 131218 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.755994 # CPI: Total CPI of All Threads
system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads
system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes
system.cpu.fp_regfile_reads 77822211 # number of floating regfile reads
system.cpu.fp_regfile_writes 52656376 # number of floating regfile writes
system.cpu.cpi 0.705719 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.705719 # CPI: Total CPI of All Threads
system.cpu.ipc 1.416994 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.416994 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2630024814 # number of integer regfile reads
system.cpu.int_regfile_writes 1492719850 # number of integer regfile writes
system.cpu.fp_regfile_reads 77822488 # number of floating regfile reads
system.cpu.fp_regfile_writes 52815654 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 8102 # number of replacements
system.cpu.icache.tagsinuse 1613.087790 # Cycle average of tags in use
system.cpu.icache.total_refs 343688083 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9773 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 35167.101504 # Average number of references to valid blocks.
system.cpu.icache.replacements 8249 # number of replacements
system.cpu.icache.tagsinuse 1648.525353 # Cycle average of tags in use
system.cpu.icache.total_refs 398161333 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9955 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 39996.115821 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 343688083 # number of ReadReq hits
system.cpu.icache.demand_hits 343688083 # number of demand (read+write) hits
system.cpu.icache.overall_hits 343688083 # number of overall hits
system.cpu.icache.ReadReq_misses 10589 # number of ReadReq misses
system.cpu.icache.demand_misses 10589 # number of demand (read+write) misses
system.cpu.icache.overall_misses 10589 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 166169000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 166169000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 166169000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 343698672 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 343698672 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 15692.605534 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 15692.605534 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency
system.cpu.icache.occ_blocks::0 1648.525353 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.804944 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 398161333 # number of ReadReq hits
system.cpu.icache.demand_hits 398161333 # number of demand (read+write) hits
system.cpu.icache.overall_hits 398161333 # number of overall hits
system.cpu.icache.ReadReq_misses 11104 # number of ReadReq misses
system.cpu.icache.demand_misses 11104 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11104 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 182797500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 182797500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 182797500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 398172437 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 398172437 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 398172437 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 16462.310879 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 16462.310879 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 16462.310879 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,161 +343,170 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 815 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 815 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 815 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 9774 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 9774 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 9774 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 1148 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1148 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1148 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 9956 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 9956 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 9956 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 113082000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 113082000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 113082000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 119908500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 119908500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 119908500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11569.674647 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12043.842909 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12043.842909 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12043.842909 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1526504 # number of replacements
system.cpu.dcache.tagsinuse 4095.093805 # Cycle average of tags in use
system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1530600 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 438.041746 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 460219169 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 210247520 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 670466689 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 670466689 # number of overall hits
system.cpu.dcache.ReadReq_misses 1925769 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 547376 # number of WriteReq misses
system.cpu.dcache.demand_misses 2473145 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2473145 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 71430113000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 20787135492 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 92217248492 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 92217248492 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 462144938 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 1526943 # number of replacements
system.cpu.dcache.tagsinuse 4095.108553 # Cycle average of tags in use
system.cpu.dcache.total_refs 660714952 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1531039 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 431.546781 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 256550000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4095.108553 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999782 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 450471495 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 210243448 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 660714943 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 660714943 # number of overall hits
system.cpu.dcache.ReadReq_misses 1926978 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 551448 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2478426 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2478426 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 71403545500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 20877102491 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 92500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 92280647991 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 92280647991 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 452398473 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 672939834 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004167 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.003675 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.003675 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 37091.734782 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 37975.971712 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 37287.441089 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 67000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 14000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.dcache.LoadLockedReq_accesses 12 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 663193369 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 663193369 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004259 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002616 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.250000 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.003737 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.003737 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 37054.676026 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 37858.696543 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 30833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 37233.570012 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 37233.570012 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 73500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 17000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5583.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5653.846154 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 17000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 107391 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 466816 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 475729 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 942545 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 942545 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1458953 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 71647 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1530600 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1530600 # number of overall MSHR misses
system.cpu.dcache.writebacks 107355 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 467583 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 479805 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 947388 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 947388 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1459395 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 71643 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1531038 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1531038 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 49864130500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2492449500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52356580000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52356580000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 49913534500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2493312500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52406847000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52406847000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002274 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002274 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34178.023898 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34787.911566 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.083333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34201.524947 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34801.899697 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34229.618729 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34229.618729 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480376 # number of replacements
system.cpu.l2cache.tagsinuse 31940.931964 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62599 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1513063 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.041372 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 1480567 # number of replacements
system.cpu.l2cache.tagsinuse 31934.538641 # Cycle average of tags in use
system.cpu.l2cache.total_refs 62997 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1513254 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.041630 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 54988 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 107391 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 59781 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 59781 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1413739 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 66854 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1480593 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1480593 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48438065500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2348993500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50787059000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50787059000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1468727 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107391 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 71647 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1540374 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.962561 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.933103 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.961191 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.961191 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34262.381882 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.169863 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34301.836494 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked
system.cpu.l2cache.occ_blocks::0 28868.809118 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3065.729523 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.881006 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.093559 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 55380 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 107355 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 4788 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 60168 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 60168 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1413972 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1480827 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1480827 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48486615500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2348963000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50835578500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50835578500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1469352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107355 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 71643 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1540995 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1540995 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.962310 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.933169 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.960955 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.960955 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34291.071888 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 35135.188094 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34329.181262 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34329.181262 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 66898 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1413739 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66854 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1480593 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1480593 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 1413972 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1480827 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1480827 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43826861000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148213000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 45975074000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 45975074000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 43834352500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147649000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 45982001500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 45982001500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962561 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933103 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.961191 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.961191 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.673392 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32132.901547 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962310 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933169 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.960955 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.960955 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.863171 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32123.984743 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568819 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

2
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr
View file

@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: fcntl64(3, 2) passed through to host
For more information see: http://www.m5sim.org/warn/a55e2c46
hack: be nice to actually delete the event here

20
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 15:11:57
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 02:34:35
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -1391,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 795626752000 because target called exit()
Exiting @ tick 744105966500 because target called exit()

794
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.795627 # Number of seconds simulated
sim_ticks 795626752000 # Number of ticks simulated
sim_seconds 0.744106 # Number of seconds simulated
sim_ticks 744105966500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 37469 # Simulator instruction rate (inst/s)
host_tick_rate 15812352 # Simulator tick rate (ticks/s)
host_mem_usage 261444 # Number of bytes of host memory used
host_seconds 50316.79 # Real time elapsed on the host
sim_insts 1885343131 # Number of instructions simulated
host_inst_rate 75556 # Simulator instruction rate (inst/s)
host_tick_rate 29820362 # Simulator tick rate (ticks/s)
host_mem_usage 264164 # Number of bytes of host memory used
host_seconds 24952.95 # Real time elapsed on the host
sim_insts 1885342016 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1591253505 # number of cpu cycles simulated
system.cpu.numCycles 1488211934 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 519677239 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 398144928 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 40174420 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 410482703 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 293585496 # Number of BTB hits
system.cpu.BPredUnit.lookups 518896793 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 400040732 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 32908651 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 412694566 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 290043770 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 53540823 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2841317 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 361951635 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2537428028 # Number of instructions fetch has processed
system.cpu.fetch.Branches 519677239 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 347126319 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 659124412 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 47088491 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 166 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 361951635 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 20842559 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1554259692 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.199934 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.044955 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 65454853 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2848873 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 431006584 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2627710278 # Number of instructions fetch has processed
system.cpu.fetch.Branches 518896793 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 355498623 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 704801435 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 227434994 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 113516280 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 5111 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 399257672 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8382302 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1436630001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.536830 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.149737 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 895170810 57.59% 57.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 41935957 2.70% 60.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 103275417 6.64% 66.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 61539532 3.96% 70.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 89553793 5.76% 76.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 52982183 3.41% 80.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 34961510 2.25% 82.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 45455804 2.92% 85.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 229384686 14.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 731865766 50.94% 50.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 52278672 3.64% 54.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 109951004 7.65% 62.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 64331025 4.48% 66.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 92104513 6.41% 73.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 55434190 3.86% 76.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39408243 2.74% 79.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 32778762 2.28% 82.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 258477826 17.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1554259692 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.326584 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.594610 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 723197107 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 41283634 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 642007597 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1402750 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 146368604 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 76799900 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 11033 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3347346347 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 20349 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 146368604 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 756568519 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 25444222 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3271742 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 608636712 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 13969893 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3194137589 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3931047 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 7404635 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 3358259430 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 15045243779 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 14391074287 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 654169492 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993168551 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1365090874 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 254462 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 254764 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 34849726 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 925173948 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 465395627 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 97302082 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 144361448 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2889677990 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 244825 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2448298992 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 12457526 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 987757973 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2669097969 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 33037 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1554259692 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.575219 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.653577 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 1436630001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.348671 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.765683 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 474703889 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 92089695 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 671736516 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 10812998 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 187286903 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 70416009 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13639 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3539876246 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 23440 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 187286903 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 514963010 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 29220198 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3511276 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 640788708 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 60859906 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3412725631 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4123400 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 48521988 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 3397910620 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 16198267301 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 15450730698 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 747536603 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993166767 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1404743848 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 278280 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 278424 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 178635722 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1114561414 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 545702989 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 154567236 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 147667095 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 3238356442 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 281581 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2642482384 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5796308 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1352960304 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3645177300 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 70016 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1436630001 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.839362 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.852230 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 571543598 36.77% 36.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 302403348 19.46% 56.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 272921305 17.56% 73.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 170079995 10.94% 84.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 141872535 9.13% 93.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 62133878 4.00% 97.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 24302902 1.56% 99.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6180941 0.40% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2821190 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 506457907 35.25% 35.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 223599177 15.56% 50.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 229642094 15.98% 66.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 172448421 12.00% 78.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 157180454 10.94% 89.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 90857048 6.32% 96.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 40453427 2.82% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11405646 0.79% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4585827 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1554259692 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1436630001 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5100 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23970 0.03% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 52395536 69.00% 69.04% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23506568 30.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1185558 1.85% 1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23950 0.04% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 40505203 63.35% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 22224408 34.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1194651657 48.80% 48.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11220052 0.46% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 6176938 0.25% 49.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 25435651 1.04% 50.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 792339955 32.36% 83.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 410214348 16.76% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1237165385 46.82% 46.82% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11226668 0.42% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 8630 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 47.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.26% 47.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 6142371 0.23% 47.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 24460385 0.93% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 896605446 33.93% 82.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 458621735 17.36% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2448298992 # Type of FU issued
system.cpu.iq.rate 1.538598 # Inst issue rate
system.cpu.iq.fu_busy_cnt 75931174 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.031014 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6412694569 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3775928903 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2259827011 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 126551807 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 103128995 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 57766877 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2458203699 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 66026467 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 38019387 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2642482384 # Type of FU issued
system.cpu.iq.rate 1.775609 # Inst issue rate
system.cpu.iq.fu_busy_cnt 63939119 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024197 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6661297580 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 4469277070 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2420670942 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 130032616 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 124010144 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 59075392 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2641405327 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 65016176 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 73114963 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 293783209 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1377644 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 2672008 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 188396774 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 483170898 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 99011 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 3650929 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 268704359 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 146368604 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 17402025 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3966817 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2889988302 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 9053008 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 925173948 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 465395627 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 232022 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2656731 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 304 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 2672008 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 37424548 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 12425696 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 49850244 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2354181989 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 757207603 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 94117003 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 187286903 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16548451 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1477546 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3238703739 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 11872283 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1114561414 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 545702989 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 268887 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1475433 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 305 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 3650929 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 36090139 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8517669 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 44607808 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2538548253 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 842723322 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 103934131 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 65487 # number of nop insts executed
system.cpu.iew.exec_refs 1128829223 # number of memory reference insts executed
system.cpu.iew.exec_branches 348669519 # Number of branches executed
system.cpu.iew.exec_stores 371621620 # Number of stores executed
system.cpu.iew.exec_rate 1.479451 # Inst execution rate
system.cpu.iew.wb_sent 2328619665 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2317593888 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1309821619 # num instructions producing a value
system.cpu.iew.wb_consumers 2336262105 # num instructions consuming a value
system.cpu.iew.exec_nop 65716 # number of nop insts executed
system.cpu.iew.exec_refs 1272992998 # number of memory reference insts executed
system.cpu.iew.exec_branches 351489842 # Number of branches executed
system.cpu.iew.exec_stores 430269676 # Number of stores executed
system.cpu.iew.exec_rate 1.705771 # Inst execution rate
system.cpu.iew.wb_sent 2508384244 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2479746334 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1467036313 # num instructions producing a value
system.cpu.iew.wb_consumers 2710651250 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.456458 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.560648 # average fanout of values written-back
system.cpu.iew.wb_rate 1.666259 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.541212 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1004600706 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 45699022 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1407891090 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.339134 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.034210 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 1885353032 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1353312364 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211565 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38431023 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1249343100 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.509075 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.191779 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 652274208 46.33% 46.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 388083214 27.56% 73.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 132034153 9.38% 83.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 69283607 4.92% 88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 48326626 3.43% 91.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18528976 1.32% 92.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 23779079 1.69% 94.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 7923868 0.56% 95.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 67657359 4.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 548617532 43.91% 43.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 340979538 27.29% 71.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 105479188 8.44% 79.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 77201400 6.18% 85.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 51871134 4.15% 89.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18884009 1.51% 91.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20943022 1.68% 93.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8690011 0.70% 93.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 76677266 6.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1407891090 # Number of insts commited each cycle
system.cpu.commit.count 1885354147 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 1249343100 # Number of insts commited each cycle
system.cpu.commit.count 1885353032 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908389591 # Number of memory references committed
system.cpu.commit.loads 631390738 # Number of loads committed
system.cpu.commit.refs 908389145 # Number of memory references committed
system.cpu.commit.loads 631390515 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 291352101 # Number of branches committed
system.cpu.commit.branches 291351878 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653713099 # Number of committed integer instructions.
system.cpu.commit.int_insts 1653712207 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 67657359 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 76677266 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4230170239 # The number of ROB reads
system.cpu.rob.rob_writes 5926292122 # The number of ROB writes
system.cpu.timesIdled 1344848 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 36993813 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1885343131 # Number of Instructions Simulated
system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated
system.cpu.cpi 0.844013 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.844013 # CPI: Total CPI of All Threads
system.cpu.ipc 1.184816 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.184816 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 11587728749 # number of integer regfile reads
system.cpu.int_regfile_writes 2306495167 # number of integer regfile writes
system.cpu.fp_regfile_reads 69468418 # number of floating regfile reads
system.cpu.fp_regfile_writes 51554923 # number of floating regfile writes
system.cpu.misc_regfile_reads 3827336094 # number of misc regfile reads
system.cpu.misc_regfile_writes 13780014 # number of misc regfile writes
system.cpu.icache.replacements 25559 # number of replacements
system.cpu.icache.tagsinuse 1546.566470 # Cycle average of tags in use
system.cpu.icache.total_refs 361924025 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 27145 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13332.990422 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 4411312885 # The number of ROB reads
system.cpu.rob.rob_writes 6664635759 # The number of ROB writes
system.cpu.timesIdled 1344981 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51581933 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1885342016 # Number of Instructions Simulated
system.cpu.committedInsts_total 1885342016 # Number of Instructions Simulated
system.cpu.cpi 0.789359 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.789359 # CPI: Total CPI of All Threads
system.cpu.ipc 1.266850 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.266850 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12578509945 # number of integer regfile reads
system.cpu.int_regfile_writes 2395231974 # number of integer regfile writes
system.cpu.fp_regfile_reads 70809202 # number of floating regfile reads
system.cpu.fp_regfile_writes 51453484 # number of floating regfile writes
system.cpu.misc_regfile_reads 4059454744 # number of misc regfile reads
system.cpu.misc_regfile_writes 13779568 # number of misc regfile writes
system.cpu.icache.replacements 25817 # number of replacements
system.cpu.icache.tagsinuse 1640.813432 # Cycle average of tags in use
system.cpu.icache.total_refs 399229379 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 27501 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14516.904076 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1546.566470 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.755159 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 361924028 # number of ReadReq hits
system.cpu.icache.demand_hits 361924028 # number of demand (read+write) hits
system.cpu.icache.overall_hits 361924028 # number of overall hits
system.cpu.icache.ReadReq_misses 27607 # number of ReadReq misses
system.cpu.icache.demand_misses 27607 # number of demand (read+write) misses
system.cpu.icache.overall_misses 27607 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 250013500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 250013500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 250013500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 361951635 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 361951635 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 361951635 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 9056.163292 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 9056.163292 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 9056.163292 # average overall miss latency
system.cpu.icache.occ_blocks::0 1640.813432 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.801178 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 399229380 # number of ReadReq hits
system.cpu.icache.demand_hits 399229380 # number of demand (read+write) hits
system.cpu.icache.overall_hits 399229380 # number of overall hits
system.cpu.icache.ReadReq_misses 28292 # number of ReadReq misses
system.cpu.icache.demand_misses 28292 # number of demand (read+write) misses
system.cpu.icache.overall_misses 28292 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 269405500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 269405500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 269405500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 399257672 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 399257672 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 399257672 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000071 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 9522.320797 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 9522.320797 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 9522.320797 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -351,143 +353,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 455 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 455 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 455 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 27152 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 27152 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 27152 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 785 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 785 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 785 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 27507 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 27507 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 27507 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 155884000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 155884000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 155884000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 166096000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 166096000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 166096000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5741.160872 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6038.317519 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1531405 # number of replacements
system.cpu.dcache.tagsinuse 4094.850466 # Cycle average of tags in use
system.cpu.dcache.total_refs 980041629 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1535501 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 638.255285 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 325046000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.850466 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 703882480 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 276128743 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 16835 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 13541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 980011223 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 980011223 # number of overall hits
system.cpu.dcache.ReadReq_misses 1932681 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 806935 # number of WriteReq misses
system.cpu.dcache.replacements 1531025 # number of replacements
system.cpu.dcache.tagsinuse 4094.846671 # Cycle average of tags in use
system.cpu.dcache.total_refs 1028461825 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1535121 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 669.954893 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306448000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.846671 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999718 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 752304344 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 276127089 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 17060 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 13318 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 1028431433 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 1028431433 # number of overall hits
system.cpu.dcache.ReadReq_misses 1932486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 808589 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2739616 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2739616 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 66544329000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28306423000 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 2741075 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2741075 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 69636872500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28315241500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 94850752000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 94850752000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 705815161 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 97952114000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 97952114000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 754236830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 16838 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 13541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 982750839 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 982750839 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002738 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000178 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.002788 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002788 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 34431.098045 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35078.938204 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_accesses 17063 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 13318 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 1031172508 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 1031172508 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002562 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002920 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.002658 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002658 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 36034.865194 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35018.088918 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 34621.914896 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 34621.914896 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency 35734.926626 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35734.926626 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 59000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14750 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 107019 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 469901 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 734207 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 106614 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 470081 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 735866 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1204108 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1204108 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1462780 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 72728 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1535508 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1535508 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 1205947 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1205947 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1462405 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 72723 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1535128 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1535128 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 49902321500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2361229000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52263550500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52263550500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 50067282500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2361289000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52428571500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52428571500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002072 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001939 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001562 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001562 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34114.714106 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.574084 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.001489 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001489 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34236.263210 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.631341 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1479610 # number of replacements
system.cpu.l2cache.tagsinuse 31966.303160 # Cycle average of tags in use
system.cpu.l2cache.total_refs 83557 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512330 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.055251 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 1479866 # number of replacements
system.cpu.l2cache.tagsinuse 31973.633477 # Cycle average of tags in use
system.cpu.l2cache.total_refs 82869 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.054786 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 28970.488218 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2995.814942 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.884109 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.091425 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 75230 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 107019 # number of Writeback hits
system.cpu.l2cache.occ_blocks::0 29008.320334 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2965.313143 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.090494 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 74752 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 106614 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 6637 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 81867 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 81867 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1414695 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 66084 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1480779 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1480779 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48470185000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2279814000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50749999000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50749999000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1489925 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107019 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 7 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 72721 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1562646 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1562646 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.949508 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.714286 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.908733 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.947610 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.947610 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34261.932784 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.728891 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34272.500488 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34272.500488 # average overall miss latency
system.cpu.l2cache.ReadExReq_hits 6636 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 81388 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 81388 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1415154 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1481235 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1481235 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48603615500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2279719000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50883334500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50883334500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1489906 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 106614 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 72717 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1562623 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1562623 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.949828 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.908742 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.947916 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.947916 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34345.106964 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.857463 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34351.966096 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34351.966096 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -497,31 +499,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 23 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1414672 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66084 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1480756 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1480756 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1415127 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1481208 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1481208 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43855333500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048687000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 45904020500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 45904020500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 44021028500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048574500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 46069603000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 46069603000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949492 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908733 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.947595 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.947595 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.354499 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949810 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908742 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.947899 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.947899 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.475513 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.255977 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.960942 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -199,12 +200,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

10
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 13:35:14
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 16:45:59
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 46960422500 because target called exit()
Exiting @ tick 46914279500 because target called exit()

368
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.046960 # Number of seconds simulated
sim_ticks 46960422500 # Number of ticks simulated
sim_seconds 0.046914 # Number of seconds simulated
sim_ticks 46914279500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 121209 # Simulator instruction rate (inst/s)
host_tick_rate 64432457 # Simulator tick rate (ticks/s)
host_mem_usage 201704 # Number of bytes of host memory used
host_seconds 728.83 # Real time elapsed on the host
host_inst_rate 53929 # Simulator instruction rate (inst/s)
host_tick_rate 28639497 # Simulator tick rate (ticks/s)
host_mem_usage 254456 # Number of bytes of host memory used
host_seconds 1638.10 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277221 # DTB read hits
system.cpu.dtb.read_hits 20277222 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367369 # DTB read accesses
system.cpu.dtb.read_accesses 20367370 # DTB read accesses
system.cpu.dtb.write_hits 14736811 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14744063 # DTB write accesses
system.cpu.dtb.data_hits 35014032 # DTB hits
system.cpu.dtb.data_hits 35014033 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35111432 # DTB accesses
system.cpu.itb.fetch_hits 12387546 # ITB hits
system.cpu.itb.fetch_misses 10588 # ITB misses
system.cpu.dtb.data_accesses 35111433 # DTB accesses
system.cpu.itb.fetch_hits 12380499 # ITB hits
system.cpu.itb.fetch_misses 10576 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12398134 # ITB accesses
system.cpu.itb.fetch_accesses 12391075 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 93920846 # number of cpu cycles simulated
system.cpu.numCycles 93828560 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77525843 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 305872 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24229643 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69691203 # Number of cycles cpu stages are processed.
system.cpu.activity 74.202061 # Percentage of cycles cpu is active
system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed.
system.cpu.activity 74.177435 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
@ -61,212 +61,212 @@ system.cpu.comFloats 151453 # Nu
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.cpi 1.063167 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.063167 # CPI: Total CPI of All Threads
system.cpu.ipc 0.940586 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads
system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.940586 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 18775711 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12354362 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4821711 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 15677307 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4750423 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 30.301269 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8154380 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10621331 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74177297 # Number of Reads from Int. Register File
system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126496547 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65349 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 292979 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14162850 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35055536 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4522867 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 188344 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4711211 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9061038 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 34.208000 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44765481 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35053135 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 41151668 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52769178 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 56.184735 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 51441694 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42479152 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.228673 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 50863748 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43057098 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.844027 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 71800106 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22120740 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.552535 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47858752 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46062094 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 49.043525 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 83802 # number of replacements
system.cpu.icache.tagsinuse 1886.866724 # Cycle average of tags in use
system.cpu.icache.total_refs 12270472 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 85848 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 142.932532 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 83610 # number of replacements
system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use
system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1886.866724 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.921322 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12270472 # number of ReadReq hits
system.cpu.icache.demand_hits 12270472 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12270472 # number of overall hits
system.cpu.icache.ReadReq_misses 117039 # number of ReadReq misses
system.cpu.icache.demand_misses 117039 # number of demand (read+write) misses
system.cpu.icache.overall_misses 117039 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 2068714000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 2068714000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 2068714000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12387511 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12387511 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12387511 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.009448 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.009448 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.009448 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 17675.424431 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 17675.424431 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 17675.424431 # average overall miss latency
system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits
system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12263478 # number of overall hits
system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses
system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses
system.cpu.icache.overall_misses 116984 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 1666000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 174 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 9574.712644 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 31191 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 31191 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 31191 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 85848 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 85848 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 85848 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 1347366500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 1347366500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 1347366500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006930 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.006930 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.006930 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15694.791958 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200251 # number of replacements
system.cpu.dcache.tagsinuse 4073.088977 # Cycle average of tags in use
system.cpu.dcache.total_refs 34126006 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use
system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.000279 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 486750000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4073.088977 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994406 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 20180454 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 13945552 # number of WriteReq hits
system.cpu.dcache.demand_hits 34126006 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 34126006 # number of overall hits
system.cpu.dcache.ReadReq_misses 96184 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 667825 # number of WriteReq misses
system.cpu.dcache.demand_misses 764009 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 764009 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 4158459500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 35331617000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 39490076500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39490076500 # number of overall miss cycles
system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits
system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 34126014 # number of overall hits
system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses
system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 764001 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.045700 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.021898 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021898 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 43234.420486 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 52905.502190 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 51687.972917 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 51687.972917 # average overall miss latency
system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6330419000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124111 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51006.107436 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 161216 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 35417 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 524245 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 559662 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 559662 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2088747000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 7254442500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9343189500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9343189500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34373.047871 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.438780 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 148058 # number of replacements
system.cpu.l2cache.tagsinuse 18662.722702 # Cycle average of tags in use
system.cpu.l2cache.total_refs 131525 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 173403 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.758493 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 148060 # number of replacements
system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use
system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3004.603682 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15658.119020 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.091693 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.477848 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 103488 # number of ReadReq hits
system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 115758 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 115758 # number of overall hits
system.cpu.l2cache.ReadReq_misses 42937 # number of ReadReq misses
system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 115564 # number of overall hits
system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 174437 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 174437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 2242217000 # number of ReadReq miss cycles
system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 174439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 9096602000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 9096602000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 146425 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 290195 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 290195 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.293235 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.601103 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.601103 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52221.091366 # average ReadReq miss latency
system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52148.351554 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52148.351554 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 120515 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 42937 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 174437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 174437 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1718546000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262803000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 6981349000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 6981349000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293235 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.601103 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.601103 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.827072 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40021.315589 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864

10
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:05:16
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 17:12:27
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 25567234000 because target called exit()
Exiting @ tick 24044597000 because target called exit()

786
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.025567 # Number of seconds simulated
sim_ticks 25567234000 # Number of ticks simulated
sim_seconds 0.024045 # Number of seconds simulated
sim_ticks 24044597000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 215433 # Simulator instruction rate (inst/s)
host_tick_rate 69203497 # Simulator tick rate (ticks/s)
host_mem_usage 202972 # Number of bytes of host memory used
host_seconds 369.45 # Real time elapsed on the host
host_inst_rate 91114 # Simulator instruction rate (inst/s)
host_tick_rate 27525458 # Simulator tick rate (ticks/s)
host_mem_usage 256064 # Number of bytes of host memory used
host_seconds 873.54 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 21577330 # DTB read hits
system.cpu.dtb.read_misses 171148 # DTB read misses
system.cpu.dtb.read_acv 19 # DTB read access violations
system.cpu.dtb.read_accesses 21748478 # DTB read accesses
system.cpu.dtb.write_hits 15194902 # DTB write hits
system.cpu.dtb.write_misses 30538 # DTB write misses
system.cpu.dtb.write_acv 1 # DTB write access violations
system.cpu.dtb.write_accesses 15225440 # DTB write accesses
system.cpu.dtb.data_hits 36772232 # DTB hits
system.cpu.dtb.data_misses 201686 # DTB misses
system.cpu.dtb.data_acv 20 # DTB access violations
system.cpu.dtb.data_accesses 36973918 # DTB accesses
system.cpu.itb.fetch_hits 13158718 # ITB hits
system.cpu.itb.fetch_misses 26109 # ITB misses
system.cpu.dtb.read_hits 23266854 # DTB read hits
system.cpu.dtb.read_misses 225542 # DTB read misses
system.cpu.dtb.read_acv 45 # DTB read access violations
system.cpu.dtb.read_accesses 23492396 # DTB read accesses
system.cpu.dtb.write_hits 16036454 # DTB write hits
system.cpu.dtb.write_misses 32845 # DTB write misses
system.cpu.dtb.write_acv 10 # DTB write access violations
system.cpu.dtb.write_accesses 16069299 # DTB write accesses
system.cpu.dtb.data_hits 39303308 # DTB hits
system.cpu.dtb.data_misses 258387 # DTB misses
system.cpu.dtb.data_acv 55 # DTB access violations
system.cpu.dtb.data_accesses 39561695 # DTB accesses
system.cpu.itb.fetch_hits 15336941 # ITB hits
system.cpu.itb.fetch_misses 33582 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 13184827 # ITB accesses
system.cpu.itb.fetch_accesses 15370523 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 51134470 # number of cpu cycles simulated
system.cpu.numCycles 48089197 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits
system.cpu.BPredUnit.lookups 18361326 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11820514 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 546274 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 16009789 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9688195 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 2216159 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 37765 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 16493376 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 115096464 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18361326 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11904354 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22748230 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3321567 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5575284 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 7555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 339871 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 15336941 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 325972 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 47646209 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.415648 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.066102 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 31126722 61.37% 61.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1893724 3.73% 65.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1511025 2.98% 68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1863843 3.67% 71.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3852588 7.60% 79.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1892655 3.73% 83.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 670633 1.32% 84.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1088115 2.15% 86.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6818701 13.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 24897979 52.26% 52.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2453036 5.15% 57.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1946901 4.09% 61.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2330257 4.89% 66.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4220177 8.86% 75.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2180283 4.58% 79.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 821973 1.73% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1319930 2.77% 84.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 7475673 15.69% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 47646209 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.381818 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.393395 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17905619 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 5001845 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21498707 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 855219 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2384819 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4163553 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 99872 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 112485204 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 269698 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2384819 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18579816 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2454161 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 95593 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 21627471 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 2504349 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 110486741 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 205 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 26203 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2324239 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 66683343 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 133326137 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 132820452 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 505685 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 14136462 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5422 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5420 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 5146770 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 24822811 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 17209754 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6587978 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5178123 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 97041243 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5374 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 92467963 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 130783 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 16243425 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 8385088 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 791 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 47646209 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.940720 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.968352 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 15463365 32.45% 32.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9039378 18.97% 51.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 7091354 14.88% 66.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5453112 11.45% 77.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4876639 10.24% 87.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2621564 5.50% 93.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1784714 3.75% 97.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 964783 2.02% 99.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 351300 0.74% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 47646209 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 124763 7.84% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 734633 46.19% 54.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 731207 45.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 52052276 56.29% 56.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 44017 0.05% 56.34% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 126208 0.14% 56.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 127891 0.14% 56.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 38663 0.04% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23785526 25.72% 82.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 16293239 17.62% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued
system.cpu.iq.rate 1.671631 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 92467963 # Type of FU issued
system.cpu.iq.rate 1.922843 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1590603 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.017202 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 233677952 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 112998578 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 89931166 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 625569 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 496845 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 303653 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 93745634 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 312932 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1274888 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 4546173 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 15179 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 214045 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2596377 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 1708 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 2384819 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1408212 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 65481 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 106909939 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 348634 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 24822811 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 17209754 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 5373 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 47651 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1257 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 214045 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 396366 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 133925 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 530291 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 91241048 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23498667 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1226915 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9311504 # number of nop insts executed
system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed
system.cpu.iew.exec_branches 14700654 # Number of branches executed
system.cpu.iew.exec_stores 15225695 # Number of stores executed
system.cpu.iew.exec_rate 1.660486 # Inst execution rate
system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back
system.cpu.iew.wb_producers 31039892 # num instructions producing a value
system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value
system.cpu.iew.exec_nop 9863322 # number of nop insts executed
system.cpu.iew.exec_refs 39568381 # number of memory reference insts executed
system.cpu.iew.exec_branches 15970661 # Number of branches executed
system.cpu.iew.exec_stores 16069714 # Number of stores executed
system.cpu.iew.exec_rate 1.897329 # Inst execution rate
system.cpu.iew.wb_sent 90664382 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 90234819 # cumulative count of insts written-back
system.cpu.iew.wb_producers 34760730 # num instructions producing a value
system.cpu.iew.wb_consumers 45726026 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back
system.cpu.iew.wb_rate 1.876405 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.760196 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 15596601 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 449200 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 45261390 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.951789 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.640164 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 20510945 45.32% 45.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 8049130 17.78% 63.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4022759 8.89% 71.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2704759 5.98% 77.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2151725 4.75% 82.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1309190 2.89% 85.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1156461 2.56% 88.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 811237 1.79% 89.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4545184 10.04% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 45261390 # Number of insts commited each cycle
system.cpu.commit.count 88340672 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 34890015 # Number of memory references committed
@ -288,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 4545184 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 139404893 # The number of ROB reads
system.cpu.rob.rob_writes 190882895 # The number of ROB writes
system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 143336137 # The number of ROB reads
system.cpu.rob.rob_writes 210280269 # The number of ROB writes
system.cpu.timesIdled 17593 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 442988 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads
system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 112360564 # number of integer regfile reads
system.cpu.int_regfile_writes 55786710 # number of integer regfile writes
system.cpu.fp_regfile_reads 235864 # number of floating regfile reads
system.cpu.fp_regfile_writes 240719 # number of floating regfile writes
system.cpu.misc_regfile_reads 37825 # number of misc regfile reads
system.cpu.cpi 0.604198 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.604198 # CPI: Total CPI of All Threads
system.cpu.ipc 1.655086 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.655086 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 120263319 # number of integer regfile reads
system.cpu.int_regfile_writes 59810170 # number of integer regfile writes
system.cpu.fp_regfile_reads 254298 # number of floating regfile reads
system.cpu.fp_regfile_writes 248799 # number of floating regfile writes
system.cpu.misc_regfile_reads 38083 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 83010 # number of replacements
system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use
system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits
system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits
system.cpu.icache.overall_hits 13070837 # number of overall hits
system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses
system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses
system.cpu.icache.overall_misses 87881 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency
system.cpu.icache.replacements 89120 # number of replacements
system.cpu.icache.tagsinuse 1938.678415 # Cycle average of tags in use
system.cpu.icache.total_refs 15241390 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 91168 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 167.179164 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 19910148000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1938.678415 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.946620 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 15241390 # number of ReadReq hits
system.cpu.icache.demand_hits 15241390 # number of demand (read+write) hits
system.cpu.icache.overall_hits 15241390 # number of overall hits
system.cpu.icache.ReadReq_misses 95551 # number of ReadReq misses
system.cpu.icache.demand_misses 95551 # number of demand (read+write) misses
system.cpu.icache.overall_misses 95551 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 914249000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 914249000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 914249000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 15336941 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 15336941 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 15336941 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.006230 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.006230 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.006230 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 9568.178250 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 9568.178250 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 9568.178250 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 4382 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 4382 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 4382 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 91169 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 91169 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 543344000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 543344000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 543344000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.005944 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.005944 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.005944 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5959.745089 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 201055 # number of replacements
system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use
system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 33980573 # number of overall hits
system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses
system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1192412 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 201407 # number of replacements
system.cpu.dcache.tagsinuse 4078.388125 # Cycle average of tags in use
system.cpu.dcache.total_refs 35317915 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 205503 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 171.860824 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 157900000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4078.388125 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995700 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 21738841 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 13579023 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 51 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 35317864 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 35317864 # number of overall hits
system.cpu.dcache.ReadReq_misses 251339 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1034354 # number of WriteReq misses
system.cpu.dcache.demand_misses 1285693 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1285693 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 8138657000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 33935878000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 42074535000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 42074535000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 21990180 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 36603557 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 36603557 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.011430 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.070781 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.035125 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035125 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32381.194323 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 32808.765664 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 32725.180117 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 32725.180117 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2916.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 161514 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses
system.cpu.dcache.writebacks 161690 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 189291 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 890899 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1080190 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1080190 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 62048 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 205503 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 205503 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1276790500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4734659000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 6011449500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 6011449500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002822 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.005614 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.005614 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20577.464221 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33004.489213 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 148713 # number of replacements
system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use
system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 149093 # number of replacements
system.cpu.l2cache.tagsinuse 19055.908605 # Cycle average of tags in use
system.cpu.l2cache.total_refs 137732 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 174459 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.789481 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 115146 # number of overall hits
system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 175063 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 3306.185097 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15749.723508 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.100897 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.480643 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 109176 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 161690 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 12067 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 121243 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 121243 # number of overall hits
system.cpu.l2cache.ReadReq_misses 44033 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 131396 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 175429 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 175429 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1515312500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 4525725000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 6041037500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 6041037500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 153209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 161690 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 143463 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 296672 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 296672 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.287405 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.915888 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.591323 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.591323 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34413.110622 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34443.400104 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34435.797388 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34435.797388 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -475,27 +477,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 120512 # number of writebacks
system.cpu.l2cache.writebacks 120514 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 44033 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 131396 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 175429 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 175429 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1366746000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118762500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 5485508500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 5485508500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287405 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915888 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.591323 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.591323 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31039.129744 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31346.178727 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,7 +494,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
egid=100
env=
errout=cerr

1
tests/long/50.vortex/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,17 +1,11 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 15:12:09
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 03:29:41
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 36348210000 because target called exit()
Exiting @ tick 36244603000 because target called exit()

804
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.036348 # Number of seconds simulated
sim_ticks 36348210000 # Number of ticks simulated
sim_seconds 0.036245 # Number of seconds simulated
sim_ticks 36244603000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54516 # Simulator instruction rate (inst/s)
host_tick_rate 19691005 # Simulator tick rate (ticks/s)
host_mem_usage 264076 # Number of bytes of host memory used
host_seconds 1845.93 # Real time elapsed on the host
sim_insts 100633035 # Number of instructions simulated
host_inst_rate 68946 # Simulator instruction rate (inst/s)
host_tick_rate 24831957 # Simulator tick rate (ticks/s)
host_mem_usage 266536 # Number of bytes of host memory used
host_seconds 1459.60 # Real time elapsed on the host
sim_insts 100633890 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,296 +51,300 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 72696421 # number of cpu cycles simulated
system.cpu.numCycles 72489207 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 17573172 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11453458 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 851549 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 14915035 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9554942 # Number of BTB hits
system.cpu.BPredUnit.lookups 18012293 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11774570 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 831874 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 15324494 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9861947 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1842823 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 176515 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 11675232 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 87296891 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17573172 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11397765 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22503406 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 923751 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 11675232 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 177839 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 71670018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.692121 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.915842 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 1962775 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 178630 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 13228591 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90356599 # Number of instructions fetch has processed
system.cpu.fetch.Branches 18012293 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11824722 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 23464914 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3236873 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 32247240 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1180 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12447619 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 228695 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 71274247 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.770511 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.958690 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 49181996 68.62% 68.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2373056 3.31% 71.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2569214 3.58% 75.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2298620 3.21% 78.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1644656 2.29% 81.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1723119 2.40% 83.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 990721 1.38% 84.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1380652 1.93% 86.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9507984 13.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 47826013 67.10% 67.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2503425 3.51% 70.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2625051 3.68% 74.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2508744 3.52% 77.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1756176 2.46% 80.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1729968 2.43% 82.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1023399 1.44% 84.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1314592 1.84% 85.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9986879 14.01% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 71670018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.241734 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.200842 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 25114154 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 22709447 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21527142 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 497633 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1821642 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3527413 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 94287 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 118399354 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 324192 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1821642 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 26632137 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2439992 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 16812666 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20410601 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3552980 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 115899857 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 27143 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2453549 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 118034319 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 532748209 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 532647632 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 100577 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99142525 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 18891789 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 756618 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 756606 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 10359843 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29552116 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22027852 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 13146932 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13132796 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 110916590 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 749122 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 106735970 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 111004 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10702418 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 27336640 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 48262 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 71670018 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.489269 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.647816 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 71274247 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.248482 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.246483 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15570258 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 30538007 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21052115 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1880159 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2233708 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3555145 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 100131 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 123096705 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 322054 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2233708 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 17831809 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 3189949 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20082985 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20587918 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 7347878 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 119869132 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 121794 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5771428 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 121512131 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 551578616 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 551477586 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 101030 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99143893 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 22368233 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 776347 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 776986 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 18154637 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 30367199 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22985654 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 18156398 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 16040246 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 114470256 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 775996 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107895562 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 172092 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 14439119 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 40080708 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 74965 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 71274247 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.513809 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.644216 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 26697633 37.25% 37.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 17182939 23.98% 61.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10552290 14.72% 75.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7611894 10.62% 86.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5202284 7.26% 93.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2658918 3.71% 97.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1053563 1.47% 99.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 496311 0.69% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 214186 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 25395561 35.63% 35.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 17825655 25.01% 60.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10968613 15.39% 76.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7406587 10.39% 86.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5364628 7.53% 93.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2359706 3.31% 97.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1195437 1.68% 98.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 581224 0.82% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 176836 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 71670018 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 71274247 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 81861 4.61% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1408075 79.27% 83.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 286311 16.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 116212 6.09% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1547826 81.16% 87.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 243196 12.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 56941286 53.35% 53.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 86568 0.08% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28575402 26.77% 80.20% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21132684 19.80% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57756458 53.53% 53.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 87061 0.08% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28748785 26.65% 80.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21303228 19.74% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 106735970 # Type of FU issued
system.cpu.iq.rate 1.468242 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1776247 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016642 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 287029038 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 122376660 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105058655 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 171 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 178 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 108512130 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1096048 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 107895562 # Type of FU issued
system.cpu.iq.rate 1.488436 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1907234 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.017677 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 289144533 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 129693775 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105980227 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 164 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 164 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 109802713 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1086375 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2243776 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 9239 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1470884 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 3058688 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1951 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 8954 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2428515 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1821642 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 971169 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 52846 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 111742721 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 886869 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29552116 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22027852 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 732058 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3681 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5880 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 9239 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 680356 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 238968 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 919324 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 105624762 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28223458 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1111208 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 2233708 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1028781 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 38378 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 115325010 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 602761 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 30367199 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22985654 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 758781 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 5441 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5622 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 8954 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 689500 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 204403 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 893903 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 106692632 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28420136 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1202930 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 77009 # number of nop insts executed
system.cpu.iew.exec_refs 49234670 # number of memory reference insts executed
system.cpu.iew.exec_branches 14652571 # Number of branches executed
system.cpu.iew.exec_stores 21011212 # Number of stores executed
system.cpu.iew.exec_rate 1.452957 # Inst execution rate
system.cpu.iew.wb_sent 105223313 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105058729 # cumulative count of insts written-back
system.cpu.iew.wb_producers 51964381 # num instructions producing a value
system.cpu.iew.wb_consumers 99748825 # num instructions consuming a value
system.cpu.iew.exec_nop 78758 # number of nop insts executed
system.cpu.iew.exec_refs 49527893 # number of memory reference insts executed
system.cpu.iew.exec_branches 14765827 # Number of branches executed
system.cpu.iew.exec_stores 21107757 # Number of stores executed
system.cpu.iew.exec_rate 1.471842 # Inst execution rate
system.cpu.iew.wb_sent 106228534 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105980298 # cumulative count of insts written-back
system.cpu.iew.wb_producers 55087779 # num instructions producing a value
system.cpu.iew.wb_consumers 106077594 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.445171 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.520952 # average fanout of values written-back
system.cpu.iew.wb_rate 1.462015 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.519316 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 100638587 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 11026953 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 700860 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 821298 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 69848377 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.440815 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.128695 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 100639442 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 14606204 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 701031 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 796162 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 69040540 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.457686 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.138867 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 31252601 44.74% 44.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 20067748 28.73% 73.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4700774 6.73% 80.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4062261 5.82% 86.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3060219 4.38% 90.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1682719 2.41% 92.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 680213 0.97% 93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 487977 0.70% 94.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3853865 5.52% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 30680365 44.44% 44.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 19612880 28.41% 72.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4794365 6.94% 79.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4311364 6.24% 86.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3142866 4.55% 90.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1355731 1.96% 92.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 737162 1.07% 93.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 515807 0.75% 94.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3890000 5.63% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 69848377 # Number of insts commited each cycle
system.cpu.commit.count 100638587 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 69040540 # Number of insts commited each cycle
system.cpu.commit.count 100639442 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47865307 # Number of memory references committed
system.cpu.commit.loads 27308339 # Number of loads committed
system.cpu.commit.refs 47865649 # Number of memory references committed
system.cpu.commit.loads 27308510 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.branches 13669858 # Number of branches committed
system.cpu.commit.branches 13670029 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91477707 # Number of committed integer instructions.
system.cpu.commit.int_insts 91478391 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 3853865 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 3890000 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 177634753 # The number of ROB reads
system.cpu.rob.rob_writes 225156428 # The number of ROB writes
system.cpu.timesIdled 61363 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1026403 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 100633035 # Number of Instructions Simulated
system.cpu.committedInsts_total 100633035 # Number of Instructions Simulated
system.cpu.cpi 0.722391 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.722391 # CPI: Total CPI of All Threads
system.cpu.ipc 1.384291 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.384291 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 508078422 # number of integer regfile reads
system.cpu.int_regfile_writes 103555080 # number of integer regfile writes
system.cpu.fp_regfile_reads 153 # number of floating regfile reads
system.cpu.fp_regfile_writes 125 # number of floating regfile writes
system.cpu.misc_regfile_reads 144338885 # number of misc regfile reads
system.cpu.misc_regfile_writes 34300 # number of misc regfile writes
system.cpu.icache.replacements 23105 # number of replacements
system.cpu.icache.tagsinuse 1790.585512 # Cycle average of tags in use
system.cpu.icache.total_refs 11649212 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 25136 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 463.447327 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 180370887 # The number of ROB reads
system.cpu.rob.rob_writes 232731384 # The number of ROB writes
system.cpu.timesIdled 61980 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1214960 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 100633890 # Number of Instructions Simulated
system.cpu.committedInsts_total 100633890 # Number of Instructions Simulated
system.cpu.cpi 0.720326 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.720326 # CPI: Total CPI of All Threads
system.cpu.ipc 1.388260 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.388260 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 512693416 # number of integer regfile reads
system.cpu.int_regfile_writes 104594218 # number of integer regfile writes
system.cpu.fp_regfile_reads 142 # number of floating regfile reads
system.cpu.fp_regfile_writes 118 # number of floating regfile writes
system.cpu.misc_regfile_reads 148024846 # number of misc regfile reads
system.cpu.misc_regfile_writes 34642 # number of misc regfile writes
system.cpu.icache.replacements 27879 # number of replacements
system.cpu.icache.tagsinuse 1824.272906 # Cycle average of tags in use
system.cpu.icache.total_refs 12416599 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 29916 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 415.048770 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1790.585512 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.874309 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 11649212 # number of ReadReq hits
system.cpu.icache.demand_hits 11649212 # number of demand (read+write) hits
system.cpu.icache.overall_hits 11649212 # number of overall hits
system.cpu.icache.ReadReq_misses 26020 # number of ReadReq misses
system.cpu.icache.demand_misses 26020 # number of demand (read+write) misses
system.cpu.icache.overall_misses 26020 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 329928500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 329928500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 329928500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 11675232 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 11675232 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 11675232 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.002229 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.002229 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.002229 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12679.803997 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12679.803997 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12679.803997 # average overall miss latency
system.cpu.icache.occ_blocks::0 1824.272906 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.890758 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12416599 # number of ReadReq hits
system.cpu.icache.demand_hits 12416599 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12416599 # number of overall hits
system.cpu.icache.ReadReq_misses 31020 # number of ReadReq misses
system.cpu.icache.demand_misses 31020 # number of demand (read+write) misses
system.cpu.icache.overall_misses 31020 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 368970500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 368970500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 368970500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12447619 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12447619 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12447619 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.002492 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.002492 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.002492 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 11894.600258 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 11894.600258 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 11894.600258 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -350,145 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 875 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 875 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 875 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 25145 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 25145 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 25145 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 1093 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1093 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1093 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 29927 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 29927 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 29927 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 230769000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 230769000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 230769000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 251359000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 251359000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 251359000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.002154 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.002154 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.002154 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 9177.530324 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.002404 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.002404 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.002404 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8399.071073 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157197 # number of replacements
system.cpu.dcache.tagsinuse 4074.737833 # Cycle average of tags in use
system.cpu.dcache.total_refs 45133660 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 161293 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 279.824047 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 314597000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4074.737833 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994809 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 26793039 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 18304159 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 19298 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 17149 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 45097198 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 45097198 # number of overall hits
system.cpu.dcache.ReadReq_misses 104208 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1545742 # number of WriteReq misses
system.cpu.dcache.replacements 157560 # number of replacements
system.cpu.dcache.tagsinuse 4075.609715 # Cycle average of tags in use
system.cpu.dcache.total_refs 45320510 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 161656 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 280.351549 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 305782000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4075.609715 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995022 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 26986553 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 18297687 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 18928 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 17320 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 45284240 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 45284240 # number of overall hits
system.cpu.dcache.ReadReq_misses 104971 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1552214 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1649950 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1649950 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2387617500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 50445288500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 403500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 52832906000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 52832906000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 26897247 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses 1657185 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1657185 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2340490500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 51751425000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 435500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 54091915500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 54091915500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 27091524 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 19329 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 17149 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 46747148 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 46747148 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.077872 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001604 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.035295 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035295 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 32020.913361 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 32020.913361 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 18959 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 17320 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 46941425 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 46941425 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.003875 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.078198 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001635 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.035303 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035303 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 22296.543807 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33340.393142 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 32640.843056 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 32640.843056 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 170000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 165500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 123219 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 49816 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1438831 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 123328 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 50205 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1445313 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1488647 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1488647 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 54392 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106911 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 161303 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 161303 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 1495518 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1495518 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 54766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106901 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 161667 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 161667 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1030956000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3651524500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4682480500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4682480500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1030464500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3652588500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4683053000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4683053000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003451 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003451 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.770734 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.954463 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 114546 # number of replacements
system.cpu.l2cache.tagsinuse 18280.291791 # Cycle average of tags in use
system.cpu.l2cache.total_refs 68908 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 133392 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.516583 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 114937 # number of replacements
system.cpu.l2cache.tagsinuse 18374.975698 # Cycle average of tags in use
system.cpu.l2cache.total_refs 73734 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 133793 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.551105 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2302.452210 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15977.839581 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.070265 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487605 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 47261 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 123219 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 4298 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 51559 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 51559 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32262 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 134867 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 134867 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1107753000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3528908000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4636661000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4636661000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 79523 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 123219 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 9 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106903 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 186426 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 186426 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.405694 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.444444 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.959795 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.723434 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.723434 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 8500 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34379.507218 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34379.507218 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 2397.200904 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15977.774794 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.073157 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487603 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 51991 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 123328 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 4303 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 56294 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 56294 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32687 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 7 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 102588 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 135275 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 135275 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1117411000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3525778500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4643189500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4643189500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 84678 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 123328 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106891 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 191569 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 191569 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.386015 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.959744 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.706142 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.706142 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34185.180653 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.332554 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34324.076880 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34324.076880 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -497,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 88455 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 63 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32199 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 134804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 134804 # number of overall MSHR misses
system.cpu.l2cache.writebacks 88452 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32606 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 102588 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 135194 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 135194 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1001736500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205255000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 4206991500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 4206991500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012684500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 217000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200382500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 4213067000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 4213067000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404902 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.444444 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959795 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.723097 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.723097 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.385059 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959744 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.705720 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.705720 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.225480 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -199,12 +200,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

10
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 08:31:13
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 17:14:45
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1016488689500 because target called exit()
Exiting @ tick 1009857089500 because target called exit()

298
tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.016489 # Number of seconds simulated
sim_ticks 1016488689500 # Number of ticks simulated
sim_seconds 1.009857 # Number of seconds simulated
sim_ticks 1009857089500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 111625 # Simulator instruction rate (inst/s)
host_tick_rate 62351436 # Simulator tick rate (ticks/s)
host_mem_usage 193064 # Number of bytes of host memory used
host_seconds 16302.57 # Real time elapsed on the host
host_inst_rate 45175 # Simulator instruction rate (inst/s)
host_tick_rate 25069239 # Simulator tick rate (ticks/s)
host_mem_usage 245844 # Number of bytes of host memory used
host_seconds 40282.72 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444614416 # DTB read hits
system.cpu.dtb.read_hits 444614420 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449511494 # DTB read accesses
system.cpu.dtb.write_hits 160920901 # DTB write hits
system.cpu.dtb.read_accesses 449511498 # DTB read accesses
system.cpu.dtb.write_hits 160920903 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162622205 # DTB write accesses
system.cpu.dtb.data_hits 605535317 # DTB hits
system.cpu.dtb.write_accesses 162622207 # DTB write accesses
system.cpu.dtb.data_hits 605535323 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612133699 # DTB accesses
system.cpu.itb.fetch_hits 237932826 # ITB hits
system.cpu.dtb.data_accesses 612133705 # DTB accesses
system.cpu.itb.fetch_hits 233080732 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 237932848 # ITB accesses
system.cpu.itb.fetch_accesses 233080754 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2032977380 # number of cpu cycles simulated
system.cpu.numCycles 2019714180 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1759886457 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7533536 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 440243372 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1592734008 # Number of cycles cpu stages are processed.
system.cpu.activity 78.344896 # Percentage of cycles cpu is active
system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed.
system.cpu.activity 78.072669 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@ -61,85 +61,85 @@ system.cpu.comFloats 190 # Nu
system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total)
system.cpu.cpi 1.117156 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.117156 # CPI: Total CPI of All Threads
system.cpu.ipc 0.895131 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads
system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.895131 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 338882102 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 262365824 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 145832523 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 223761389 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 153206045 # Number of BTB hits
system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 68.468490 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 189687399 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 149194703 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1667621622 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3043824239 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 226 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 571 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 655476684 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617179738 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 132311663 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 6922402 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 139234065 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 75965071 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 64.700104 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1137833135 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617252269 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 823371490 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1209605890 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.499230 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1094712452 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 938264928 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.152256 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1056818268 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 976159112 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.016231 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1623201304 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409776076 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.156450 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 1008711848 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1024265532 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.382535 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 664.417711 # Cycle average of tags in use
system.cpu.icache.total_refs 237931761 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use
system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277309.744755 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 664.417711 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.324423 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 237931761 # number of ReadReq hits
system.cpu.icache.demand_hits 237931761 # number of demand (read+write) hits
system.cpu.icache.overall_hits 237931761 # number of overall hits
system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits
system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits
system.cpu.icache.overall_hits 233079667 # number of overall hits
system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses
system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1062 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 58372500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 58372500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 58372500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 237932823 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 237932823 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 237932823 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 54964.689266 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 54964.689266 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 54964.689266 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 81000 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
@ -150,97 +150,97 @@ system.cpu.icache.ReadReq_mshr_misses 858 # nu
system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 45874500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45874500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45874500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53466.783217 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107352 # number of replacements
system.cpu.dcache.tagsinuse 4082.698985 # Cycle average of tags in use
system.cpu.dcache.total_refs 595070238 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use
system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310172 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12613555000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4082.698985 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.996753 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 437271427 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 157798811 # number of WriteReq hits
system.cpu.dcache.demand_hits 595070238 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 595070238 # number of overall hits
system.cpu.dcache.ReadReq_misses 7324236 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 2929691 # number of WriteReq misses
system.cpu.dcache.demand_misses 10253927 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 10253927 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 180890019000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 110280256500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 291170275500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 291170275500 # number of overall miss cycles
system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits
system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 595070081 # number of overall hits
system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses
system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 10254084 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.018228 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 24697.459093 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 37642.282582 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 28395.977024 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 28395.977024 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10999500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8090380500 # number of cycles access was blocked
system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208980 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.882651 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38713.659202 # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3058572 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 101954 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1040525 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1142479 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1142479 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 156087353000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 59191861000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 215279214000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 215279214000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.916151 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.270960 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686299 # number of replacements
system.cpu.l2cache.tagsinuse 26362.253179 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 225759748000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15507.582634 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10854.670545 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.473254 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.331258 # Average percentage of cache occupancy
system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits
@ -250,10 +250,10 @@ system.cpu.l2cache.ReadReq_misses 1807881 # nu
system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2697156 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 94453448000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 46507349000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 140960797000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 140960797000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses)
@ -263,10 +263,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.250305 # mi
system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52245.390045 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.050659 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52262.752692 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52262.752692 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
@ -283,19 +283,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 889275 # nu
system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 72354306000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671086000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 108025392000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 108025392000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.608723 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.547862 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864

10
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:58:23
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 17:16:45
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 701966325500 because target called exit()
Exiting @ tick 635013348500 because target called exit()

784
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.701966 # Number of seconds simulated
sim_ticks 701966325500 # Number of ticks simulated
sim_seconds 0.635013 # Number of seconds simulated
sim_ticks 635013348500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 187255 # Simulator instruction rate (inst/s)
host_tick_rate 75716158 # Simulator tick rate (ticks/s)
host_mem_usage 193592 # Number of bytes of host memory used
host_seconds 9271.02 # Real time elapsed on the host
host_inst_rate 68058 # Simulator instruction rate (inst/s)
host_tick_rate 24894495 # Simulator tick rate (ticks/s)
host_mem_usage 246392 # Number of bytes of host memory used
host_seconds 25508.18 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 563960671 # DTB read hits
system.cpu.dtb.read_misses 9341526 # DTB read misses
system.cpu.dtb.read_hits 603338361 # DTB read hits
system.cpu.dtb.read_misses 10295627 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 573302197 # DTB read accesses
system.cpu.dtb.write_hits 197357333 # DTB write hits
system.cpu.dtb.write_misses 6267768 # DTB write misses
system.cpu.dtb.read_accesses 613633988 # DTB read accesses
system.cpu.dtb.write_hits 208599183 # DTB write hits
system.cpu.dtb.write_misses 6680918 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 203625101 # DTB write accesses
system.cpu.dtb.data_hits 761318004 # DTB hits
system.cpu.dtb.data_misses 15609294 # DTB misses
system.cpu.dtb.write_accesses 215280101 # DTB write accesses
system.cpu.dtb.data_hits 811937544 # DTB hits
system.cpu.dtb.data_misses 16976545 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 776927298 # DTB accesses
system.cpu.itb.fetch_hits 346935606 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.dtb.data_accesses 828914089 # DTB accesses
system.cpu.itb.fetch_hits 391544242 # ITB hits
system.cpu.itb.fetch_misses 36 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 346935639 # ITB accesses
system.cpu.itb.fetch_accesses 391544278 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 1403932652 # number of cpu cycles simulated
system.cpu.numCycles 1270026698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits
system.cpu.BPredUnit.lookups 374312464 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 289169438 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 19496445 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 340941395 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 334345011 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed
system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 24666648 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1937 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 404704037 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3147798119 # Number of instructions fetch has processed
system.cpu.fetch.Branches 374312464 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 359011659 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 616794499 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 137998027 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 125668111 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 391544242 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 8927962 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1258617999 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.500996 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.012045 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 848087817 60.78% 60.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 47124000 3.38% 64.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30216424 2.17% 66.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 49573099 3.55% 69.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 121201096 8.69% 78.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 67474425 4.84% 83.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 44590738 3.20% 86.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37036211 2.65% 89.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 149944946 10.75% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 641823500 50.99% 50.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 53319636 4.24% 55.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 35799554 2.84% 58.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 54964384 4.37% 62.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 137079474 10.89% 73.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 75209346 5.98% 79.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 52974044 4.21% 83.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 43807155 3.48% 87.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 163640906 13.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 1258617999 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.294728 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.478529 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 434225808 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 112156946 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 585871640 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 14914010 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 111449595 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 58364893 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 867 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3066482661 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1948 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 111449595 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 456759816 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 64512146 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 4249 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 576631270 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 49260923 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2982899565 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 509098 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 7685931 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 38326944 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2232338965 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3854814610 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3853783957 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1030653 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 50 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 856136002 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 193 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 190 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 103200080 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 676333170 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 252017068 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 107962644 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 56514638 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2687392423 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 179 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2469741583 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1752104 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 940434860 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 416211296 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 150 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1258617999 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.962265 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.926131 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 411515074 32.70% 32.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 202456949 16.09% 48.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 202249342 16.07% 64.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 156364195 12.42% 77.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 139152023 11.06% 88.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 73667183 5.85% 94.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 48795801 3.88% 98.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 19364904 1.54% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5052528 0.40% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1258617999 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 3576452 24.84% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9406298 65.33% 90.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1415397 9.83% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1617611726 65.50% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 92 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 252 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 146 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 18 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 631548427 25.57% 91.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 220580878 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued
system.cpu.iq.rate 1.640295 # Inst issue rate
system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2469741583 # Type of FU issued
system.cpu.iq.rate 1.944638 # Inst issue rate
system.cpu.iq.fu_busy_cnt 14398147 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.005830 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6212471762 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3627257196 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2370962102 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 1779654 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1040695 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 834376 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2483251910 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 887820 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 52535371 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 231737507 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 276679 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 497053 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 91288566 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 59 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 156775 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 111449595 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23764552 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1337877 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2830649403 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12818049 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 676333170 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 252017068 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 179 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 569958 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 21987 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 497053 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 20334660 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2042240 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 22376900 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2418005225 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 613634241 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 51736358 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 128264130 # number of nop insts executed
system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed
system.cpu.iew.exec_branches 278210520 # Number of branches executed
system.cpu.iew.exec_stores 203625107 # Number of stores executed
system.cpu.iew.exec_rate 1.613458 # Inst execution rate
system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1225810379 # num instructions producing a value
system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value
system.cpu.iew.exec_nop 143256801 # number of nop insts executed
system.cpu.iew.exec_refs 828914361 # number of memory reference insts executed
system.cpu.iew.exec_branches 295415710 # Number of branches executed
system.cpu.iew.exec_stores 215280120 # Number of stores executed
system.cpu.iew.exec_rate 1.903901 # Inst execution rate
system.cpu.iew.wb_sent 2397586638 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2371796478 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1365189773 # num instructions producing a value
system.cpu.iew.wb_consumers 1727887810 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back
system.cpu.iew.wb_rate 1.867517 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.790092 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 780151578 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 19495666 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1147168404 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.586323 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.463059 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 609653045 53.14% 53.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 194676784 16.97% 70.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 91786029 8.00% 78.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 52706326 4.59% 82.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 37714625 3.29% 86.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27440530 2.39% 88.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 24523987 2.14% 90.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 21129390 1.84% 92.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 87537688 7.63% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1147168404 # Number of insts commited each cycle
system.cpu.commit.count 1819780126 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
@ -288,50 +290,50 @@ system.cpu.commit.branches 214632552 # Nu
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 87537688 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3541690829 # The number of ROB reads
system.cpu.rob.rob_writes 4844528665 # The number of ROB writes
system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 3573783220 # The number of ROB reads
system.cpu.rob.rob_writes 5311487808 # The number of ROB writes
system.cpu.timesIdled 516531 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11408699 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads
system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads
system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes
system.cpu.fp_regfile_reads 788 # number of floating regfile reads
system.cpu.fp_regfile_writes 457 # number of floating regfile writes
system.cpu.cpi 0.731564 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.731564 # CPI: Total CPI of All Threads
system.cpu.ipc 1.366935 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.366935 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3252607111 # number of integer regfile reads
system.cpu.int_regfile_writes 1898786107 # number of integer regfile writes
system.cpu.fp_regfile_reads 15156 # number of floating regfile reads
system.cpu.fp_regfile_writes 507 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use
system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 750.127276 # Cycle average of tags in use
system.cpu.icache.total_refs 391542886 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 415209.847296 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits
system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits
system.cpu.icache.overall_hits 346934350 # number of overall hits
system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses
system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1256 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency
system.cpu.icache.occ_blocks::0 750.127276 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.366273 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 391542886 # number of ReadReq hits
system.cpu.icache.demand_hits 391542886 # number of demand (read+write) hits
system.cpu.icache.overall_hits 391542886 # number of overall hits
system.cpu.icache.ReadReq_misses 1356 # number of ReadReq misses
system.cpu.icache.demand_misses 1356 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1356 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 47427000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 47427000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 47427000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 391544242 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 391544242 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 391544242 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 34975.663717 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34975.663717 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34975.663717 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -341,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 33462000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 33462000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35484.623542 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9157179 # number of replacements
system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use
system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits
system.cpu.dcache.replacements 9159383 # number of replacements
system.cpu.dcache.tagsinuse 4087.248136 # Cycle average of tags in use
system.cpu.dcache.total_refs 696439531 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9163479 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 76.001651 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5155151000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4087.248136 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997863 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 540576764 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 155862765 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 670151455 # number of overall hits
system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses
system.cpu.dcache.demand_hits 696439529 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 696439529 # number of overall hits
system.cpu.dcache.ReadReq_misses 10153388 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4865737 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 14741918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 15019125 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 15019125 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 168572903500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 135364757471 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 303937660971 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 303937660971 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 550730152 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses
system.cpu.dcache.demand_accesses 711458654 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 711458654 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.018436 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.030273 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency
system.cpu.dcache.demand_miss_rate 0.021110 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021110 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16602.625990 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27819.990573 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked
system.cpu.dcache.demand_avg_miss_latency 20236.708928 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 20236.708928 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 117209937 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2148380000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 37031 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 65114 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3165.184224 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 32994.133366 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3077964 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses
system.cpu.dcache.writebacks 3077410 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2875087 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 2980560 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5855647 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5855647 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7278301 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1885177 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_misses 9163478 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9163478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 80739671500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 38395339625 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 119135011125 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 119135011125 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013216 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011729 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.012880 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.012880 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11093.203139 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20366.967996 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2693244 # number of replacements
system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6458351 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2703837 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked
system.cpu.l2cache.replacements 2693761 # number of replacements
system.cpu.l2cache.tagsinuse 26701.570875 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7632488 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2718396 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.807717 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 128397458500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15961.645382 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10739.925493 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.487111 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.327757 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5458441 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3077410 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 1001668 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6460109 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6460109 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1820800 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 883513 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2704313 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2704313 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 62491098500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 30447807000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 92938905500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 92938905500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7279241 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3077410 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1885181 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9164422 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9164422 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.250136 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.468662 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.295088 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.295088 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34320.682392 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34462.205989 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34366.918881 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34366.918881 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 17342500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1668 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10397.182254 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 1171773 # number of writebacks
system.cpu.l2cache.writebacks 1171800 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 1820800 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 883513 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2704313 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2704313 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 56720900500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 27626952000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 84347852500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 84347852500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250136 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468662 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.295088 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.295088 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.636918 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.434632 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

1
tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 19:27:10
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 03:49:53
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -30,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 566011920000 because target called exit()
Exiting @ tick 524441606000 because target called exit()

797
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.566012 # Number of seconds simulated
sim_ticks 566011920000 # Number of ticks simulated
sim_seconds 0.524442 # Number of seconds simulated
sim_ticks 524441606000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 52057 # Simulator instruction rate (inst/s)
host_tick_rate 17100212 # Simulator tick rate (ticks/s)
host_mem_usage 255500 # Number of bytes of host memory used
host_seconds 33099.70 # Real time elapsed on the host
sim_insts 1723073884 # Number of instructions simulated
host_inst_rate 101251 # Simulator instruction rate (inst/s)
host_tick_rate 30817067 # Simulator tick rate (ticks/s)
host_mem_usage 257952 # Number of bytes of host memory used
host_seconds 17017.90 # Real time elapsed on the host
sim_insts 1723073904 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,297 +51,300 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1132023841 # number of cpu cycles simulated
system.cpu.numCycles 1048883213 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 287218932 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 236434259 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18348095 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 250920104 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 213740165 # Number of BTB hits
system.cpu.BPredUnit.lookups 317450426 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 259852467 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18436703 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 279904663 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 254677721 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18278609 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 393 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 265451297 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2081730004 # Number of instructions fetch has processed
system.cpu.fetch.Branches 287218932 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 232018774 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 452716467 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 20281434 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 265451297 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5801201 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1120688032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.061143 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.942664 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 20220648 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 4428 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 315501768 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2280935015 # Number of instructions fetch has processed
system.cpu.fetch.Branches 317450426 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 274898369 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 509081814 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 103935328 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 124227879 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 270 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 303015456 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6379891 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1031116877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.459992 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.013809 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 667971623 59.60% 59.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32961041 2.94% 62.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 55903718 4.99% 67.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 56895013 5.08% 72.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 45557119 4.07% 76.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 54242890 4.84% 81.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 48750643 4.35% 85.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18749981 1.67% 87.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 139656004 12.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 522035116 50.63% 50.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 37818104 3.67% 54.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 65533745 6.36% 60.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 69512456 6.74% 67.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 53414736 5.18% 72.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 61047606 5.92% 78.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 57075579 5.54% 84.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 19670108 1.91% 85.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 145009427 14.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1120688032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.253722 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.838945 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 546126816 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 71463989 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 435974123 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 6702645 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 60420459 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 43189829 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 635 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2259641783 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2302 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 60420459 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 563998095 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 40175582 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14256 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 424146965 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 31932675 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2194117520 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 11722 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3482918 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 25684334 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2171048745 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10125608138 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10125607580 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 558 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706320007 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 464728733 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 633 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 629 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 66642282 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 598549667 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 212535274 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 87730642 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 84698913 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2112468775 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 616 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1975042527 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 852567 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 380766314 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 858455180 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1120688032 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.762348 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.680120 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 1031116877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.302656 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.174632 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 346461175 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 106173290 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 477865699 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 18312225 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 82304488 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 48528259 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2473135818 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2289 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 82304488 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 368931509 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 50902781 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20077 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 472181274 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 56776748 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2411760057 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 18939 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5901279 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 44092765 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2386823429 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 11134835710 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 11134834246 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1464 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706320039 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 680503385 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 855 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 848 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 119214990 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 651763451 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 230362141 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 123114303 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 108844207 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2285934828 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 851 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2067906375 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3040241 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 557691684 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1352307582 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 383 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1031116877 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.005501 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.810247 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 337912961 30.15% 30.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 234234895 20.90% 51.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 220010483 19.63% 70.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 141420525 12.62% 83.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 101836492 9.09% 92.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 53894209 4.81% 97.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 20983167 1.87% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 9353324 0.83% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1041976 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 302093175 29.30% 29.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 161453829 15.66% 44.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 185974655 18.04% 62.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 152722281 14.81% 77.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 122859599 11.92% 89.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 63855935 6.19% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 30343304 2.94% 98.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10954294 1.06% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 859805 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1120688032 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1031116877 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 517494 2.12% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 1 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 23433886 96.11% 98.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 430313 1.76% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 735734 3.76% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 145 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 17865428 91.35% 95.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 956298 4.89% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1219473147 61.74% 61.74% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1083372 0.05% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 566098039 28.66% 90.46% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 188387953 9.54% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1267972738 61.32% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1165735 0.06% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 9 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 605808033 29.30% 90.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 192959848 9.33% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1975042527 # Type of FU issued
system.cpu.iq.rate 1.744700 # Inst issue rate
system.cpu.iq.fu_busy_cnt 24381694 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5096007233 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2495143403 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1922135162 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 114 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1999424161 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 34829517 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2067906375 # Type of FU issued
system.cpu.iq.rate 1.971532 # Inst issue rate
system.cpu.iq.fu_busy_cnt 19557605 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009458 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5189527225 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2846700346 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1993811028 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 105 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2087463854 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 48700640 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 112622888 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 463072 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1914554 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 37688221 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 165836668 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 182984 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 3082033 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 55515084 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 273360 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 451401 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 60420459 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 18632955 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1195402 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2112469674 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 6157143 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 598549667 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 212535274 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 546 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 334650 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 56652 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1914554 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 16889121 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3256921 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 20146042 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1946822051 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 556717785 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 28220476 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 82304488 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 22549936 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1320929 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2286019853 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 6521602 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 651763451 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 230362141 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 777 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 333118 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 65136 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 3082033 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18892989 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1847041 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 20740030 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2026288483 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 583345448 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 41617892 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 283 # number of nop insts executed
system.cpu.iew.exec_refs 742905406 # number of memory reference insts executed
system.cpu.iew.exec_branches 235411550 # Number of branches executed
system.cpu.iew.exec_stores 186187621 # Number of stores executed
system.cpu.iew.exec_rate 1.719771 # Inst execution rate
system.cpu.iew.wb_sent 1926889510 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1922135210 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1211916900 # num instructions producing a value
system.cpu.iew.wb_consumers 1896005064 # num instructions consuming a value
system.cpu.iew.exec_nop 84174 # number of nop insts executed
system.cpu.iew.exec_refs 773137523 # number of memory reference insts executed
system.cpu.iew.exec_branches 241378100 # Number of branches executed
system.cpu.iew.exec_stores 189792075 # Number of stores executed
system.cpu.iew.exec_rate 1.931853 # Inst execution rate
system.cpu.iew.wb_sent 2004592772 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1993811133 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1313765556 # num instructions producing a value
system.cpu.iew.wb_consumers 2094642495 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.697964 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.639195 # average fanout of values written-back
system.cpu.iew.wb_rate 1.900890 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.627203 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1723073902 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 389560093 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 464 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18347567 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1060267574 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.625131 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.338631 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 1723073922 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 563083903 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 468 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18443845 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 948812390 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.816032 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.570732 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 472290035 44.54% 44.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 255203775 24.07% 68.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 110318720 10.40% 79.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 55061761 5.19% 84.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28404469 2.68% 86.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27943387 2.64% 89.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20897685 1.97% 91.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 17855453 1.68% 93.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 72292289 6.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 421119309 44.38% 44.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 219659546 23.15% 67.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 84920332 8.95% 76.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 40130029 4.23% 80.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24924955 2.63% 83.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30334777 3.20% 86.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 23612661 2.49% 89.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12752294 1.34% 90.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 91358487 9.63% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1060267574 # Number of insts commited each cycle
system.cpu.commit.count 1723073902 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 948812390 # Number of insts commited each cycle
system.cpu.commit.count 1723073922 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773831 # Number of memory references committed
system.cpu.commit.loads 485926778 # Number of loads committed
system.cpu.commit.refs 660773839 # Number of memory references committed
system.cpu.commit.loads 485926782 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462372 # Number of branches committed
system.cpu.commit.branches 213462376 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions.
system.cpu.commit.int_insts 1536941897 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 72292289 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 91358487 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3100608681 # The number of ROB reads
system.cpu.rob.rob_writes 4285815110 # The number of ROB writes
system.cpu.timesIdled 696063 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11335809 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1723073884 # Number of Instructions Simulated
system.cpu.committedInsts_total 1723073884 # Number of Instructions Simulated
system.cpu.cpi 0.656979 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.656979 # CPI: Total CPI of All Threads
system.cpu.ipc 1.522118 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.522118 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9738255749 # number of integer regfile reads
system.cpu.int_regfile_writes 1902471542 # number of integer regfile writes
system.cpu.fp_regfile_reads 36 # number of floating regfile reads
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
system.cpu.misc_regfile_reads 2800450937 # number of misc regfile reads
system.cpu.misc_regfile_writes 140 # number of misc regfile writes
system.cpu.rob.rob_reads 3143611129 # The number of ROB reads
system.cpu.rob.rob_writes 4654874733 # The number of ROB writes
system.cpu.timesIdled 997575 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 17766336 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1723073904 # Number of Instructions Simulated
system.cpu.committedInsts_total 1723073904 # Number of Instructions Simulated
system.cpu.cpi 0.608728 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.608728 # CPI: Total CPI of All Threads
system.cpu.ipc 1.642770 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.642770 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10134733413 # number of integer regfile reads
system.cpu.int_regfile_writes 1980533280 # number of integer regfile writes
system.cpu.fp_regfile_reads 92 # number of floating regfile reads
system.cpu.fp_regfile_writes 35 # number of floating regfile writes
system.cpu.misc_regfile_reads 3028358925 # number of misc regfile reads
system.cpu.misc_regfile_writes 148 # number of misc regfile writes
system.cpu.icache.replacements 9 # number of replacements
system.cpu.icache.tagsinuse 573.017722 # Cycle average of tags in use
system.cpu.icache.total_refs 265450383 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 717 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 370223.686192 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 611.010403 # Cycle average of tags in use
system.cpu.icache.total_refs 303014437 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 739 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 410033.067659 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 573.017722 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.279794 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 265450383 # number of ReadReq hits
system.cpu.icache.demand_hits 265450383 # number of demand (read+write) hits
system.cpu.icache.overall_hits 265450383 # number of overall hits
system.cpu.icache.ReadReq_misses 914 # number of ReadReq misses
system.cpu.icache.demand_misses 914 # number of demand (read+write) misses
system.cpu.icache.overall_misses 914 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32210500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32210500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32210500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 265451297 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 265451297 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 265451297 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 611.010403 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.298345 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 303014437 # number of ReadReq hits
system.cpu.icache.demand_hits 303014437 # number of demand (read+write) hits
system.cpu.icache.overall_hits 303014437 # number of overall hits
system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses
system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1019 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 35224000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 35224000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 35224000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 303015456 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 303015456 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 303015456 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35241.247265 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35241.247265 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35241.247265 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 34567.222767 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34567.222767 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34567.222767 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -351,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 197 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 197 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 197 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 717 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 717 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 717 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 739 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 739 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 739 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 24697500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 24697500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 24697500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 25462500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25462500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25462500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34455.345061 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9552367 # number of replacements
system.cpu.dcache.tagsinuse 4082.984998 # Cycle average of tags in use
system.cpu.dcache.total_refs 675087648 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9556463 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.641999 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 6495236000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4082.984998 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.996823 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 507131941 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 167955564 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 69 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 675087505 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 675087505 # number of overall hits
system.cpu.dcache.ReadReq_misses 10254687 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4630483 # number of WriteReq misses
system.cpu.dcache.replacements 9572098 # number of replacements
system.cpu.dcache.tagsinuse 4088.159469 # Cycle average of tags in use
system.cpu.dcache.total_refs 687277052 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9576194 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 71.769333 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3603059000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4088.159469 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.998086 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 519599165 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 167677732 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 82 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 73 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 687276897 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 687276897 # number of overall hits
system.cpu.dcache.ReadReq_misses 10430920 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 4908315 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 14885170 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 14885170 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 173914872000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 112892331168 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 15339235 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 15339235 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 181621482000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 122280886057 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 286807203168 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 286807203168 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 517386628 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 303902368057 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 303902368057 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 530030085 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 69 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 689972675 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 689972675 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.026830 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.021574 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021574 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_accesses 85 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 73 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 702616132 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 702616132 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.019680 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.028440 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.035294 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.021832 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.021832 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 17411.837307 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24913.007021 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 19267.983044 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 19267.983044 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 148361910 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 35813 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4142.683104 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
system.cpu.dcache.demand_avg_miss_latency 19812.094153 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 19812.094153 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 267003640 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 90682 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2944.395139 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21777.777778 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3126452 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2590385 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 2738322 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 3128448 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2747497 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 3015544 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5328707 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5328707 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7664302 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1892161 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9556463 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9556463 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 5763041 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5763041 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7683423 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1892771 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9576194 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9576194 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 89320855000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 42428124877 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 131748979877 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 131748979877 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 90753159500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 45245223293 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 135998382793 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 135998382793 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014813 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.013850 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.013850 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014496 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.013629 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.013629 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11811.553197 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23904.224702 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2920822 # number of replacements
system.cpu.l2cache.tagsinuse 26404.864855 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7838163 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2948145 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.658676 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 129803245500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15746.128543 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10658.736312 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.480534 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.325279 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5643332 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3126452 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 980638 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6623970 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6623970 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2021685 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 911525 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2933210 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2933210 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 69338469500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 31601923000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 100940392500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 100940392500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7665017 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3126452 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1892163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9557180 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9557180 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.263755 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.481737 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.306912 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.306912 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34412.944351 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34412.944351 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 48964500 # number of cycles access was blocked
system.cpu.l2cache.replacements 2927988 # number of replacements
system.cpu.l2cache.tagsinuse 26803.816569 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7852126 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2955312 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.656953 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 105427800500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15979.704689 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10824.111881 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.487662 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.330326 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5656220 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3128448 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 980310 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6636530 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6636530 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2027940 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 912463 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2940403 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2940403 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 69613457000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 31659273500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 101272730500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 101272730500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7684160 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3128448 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1892773 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9576933 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9576933 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.263912 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.482077 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.307030 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.307030 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34327.177826 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.501118 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34441.785871 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34441.785871 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 56425500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 5689 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6606 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8606.872913 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8541.553134 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 1216359 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 2021675 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 911525 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2933200 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2933200 # number of overall MSHR misses
system.cpu.l2cache.writebacks 1217599 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 2027928 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 912463 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2940391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2940391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 62968532000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28735558500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 91704090500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 91704090500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 63193895000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28814819500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 92008714500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 92008714500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263753 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481737 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.306911 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.306911 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263910 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482077 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.307028 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.307028 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.804068 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.164854 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -199,12 +200,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 06:59:18
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 17:47:44
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 42094188000 because target called exit()
122 123 124 Exiting @ tick 41833966000 because target called exit()

336
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,12 +1,12 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.042094 # Number of seconds simulated
sim_ticks 42094188000 # Number of ticks simulated
sim_seconds 0.041834 # Number of seconds simulated
sim_ticks 41833966000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 121365 # Simulator instruction rate (inst/s)
host_tick_rate 55588778 # Simulator tick rate (ticks/s)
host_mem_usage 196912 # Number of bytes of host memory used
host_seconds 757.24 # Real time elapsed on the host
host_inst_rate 47398 # Simulator instruction rate (inst/s)
host_tick_rate 21575287 # Simulator tick rate (ticks/s)
host_mem_usage 249684 # Number of bytes of host memory used
host_seconds 1938.98 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 26498119 # DT
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498152 # DTB accesses
system.cpu.itb.fetch_hits 10077672 # ITB hits
system.cpu.itb.fetch_hits 9991202 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 10077721 # ITB accesses
system.cpu.itb.fetch_accesses 9991251 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 84188377 # number of cpu cycles simulated
system.cpu.numCycles 83667933 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 83816425 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 10559 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7701629 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76486748 # Number of cycles cpu stages are processed.
system.cpu.activity 90.851909 # Percentage of cycles cpu is active
system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed.
system.cpu.activity 90.796172 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
@ -61,129 +61,129 @@ system.cpu.comFloats 3775974 # Nu
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.cpi 0.916056 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.916056 # CPI: Total CPI of All Threads
system.cpu.ipc 1.091636 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads
system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.091636 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 13660151 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 10092693 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4598416 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 8981993 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4278316 # Number of BTB hits
system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 131 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 47.632146 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 6418014 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7242137 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73810840 # Number of Reads from Int. Register File
system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136386312 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206031 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8057919 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38650469 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26688179 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3946440 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 651118 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4597558 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5643144 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 44.894950 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57370437 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26652325 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 27496111 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56692266 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 67.339778 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34731944 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49456433 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.744965 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34177132 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 50011245 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.403978 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 66154944 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18033433 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.420336 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30219873 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53968504 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.104459 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7205 # number of replacements
system.cpu.icache.tagsinuse 1491.617776 # Cycle average of tags in use
system.cpu.icache.total_refs 10066620 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9090 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1107.438944 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7551 # number of replacements
system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use
system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1491.617776 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.728329 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 10066620 # number of ReadReq hits
system.cpu.icache.demand_hits 10066620 # number of demand (read+write) hits
system.cpu.icache.overall_hits 10066620 # number of overall hits
system.cpu.icache.ReadReq_misses 11049 # number of ReadReq misses
system.cpu.icache.demand_misses 11049 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11049 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 285327000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 285327000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 285327000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 10077669 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 10077669 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 10077669 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 25823.784958 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 25823.784958 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 25823.784958 # average overall miss latency
system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits
system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits
system.cpu.icache.overall_hits 9979713 # number of overall hits
system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses
system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11486 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 13900 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1959 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1959 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1959 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 9090 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 9090 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 9090 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 218831500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 218831500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 218831500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000902 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000902 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000902 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24073.872387 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1441.601089 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491207 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11916.872245 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1441.601089 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.351953 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 19995646 # number of ReadReq hits
system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits
system.cpu.dcache.demand_hits 26491207 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 26491207 # number of overall hits
system.cpu.dcache.ReadReq_misses 552 # number of ReadReq misses
system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 26491206 # number of overall hits
system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses
system.cpu.dcache.demand_misses 6094 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 6094 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 28390000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 303795000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 332185000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 332185000 # number of overall miss cycles
system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 6095 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
@ -192,81 +192,81 @@ system.cpu.dcache.ReadReq_miss_rate 0.000028 # mi
system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 51431.159420 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 54816.853122 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54510.173942 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54510.173942 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41040500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49866.950182 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 77 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 3871 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 3871 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 92992000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 116205000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 116205000 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53199.084668 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2189.147121 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6359 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3281 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.938129 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2171.310088 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.837033 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.066263 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 6350 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6376 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6376 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3215 # number of ReadReq misses
system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6721 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 4937 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 4937 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 168259500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 90562500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 258822000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 258822000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 9565 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 11313 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 11313 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.336121 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.436401 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.436401 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52335.769829 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52591.463415 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52424.954426 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52424.954426 # average overall miss latency
system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3215 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 4937 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 4937 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 129008000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 198352500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 198352500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.336121 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.436401 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.436401 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40126.905132 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.744483 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:11:56
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 18:07:05
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 34191076000 because target called exit()
122 123 124 Exiting @ tick 32092296500 because target called exit()

775
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.034191 # Number of seconds simulated
sim_ticks 34191076000 # Number of ticks simulated
sim_seconds 0.032092 # Number of seconds simulated
sim_ticks 32092296500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 184031 # Simulator instruction rate (inst/s)
host_tick_rate 74747519 # Simulator tick rate (ticks/s)
host_mem_usage 197584 # Number of bytes of host memory used
host_seconds 457.42 # Real time elapsed on the host
host_inst_rate 73581 # Simulator instruction rate (inst/s)
host_tick_rate 28051508 # Simulator tick rate (ticks/s)
host_mem_usage 250560 # Number of bytes of host memory used
host_seconds 1144.05 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 24606273 # DTB read hits
system.cpu.dtb.read_misses 355468 # DTB read misses
system.cpu.dtb.read_hits 25665074 # DTB read hits
system.cpu.dtb.read_misses 532377 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 24961741 # DTB read accesses
system.cpu.dtb.write_hits 7276928 # DTB write hits
system.cpu.dtb.write_misses 1204 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 7278132 # DTB write accesses
system.cpu.dtb.data_hits 31883201 # DTB hits
system.cpu.dtb.data_misses 356672 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 32239873 # DTB accesses
system.cpu.itb.fetch_hits 17397269 # ITB hits
system.cpu.itb.fetch_misses 74 # ITB misses
system.cpu.dtb.read_accesses 26197451 # DTB read accesses
system.cpu.dtb.write_hits 7413229 # DTB write hits
system.cpu.dtb.write_misses 1159 # DTB write misses
system.cpu.dtb.write_acv 5 # DTB write access violations
system.cpu.dtb.write_accesses 7414388 # DTB write accesses
system.cpu.dtb.data_hits 33078303 # DTB hits
system.cpu.dtb.data_misses 533536 # DTB misses
system.cpu.dtb.data_acv 5 # DTB access violations
system.cpu.dtb.data_accesses 33611839 # DTB accesses
system.cpu.itb.fetch_hits 19743768 # ITB hits
system.cpu.itb.fetch_misses 86 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 17397343 # ITB accesses
system.cpu.itb.fetch_accesses 19743854 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,243 +41,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 68382153 # number of cpu cycles simulated
system.cpu.numCycles 64184594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits
system.cpu.BPredUnit.lookups 19638238 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 14616795 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1934317 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 16315844 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 12540710 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 1821712 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2747 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 21008427 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 166538758 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19638238 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 14362422 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 30824536 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 9451370 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 4886757 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 19743768 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 631936 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 64091521 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.598452 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.236190 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33266985 51.91% 51.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3147764 4.91% 56.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2102748 3.28% 60.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3556460 5.55% 65.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4397921 6.86% 72.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1522590 2.38% 74.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1866548 2.91% 77.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1731844 2.70% 80.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 12498661 19.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 64091521 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.305965 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.594684 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 23134324 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3873003 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 28813163 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 914553 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 7356478 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3062607 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 160619110 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 43067 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 7356478 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 24847542 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1029661 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6037 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 27972484 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 2879319 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 153930695 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 698435 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1852837 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 113010867 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 199187244 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 187702425 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 11484819 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 469 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 44583506 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 529 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 520 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 7678386 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 31845410 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9896316 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6196134 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1567027 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 129169470 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 502 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107327436 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 534587 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 44082208 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 35410789 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 113 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 64091521 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.674596 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.788065 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 23013905 35.91% 35.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13200417 20.60% 56.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 9655349 15.06% 71.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7236543 11.29% 82.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 5456935 8.51% 91.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2848092 4.44% 95.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1848148 2.88% 98.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 707452 1.10% 99.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 124680 0.19% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 64091521 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 206408 12.63% 12.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 12.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 12.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 6500 0.40% 13.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5851 0.36% 13.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 847321 51.84% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 65.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 476077 29.13% 94.37% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 91992 5.63% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 65553727 61.08% 61.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 486899 0.45% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2819079 2.63% 64.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 64.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2427572 2.26% 66.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 312395 0.29% 66.82% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 763362 0.71% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 27299077 25.44% 92.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7549954 7.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued
system.cpu.iq.rate 1.490981 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 107327436 # Type of FU issued
system.cpu.iq.rate 1.672168 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1634345 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.015228 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 265519684 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 162160015 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 94997457 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15395641 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 11288937 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7141397 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 100830916 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 8130858 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1254132 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 11849212 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 9154 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 349266 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 3395213 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 10688 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 7356478 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 94659 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 31189 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 141503695 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 872227 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 31845410 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 9896316 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 502 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 12366 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 349266 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1814664 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 342809 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 2157473 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104568587 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 26198042 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2758849 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 11194543 # number of nop insts executed
system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed
system.cpu.iew.exec_branches 12448390 # Number of branches executed
system.cpu.iew.exec_stores 7278167 # Number of stores executed
system.cpu.iew.exec_rate 1.455255 # Inst execution rate
system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64595544 # num instructions producing a value
system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value
system.cpu.iew.exec_nop 12333723 # number of nop insts executed
system.cpu.iew.exec_refs 33612538 # number of memory reference insts executed
system.cpu.iew.exec_branches 13292388 # Number of branches executed
system.cpu.iew.exec_stores 7414496 # Number of stores executed
system.cpu.iew.exec_rate 1.629185 # Inst execution rate
system.cpu.iew.wb_sent 103278074 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102138854 # cumulative count of insts written-back
system.cpu.iew.wb_producers 68941212 # num instructions producing a value
system.cpu.iew.wb_consumers 95281048 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back
system.cpu.iew.wb_rate 1.591330 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.723556 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 49602328 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 1920862 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 56735043 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.619864 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.379821 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 26448220 46.62% 46.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 12595125 22.20% 68.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5584191 9.84% 78.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2979320 5.25% 83.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1760489 3.10% 87.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1489209 2.62% 89.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 769969 1.36% 91.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 774387 1.36% 92.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4334133 7.64% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 56735043 # Number of insts commited each cycle
system.cpu.commit.count 91903055 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
@ -287,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 4334133 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 186605606 # The number of ROB reads
system.cpu.rob.rob_writes 260771760 # The number of ROB writes
system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 193905253 # The number of ROB reads
system.cpu.rob.rob_writes 290432006 # The number of ROB writes
system.cpu.timesIdled 2283 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 93073 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads
system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 134796814 # number of integer regfile reads
system.cpu.int_regfile_writes 73485618 # number of integer regfile writes
system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads
system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes
system.cpu.misc_regfile_reads 712206 # number of misc regfile reads
system.cpu.cpi 0.762471 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.762471 # CPI: Total CPI of All Threads
system.cpu.ipc 1.311525 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.311525 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 141097992 # number of integer regfile reads
system.cpu.int_regfile_writes 77269821 # number of integer regfile writes
system.cpu.fp_regfile_reads 6208793 # number of floating regfile reads
system.cpu.fp_regfile_writes 6125599 # number of floating regfile writes
system.cpu.misc_regfile_reads 715479 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 8218 # number of replacements
system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use
system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks.
system.cpu.icache.replacements 8662 # number of replacements
system.cpu.icache.tagsinuse 1591.987817 # Cycle average of tags in use
system.cpu.icache.total_refs 19731988 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1863.266100 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits
system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits
system.cpu.icache.overall_hits 17386201 # number of overall hits
system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses
system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11068 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency
system.cpu.icache.occ_blocks::0 1591.987817 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.777338 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 19731988 # number of ReadReq hits
system.cpu.icache.demand_hits 19731988 # number of demand (read+write) hits
system.cpu.icache.overall_hits 19731988 # number of overall hits
system.cpu.icache.ReadReq_misses 11780 # number of ReadReq misses
system.cpu.icache.demand_misses 11780 # number of demand (read+write) misses
system.cpu.icache.overall_misses 11780 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 187835000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 187835000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 187835000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 19743768 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 19743768 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 19743768 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000597 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000597 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000597 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 15945.246180 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 15945.246180 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 15945.246180 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -340,132 +343,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 1190 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1190 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1190 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 124617500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 124617500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 124617500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000536 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000536 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000536 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11767.469311 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 160 # number of replacements
system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use
system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks.
system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.tagsinuse 1458.064990 # Cycle average of tags in use
system.cpu.dcache.total_refs 30892362 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13785.078983 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 30012251 # number of overall hits
system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses
system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 8940 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.occ_blocks::0 1458.064990 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.355973 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24399260 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 6493052 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits 30892312 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 30892312 # number of overall hits
system.cpu.dcache.ReadReq_misses 942 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 8051 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 8993 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 8993 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 28111000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 289250500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 317361500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 317361500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 24400202 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses
system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 30901305 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 30901305 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.019608 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 29841.825902 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35927.276115 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 35289.836540 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35289.836540 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 109 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses
system.cpu.dcache.writebacks 108 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6318 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 6753 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6753 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 507 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 16260000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 61635000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 77895000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 77895000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.019608 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32071.005917 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35565.493364 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2392.328540 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7626 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3548 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.149380 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 7279 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5098 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 2374.739172 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 17.589369 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.072471 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 7618 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 7644 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 7644 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3480 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5187 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5187 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 119535500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 59266000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 178801500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 178801500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 11098 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 12831 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 12831 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.313570 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.984997 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.404255 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.404255 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34349.281609 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34719.390744 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34471.081550 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34471.081550 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -477,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 3480 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5187 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5187 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 108240500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 53874500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 162115000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 162115000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313570 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984997 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.404255 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.404255 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.591954 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31560.925600 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

1
tests/long/70.twolf/ref/arm/linux/o3-timing/simerr
View file

@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

20
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,16 +1,10 @@
Redirecting stdout to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simerr
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 16 2011 15:11:25
M5 started May 16 2011 16:39:45
M5 executing on nadc-0271
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
gem5 compiled Jul 8 2011 15:18:43
gem5 started Jul 9 2011 04:18:32
gem5 executing on u200439-lin.austin.arm.com
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -27,4 +21,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 114583980000 because target called exit()
122 123 124 Exiting @ tick 110281184000 because target called exit()

782
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.114584 # Number of seconds simulated
sim_ticks 114583980000 # Number of ticks simulated
sim_seconds 0.110281 # Number of seconds simulated
sim_ticks 110281184000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 37904 # Simulator instruction rate (inst/s)
host_tick_rate 23020273 # Simulator tick rate (ticks/s)
host_mem_usage 259288 # Number of bytes of host memory used
host_seconds 4977.52 # Real time elapsed on the host
sim_insts 188668727 # Number of instructions simulated
host_inst_rate 65382 # Simulator instruction rate (inst/s)
host_tick_rate 38217412 # Simulator tick rate (ticks/s)
host_mem_usage 261804 # Number of bytes of host memory used
host_seconds 2885.63 # Real time elapsed on the host
sim_insts 188667677 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,296 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 229167961 # number of cpu cycles simulated
system.cpu.numCycles 220562369 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 98244922 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 77066129 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 10346796 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 79994397 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 74750808 # Number of BTB hits
system.cpu.BPredUnit.lookups 104258409 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 82362571 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 9936095 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 86105898 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 80445450 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 4424088 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 111792 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 36996487 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 401246546 # Number of instructions fetch has processed
system.cpu.fetch.Branches 98244922 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79174896 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 102059455 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 10739700 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 36996487 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2084614 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 229101172 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.893988 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.602493 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 4758962 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 112969 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 46358647 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 433367935 # Number of instructions fetch has processed
system.cpu.fetch.Branches 104258409 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 85204412 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 111822484 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 35665794 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 36992864 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.CacheLines 42110119 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2232853 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 220504638 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.132131 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.672325 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 127219261 55.53% 55.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4017584 1.75% 57.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 29118578 12.71% 69.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 15726187 6.86% 76.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 9819635 4.29% 81.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13296507 5.80% 86.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7877710 3.44% 90.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4751479 2.07% 92.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 17274231 7.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 108888253 49.38% 49.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4953673 2.25% 51.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 33070296 15.00% 66.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 18447401 8.37% 74.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 9377183 4.25% 79.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12785261 5.80% 85.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 8550568 3.88% 88.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4486115 2.03% 90.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 19945888 9.05% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 229101172 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.428703 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.750884 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 79313906 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 32327887 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 94878595 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 682758 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 21898026 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 14316236 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 166090 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 406876598 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 708405 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 21898026 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 88099979 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 621468 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 27861388 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 86740372 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3879939 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 372161493 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 76195 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1579800 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 635133998 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1589359787 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1572376571 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16983216 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298063696 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 337070297 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2567300 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2531045 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 20595382 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 47397575 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16557205 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 6544934 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4003679 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 318729231 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2207616 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 261466746 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 554929 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 126483137 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 283584721 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 571778 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 229101172 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.141272 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.407939 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 220504638 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.472694 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.964832 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 55339748 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 35376598 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 103212898 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1403307 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 25172087 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 14322485 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 170339 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 440125451 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 696276 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 25172087 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 64672455 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 776963 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 29575154 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 95204893 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 5103086 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 403993606 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 69868 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2710880 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 687477122 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1728388844 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1709997227 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 18391617 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298062016 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 389415097 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2865354 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2816189 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 26097925 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 51690689 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 18730866 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 8573671 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5359744 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 346939727 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2374386 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 267717167 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 907172 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 158256505 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 384971202 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 738758 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 220504638 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.214111 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.476414 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 108324411 47.28% 47.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 46627729 20.35% 67.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 34182087 14.92% 82.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 22115521 9.65% 92.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11617915 5.07% 97.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4157757 1.81% 99.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1774100 0.77% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 189981 0.08% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 111671 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 103384796 46.89% 46.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 39397520 17.87% 64.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 35187917 15.96% 80.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 23179085 10.51% 91.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11803879 5.35% 96.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4771097 2.16% 98.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2229685 1.01% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 447825 0.20% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 102834 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 229101172 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 220504638 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 110643 6.25% 6.25% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5520 0.31% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 24 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1295953 73.23% 79.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 357680 20.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 341650 17.75% 17.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 6050 0.31% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 35 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 4 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 93 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1226198 63.72% 81.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 350464 18.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 205127791 78.45% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 918034 0.35% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 10104 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 32866 0.01% 78.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 166342 0.06% 78.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 251406 0.10% 78.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 76052 0.03% 79.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 462257 0.18% 79.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 207196 0.08% 79.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71628 0.03% 79.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 79.29% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 40426138 15.46% 94.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 13716608 5.25% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 208615296 77.92% 77.92% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 925342 0.35% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 6202 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 33026 0.01% 78.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 166299 0.06% 78.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 260522 0.10% 78.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 76108 0.03% 78.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 471200 0.18% 78.65% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 207528 0.08% 78.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71629 0.03% 78.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 327 0.00% 78.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 42633393 15.92% 94.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 14250295 5.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 261466746 # Type of FU issued
system.cpu.iq.rate 1.140939 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1769820 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006769 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 750657753 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 445688656 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 241497013 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3701660 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2110445 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1822638 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 261381402 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1855164 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 983049 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 267717167 # Type of FU issued
system.cpu.iq.rate 1.213793 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1924494 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007189 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 754979573 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 505620151 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 248098864 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3791065 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2339721 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1843061 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 267732701 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1908960 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1050657 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 17545646 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 834 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 453061 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 3910128 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 21838970 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7625 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 472350 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6083999 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 21898026 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16044 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3524 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 320989557 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 8588110 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 47397575 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16557205 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2183565 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 259 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 3132 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 453061 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 9663378 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2166474 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 11829852 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 247483110 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 38551878 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 13983636 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 25172087 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 44760 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3320 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 349368262 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 3978827 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 51690689 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 18730866 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2350473 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 564 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2427 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 472350 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 10008076 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1698961 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 11707037 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 254915521 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 40541135 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 12801646 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 52710 # number of nop insts executed
system.cpu.iew.exec_refs 51991708 # number of memory reference insts executed
system.cpu.iew.exec_branches 51968856 # Number of branches executed
system.cpu.iew.exec_stores 13439830 # Number of stores executed
system.cpu.iew.exec_rate 1.079920 # Inst execution rate
system.cpu.iew.wb_sent 244574618 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 243319651 # cumulative count of insts written-back
system.cpu.iew.wb_producers 146548425 # num instructions producing a value
system.cpu.iew.wb_consumers 237755963 # num instructions consuming a value
system.cpu.iew.exec_nop 54149 # number of nop insts executed
system.cpu.iew.exec_refs 54377446 # number of memory reference insts executed
system.cpu.iew.exec_branches 53214768 # Number of branches executed
system.cpu.iew.exec_stores 13836311 # Number of stores executed
system.cpu.iew.exec_rate 1.155753 # Inst execution rate
system.cpu.iew.wb_sent 251638468 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 249941925 # cumulative count of insts written-back
system.cpu.iew.wb_producers 151812393 # num instructions producing a value
system.cpu.iew.wb_consumers 254020317 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.061752 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.616382 # average fanout of values written-back
system.cpu.iew.wb_rate 1.133203 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.597639 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 188683115 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 132297419 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1635838 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 10209212 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 207203147 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.910619 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.539035 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 188682065 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 160676887 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1635628 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9797761 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 195332552 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.965953 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.628775 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 117680182 56.79% 56.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 47355200 22.85% 79.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20289931 9.79% 89.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8457444 4.08% 93.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5251466 2.53% 96.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1928686 0.93% 96.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2144986 1.04% 98.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 905505 0.44% 98.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3189747 1.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 109939001 56.28% 56.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 42858902 21.94% 78.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20127469 10.30% 88.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 8563678 4.38% 92.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5111696 2.62% 95.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2060801 1.06% 96.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1694385 0.87% 97.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 852868 0.44% 97.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4123752 2.11% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 207203147 # Number of insts commited each cycle
system.cpu.commit.count 188683115 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 195332552 # Number of insts commited each cycle
system.cpu.commit.count 188682065 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 42499005 # Number of memory references committed
system.cpu.commit.loads 29851928 # Number of loads committed
system.cpu.commit.refs 42498585 # Number of memory references committed
system.cpu.commit.loads 29851718 # Number of loads committed
system.cpu.commit.membars 22408 # Number of memory barriers committed
system.cpu.commit.branches 40284126 # Number of branches committed
system.cpu.commit.branches 40283916 # Number of branches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
system.cpu.commit.int_insts 150115997 # Number of committed integer instructions.
system.cpu.commit.int_insts 150115157 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
system.cpu.commit.bw_lim_events 3189747 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 4123752 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 524988733 # The number of ROB reads
system.cpu.rob.rob_writes 663890510 # The number of ROB writes
system.cpu.timesIdled 1538 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 66789 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 188668727 # Number of Instructions Simulated
system.cpu.committedInsts_total 188668727 # Number of Instructions Simulated
system.cpu.cpi 1.214658 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.214658 # CPI: Total CPI of All Threads
system.cpu.ipc 0.823277 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.823277 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1105306330 # number of integer regfile reads
system.cpu.int_regfile_writes 405513282 # number of integer regfile writes
system.cpu.fp_regfile_reads 2915970 # number of floating regfile reads
system.cpu.fp_regfile_writes 2459492 # number of floating regfile writes
system.cpu.misc_regfile_reads 485972392 # number of misc regfile reads
system.cpu.misc_regfile_writes 824922 # number of misc regfile writes
system.cpu.icache.replacements 1867 # number of replacements
system.cpu.icache.tagsinuse 1275.783892 # Cycle average of tags in use
system.cpu.icache.total_refs 36992467 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3528 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10485.393141 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 540562551 # The number of ROB reads
system.cpu.rob.rob_writes 723954086 # The number of ROB writes
system.cpu.timesIdled 1712 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 57731 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 188667677 # Number of Instructions Simulated
system.cpu.committedInsts_total 188667677 # Number of Instructions Simulated
system.cpu.cpi 1.169052 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.169052 # CPI: Total CPI of All Threads
system.cpu.ipc 0.855394 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.855394 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1139481673 # number of integer regfile reads
system.cpu.int_regfile_writes 415646596 # number of integer regfile writes
system.cpu.fp_regfile_reads 2922802 # number of floating regfile reads
system.cpu.fp_regfile_writes 2492399 # number of floating regfile writes
system.cpu.misc_regfile_reads 524104390 # number of misc regfile reads
system.cpu.misc_regfile_writes 824502 # number of misc regfile writes
system.cpu.icache.replacements 1939 # number of replacements
system.cpu.icache.tagsinuse 1330.149475 # Cycle average of tags in use
system.cpu.icache.total_refs 42105837 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3648 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 11542.170230 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1275.783892 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.622941 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 36992467 # number of ReadReq hits
system.cpu.icache.demand_hits 36992467 # number of demand (read+write) hits
system.cpu.icache.overall_hits 36992467 # number of overall hits
system.cpu.icache.ReadReq_misses 4020 # number of ReadReq misses
system.cpu.icache.demand_misses 4020 # number of demand (read+write) misses
system.cpu.icache.overall_misses 4020 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 95473000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 95473000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 95473000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 36996487 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 36996487 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 36996487 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000109 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000109 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000109 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 23749.502488 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 23749.502488 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 23749.502488 # average overall miss latency
system.cpu.icache.occ_blocks::0 1330.149475 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.649487 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 42105837 # number of ReadReq hits
system.cpu.icache.demand_hits 42105837 # number of demand (read+write) hits
system.cpu.icache.overall_hits 42105837 # number of overall hits
system.cpu.icache.ReadReq_misses 4282 # number of ReadReq misses
system.cpu.icache.demand_misses 4282 # number of demand (read+write) misses
system.cpu.icache.overall_misses 4282 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 102623500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 102623500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 102623500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 42110119 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 42110119 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 42110119 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 23966.254087 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 23966.254087 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 23966.254087 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -350,142 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 491 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 491 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 491 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 3529 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 3529 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 3529 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 634 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 634 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 634 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 3648 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 3648 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 3648 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 71843000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 71843000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 71843000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 74999500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 74999500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 74999500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000095 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000095 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000095 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20357.891754 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 49 # number of replacements
system.cpu.dcache.tagsinuse 1395.560229 # Cycle average of tags in use
system.cpu.dcache.total_refs 49245913 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1834 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 26851.642857 # Average number of references to valid blocks.
system.cpu.dcache.replacements 53 # number of replacements
system.cpu.dcache.tagsinuse 1408.348450 # Cycle average of tags in use
system.cpu.dcache.total_refs 51108076 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1850 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27625.987027 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1395.560229 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.340713 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 36836047 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 12356734 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 28275 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 24850 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 49192781 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 49192781 # number of overall hits
system.cpu.dcache.ReadReq_misses 1779 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 7553 # number of WriteReq misses
system.cpu.dcache.occ_blocks::0 1408.348450 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.343835 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 38699028 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 27661 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 24640 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 51055775 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 51055775 # number of overall hits
system.cpu.dcache.ReadReq_misses 1814 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 9332 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 9332 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 57926000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 236821500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 294747500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 294747500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 36837826 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_misses 9354 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 9354 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 59541500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 236790000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 296331500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 296331500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 38700842 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 28277 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 24850 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 49202113 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 49202113 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000048 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000071 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000190 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000190 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32560.989320 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 31354.627300 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 31584.601372 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 31584.601372 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 27663 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 24640 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 51065129 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 51065129 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000183 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000183 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 31679.655762 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 31679.655762 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 17 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1036 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6461 # number of WriteReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6451 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 7497 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 7497 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 743 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1835 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1835 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 7504 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 7504 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1089 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1850 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1850 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 23910500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 38348500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 62259000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 62259000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 24275500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 38318500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 62594000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 62594000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32181.022880 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35117.673993 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1850.961242 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1671 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2592 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.644676 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 1929.340531 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2692 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.635587 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1847.906973 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3.054268 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.056394 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1926.279074 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 3.061457 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.058785 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1671 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1680 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1680 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2600 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 3682 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 3682 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 89152000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 126314000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 126314000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 4271 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1719 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1719 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2698 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 3779 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 3779 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 92484500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 37157500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 129642000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 129642000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 4409 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 5362 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 5362 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.608757 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.686684 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.686684 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34289.230769 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34345.656192 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34305.812059 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34305.812059 # average overall miss latency
system.cpu.l2cache.ReadExReq_accesses 1089 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 5498 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 5498 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.611930 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.992654 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.687341 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.687341 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34305.901032 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34305.901032 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -495,31 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 2584 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 3666 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 3666 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 2683 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 3764 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 3764 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 80301000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33586500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 113887500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 113887500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 83387000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33564500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 116951500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 116951500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605011 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.683700 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.683700 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31076.238390 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608528 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992654 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.684613 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.684613 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -493,12 +494,12 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864

14
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 27 2011 02:06:34
gem5 started Jun 27 2011 02:06:35
gem5 executing on burrito
command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
gem5 compiled Jul 8 2011 15:18:15
gem5 started Jul 9 2011 00:22:05
gem5 executing on u200439-lin.austin.arm.com
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -24,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 106734154000 because target called exit()
122 123 124 Exiting @ tick 105045070000 because target called exit()

713
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,248 +1,251 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.106734 # Number of seconds simulated
sim_ticks 106734154000 # Number of ticks simulated
sim_seconds 0.105045 # Number of seconds simulated
sim_ticks 105045070000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 152335 # Simulator instruction rate (inst/s)
host_tick_rate 73451239 # Simulator tick rate (ticks/s)
host_mem_usage 239116 # Number of bytes of host memory used
host_seconds 1453.13 # Real time elapsed on the host
host_inst_rate 49247 # Simulator instruction rate (inst/s)
host_tick_rate 23369426 # Simulator tick rate (ticks/s)
host_mem_usage 262348 # Number of bytes of host memory used
host_seconds 4494.98 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 213468309 # number of cpu cycles simulated
system.cpu.numCycles 210090141 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 25050494 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 25050494 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3072725 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 22404993 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 19578906 # Number of BTB hits
system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27480404 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 261552197 # Number of instructions fetch has processed
system.cpu.fetch.Branches 25050494 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 19578906 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 69713468 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3100277 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.CacheLines 27480404 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 444252 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 213378820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.014955 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.225944 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 145514774 68.20% 68.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3945621 1.85% 70.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3133148 1.47% 71.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4337653 2.03% 73.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4594142 2.15% 75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4407004 2.07% 77.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5010346 2.35% 80.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3238927 1.52% 81.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39197205 18.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 213378820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.117350 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.225251 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 66958522 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 57001085 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 60412397 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 5858231 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 23148585 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 419968775 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 23148585 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 74832356 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 18068346 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 22426 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 57435303 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 39871804 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 409779933 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 21501033 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 16352489 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 430797248 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1054244247 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1043122682 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 11121565 # Number of floating rename lookups
system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 196433839 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1310 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 83098346 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 104980766 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37095594 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 90430174 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 30425407 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 395507957 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 281825994 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 65208 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 173816854 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 357698242 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 213378820 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.320778 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.372811 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 72508898 33.98% 33.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 65573468 30.73% 64.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 36643591 17.17% 81.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20570957 9.64% 91.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12013670 5.63% 97.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3959812 1.86% 99.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1477782 0.69% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 513095 0.24% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 117547 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 213378820 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 68694 2.44% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2379905 84.54% 86.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 366520 13.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1200241 0.43% 0.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187039988 66.37% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1589434 0.56% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 68492447 24.30% 91.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23503884 8.34% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 281825994 # Type of FU issued
system.cpu.iq.rate 1.320224 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2815119 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009989 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 774676274 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 563666202 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 273457668 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5234861 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 5690969 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2532279 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 280803234 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2637638 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 16340040 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued
system.cpu.iq.rate 1.342042 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 48331176 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20419 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34128 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 16579878 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 45973 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 23148585 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 533368 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 548562 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 395509381 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 255580 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 104980766 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37095594 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 479390 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 13059 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34128 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2541200 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 744980 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3286180 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 278309942 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 67077031 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3516052 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 90250007 # number of memory reference insts executed
system.cpu.iew.exec_branches 15873940 # Number of branches executed
system.cpu.iew.exec_stores 23172976 # Number of stores executed
system.cpu.iew.exec_rate 1.303753 # Inst execution rate
system.cpu.iew.wb_sent 277022685 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 275989947 # cumulative count of insts written-back
system.cpu.iew.wb_producers 222941067 # num instructions producing a value
system.cpu.iew.wb_consumers 371922286 # num instructions consuming a value
system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed
system.cpu.iew.exec_branches 15748098 # Number of branches executed
system.cpu.iew.exec_stores 23391917 # Number of stores executed
system.cpu.iew.exec_rate 1.327442 # Inst execution rate
system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back
system.cpu.iew.wb_producers 222890509 # num instructions producing a value
system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.292885 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.599429 # average fanout of values written-back
system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 174164320 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3072754 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 190230235 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.163658 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.518986 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 74059520 38.93% 38.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 71187215 37.42% 76.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 18215863 9.58% 85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12685132 6.67% 92.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5921003 3.11% 95.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2781558 1.46% 97.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1922219 1.01% 98.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1098236 0.58% 98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2359489 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 190230235 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed
@ -252,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 2359489 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 583398083 # The number of ROB reads
system.cpu.rob.rob_writes 814214435 # The number of ROB writes
system.cpu.timesIdled 1914 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 89489 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 585604683 # The number of ROB reads
system.cpu.rob.rob_writes 827851683 # The number of ROB writes
system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.964336 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.964336 # CPI: Total CPI of All Threads
system.cpu.ipc 1.036983 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.036983 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 516519288 # number of integer regfile reads
system.cpu.int_regfile_writes 284023651 # number of integer regfile writes
system.cpu.fp_regfile_reads 3512884 # number of floating regfile reads
system.cpu.fp_regfile_writes 2186553 # number of floating regfile writes
system.cpu.misc_regfile_reads 145156303 # number of misc regfile reads
system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads
system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 516476198 # number of integer regfile reads
system.cpu.int_regfile_writes 284804952 # number of integer regfile writes
system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads
system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes
system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 3419 # number of replacements
system.cpu.icache.tagsinuse 1603.937064 # Cycle average of tags in use
system.cpu.icache.total_refs 27474068 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 5377 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5109.553282 # Average number of references to valid blocks.
system.cpu.icache.replacements 4263 # number of replacements
system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use
system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1603.937064 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.783172 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 27474068 # number of ReadReq hits
system.cpu.icache.demand_hits 27474068 # number of demand (read+write) hits
system.cpu.icache.overall_hits 27474068 # number of overall hits
system.cpu.icache.ReadReq_misses 6336 # number of ReadReq misses
system.cpu.icache.demand_misses 6336 # number of demand (read+write) misses
system.cpu.icache.overall_misses 6336 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 161881500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 161881500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 161881500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 27480404 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 27480404 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 27480404 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000231 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000231 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000231 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 25549.479167 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 25549.479167 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 25549.479167 # average overall miss latency
system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits
system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits
system.cpu.icache.overall_hits 28884352 # number of overall hits
system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses
system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses
system.cpu.icache.overall_misses 7220 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -305,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 957 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 957 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 957 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 5379 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 5379 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 5379 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 120710000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 120710000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 120710000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 48 # number of replacements
system.cpu.dcache.tagsinuse 1400.553684 # Cycle average of tags in use
system.cpu.dcache.total_refs 71034499 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36334.782097 # Average number of references to valid blocks.
system.cpu.dcache.replacements 50 # number of replacements
system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use
system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1400.553684 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.341932 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 50525866 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 20508631 # number of WriteReq hits
system.cpu.dcache.demand_hits 71034497 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 71034497 # number of overall hits
system.cpu.dcache.ReadReq_misses 700 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 7099 # number of WriteReq misses
system.cpu.dcache.demand_misses 7799 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 7799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 23034500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 187834000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 210868500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 210868500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 50526566 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits
system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 70508699 # number of overall hits
system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses
system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 7819 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 71042296 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 71042296 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27037.889473 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27037.889473 # average overall miss latency
system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -367,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 312 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 5530 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5842 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5842 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 13276000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 55641500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 68917500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 68917500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2429.026594 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2107 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3661 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.575526 # Average number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2428.011682 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014912 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.074097 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2107 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2113 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2113 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3657 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5219 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5219 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 125400000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 53945500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 179345500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 179345500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 5764 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2876 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5318 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 7332 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 7332 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.634455 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.711811 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.711811 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34363.958613 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34363.958613 # average overall miss latency
system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -443,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3657 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5219 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5219 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 113519000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48964500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 162483500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 162483500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634455 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.711811 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.711811 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -204,7 +205,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 23:40:02
gem5 started Jun 20 2011 08:26:33
gem5 executing on zooks
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 15:20:58
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 21228000 because target called exit()
Exiting @ tick 21216000 because target called exit()

210
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,12 +1,12 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 21228000 # Number of ticks simulated
sim_ticks 21216000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 45998 # Simulator instruction rate (inst/s)
host_tick_rate 152436103 # Simulator tick rate (ticks/s)
host_mem_usage 157012 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_inst_rate 29106 # Simulator instruction rate (inst/s)
host_tick_rate 96412699 # Simulator tick rate (ticks/s)
host_mem_usage 242900 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 2084 # DT
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2094 # DTB accesses
system.cpu.itb.fetch_hits 932 # ITB hits
system.cpu.itb.fetch_hits 929 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 949 # ITB accesses
system.cpu.itb.fetch_accesses 946 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 42457 # number of cpu cycles simulated
system.cpu.numCycles 42433 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35048 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7409 # Number of cycles cpu stages are processed.
system.cpu.activity 17.450597 # Percentage of cycles cpu is active
system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7383 # Number of cycles cpu stages are processed.
system.cpu.activity 17.399194 # Percentage of cycles cpu is active
system.cpu.comLoads 1185 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1051 # Number of Branches instructions committed
@ -61,79 +61,79 @@ system.cpu.comFloats 2 # Nu
system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
system.cpu.cpi 6.629763 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.629763 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150835 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.150835 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1674 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 720 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1422 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits
system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1670 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 29.465541 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1104 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5167 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9747 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2137 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4444 # Number of Instructions Executed.
system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2138 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4447 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 37460 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4997 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.769555 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38535 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3922 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.237582 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38269 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4188 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.864098 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41117 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.156134 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 37979 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.547142 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.808044 # Cycle average of tags in use
system.cpu.icache.total_refs 584 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use
system.cpu.icache.total_refs 581 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.940199 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 138.808044 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.067777 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 584 # number of ReadReq hits
system.cpu.icache.demand_hits 584 # number of demand (read+write) hits
system.cpu.icache.overall_hits 584 # number of overall hits
system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits
system.cpu.icache.demand_hits 581 # number of demand (read+write) hits
system.cpu.icache.overall_hits 581 # number of overall hits
system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses
system.cpu.icache.demand_misses 348 # number of demand (read+write) misses
system.cpu.icache.overall_misses 348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 19242000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 19242000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 19242000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 932 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 932 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 932 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.373391 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.373391 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.373391 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55293.103448 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55293.103448 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55293.103448 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -150,28 +150,28 @@ system.cpu.icache.ReadReq_mshr_misses 302 # nu
system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 16050000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 16050000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 16050000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.324034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.324034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.324034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53145.695364 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.626911 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use
system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 102.626911 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.025055 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits
system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits
@ -181,9 +181,9 @@ system.cpu.dcache.WriteReq_misses 250 # nu
system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 347 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 13555000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 19063500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 19063500 # number of overall miss cycles
system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
@ -193,9 +193,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.289017 # mi
system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 54220 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54938.040346 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54938.040346 # average overall miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -215,30 +215,30 @@ system.cpu.dcache.demand_mshr_misses 168 # nu
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3909500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9023500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9023500 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.794521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 195.111607 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 195.111607 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005954 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1 # number of overall hits
@ -246,8 +246,8 @@ system.cpu.l2cache.ReadReq_misses 396 # nu
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 20702500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3821500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses)
@ -258,8 +258,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997481 # mi
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52279.040404 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52349.315068 # average ReadExReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@ -278,19 +278,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 73 # nu
system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 15876500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18819000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18819000 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40092.171717 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -498,7 +499,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

10
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 19 2011 06:59:13
gem5 started Jun 19 2011 07:04:58
gem5 executing on m60-009.pool
command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
gem5 compiled Jul 8 2011 15:00:53
gem5 started Jul 8 2011 15:20:58
gem5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 12357500 because target called exit()
Exiting @ tick 12002500 because target called exit()

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