regess: protocol regression tester updates
This commit is contained in:
Brad Beckmann
parent
ea9d4c3a97
commit
4eab18fd06
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@ -1,13 +1,22 @@
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[root]
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type=Root
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children=system
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dummy=0
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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[system]
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type=System
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children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
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mem_mode=timing
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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[system.cpu]
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type=TimingSimpleCPU
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@ -54,7 +63,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -186,6 +195,7 @@ tracer=system.ruby.tracer
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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@ -34,27 +34,27 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Jan/13/2011 22:36:30
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Real time: Feb/08/2011 17:31:55
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 2
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Elapsed_time_in_minutes: 0.0333333
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Elapsed_time_in_hours: 0.000555556
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Elapsed_time_in_days: 2.31481e-05
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 1.2
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Virtual_time_in_minutes: 0.02
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Virtual_time_in_hours: 0.000333333
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Virtual_time_in_days: 1.38889e-05
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Virtual_time_in_seconds: 0.51
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Virtual_time_in_minutes: 0.0085
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Virtual_time_in_hours: 0.000141667
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Virtual_time_in_days: 5.90278e-06
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Ruby_current_time: 275313
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Ruby_start_time: 0
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Ruby_cycles: 275313
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mbytes_resident: 22.0195
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mbytes_total: 156.82
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resident_ratio: 0.140462
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mbytes_resident: 37.0469
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mbytes_total: 210.465
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resident_ratio: 0.176098
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ruby_cycles_executed: [ 275314 ]
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@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standa
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Resource Usage
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--------------
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page_size: 4096
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user_time: 1
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user_time: 0
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system_time: 0
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page_reclaims: 6300
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page_reclaims: 10681
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page_faults: 0
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swaps: 0
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block_inputs: 0
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jan 13 2011 22:36:25
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M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
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M5 started Jan 13 2011 22:36:28
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M5 executing on scamorza.cs.wisc.edu
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M5 compiled Feb 8 2011 17:31:51
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M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
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M5 started Feb 8 2011 17:31:55
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M5 executing on SC2B0617
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command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 4080 # Simulator instruction rate (inst/s)
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host_mem_usage 160588 # Number of bytes of host memory used
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host_seconds 1.57 # Real time elapsed on the host
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host_tick_rate 175338 # Simulator tick rate (ticks/s)
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host_inst_rate 30108 # Simulator instruction rate (inst/s)
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host_mem_usage 215520 # Number of bytes of host memory used
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host_seconds 0.21 # Real time elapsed on the host
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host_tick_rate 1293296 # Simulator tick rate (ticks/s)
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_insts 6404 # Number of instructions simulated
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sim_seconds 0.000275 # Number of seconds simulated
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@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 275313 # number of cpu cycles simulated
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 275313 # Number of busy cycles
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system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
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system.cpu.num_fp_insts 10 # number of float instructions
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system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
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system.cpu.num_func_calls 251 # number of times a function call or return occured
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_insts 6404 # Number of instructions executed
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system.cpu.num_refs 2060 # Number of memory references
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system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
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system.cpu.num_int_insts 6331 # number of integer instructions
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system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
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system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
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system.cpu.num_load_insts 1192 # Number of load instructions
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system.cpu.num_mem_refs 2060 # number of memory refs
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system.cpu.num_store_insts 868 # Number of store instructions
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system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
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---------- End Simulation Statistics ----------
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@ -1,13 +1,22 @@
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[root]
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type=Root
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children=system
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dummy=0
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time_sync_enable=false
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time_sync_period=100000000
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time_sync_spin_threshold=100000
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[system]
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type=System
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children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
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mem_mode=timing
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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[system.cpu]
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type=TimingSimpleCPU
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@ -32,8 +41,8 @@ progress_interval=0
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.l1_cntrl0.sequencer.port[1]
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icache_port=system.l1_cntrl0.sequencer.port[0]
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dcache_port=system.ruby.cpu_ruby_ports.port[1]
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icache_port=system.ruby.cpu_ruby_ports.port[0]
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[system.cpu.dtb]
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type=AlphaTLB
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@ -54,7 +63,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -108,32 +117,19 @@ version=0
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[system.l1_cntrl0]
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type=L1Cache_Controller
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children=sequencer
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L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
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L1IcacheMemory=system.l1_cntrl0.sequencer.icache
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children=L1DcacheMemory L1IcacheMemory
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L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
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L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
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buffer_size=0
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l2_select_num_bits=0
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number_of_TBEs=256
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recycle_latency=10
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request_latency=2
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sequencer=system.l1_cntrl0.sequencer
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sequencer=system.ruby.cpu_ruby_ports
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transitions_per_cycle=32
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version=0
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[system.l1_cntrl0.sequencer]
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type=RubySequencer
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children=dcache icache
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dcache=system.l1_cntrl0.sequencer.dcache
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deadlock_threshold=500000
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icache=system.l1_cntrl0.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.l1_cntrl0.sequencer.dcache]
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[system.l1_cntrl0.L1DcacheMemory]
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type=RubyCache
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assoc=2
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latency=3
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@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
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size=256
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start_index_bit=6
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[system.l1_cntrl0.sequencer.icache]
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[system.l1_cntrl0.L1IcacheMemory]
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type=RubyCache
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assoc=2
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latency=3
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@ -177,14 +173,13 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.l1_cntrl0.sequencer.physMemPort
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port=system.ruby.cpu_ruby_ports.physMemPort
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[system.ruby]
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type=RubySystem
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children=debug network profiler tracer
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children=cpu_ruby_ports network profiler tracer
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block_size_bytes=64
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clock=1
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debug=system.ruby.debug
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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@ -194,13 +189,18 @@ randomization=false
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stats_filename=ruby.stats
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tracer=system.ruby.tracer
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[system.ruby.debug]
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type=RubyDebug
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filter_string=none
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output_filename=none
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protocol_trace=false
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start_time=1
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verbosity_string=none
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[system.ruby.cpu_ruby_ports]
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type=RubySequencer
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access_phys_mem=true
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dcache=system.l1_cntrl0.L1DcacheMemory
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deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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port=system.cpu.icache_port system.cpu.dcache_port
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[system.ruby.network]
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type=SimpleNetwork
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@ -216,9 +216,9 @@ topology=system.ruby.network.topology
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[system.ruby.network.topology]
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type=Topology
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children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
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description=Crossbar
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ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
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int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
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name=Crossbar
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num_int_nodes=4
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print_config=false
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@ -13,7 +13,7 @@ RubySystem config:
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: Crossbar
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topology:
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virtual_net_0: active, unordered
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virtual_net_1: active, unordered
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@ -34,27 +34,27 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Aug/05/2010 10:35:39
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Real time: Feb/08/2011 17:41:43
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.44
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Virtual_time_in_minutes: 0.00733333
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Virtual_time_in_hours: 0.000122222
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Virtual_time_in_days: 5.09259e-06
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Virtual_time_in_seconds: 0.52
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Virtual_time_in_minutes: 0.00866667
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Virtual_time_in_hours: 0.000144444
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Virtual_time_in_days: 6.01852e-06
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Ruby_current_time: 223854
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Ruby_start_time: 0
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Ruby_cycles: 223854
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mbytes_resident: 34.9609
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mbytes_total: 34.9688
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resident_ratio: 1
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mbytes_resident: 37.1562
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mbytes_total: 210.609
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resident_ratio: 0.176478
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ruby_cycles_executed: [ 223855 ]
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@ -119,8 +119,8 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 7630
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page_faults: 2184
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page_reclaims: 10696
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page_faults: 0
|
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swaps: 0
|
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block_inputs: 0
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block_outputs: 0
|
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@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.349752
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outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
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|
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Cache Stats: system.l1_cntrl0.sequencer.icache
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system.l1_cntrl0.sequencer.icache_total_misses: 0
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system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
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system.l1_cntrl0.sequencer.icache_total_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.L1IcacheMemory
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system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
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|
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Cache Stats: system.l1_cntrl0.sequencer.dcache
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system.l1_cntrl0.sequencer.dcache_total_misses: 0
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system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
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system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
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system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
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Cache Stats: system.l1_cntrl0.L1DcacheMemory
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system.l1_cntrl0.L1DcacheMemory_total_misses: 0
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system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
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system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
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system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
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system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
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|
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|
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--- L1Cache ---
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
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All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:34:54
|
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M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
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M5 started Aug 5 2010 10:35:39
|
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M5 executing on svvint09
|
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M5 compiled Feb 8 2011 17:41:34
|
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M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
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M5 started Feb 8 2011 17:41:42
|
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M5 executing on SC2B0617
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command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 23717 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212528 # Number of bytes of host memory used
|
||||
host_seconds 0.27 # Real time elapsed on the host
|
||||
host_tick_rate 829037 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 26297 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215668 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 918519 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000224 # Number of seconds simulated
|
||||
|
|
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
|||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 223854 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 223854 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -32,8 +41,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -111,9 +120,9 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -125,24 +134,11 @@ no_mig_atomic=true
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
|
|||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -188,14 +184,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -205,13 +200,18 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -227,9 +227,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:42:35
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.27
|
||||
Virtual_time_in_minutes: 0.0045
|
||||
Virtual_time_in_hours: 7.5e-05
|
||||
Virtual_time_in_days: 3.125e-06
|
||||
Virtual_time_in_seconds: 0.4
|
||||
Virtual_time_in_minutes: 0.00666667
|
||||
Virtual_time_in_hours: 0.000111111
|
||||
Virtual_time_in_days: 4.62963e-06
|
||||
|
||||
Ruby_current_time: 243131
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 243131
|
||||
|
||||
mbytes_resident: 34.8711
|
||||
mbytes_total: 34.8789
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 37.0508
|
||||
mbytes_total: 210.492
|
||||
resident_ratio: 0.176057
|
||||
|
||||
ruby_cycles_executed: [ 243132 ]
|
||||
|
||||
|
|
@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -89,13 +89,13 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 ave
|
|||
imcomplete_dir_Times: 1300
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -127,8 +127,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7568
|
||||
page_faults: 2181
|
||||
page_reclaims: 10655
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -197,28 +197,28 @@ links_utilized_percent_switch_3: 0.209297
|
|||
outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 646
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 646
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 646 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 734
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 734
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.5259%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.4741%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 734 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
|
@ -226,7 +226,7 @@ Load [1185 ] 1185
|
|||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [1384 ] 1384
|
||||
L1_Replacement [1365 ] 1365
|
||||
Data_Shared [48 ] 48
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [1332 ] 1332
|
||||
|
|
@ -356,7 +356,7 @@ M_W Load [102 ] 102
|
|||
M_W Ifetch [2271 ] 2271
|
||||
M_W Store [25 ] 25
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [21 ] 21
|
||||
M_W L1_Replacement [8 ] 8
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
|
|
@ -373,7 +373,7 @@ MM_W Load [21 ] 21
|
|||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [265 ] 265
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [9 ] 9
|
||||
MM_W L1_Replacement [3 ] 3
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
|
|
@ -743,18 +743,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_reads: 1301
|
||||
memory_writes: 241
|
||||
memory_refreshes: 507
|
||||
memory_total_request_delays: 714
|
||||
memory_delays_per_request: 0.463035
|
||||
memory_total_request_delays: 709
|
||||
memory_delays_per_request: 0.459792
|
||||
memory_delays_in_input_queue: 240
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 474
|
||||
memory_stalls_for_bank_busy: 148
|
||||
memory_delays_stalled_at_head_of_bank_queue: 469
|
||||
memory_stalls_for_bank_busy: 141
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 30
|
||||
memory_stalls_for_bus: 278
|
||||
memory_stalls_for_arbitration: 33
|
||||
memory_stalls_for_bus: 279
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 18
|
||||
memory_stalls_for_read_write_turnaround: 16
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56
|
||||
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:42:35
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 45740 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212336 # Number of bytes of host memory used
|
||||
host_inst_rate 46789 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215548 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1736538 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 1774187 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000243 # Number of seconds simulated
|
||||
|
|
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
|||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 243131 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 243131 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -32,8 +41,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -70,6 +79,7 @@ type=Directory_Controller
|
|||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
|
|
@ -118,17 +128,18 @@ start_index_bit=6
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
|
|
@ -140,35 +151,6 @@ replacement_policy=PSEUDO_LRU
|
|||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -177,14 +159,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -194,13 +175,35 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.cpu_ruby_ports.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -216,9 +219,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 11:09:30
|
||||
Real time: Feb/08/2011 17:57:03
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.61
|
||||
Virtual_time_in_minutes: 0.0101667
|
||||
Virtual_time_in_hours: 0.000169444
|
||||
Virtual_time_in_days: 7.06019e-06
|
||||
Virtual_time_in_seconds: 0.42
|
||||
Virtual_time_in_minutes: 0.007
|
||||
Virtual_time_in_hours: 0.000116667
|
||||
Virtual_time_in_days: 4.86111e-06
|
||||
|
||||
Ruby_current_time: 207970
|
||||
Ruby_current_time: 208400
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 207970
|
||||
Ruby_cycles: 208400
|
||||
|
||||
mbytes_resident: 34.3633
|
||||
mbytes_total: 206.125
|
||||
resident_ratio: 0.166768
|
||||
mbytes_resident: 36.6641
|
||||
mbytes_total: 209.902
|
||||
resident_ratio: 0.174709
|
||||
|
||||
ruby_cycles_executed: [ 207971 ]
|
||||
ruby_cycles_executed: [ 208401 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
|
||||
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
|
|||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
imcomplete_dir_Times: 1158
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -126,7 +126,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9927
|
||||
page_reclaims: 10608
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -144,9 +144,9 @@ total_msgs: 20718 total_bytes: 430512
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.111284
|
||||
links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.111054
|
||||
links_utilized_percent_switch_0_link_0: 0.0694218 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.152687 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.111284
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.158256
|
||||
links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.157929
|
||||
links_utilized_percent_switch_1_link_0: 0.0381718 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.277687 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.158256
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.215632
|
||||
links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.215187
|
||||
links_utilized_percent_switch_2_link_0: 0.277687 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.152687 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215632
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 646
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
system.ruby.cpu_ruby_ports.icache_total_misses: 646
|
||||
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
|
||||
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 646 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 716
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 716
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 716 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 1159
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 1362
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1362 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [1201 ] 1201
|
||||
Ifetch [6436 ] 6436
|
||||
Store [919 ] 919
|
||||
Load [1193 ] 1193
|
||||
Ifetch [6425 ] 6425
|
||||
Store [892 ] 892
|
||||
L2_Replacement [1143 ] 1143
|
||||
L1_to_L2 [1354 ] 1354
|
||||
Trigger_L2_to_L1D [138 ] 138
|
||||
|
|
@ -231,6 +231,7 @@ Other_GETX [0 ] 0
|
|||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
|
|
@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
|
|||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
|
|
@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
|
|||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
|
|
@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
|
|||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
|
||||
M Load [368 ] 368
|
||||
|
|
@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
|
|||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
|
||||
MM Load [397 ] 397
|
||||
|
|
@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
|
|||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
|
|
@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
|
|||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
|
|
@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
|
|||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
|
|
@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
|
|||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
|
|
@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
|
|||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
|
|
@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
|
|||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
|
||||
MI Load [16 ] 16
|
||||
MI Ifetch [22 ] 22
|
||||
MI Store [54 ] 54
|
||||
MI Load [8 ] 8
|
||||
MI Ifetch [11 ] 11
|
||||
MI Store [27 ] 27
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [1143 ] 1143
|
||||
|
||||
|
|
@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
|
|||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
|
@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
|
|||
IT Other_GETS [0 ] 0
|
||||
IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
|
|
@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
|
|||
ST Other_GETS [0 ] 0
|
||||
ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
|
|
@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
|
|||
OT Other_GETS [0 ] 0
|
||||
OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
|
|
@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
|
|||
MT Other_GETS [0 ] 0
|
||||
MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
|
|
@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
|
|||
MMT Other_GETS [0 ] 0
|
||||
MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
|
@ -502,19 +521,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_total_requests: 1379
|
||||
memory_reads: 1159
|
||||
memory_writes: 220
|
||||
memory_refreshes: 434
|
||||
memory_total_request_delays: 471
|
||||
memory_delays_per_request: 0.341552
|
||||
memory_delays_in_input_queue: 15
|
||||
memory_refreshes: 435
|
||||
memory_total_request_delays: 495
|
||||
memory_delays_per_request: 0.358956
|
||||
memory_delays_in_input_queue: 3
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 456
|
||||
memory_stalls_for_bank_busy: 86
|
||||
memory_delays_stalled_at_head_of_bank_queue: 492
|
||||
memory_stalls_for_bank_busy: 124
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 30
|
||||
memory_stalls_for_arbitration: 23
|
||||
memory_stalls_for_bus: 78
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 262
|
||||
memory_stalls_for_read_write_turnaround: 267
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
|
||||
|
||||
|
|
@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
|
|||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
|
|
@ -648,6 +669,7 @@ O_B GETX [0 ] 0
|
|||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
|
||||
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 11:09:13
|
||||
M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 11:09:30
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 207970 because target called exit()
|
||||
Exiting @ tick 208400 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 31390 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211076 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 1018487 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 50833 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214944 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 1651975 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000208 # Number of seconds simulated
|
||||
sim_ticks 207970 # Number of ticks simulated
|
||||
sim_ticks 208400 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
|
@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 207970 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 208400 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 208400 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 251 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 6331 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_mem_refs 2060 # number of memory refs
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -54,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -186,6 +195,7 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
|
|||
|
|
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/13/2011 22:36:30
|
||||
Real time: Feb/08/2011 17:31:55
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 2
|
||||
Elapsed_time_in_minutes: 0.0333333
|
||||
Elapsed_time_in_hours: 0.000555556
|
||||
Elapsed_time_in_days: 2.31481e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.79
|
||||
Virtual_time_in_minutes: 0.0131667
|
||||
Virtual_time_in_hours: 0.000219444
|
||||
Virtual_time_in_days: 9.14352e-06
|
||||
Virtual_time_in_seconds: 0.39
|
||||
Virtual_time_in_minutes: 0.0065
|
||||
Virtual_time_in_hours: 0.000108333
|
||||
Virtual_time_in_days: 4.51389e-06
|
||||
|
||||
Ruby_current_time: 103637
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 103637
|
||||
|
||||
mbytes_resident: 20.9219
|
||||
mbytes_total: 156.062
|
||||
resident_ratio: 0.134111
|
||||
mbytes_resident: 35.7188
|
||||
mbytes_total: 209.473
|
||||
resident_ratio: 0.170592
|
||||
|
||||
ruby_cycles_executed: [ 103638 ]
|
||||
|
||||
|
|
@ -119,7 +119,7 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6028
|
||||
page_reclaims: 10341
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 13 2011 22:36:25
|
||||
M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
|
||||
M5 started Jan 13 2011 22:36:28
|
||||
M5 executing on scamorza.cs.wisc.edu
|
||||
M5 compiled Feb 8 2011 17:31:51
|
||||
M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:31:55
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2534 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159812 # Number of bytes of host memory used
|
||||
host_seconds 1.02 # Real time elapsed on the host
|
||||
host_tick_rate 101843 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 31237 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214504 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 1253532 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000104 # Number of seconds simulated
|
||||
|
|
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
|||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 103637 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 103637 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -32,8 +41,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -108,32 +117,19 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
|
|||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -177,14 +173,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -194,13 +189,18 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -216,9 +216,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:37:10
|
||||
Real time: Feb/08/2011 17:41:43
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.41
|
||||
Virtual_time_in_minutes: 0.00683333
|
||||
Virtual_time_in_hours: 0.000113889
|
||||
Virtual_time_in_days: 4.74537e-06
|
||||
Virtual_time_in_seconds: 0.4
|
||||
Virtual_time_in_minutes: 0.00666667
|
||||
Virtual_time_in_hours: 0.000111111
|
||||
Virtual_time_in_days: 4.62963e-06
|
||||
|
||||
Ruby_current_time: 85988
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 85988
|
||||
|
||||
mbytes_resident: 33.6484
|
||||
mbytes_total: 33.6562
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 35.8359
|
||||
mbytes_total: 209.617
|
||||
resident_ratio: 0.171015
|
||||
|
||||
ruby_cycles_executed: [ 85989 ]
|
||||
|
||||
|
|
@ -119,8 +119,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7386
|
||||
page_faults: 2090
|
||||
page_reclaims: 10362
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645
|
|||
outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
--- L1Cache ---
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:37:10
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:41:34
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:41:42
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 19822 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211548 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 661411 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 26760 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214652 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 891261 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000086 # Number of seconds simulated
|
||||
|
|
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
|||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 85988 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 85988 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -32,8 +41,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -111,9 +120,9 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -125,24 +134,11 @@ no_mig_atomic=true
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
|
|||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -188,14 +184,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -205,13 +200,18 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -227,9 +227,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:43:25
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.25
|
||||
Virtual_time_in_minutes: 0.00416667
|
||||
Virtual_time_in_hours: 6.94444e-05
|
||||
Virtual_time_in_days: 2.89352e-06
|
||||
Virtual_time_in_seconds: 0.33
|
||||
Virtual_time_in_minutes: 0.0055
|
||||
Virtual_time_in_hours: 9.16667e-05
|
||||
Virtual_time_in_days: 3.81944e-06
|
||||
|
||||
Ruby_current_time: 92099
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 92099
|
||||
|
||||
mbytes_resident: 33.5859
|
||||
mbytes_total: 33.5938
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 35.7695
|
||||
mbytes_total: 209.457
|
||||
resident_ratio: 0.17081
|
||||
|
||||
ruby_cycles_executed: [ 92100 ]
|
||||
|
||||
|
|
@ -127,8 +127,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7341
|
||||
page_faults: 2084
|
||||
page_reclaims: 10334
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
|
|||
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 270
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 270
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 243
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 243
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
|
@ -222,7 +222,7 @@ Load [415 ] 415
|
|||
Ifetch [2585 ] 2585
|
||||
Store [294 ] 294
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [506 ] 506
|
||||
L1_Replacement [503 ] 503
|
||||
Data_Shared [18 ] 18
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [495 ] 495
|
||||
|
|
@ -352,7 +352,7 @@ M_W Load [47 ] 47
|
|||
M_W Ifetch [1038 ] 1038
|
||||
M_W Store [6 ] 6
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [4 ] 4
|
||||
M_W L1_Replacement [1 ] 1
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:43:25
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 42948 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211392 # Number of bytes of host memory used
|
||||
host_inst_rate 44139 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214488 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 1534907 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 1572917 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000092 # Number of seconds simulated
|
||||
|
|
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
|
|||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 92099 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 92099 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -32,8 +41,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -70,6 +79,7 @@ type=Directory_Controller
|
|||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
|
|
@ -118,17 +128,18 @@ start_index_bit=6
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
|
|
@ -140,35 +151,6 @@ replacement_policy=PSEUDO_LRU
|
|||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -177,14 +159,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -194,13 +175,35 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.cpu_ruby_ports.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -216,9 +219,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 14:44:19
|
||||
Real time: Feb/08/2011 17:57:03
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.21
|
||||
Virtual_time_in_minutes: 0.0035
|
||||
Virtual_time_in_hours: 5.83333e-05
|
||||
Virtual_time_in_days: 2.43056e-06
|
||||
Virtual_time_in_seconds: 0.34
|
||||
Virtual_time_in_minutes: 0.00566667
|
||||
Virtual_time_in_hours: 9.44444e-05
|
||||
Virtual_time_in_days: 3.93519e-06
|
||||
|
||||
Ruby_current_time: 78408
|
||||
Ruby_current_time: 78448
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 78408
|
||||
Ruby_cycles: 78448
|
||||
|
||||
mbytes_resident: 33.3242
|
||||
mbytes_total: 33.332
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 35.3906
|
||||
mbytes_total: 208.879
|
||||
resident_ratio: 0.169469
|
||||
|
||||
ruby_cycles_executed: [ 78409 ]
|
||||
ruby_cycles_executed: [ 78449 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
|
||||
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
|
||||
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
|
|||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
imcomplete_dir_Times: 440
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -126,8 +126,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7298
|
||||
page_faults: 2071
|
||||
page_reclaims: 10290
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.110878
|
||||
links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.110822
|
||||
links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110878
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.159064
|
||||
links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.158983
|
||||
links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.159064
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.215954
|
||||
links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.215844
|
||||
links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215954
|
|||
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 270
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
system.ruby.cpu_ruby_ports.icache_total_misses: 270
|
||||
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
|
||||
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 240
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 240
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 441
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 510
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [428 ] 428
|
||||
Ifetch [2597 ] 2597
|
||||
Store [302 ] 302
|
||||
Load [422 ] 422
|
||||
Ifetch [2591 ] 2591
|
||||
Store [298 ] 298
|
||||
L2_Replacement [425 ] 425
|
||||
L1_to_L2 [502 ] 502
|
||||
Trigger_L2_to_L1D [47 ] 47
|
||||
|
|
@ -231,6 +231,7 @@ Other_GETX [0 ] 0
|
|||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
|
|
@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
|
|||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
|
|
@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
|
|||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
|
|
@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
|
|||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
|
||||
M Load [131 ] 131
|
||||
|
|
@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
|
|||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
|
||||
MM Load [138 ] 138
|
||||
|
|
@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
|
|||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
|
|
@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
|
|||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
|
|
@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
|
|||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
|
|
@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
|
|||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
|
|
@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
|
|||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
|
|
@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
|
|||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
|
||||
MI Load [13 ] 13
|
||||
MI Ifetch [12 ] 12
|
||||
MI Store [8 ] 8
|
||||
MI Load [7 ] 7
|
||||
MI Ifetch [6 ] 6
|
||||
MI Store [4 ] 4
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [425 ] 425
|
||||
|
||||
|
|
@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
|
|||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
|
@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
|
|||
IT Other_GETS [0 ] 0
|
||||
IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
|
|
@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
|
|||
ST Other_GETS [0 ] 0
|
||||
ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
|
|
@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
|
|||
OT Other_GETS [0 ] 0
|
||||
OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
|
|
@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
|
|||
MT Other_GETS [0 ] 0
|
||||
MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
|
|
@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
|
|||
MMT Other_GETS [0 ] 0
|
||||
MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
|
@ -503,18 +522,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_reads: 441
|
||||
memory_writes: 81
|
||||
memory_refreshes: 164
|
||||
memory_total_request_delays: 147
|
||||
memory_delays_per_request: 0.281609
|
||||
memory_total_request_delays: 151
|
||||
memory_delays_per_request: 0.289272
|
||||
memory_delays_in_input_queue: 2
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 145
|
||||
memory_stalls_for_bank_busy: 27
|
||||
memory_delays_stalled_at_head_of_bank_queue: 149
|
||||
memory_stalls_for_bank_busy: 22
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 6
|
||||
memory_stalls_for_bus: 23
|
||||
memory_stalls_for_arbitration: 7
|
||||
memory_stalls_for_bus: 26
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 89
|
||||
memory_stalls_for_read_write_turnaround: 94
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
|
||||
|
||||
|
|
@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
|
|||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
|
|
@ -648,6 +669,7 @@ O_B GETX [0 ] 0
|
|||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 14:43:33
|
||||
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 14:44:19
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 78408 because target called exit()
|
||||
Exiting @ tick 78448 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 42947 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211060 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 1306713 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 49095 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213896 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 1489708 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000078 # Number of seconds simulated
|
||||
sim_ticks 78408 # Number of ticks simulated
|
||||
sim_ticks 78448 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
|
@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 78408 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 78448 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 78448 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 140 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 2375 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_mem_refs 717 # number of memory refs
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
|
|
@ -492,8 +501,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -504,8 +514,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -516,8 +527,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -528,8 +540,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -540,8 +553,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -552,8 +566,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -564,8 +579,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -576,8 +592,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
|
|||
|
|
@ -34,47 +34,47 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/13/2011 22:37:51
|
||||
Real time: Feb/08/2011 17:40:23
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 83
|
||||
Elapsed_time_in_minutes: 1.38333
|
||||
Elapsed_time_in_hours: 0.0230556
|
||||
Elapsed_time_in_days: 0.000960648
|
||||
Elapsed_time_in_seconds: 508
|
||||
Elapsed_time_in_minutes: 8.46667
|
||||
Elapsed_time_in_hours: 0.141111
|
||||
Elapsed_time_in_days: 0.00587963
|
||||
|
||||
Virtual_time_in_seconds: 82.77
|
||||
Virtual_time_in_minutes: 1.3795
|
||||
Virtual_time_in_hours: 0.0229917
|
||||
Virtual_time_in_days: 0.000957986
|
||||
Virtual_time_in_seconds: 508.81
|
||||
Virtual_time_in_minutes: 8.48017
|
||||
Virtual_time_in_hours: 0.141336
|
||||
Virtual_time_in_days: 0.005889
|
||||
|
||||
Ruby_current_time: 3750455
|
||||
Ruby_current_time: 44606455
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 3750455
|
||||
Ruby_cycles: 44606455
|
||||
|
||||
mbytes_resident: 19.9609
|
||||
mbytes_total: 283.734
|
||||
resident_ratio: 0.0703783
|
||||
mbytes_resident: 36.0898
|
||||
mbytes_total: 338.191
|
||||
resident_ratio: 0.106749
|
||||
|
||||
ruby_cycles_executed: [ 3750456 3750456 3750456 3750456 3750456 3750456 3750456 3750456 ]
|
||||
ruby_cycles_executed: [ 44606456 44606456 44606456 44606456 44606456 44606456 44606456 44606456 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
||||
L2Cache-0:0
|
||||
L2Cache-0:26511
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1214418 average: 1.94809 | standard deviation: 0.221842 | 0 63038 1151380 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1209678 average: 15.9992 | standard deviation: 0.0905568 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1209558 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 4096 max: 668164 count: 1209550 average: 4719.92 | standard deviation: 8274.07 | 638780 444277 77264 20058 11632 6634 3721 2287 1498 951 565 385 192 142 161 87 51 58 50 36 40 36 47 26 23 19 17 23 21 23 19 17 18 10 12 15 16 14 17 11 13 10 18 10 10 15 7 8 5 10 13 8 6 4 7 3 3 7 7 11 4 5 2 3 4 2 3 1 2 9 3 3 0 3 1 5 2 4 3 0 0 3 2 2 2 2 2 2 2 1 1 1 1 3 2 2 1 1 1 2 1 0 2 2 2 0 0 1 1 2 1 2 4 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 4096 max: 668164 count: 786272 average: 4719.14 | standard deviation: 8618.14 | 415711 288653 50021 12927 7526 4347 2411 1503 957 613 346 254 128 93 117 61 33 39 28 17 27 20 28 16 16 10 14 18 16 18 16 13 9 9 7 9 11 8 12 7 10 6 11 7 7 8 5 8 3 6 9 3 5 2 6 3 2 6 6 9 3 4 1 2 4 1 0 1 2 6 0 3 0 2 1 2 1 3 2 0 0 2 1 2 1 2 1 2 0 1 1 1 1 2 1 1 0 1 0 2 1 0 2 1 0 0 0 1 1 2 1 1 3 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 4096 max: 528524 count: 423278 average: 4721.37 | standard deviation: 6405.47 | 223069 155624 27243 7131 4106 2287 1310 784 541 338 219 131 64 49 44 26 18 19 22 19 13 16 19 10 7 9 3 5 5 5 3 4 9 1 5 6 5 6 5 4 3 4 7 3 3 7 2 0 2 4 4 5 1 2 1 0 1 1 1 2 1 1 1 1 0 1 3 0 0 3 3 0 0 1 0 3 1 1 1 0 0 1 1 0 1 0 1 0 2 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_NULL: [binsize: 4096 max: 668164 count: 1209550 average: 4719.92 | standard deviation: 8274.07 | 638780 444277 77264 20058 11632 6634 3721 2287 1498 951 565 385 192 142 161 87 51 58 50 36 40 36 47 26 23 19 17 23 21 23 19 17 18 10 12 15 16 14 17 11 13 10 18 10 10 15 7 8 5 10 13 8 6 4 7 3 3 7 7 11 4 5 2 3 4 2 3 1 2 9 3 3 0 3 1 5 2 4 3 0 0 3 2 2 2 2 2 2 2 1 1 1 1 3 2 2 1 1 1 2 1 0 2 2 2 0 0 1 1 2 1 2 4 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,8 +85,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
|||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 0
|
||||
miss_latency_LD_NULL: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_NULL: [binsize: 4096 max: 668164 count: 786272 average: 4719.14 | standard deviation: 8618.14 | 415711 288653 50021 12927 7526 4347 2411 1503 957 613 346 254 128 93 117 61 33 39 28 17 27 20 28 16 16 10 14 18 16 18 16 13 9 9 7 9 11 8 12 7 10 6 11 7 7 8 5 8 3 6 9 3 5 2 6 3 2 6 6 9 3 4 1 2 4 1 0 1 2 6 0 3 0 2 1 2 1 3 2 0 0 2 1 2 1 2 1 2 0 1 1 1 1 2 1 1 0 1 0 2 1 0 2 1 0 0 0 1 1 2 1 1 3 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_NULL: [binsize: 4096 max: 528524 count: 423278 average: 4721.37 | standard deviation: 6405.47 | 223069 155624 27243 7131 4106 2287 1310 784 541 338 219 131 64 49 44 26 18 19 22 19 13 16 19 10 7 9 3 5 5 5 3 4 9 1 5 6 5 6 5 4 3 4 7 3 3 7 2 0 2 4 4 5 1 2 1 0 1 1 1 2 1 1 1 1 0 1 3 0 0 3 3 0 0 1 0 3 1 1 1 0 0 1 1 0 1 0 1 0 2 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -100,12 +100,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 32 max: 1060 count: 1913633 average: 23.7314 | standard deviation: 66.6438 | 1615818 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603 | standard deviation: 0.057655 | 1196518 2179 404 22 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 32 max: 1060 count: 714510 average: 63.5543 | standard deviation: 96.7696 | 416695 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_delay_cycles: [binsize: 2048 max: 81271 count: 9469233 average: 110.621 | standard deviation: 505.81 | 9455869 3415 2382 1953 1397 1072 815 622 431 313 232 152 153 103 80 56 46 40 17 18 15 12 4 8 2 6 7 3 2 2 0 1 0 0 3 0 0 0 0 2 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 1 count: 6455267 average: 5.1276e-05 | standard deviation: 0.00716072 | 6454936 331 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 2048 max: 81271 count: 3013966 average: 347.548 | standard deviation: 849.39 | 3000602 3415 2382 1953 1397 1072 815 622 431 313 232 152 153 103 80 56 46 40 17 18 15 12 4 8 2 6 7 3 2 2 0 1 0 0 3 0 0 0 0 2 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 472614 average: 0.0053257 | standard deviation: 0.0852408 | 470540 1653 399 22 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 726509 average: 0.000737775 | standard deviation: 0.0274142 | 725978 526 5 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 1 count: 1119608 average: 6.25219e-06 | standard deviation: 0.00250044 | 1119601 7 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 1 count: 5335659 average: 6.07235e-05 | standard deviation: 0.00779253 | 5335335 324 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -116,9 +116,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 82
|
||||
user_time: 508
|
||||
system_time: 0
|
||||
page_reclaims: 5799
|
||||
page_reclaims: 10505
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
@ -127,181 +127,208 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1169847 9358776
|
||||
total_msg_count_Request_Control: 1269806 10158448
|
||||
total_msg_count_Response_Data: 1417845 102084840
|
||||
total_msg_count_Response_Control: 1735406 13883248
|
||||
total_msgs: 5592904 total_bytes: 135485312
|
||||
total_msg_count_Control: 7234287 57874296
|
||||
total_msg_count_Request_Control: 3352867 26822936
|
||||
total_msg_count_Response_Data: 8501093 612078696
|
||||
total_msg_count_Response_Control: 12544428 100355424
|
||||
total_msg_count_Writeback_Data: 2803846 201876912
|
||||
total_msg_count_Writeback_Control: 1171668 9373344
|
||||
total_msgs: 35608189 total_bytes: 1008381608
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.416004
|
||||
links_utilized_percent_switch_0_link_0: 0.17421 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.657799 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.104449
|
||||
links_utilized_percent_switch_0_link_0: 0.0444403 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.164457 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 49369 394952 [ 49369 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 41367 2978424 [ 0 41367 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 71737 573896 [ 0 30695 41042 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 141029 1128232 [ 141029 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 152090 10950480 [ 0 152090 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 76021 608168 [ 0 76021 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 152092 1216736 [ 152092 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 484 34848 [ 0 484 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 200672 1605376 [ 0 49763 150909 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 117888 8487936 [ 26963 90925 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 49059 392472 [ 49059 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.412969
|
||||
links_utilized_percent_switch_1_link_0: 0.173819 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.65212 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.105352
|
||||
links_utilized_percent_switch_1_link_0: 0.0448859 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.165818 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 49257 394056 [ 49257 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 40912 2945664 [ 0 40912 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 71684 573472 [ 0 30672 41012 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 142261 1138088 [ 142261 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 153623 11060856 [ 0 153623 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 76891 615128 [ 0 76891 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 153625 1229000 [ 153625 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 491 35352 [ 0 491 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 202705 1621640 [ 0 50260 152445 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 118753 8550216 [ 27097 91656 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 49789 398312 [ 49789 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.4136
|
||||
links_utilized_percent_switch_2_link_0: 0.173041 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.654158 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.1034
|
||||
links_utilized_percent_switch_2_link_0: 0.0441434 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.162657 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 49047 392376 [ 49047 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 41125 2961000 [ 0 41125 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 71506 572048 [ 0 30453 41053 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 139745 1117960 [ 139745 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 151126 10881072 [ 0 151126 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 75386 603088 [ 0 75386 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 151129 1209032 [ 151129 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 485 34920 [ 0 485 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 199681 1597448 [ 0 49774 149907 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 116365 8378280 [ 26738 89627 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 48648 389184 [ 48648 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 0.410067
|
||||
links_utilized_percent_switch_3_link_0: 0.172661 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.647473 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.104799
|
||||
links_utilized_percent_switch_3_link_0: 0.0446279 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.16497 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 48856 390848 [ 48856 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 40642 2926224 [ 0 40642 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 71030 568240 [ 0 30194 40836 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 141577 1132616 [ 141577 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 152754 10998288 [ 0 152754 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 76191 609528 [ 0 76191 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 152758 1222064 [ 152758 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 515 37080 [ 0 515 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 201709 1613672 [ 0 50165 151544 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 118175 8508600 [ 27125 91050 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 49066 392528 [ 49066 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 0.407326
|
||||
links_utilized_percent_switch_4_link_0: 0.17208 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0.642573 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_4: 0.10421
|
||||
links_utilized_percent_switch_4_link_0: 0.0443719 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0.164048 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 48686 389488 [ 48686 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 40277 2899944 [ 0 40277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Control: 70809 566472 [ 0 30317 40492 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Request_Control: 140569 1124552 [ 140569 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 151893 10936296 [ 0 151893 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Control: 75812 606496 [ 0 75812 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 151895 1215160 [ 151895 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 513 36936 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Control: 200376 1603008 [ 0 49681 150695 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Writeback_Data: 117536 8462592 [ 27004 90532 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Writeback_Control: 48808 390464 [ 48808 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 0.408786
|
||||
links_utilized_percent_switch_5_link_0: 0.171315 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.646256 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 0.101404
|
||||
links_utilized_percent_switch_5_link_0: 0.0432323 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.159576 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 48502 388016 [ 48502 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 40634 2925648 [ 0 40634 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 70543 564344 [ 0 30139 40404 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Request_Control: 137030 1096240 [ 137030 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 147989 10655208 [ 0 147989 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Control: 73821 590568 [ 0 73821 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 147993 1183944 [ 147993 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 504 36288 [ 0 504 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Control: 195355 1562840 [ 0 48520 146835 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Writeback_Data: 114221 8223912 [ 26070 88151 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Writeback_Control: 47750 382000 [ 47750 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 0.405763
|
||||
links_utilized_percent_switch_6_link_0: 0.170848 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 0.640678 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 0.102366
|
||||
links_utilized_percent_switch_6_link_0: 0.0437156 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 0.161015 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 48385 387080 [ 48385 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 40226 2896272 [ 0 40226 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Control: 70148 561184 [ 0 30034 40114 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Request_Control: 138259 1106072 [ 138259 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 149657 10775304 [ 0 149657 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Control: 74826 598608 [ 0 74826 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 149660 1197280 [ 149660 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 453 32616 [ 0 453 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Control: 197444 1579552 [ 0 48952 148492 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Writeback_Data: 115184 8293248 [ 26197 88987 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Writeback_Control: 48629 389032 [ 48629 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 0.399042
|
||||
links_utilized_percent_switch_7_link_0: 0.169071 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 0.629013 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_7: 0.103268
|
||||
links_utilized_percent_switch_7_link_0: 0.0439489 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 0.162587 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 47845 382760 [ 47845 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 39394 2836368 [ 0 39394 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Control: 69426 555408 [ 0 29802 39624 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Request_Control: 139138 1113104 [ 139138 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 150412 10829664 [ 0 150412 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Control: 75477 603816 [ 0 75477 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 150413 1203304 [ 150413 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 521 37512 [ 0 521 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Control: 198127 1585016 [ 0 48950 149177 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Writeback_Data: 116494 8387568 [ 26667 89827 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Writeback_Control: 48807 390456 [ 48807 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 1.37261
|
||||
links_utilized_percent_switch_8_link_0: 0.520924 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 2.22429 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_8: 1.35802
|
||||
links_utilized_percent_switch_8_link_0: 0.662373 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 2.05366 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Control: 324576 2596608 [ 0 0 324576 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Request_Control: 324578 2596624 [ 324578 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 148028 10658016 [ 0 148028 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Control: 11586 92688 [ 0 11586 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 1209565 9676520 [ 1209565 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Data: 1203036 86618592 [ 0 1203036 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Response_Control: 2797904 22383232 [ 0 1597900 1200004 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Writeback_Data: 934615 67292280 [ 213861 720754 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Writeback_Control: 390556 3124448 [ 390556 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Request_Control: 1113651 8909208 [ 1113651 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 1624693 116977896 [ 0 1624693 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Control: 1383558 11068464 [ 0 1383558 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 2
|
||||
switch_9_outlinks: 2
|
||||
links_utilized_percent_switch_9: 1.23318e-05
|
||||
links_utilized_percent_switch_9_link_0: 6.66586e-07 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 2.39971e-05 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9: 0.754651
|
||||
links_utilized_percent_switch_9_link_0: 0.162123 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 1.34718 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 422708 30434976 [ 0 422708 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Control: 779147 6233176 [ 0 779147 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 1201858 86533776 [ 0 1201858 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Control: 1201849 9614792 [ 0 1201849 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_10_inlinks: 10
|
||||
switch_10_outlinks: 10
|
||||
links_utilized_percent_switch_10: 0.759188
|
||||
links_utilized_percent_switch_10_link_0: 0.696839 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_1: 0.695276 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_2: 0.692165 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_3: 0.690646 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_4: 0.68832 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_5: 0.68526 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_6: 0.683393 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_7: 0.676283 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_8: 2.0837 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_9: 2.66634e-06 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10: 0.471145
|
||||
links_utilized_percent_switch_10_link_0: 0.177761 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_1: 0.179543 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_2: 0.176574 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_3: 0.178512 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_4: 0.177488 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_5: 0.172929 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_6: 0.174862 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_7: 0.175796 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_8: 2.64949 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_9: 0.648492 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_10_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Control: 324577 2596616 [ 0 0 324577 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Request_Control: 141029 1128232 [ 141029 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Data: 152090 10950480 [ 0 152090 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_0_Response_Control: 76021 608168 [ 0 76021 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Request_Control: 142261 1138088 [ 142261 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Data: 153623 11060856 [ 0 153623 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_1_Response_Control: 76891 615128 [ 0 76891 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Request_Control: 139745 1117960 [ 139745 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Data: 151126 10881072 [ 0 151126 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_2_Response_Control: 75386 603088 [ 0 75386 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Request_Control: 141577 1132616 [ 141577 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Data: 152754 10998288 [ 0 152754 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_3_Response_Control: 76191 609528 [ 0 76191 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Request_Control: 140569 1124552 [ 140569 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Data: 151893 10936296 [ 0 151893 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_4_Response_Control: 75812 606496 [ 0 75812 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Request_Control: 137030 1096240 [ 137030 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Data: 147989 10655208 [ 0 147989 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_5_Response_Control: 73821 590568 [ 0 73821 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Request_Control: 138259 1106072 [ 138259 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Data: 149657 10775304 [ 0 149657 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_6_Response_Control: 74826 598608 [ 0 74826 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Request_Control: 139138 1113104 [ 139138 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Data: 150412 10829664 [ 0 150412 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_7_Response_Control: 75477 603816 [ 0 75477 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Control: 1209565 9676520 [ 1209565 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Data: 1203036 86618592 [ 0 1203036 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Response_Control: 2797904 22383232 [ 0 1597900 1200004 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Writeback_Data: 934615 67292280 [ 213861 720754 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_8_Writeback_Control: 390556 3124448 [ 390556 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Response_Data: 422708 30434976 [ 0 422708 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_10_link_9_Response_Control: 779147 6233176 [ 0 779147 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
|
|
@ -321,84 +348,84 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
|||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [98631 98244 97407 96638 100000 99918 99521 98787 ] 789146
|
||||
Load [98886 96243 97583 97728 98791 100101 98555 99215 ] 787102
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [52748 52924 52660 51759 54108 53759 53950 53363 ] 425271
|
||||
Inv [30317 30139 30034 29802 30695 30672 30453 30194 ] 242306
|
||||
L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039
|
||||
Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269
|
||||
Store [53456 51755 52117 53064 54558 53626 53073 53642 ] 425291
|
||||
Inv [140213 136671 137939 138777 140688 141916 139401 141215 ] 1116820
|
||||
L1_Replacement [59176647 59366144 59287548 59249710 59221304 59185380 59232447 59146573 ] 473865753
|
||||
Fwd_GETX [199 214 187 201 198 199 203 209 ] 1610
|
||||
Fwd_GETS [157 145 133 160 143 146 141 153 ] 1178
|
||||
Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684
|
||||
Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268
|
||||
Data_all_Acks [24963 25105 25087 24473 25787 25589 25330 25061 ] 201395
|
||||
Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622
|
||||
Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270
|
||||
WB_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
Data [0 1 0 2 0 3 0 1 ] 7
|
||||
Data_Exclusive [97101 94947 96224 96338 97462 98657 97005 97817 ] 775551
|
||||
DataS_fromL1 [145 139 155 134 142 164 149 150 ] 1178
|
||||
Data_all_Acks [54647 52902 53278 53938 54486 54799 53972 54786 ] 432808
|
||||
Ack [0 1 0 2 0 3 0 1 ] 7
|
||||
Ack_all [0 1 0 2 0 3 0 1 ] 7
|
||||
WB_Ack [75812 73819 74826 75473 76021 76885 75386 76189 ] 604411
|
||||
|
||||
- Transitions -
|
||||
NP Load [2 2 1 2 2 2 2 1 ] 14
|
||||
NP Load [98431 96234 97525 97692 98769 99980 98359 99167 ] 786157
|
||||
NP Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Store [0 0 1 0 0 0 0 1 ] 2
|
||||
NP Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
NP Store [53441 51747 52107 52691 53297 53619 52748 53573 ] 423223
|
||||
NP Inv [659 638 628 693 652 649 657 685 ] 5261
|
||||
NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
I Load [20055 19731 19824 19834 20085 20223 19939 19922 ] 159613
|
||||
I Load [15 7 22 16 17 20 15 14 ] 126
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [10642 10737 10713 10485 10952 10852 10710 10852 ] 85943
|
||||
I Store [8 5 6 14 9 6 7 4 ] 59
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
I L1_Replacement [75454 73571 74216 74266 75441 76105 75113 75916 ] 600082
|
||||
|
||||
S Load [33152 33048 32637 32620 33721 34023 33841 33185 ] 266227
|
||||
S Load [0 0 0 0 0 0 0 0 ] 0
|
||||
S Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [17987 18032 17846 17524 18330 18180 18396 18080 ] 144375
|
||||
S Inv [11616 11475 11582 11602 11637 11749 11468 11453 ] 92582
|
||||
S L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
S Store [0 0 0 0 0 0 0 0 ] 0
|
||||
S Inv [841 800 825 835 814 838 852 828 ] 6633
|
||||
S L1_Replacement [602 586 586 639 599 604 604 629 ] 4849
|
||||
|
||||
E Load [0 0 0 0 0 0 0 0 ] 0
|
||||
E Load [0 0 2 0 0 1 0 0 ] 3
|
||||
E Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
E Store [0 0 0 0 0 0 0 0 ] 0
|
||||
E Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
E L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
E Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
E Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
E Store [0 0 0 1 0 0 1 0 ] 2
|
||||
E Inv [48181 47082 47499 47422 48297 48773 48265 48652 ] 384171
|
||||
E L1_Replacement [48812 47751 48633 48809 49061 49789 48649 49067 ] 390571
|
||||
E Fwd_GETX [80 95 72 85 85 77 76 85 ] 655
|
||||
E Fwd_GETS [28 19 19 21 19 18 14 13 ] 151
|
||||
E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M Load [45422 45463 44945 44182 46192 45670 45739 45679 ] 363292
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [24119 24155 24100 23750 24826 24727 24844 24430 ] 194951
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039
|
||||
M Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269
|
||||
M Store [0 0 0 0 0 1 0 0 ] 1
|
||||
M Inv [26338 25564 25813 25909 26233 26398 25893 26331 ] 208479
|
||||
M L1_Replacement [27000 26069 26193 26665 26961 27097 26737 27124 ] 213846
|
||||
M Fwd_GETX [39 42 35 47 40 46 50 38 ] 337
|
||||
M Fwd_GETS [72 74 72 85 71 83 74 84 ] 615
|
||||
M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Inv [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935
|
||||
IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
IS DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268
|
||||
IS Data_all_Acks [6088 6007 6204 6122 6122 6065 5894 5919 ] 48421
|
||||
IS Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IS L1_Replacement [38113203 38318741 38190806 37721962 37990776 37966622 37976621 38191379 ] 304470110
|
||||
IS Data_Exclusive [97101 94947 96224 96338 97462 98657 97005 97817 ] 775551
|
||||
IS DataS_fromL1 [145 139 155 134 142 164 149 150 ] 1178
|
||||
IS Data_all_Acks [1198 1154 1165 1235 1181 1178 1219 1210 ] 9540
|
||||
|
||||
IM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IM Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684
|
||||
IM Data_all_Acks [16771 17009 16818 16254 17460 17346 17338 17043 ] 136039
|
||||
IM L1_Replacement [20911576 20899418 20947114 21377361 21078466 21065137 21104723 20802458 ] 168186253
|
||||
IM Data [0 1 0 2 0 3 0 1 ] 7
|
||||
IM Data_all_Acks [53449 51748 52113 52703 53305 53621 52753 53576 ] 423268
|
||||
IM Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SM Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Inv [16597 16575 16387 16103 16853 16745 16887 16642 ] 132789
|
||||
SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SM Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622
|
||||
SM Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270
|
||||
SM Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
SM L1_Replacement [0 8 0 8 0 26 0 0 ] 42
|
||||
SM Ack [0 1 0 2 0 3 0 1 ] 7
|
||||
SM Ack_all [0 1 0 2 0 3 0 1 ] 7
|
||||
|
||||
IS_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
|
|
@ -407,29 +434,29 @@ IS_I Inv [0 0 0 0 0 0 0 0 ] 0
|
|||
IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
|
||||
IS_I Data_all_Acks [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935
|
||||
IS_I Data_all_Acks [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
M_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Inv [64194 62587 63174 63918 64692 65258 63734 64719 ] 512276
|
||||
M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I Fwd_GETX [80 77 80 69 73 76 77 86 ] 618
|
||||
M_I Fwd_GETS [57 52 42 54 53 45 53 56 ] 412
|
||||
M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I WB_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
M_I WB_Ack [11481 11104 11530 11433 11204 11507 11522 11330 ] 91111
|
||||
|
||||
E_I Load [0 0 0 0 0 0 0 0 ] 0
|
||||
E_I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
E_I Store [0 0 0 0 0 0 0 0 ] 0
|
||||
E_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
SINK_WB_ACK Load [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK Load [440 2 34 20 5 100 181 34 ] 816
|
||||
SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK Store [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK Store [7 3 4 358 1252 0 317 65 ] 2006
|
||||
SINK_WB_ACK Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [0 0 0 0 0 0 0 0 ] 0
|
||||
SINK_WB_ACK WB_Ack [64331 62715 63296 64040 64817 65378 63864 64859 ] 513300
|
||||
|
||||
Cache Stats: system.l1_cntrl1.L1IcacheMemory
|
||||
system.l1_cntrl1.L1IcacheMemory_total_misses: 0
|
||||
|
|
@ -554,69 +581,69 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
|
|||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR [0 ] 0
|
||||
L1_GETS [2029346 ] 2029346
|
||||
L1_GETX [2583035 ] 2583035
|
||||
L1_UPGRADE [318717 ] 318717
|
||||
L1_PUTX [0 ] 0
|
||||
L1_PUTX_old [0 ] 0
|
||||
L1_GETS [848065 ] 848065
|
||||
L1_GETX [519919 ] 519919
|
||||
L1_UPGRADE [0 ] 0
|
||||
L1_PUTX [94198 ] 94198
|
||||
L1_PUTX_old [525501 ] 525501
|
||||
Fwd_L1_GETX [0 ] 0
|
||||
Fwd_L1_GETS [0 ] 0
|
||||
Fwd_L1_GET_INSTR [0 ] 0
|
||||
L2_Replacement [0 ] 0
|
||||
L2_Replacement_clean [0 ] 0
|
||||
Mem_Data [2 ] 2
|
||||
Mem_Ack [0 ] 0
|
||||
WB_Data [94268 ] 94268
|
||||
WB_Data_clean [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_all [0 ] 0
|
||||
Unblock [94268 ] 94268
|
||||
L2_Replacement [34658 ] 34658
|
||||
L2_Replacement_clean [105741810 ] 105741810
|
||||
Mem_Data [1201858 ] 1201858
|
||||
Mem_Ack [1201849 ] 1201849
|
||||
WB_Data [390262 ] 390262
|
||||
WB_Data_clean [331670 ] 331670
|
||||
Ack [5950 ] 5950
|
||||
Ack_all [390101 ] 390101
|
||||
Unblock [1178 ] 1178
|
||||
Unblock_Cancel [0 ] 0
|
||||
Exclusive_Unblock [230308 ] 230308
|
||||
Exclusive_Unblock [1198826 ] 1198826
|
||||
MEM_Inv [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR [0 ] 0
|
||||
NP L1_GETS [2 ] 2
|
||||
NP L1_GETX [0 ] 0
|
||||
NP L1_GETS [780251 ] 780251
|
||||
NP L1_GETX [421614 ] 421614
|
||||
NP L1_PUTX [0 ] 0
|
||||
NP L1_PUTX_old [0 ] 0
|
||||
NP L1_PUTX_old [454090 ] 454090
|
||||
|
||||
SS L1_GET_INSTR [0 ] 0
|
||||
SS L1_GETS [65342 ] 65342
|
||||
SS L1_GETX [82684 ] 82684
|
||||
SS L1_UPGRADE [11586 ] 11586
|
||||
SS L1_GETS [9 ] 9
|
||||
SS L1_GETX [7 ] 7
|
||||
SS L1_UPGRADE [0 ] 0
|
||||
SS L1_PUTX [0 ] 0
|
||||
SS L1_PUTX_old [0 ] 0
|
||||
SS L2_Replacement [0 ] 0
|
||||
SS L2_Replacement_clean [0 ] 0
|
||||
SS L2_Replacement [1026 ] 1026
|
||||
SS L2_Replacement_clean [4905 ] 4905
|
||||
SS MEM_Inv [0 ] 0
|
||||
|
||||
M L1_GET_INSTR [0 ] 0
|
||||
M L1_GETS [0 ] 0
|
||||
M L1_GETX [0 ] 0
|
||||
M L1_GETS [66 ] 66
|
||||
M L1_GETX [45 ] 45
|
||||
M L1_PUTX [0 ] 0
|
||||
M L1_PUTX_old [0 ] 0
|
||||
M L2_Replacement [0 ] 0
|
||||
M L2_Replacement_clean [0 ] 0
|
||||
M L1_PUTX_old [15 ] 15
|
||||
M L2_Replacement [32427 ] 32427
|
||||
M L2_Replacement_clean [58573 ] 58573
|
||||
M MEM_Inv [0 ] 0
|
||||
|
||||
MT L1_GET_INSTR [0 ] 0
|
||||
MT L1_GETS [94269 ] 94269
|
||||
MT L1_GETX [136039 ] 136039
|
||||
MT L1_PUTX [0 ] 0
|
||||
MT L1_PUTX_old [0 ] 0
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L2_Replacement_clean [0 ] 0
|
||||
MT L1_GETS [1178 ] 1178
|
||||
MT L1_GETX [1610 ] 1610
|
||||
MT L1_PUTX [91111 ] 91111
|
||||
MT L1_PUTX_old [386 ] 386
|
||||
MT L2_Replacement [28 ] 28
|
||||
MT L2_Replacement_clean [1104898 ] 1104898
|
||||
MT MEM_Inv [0 ] 0
|
||||
|
||||
M_I L1_GET_INSTR [0 ] 0
|
||||
M_I L1_GETS [0 ] 0
|
||||
M_I L1_GETX [0 ] 0
|
||||
M_I L1_GETS [6331 ] 6331
|
||||
M_I L1_GETX [3188 ] 3188
|
||||
M_I L1_UPGRADE [0 ] 0
|
||||
M_I L1_PUTX [0 ] 0
|
||||
M_I L1_PUTX_old [0 ] 0
|
||||
M_I Mem_Ack [0 ] 0
|
||||
M_I L1_PUTX_old [56154 ] 56154
|
||||
M_I Mem_Ack [1201849 ] 1201849
|
||||
M_I MEM_Inv [0 ] 0
|
||||
|
||||
MT_I L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -625,29 +652,29 @@ MT_I L1_GETX [0 ] 0
|
|||
MT_I L1_UPGRADE [0 ] 0
|
||||
MT_I L1_PUTX [0 ] 0
|
||||
MT_I L1_PUTX_old [0 ] 0
|
||||
MT_I WB_Data [0 ] 0
|
||||
MT_I WB_Data [8 ] 8
|
||||
MT_I WB_Data_clean [0 ] 0
|
||||
MT_I Ack_all [0 ] 0
|
||||
MT_I Ack_all [20 ] 20
|
||||
MT_I MEM_Inv [0 ] 0
|
||||
|
||||
MCT_I L1_GET_INSTR [0 ] 0
|
||||
MCT_I L1_GETS [0 ] 0
|
||||
MCT_I L1_GETX [0 ] 0
|
||||
MCT_I L1_GETS [266 ] 266
|
||||
MCT_I L1_GETX [392 ] 392
|
||||
MCT_I L1_UPGRADE [0 ] 0
|
||||
MCT_I L1_PUTX [0 ] 0
|
||||
MCT_I L1_PUTX_old [0 ] 0
|
||||
MCT_I WB_Data [0 ] 0
|
||||
MCT_I WB_Data_clean [0 ] 0
|
||||
MCT_I Ack_all [0 ] 0
|
||||
MCT_I L1_PUTX_old [12610 ] 12610
|
||||
MCT_I WB_Data [389227 ] 389227
|
||||
MCT_I WB_Data_clean [331519 ] 331519
|
||||
MCT_I Ack_all [384151 ] 384151
|
||||
|
||||
I_I L1_GET_INSTR [0 ] 0
|
||||
I_I L1_GETS [0 ] 0
|
||||
I_I L1_GETX [0 ] 0
|
||||
I_I L1_GETX [2 ] 2
|
||||
I_I L1_UPGRADE [0 ] 0
|
||||
I_I L1_PUTX [0 ] 0
|
||||
I_I L1_PUTX_old [0 ] 0
|
||||
I_I Ack [0 ] 0
|
||||
I_I Ack_all [0 ] 0
|
||||
I_I Ack [4915 ] 4915
|
||||
I_I Ack_all [4904 ] 4904
|
||||
|
||||
S_I L1_GET_INSTR [0 ] 0
|
||||
S_I L1_GETS [0 ] 0
|
||||
|
|
@ -655,62 +682,62 @@ S_I L1_GETX [0 ] 0
|
|||
S_I L1_UPGRADE [0 ] 0
|
||||
S_I L1_PUTX [0 ] 0
|
||||
S_I L1_PUTX_old [0 ] 0
|
||||
S_I Ack [0 ] 0
|
||||
S_I Ack_all [0 ] 0
|
||||
S_I Ack [1035 ] 1035
|
||||
S_I Ack_all [1026 ] 1026
|
||||
S_I MEM_Inv [0 ] 0
|
||||
|
||||
ISS L1_GET_INSTR [0 ] 0
|
||||
ISS L1_GETS [2 ] 2
|
||||
ISS L1_GETX [1 ] 1
|
||||
ISS L1_GETS [4760 ] 4760
|
||||
ISS L1_GETX [57052 ] 57052
|
||||
ISS L1_PUTX [0 ] 0
|
||||
ISS L1_PUTX_old [0 ] 0
|
||||
ISS L1_PUTX_old [869 ] 869
|
||||
ISS L2_Replacement [0 ] 0
|
||||
ISS L2_Replacement_clean [0 ] 0
|
||||
ISS Mem_Data [0 ] 0
|
||||
ISS L2_Replacement_clean [63408696 ] 63408696
|
||||
ISS Mem_Data [775485 ] 775485
|
||||
ISS MEM_Inv [0 ] 0
|
||||
|
||||
IS L1_GET_INSTR [0 ] 0
|
||||
IS L1_GETS [10 ] 10
|
||||
IS L1_GETX [60 ] 60
|
||||
IS L1_GETS [11 ] 11
|
||||
IS L1_GETX [353 ] 353
|
||||
IS L1_PUTX [0 ] 0
|
||||
IS L1_PUTX_old [0 ] 0
|
||||
IS L1_PUTX_old [3 ] 3
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L2_Replacement_clean [0 ] 0
|
||||
IS Mem_Data [2 ] 2
|
||||
IS L2_Replacement_clean [465689 ] 465689
|
||||
IS Mem_Data [4760 ] 4760
|
||||
IS MEM_Inv [0 ] 0
|
||||
|
||||
IM L1_GET_INSTR [0 ] 0
|
||||
IM L1_GETS [0 ] 0
|
||||
IM L1_GETX [0 ] 0
|
||||
IM L1_GETS [52721 ] 52721
|
||||
IM L1_GETX [31631 ] 31631
|
||||
IM L1_PUTX [0 ] 0
|
||||
IM L1_PUTX_old [0 ] 0
|
||||
IM L1_PUTX_old [1371 ] 1371
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L2_Replacement_clean [0 ] 0
|
||||
IM Mem_Data [0 ] 0
|
||||
IM L2_Replacement_clean [34417195 ] 34417195
|
||||
IM Mem_Data [421613 ] 421613
|
||||
IM MEM_Inv [0 ] 0
|
||||
|
||||
SS_MB L1_GET_INSTR [0 ] 0
|
||||
SS_MB L1_GETS [471755 ] 471755
|
||||
SS_MB L1_GETX [572825 ] 572825
|
||||
SS_MB L1_UPGRADE [265946 ] 265946
|
||||
SS_MB L1_GETS [0 ] 0
|
||||
SS_MB L1_GETX [0 ] 0
|
||||
SS_MB L1_UPGRADE [0 ] 0
|
||||
SS_MB L1_PUTX [0 ] 0
|
||||
SS_MB L1_PUTX_old [0 ] 0
|
||||
SS_MB L2_Replacement [0 ] 0
|
||||
SS_MB L2_Replacement_clean [0 ] 0
|
||||
SS_MB L2_Replacement_clean [23 ] 23
|
||||
SS_MB Unblock_Cancel [0 ] 0
|
||||
SS_MB Exclusive_Unblock [94269 ] 94269
|
||||
SS_MB Exclusive_Unblock [7 ] 7
|
||||
SS_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_MB L1_GET_INSTR [0 ] 0
|
||||
MT_MB L1_GETS [858796 ] 858796
|
||||
MT_MB L1_GETX [1078050 ] 1078050
|
||||
MT_MB L1_GETS [2451 ] 2451
|
||||
MT_MB L1_GETX [4019 ] 4019
|
||||
MT_MB L1_UPGRADE [0 ] 0
|
||||
MT_MB L1_PUTX [0 ] 0
|
||||
MT_MB L1_PUTX_old [0 ] 0
|
||||
MT_MB L1_PUTX [1851 ] 1851
|
||||
MT_MB L1_PUTX_old [3 ] 3
|
||||
MT_MB L2_Replacement [0 ] 0
|
||||
MT_MB L2_Replacement_clean [0 ] 0
|
||||
MT_MB L2_Replacement_clean [6280543 ] 6280543
|
||||
MT_MB Unblock_Cancel [0 ] 0
|
||||
MT_MB Exclusive_Unblock [136039 ] 136039
|
||||
MT_MB Exclusive_Unblock [1198819 ] 1198819
|
||||
MT_MB MEM_Inv [0 ] 0
|
||||
|
||||
M_MB L1_GET_INSTR [0 ] 0
|
||||
|
|
@ -725,15 +752,15 @@ M_MB Exclusive_Unblock [0 ] 0
|
|||
M_MB MEM_Inv [0 ] 0
|
||||
|
||||
MT_IIB L1_GET_INSTR [0 ] 0
|
||||
MT_IIB L1_GETS [384618 ] 384618
|
||||
MT_IIB L1_GETX [506028 ] 506028
|
||||
MT_IIB L1_GETS [14 ] 14
|
||||
MT_IIB L1_GETX [4 ] 4
|
||||
MT_IIB L1_UPGRADE [0 ] 0
|
||||
MT_IIB L1_PUTX [0 ] 0
|
||||
MT_IIB L1_PUTX [824 ] 824
|
||||
MT_IIB L1_PUTX_old [0 ] 0
|
||||
MT_IIB L2_Replacement [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [0 ] 0
|
||||
MT_IIB WB_Data [94268 ] 94268
|
||||
MT_IIB WB_Data_clean [0 ] 0
|
||||
MT_IIB L2_Replacement_clean [1252 ] 1252
|
||||
MT_IIB WB_Data [1027 ] 1027
|
||||
MT_IIB WB_Data_clean [151 ] 151
|
||||
MT_IIB Unblock [0 ] 0
|
||||
MT_IIB MEM_Inv [0 ] 0
|
||||
|
||||
|
|
@ -751,48 +778,48 @@ MT_IB Unblock_Cancel [0 ] 0
|
|||
MT_IB MEM_Inv [0 ] 0
|
||||
|
||||
MT_SB L1_GET_INSTR [0 ] 0
|
||||
MT_SB L1_GETS [154552 ] 154552
|
||||
MT_SB L1_GETX [207348 ] 207348
|
||||
MT_SB L1_UPGRADE [41185 ] 41185
|
||||
MT_SB L1_PUTX [0 ] 0
|
||||
MT_SB L1_GETS [7 ] 7
|
||||
MT_SB L1_GETX [2 ] 2
|
||||
MT_SB L1_UPGRADE [0 ] 0
|
||||
MT_SB L1_PUTX [412 ] 412
|
||||
MT_SB L1_PUTX_old [0 ] 0
|
||||
MT_SB L2_Replacement [0 ] 0
|
||||
MT_SB L2_Replacement_clean [0 ] 0
|
||||
MT_SB Unblock [94268 ] 94268
|
||||
MT_SB L2_Replacement [1177 ] 1177
|
||||
MT_SB L2_Replacement_clean [36 ] 36
|
||||
MT_SB Unblock [1178 ] 1178
|
||||
MT_SB MEM_Inv [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 2
|
||||
memory_reads: 2
|
||||
memory_writes: 0
|
||||
memory_refreshes: 22
|
||||
memory_total_request_delays: 31
|
||||
memory_delays_per_request: 15.5
|
||||
memory_delays_in_input_queue: 1
|
||||
memory_delays_behind_head_of_bank_queue: 10
|
||||
memory_delays_stalled_at_head_of_bank_queue: 20
|
||||
memory_stalls_for_bank_busy: 20
|
||||
memory_total_requests: 1624572
|
||||
memory_reads: 1201859
|
||||
memory_writes: 422705
|
||||
memory_refreshes: 92931
|
||||
memory_total_request_delays: 21562515
|
||||
memory_delays_per_request: 13.2727
|
||||
memory_delays_in_input_queue: 799404
|
||||
memory_delays_behind_head_of_bank_queue: 2824712
|
||||
memory_delays_stalled_at_head_of_bank_queue: 17938399
|
||||
memory_stalls_for_bank_busy: 3122651
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 0
|
||||
memory_stalls_for_bus: 0
|
||||
memory_stalls_for_anti_starvation: 1448376
|
||||
memory_stalls_for_arbitration: 3657027
|
||||
memory_stalls_for_bus: 5644479
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 0
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
|
||||
memory_stalls_for_read_write_turnaround: 2899436
|
||||
memory_stalls_for_read_read_turnaround: 1166430
|
||||
accesses_per_bank: 51109 50797 50614 50783 50782 51123 51111 50505 50976 50836 51125 50801 50737 50827 50674 50360 50870 50536 51039 50708 50638 50708 50669 50566 50891 50471 50548 50407 50890 50755 51098 50618
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
Fetch [2 ] 2
|
||||
Data [0 ] 0
|
||||
Memory_Data [2 ] 2
|
||||
Memory_Ack [0 ] 0
|
||||
Fetch [1201864 ] 1201864
|
||||
Data [422708 ] 422708
|
||||
Memory_Data [1201858 ] 1201858
|
||||
Memory_Ack [422702 ] 422702
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
CleanReplacement [0 ] 0
|
||||
CleanReplacement [779147 ] 779147
|
||||
|
||||
- Transitions -
|
||||
I Fetch [2 ] 2
|
||||
I Fetch [1201864 ] 1201864
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -808,20 +835,20 @@ ID_W Memory_Ack [0 ] 0
|
|||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
|
||||
M Data [0 ] 0
|
||||
M Data [422708 ] 422708
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
M CleanReplacement [0 ] 0
|
||||
M CleanReplacement [779147 ] 779147
|
||||
|
||||
IM Fetch [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Memory_Data [2 ] 2
|
||||
IM Memory_Data [1201858 ] 1201858
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
|
||||
MI Fetch [0 ] 0
|
||||
MI Data [0 ] 0
|
||||
MI Memory_Ack [0 ] 0
|
||||
MI Memory_Ack [422702 ] 422702
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu0: completed 10000 read accesses @371396
|
||||
system.cpu2: completed 10000 read accesses @374647
|
||||
system.cpu7: completed 10000 read accesses @377314
|
||||
system.cpu1: completed 10000 read accesses @379478
|
||||
system.cpu3: completed 10000 read accesses @380787
|
||||
system.cpu5: completed 10000 read accesses @386046
|
||||
system.cpu4: completed 10000 read accesses @386470
|
||||
system.cpu6: completed 10000 read accesses @394077
|
||||
system.cpu0: completed 20000 read accesses @748308
|
||||
system.cpu2: completed 20000 read accesses @750148
|
||||
system.cpu1: completed 20000 read accesses @752701
|
||||
system.cpu3: completed 20000 read accesses @761044
|
||||
system.cpu5: completed 20000 read accesses @762156
|
||||
system.cpu4: completed 20000 read accesses @766351
|
||||
system.cpu6: completed 20000 read accesses @775961
|
||||
system.cpu7: completed 20000 read accesses @776472
|
||||
system.cpu2: completed 30000 read accesses @1125160
|
||||
system.cpu1: completed 30000 read accesses @1125369
|
||||
system.cpu0: completed 30000 read accesses @1130636
|
||||
system.cpu3: completed 30000 read accesses @1139985
|
||||
system.cpu5: completed 30000 read accesses @1141453
|
||||
system.cpu4: completed 30000 read accesses @1142264
|
||||
system.cpu6: completed 30000 read accesses @1154957
|
||||
system.cpu7: completed 30000 read accesses @1163543
|
||||
system.cpu2: completed 40000 read accesses @1501376
|
||||
system.cpu1: completed 40000 read accesses @1506717
|
||||
system.cpu0: completed 40000 read accesses @1507617
|
||||
system.cpu3: completed 40000 read accesses @1521033
|
||||
system.cpu4: completed 40000 read accesses @1523666
|
||||
system.cpu5: completed 40000 read accesses @1527373
|
||||
system.cpu6: completed 40000 read accesses @1547890
|
||||
system.cpu7: completed 40000 read accesses @1551332
|
||||
system.cpu2: completed 50000 read accesses @1879261
|
||||
system.cpu0: completed 50000 read accesses @1879360
|
||||
system.cpu1: completed 50000 read accesses @1885794
|
||||
system.cpu3: completed 50000 read accesses @1900931
|
||||
system.cpu4: completed 50000 read accesses @1902181
|
||||
system.cpu5: completed 50000 read accesses @1910820
|
||||
system.cpu6: completed 50000 read accesses @1931247
|
||||
system.cpu7: completed 50000 read accesses @1940656
|
||||
system.cpu0: completed 60000 read accesses @2246405
|
||||
system.cpu1: completed 60000 read accesses @2255112
|
||||
system.cpu2: completed 60000 read accesses @2258276
|
||||
system.cpu3: completed 60000 read accesses @2284120
|
||||
system.cpu4: completed 60000 read accesses @2284604
|
||||
system.cpu5: completed 60000 read accesses @2293116
|
||||
system.cpu6: completed 60000 read accesses @2311203
|
||||
system.cpu7: completed 60000 read accesses @2336896
|
||||
system.cpu0: completed 70000 read accesses @2626542
|
||||
system.cpu1: completed 70000 read accesses @2633209
|
||||
system.cpu2: completed 70000 read accesses @2638509
|
||||
system.cpu4: completed 70000 read accesses @2659805
|
||||
system.cpu3: completed 70000 read accesses @2663605
|
||||
system.cpu5: completed 70000 read accesses @2671213
|
||||
system.cpu6: completed 70000 read accesses @2693680
|
||||
system.cpu7: completed 70000 read accesses @2725734
|
||||
system.cpu0: completed 80000 read accesses @2999116
|
||||
system.cpu1: completed 80000 read accesses @3008858
|
||||
system.cpu2: completed 80000 read accesses @3014566
|
||||
system.cpu3: completed 80000 read accesses @3028069
|
||||
system.cpu4: completed 80000 read accesses @3040014
|
||||
system.cpu5: completed 80000 read accesses @3055346
|
||||
system.cpu6: completed 80000 read accesses @3080851
|
||||
system.cpu7: completed 80000 read accesses @3115153
|
||||
system.cpu0: completed 90000 read accesses @3374370
|
||||
system.cpu1: completed 90000 read accesses @3384044
|
||||
system.cpu2: completed 90000 read accesses @3385035
|
||||
system.cpu3: completed 90000 read accesses @3412877
|
||||
system.cpu4: completed 90000 read accesses @3422171
|
||||
system.cpu5: completed 90000 read accesses @3435207
|
||||
system.cpu6: completed 90000 read accesses @3466955
|
||||
system.cpu7: completed 90000 read accesses @3499833
|
||||
system.cpu0: completed 100000 read accesses @3750455
|
||||
system.cpu1: completed 10000 read accesses @4267815
|
||||
system.cpu0: completed 10000 read accesses @4386665
|
||||
system.cpu7: completed 10000 read accesses @4430875
|
||||
system.cpu5: completed 10000 read accesses @4607545
|
||||
system.cpu2: completed 10000 read accesses @4619185
|
||||
system.cpu6: completed 10000 read accesses @4647575
|
||||
system.cpu4: completed 10000 read accesses @4703325
|
||||
system.cpu3: completed 10000 read accesses @4708885
|
||||
system.cpu7: completed 20000 read accesses @8917485
|
||||
system.cpu1: completed 20000 read accesses @8927935
|
||||
system.cpu0: completed 20000 read accesses @8978605
|
||||
system.cpu2: completed 20000 read accesses @9011105
|
||||
system.cpu6: completed 20000 read accesses @9036385
|
||||
system.cpu3: completed 20000 read accesses @9124815
|
||||
system.cpu4: completed 20000 read accesses @9252305
|
||||
system.cpu5: completed 20000 read accesses @9314285
|
||||
system.cpu2: completed 30000 read accesses @13433315
|
||||
system.cpu6: completed 30000 read accesses @13458245
|
||||
system.cpu3: completed 30000 read accesses @13464345
|
||||
system.cpu7: completed 30000 read accesses @13518155
|
||||
system.cpu1: completed 30000 read accesses @13598825
|
||||
system.cpu0: completed 30000 read accesses @13662375
|
||||
system.cpu4: completed 30000 read accesses @13823135
|
||||
system.cpu5: completed 30000 read accesses @14030995
|
||||
system.cpu1: completed 40000 read accesses @17924245
|
||||
system.cpu3: completed 40000 read accesses @17944405
|
||||
system.cpu2: completed 40000 read accesses @17991615
|
||||
system.cpu7: completed 40000 read accesses @18065995
|
||||
system.cpu6: completed 40000 read accesses @18146535
|
||||
system.cpu4: completed 40000 read accesses @18360575
|
||||
system.cpu0: completed 40000 read accesses @18363865
|
||||
system.cpu5: completed 40000 read accesses @18573915
|
||||
system.cpu6: completed 50000 read accesses @22483915
|
||||
system.cpu1: completed 50000 read accesses @22585525
|
||||
system.cpu2: completed 50000 read accesses @22658905
|
||||
system.cpu3: completed 50000 read accesses @22664345
|
||||
system.cpu7: completed 50000 read accesses @22693455
|
||||
system.cpu0: completed 50000 read accesses @22708375
|
||||
system.cpu4: completed 50000 read accesses @22882115
|
||||
system.cpu5: completed 50000 read accesses @23249715
|
||||
system.cpu1: completed 60000 read accesses @27015465
|
||||
system.cpu3: completed 60000 read accesses @27113125
|
||||
system.cpu6: completed 60000 read accesses @27149645
|
||||
system.cpu0: completed 60000 read accesses @27234945
|
||||
system.cpu4: completed 60000 read accesses @27270805
|
||||
system.cpu7: completed 60000 read accesses @27282045
|
||||
system.cpu2: completed 60000 read accesses @27287805
|
||||
system.cpu5: completed 60000 read accesses @27813435
|
||||
system.cpu1: completed 70000 read accesses @31507655
|
||||
system.cpu3: completed 70000 read accesses @31524465
|
||||
system.cpu4: completed 70000 read accesses @31736945
|
||||
system.cpu6: completed 70000 read accesses @31758665
|
||||
system.cpu2: completed 70000 read accesses @31768595
|
||||
system.cpu7: completed 70000 read accesses @31845335
|
||||
system.cpu0: completed 70000 read accesses @31923925
|
||||
system.cpu5: completed 70000 read accesses @32335665
|
||||
system.cpu1: completed 80000 read accesses @35877115
|
||||
system.cpu3: completed 80000 read accesses @35924075
|
||||
system.cpu2: completed 80000 read accesses @36219765
|
||||
system.cpu4: completed 80000 read accesses @36272265
|
||||
system.cpu0: completed 80000 read accesses @36290615
|
||||
system.cpu7: completed 80000 read accesses @36433305
|
||||
system.cpu6: completed 80000 read accesses @36513795
|
||||
system.cpu5: completed 80000 read accesses @37012615
|
||||
system.cpu1: completed 90000 read accesses @40229765
|
||||
system.cpu3: completed 90000 read accesses @40530675
|
||||
system.cpu0: completed 90000 read accesses @40687495
|
||||
system.cpu4: completed 90000 read accesses @40754715
|
||||
system.cpu2: completed 90000 read accesses @40778275
|
||||
system.cpu6: completed 90000 read accesses @41067465
|
||||
system.cpu7: completed 90000 read accesses @41097375
|
||||
system.cpu5: completed 90000 read accesses @41743025
|
||||
system.cpu1: completed 100000 read accesses @44606455
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 13 2011 22:36:25
|
||||
M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
|
||||
M5 started Jan 13 2011 22:36:28
|
||||
M5 executing on scamorza.cs.wisc.edu
|
||||
M5 compiled Feb 8 2011 17:31:51
|
||||
M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:31:55
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3750455 because maximum number of loads reached
|
||||
Exiting @ tick 44606455 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 290548 # Number of bytes of host memory used
|
||||
host_seconds 82.41 # Real time elapsed on the host
|
||||
host_tick_rate 45509 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346312 # Number of bytes of host memory used
|
||||
host_seconds 508.61 # Real time elapsed on the host
|
||||
host_tick_rate 87702 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003750 # Number of seconds simulated
|
||||
sim_ticks 3750455 # Number of ticks simulated
|
||||
sim_seconds 0.044606 # Number of seconds simulated
|
||||
sim_ticks 44606455 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 54108 # number of write accesses completed
|
||||
system.cpu0.num_reads 98785 # number of read accesses completed
|
||||
system.cpu0.num_writes 53305 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99918 # number of read accesses completed
|
||||
system.cpu1.num_writes 53757 # number of write accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53625 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99521 # number of read accesses completed
|
||||
system.cpu2.num_writes 53948 # number of write accesses completed
|
||||
system.cpu2.num_reads 98373 # number of read accesses completed
|
||||
system.cpu2.num_writes 52754 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98786 # number of read accesses completed
|
||||
system.cpu3.num_writes 53362 # number of write accesses completed
|
||||
system.cpu3.num_reads 99177 # number of read accesses completed
|
||||
system.cpu3.num_writes 53577 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98631 # number of read accesses completed
|
||||
system.cpu4.num_writes 52746 # number of write accesses completed
|
||||
system.cpu4.num_reads 98444 # number of read accesses completed
|
||||
system.cpu4.num_writes 53449 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98242 # number of read accesses completed
|
||||
system.cpu5.num_writes 52924 # number of write accesses completed
|
||||
system.cpu5.num_reads 96240 # number of read accesses completed
|
||||
system.cpu5.num_writes 51749 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 97407 # number of read accesses completed
|
||||
system.cpu6.num_writes 52658 # number of write accesses completed
|
||||
system.cpu6.num_reads 97546 # number of read accesses completed
|
||||
system.cpu6.num_writes 52113 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 96638 # number of read accesses completed
|
||||
system.cpu7.num_writes 51757 # number of write accesses completed
|
||||
system.cpu7.num_reads 97707 # number of read accesses completed
|
||||
system.cpu7.num_writes 52706 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
|
|
@ -460,10 +469,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
|
|||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -475,8 +483,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -487,8 +496,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -499,8 +509,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -511,8 +522,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -523,8 +535,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -535,8 +548,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -547,8 +561,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -559,8 +574,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -569,14 +585,6 @@ version=7
|
|||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu3: completed 10000 read accesses @323743
|
||||
system.cpu2: completed 10000 read accesses @336402
|
||||
system.cpu1: completed 10000 read accesses @338132
|
||||
system.cpu0: completed 10000 read accesses @340751
|
||||
system.cpu5: completed 10000 read accesses @341263
|
||||
system.cpu4: completed 10000 read accesses @346558
|
||||
system.cpu7: completed 10000 read accesses @346738
|
||||
system.cpu6: completed 10000 read accesses @348135
|
||||
system.cpu3: completed 20000 read accesses @670303
|
||||
system.cpu0: completed 20000 read accesses @670934
|
||||
system.cpu2: completed 20000 read accesses @675651
|
||||
system.cpu1: completed 20000 read accesses @679374
|
||||
system.cpu6: completed 20000 read accesses @683883
|
||||
system.cpu7: completed 20000 read accesses @684999
|
||||
system.cpu4: completed 20000 read accesses @688475
|
||||
system.cpu5: completed 20000 read accesses @691089
|
||||
system.cpu3: completed 30000 read accesses @1012754
|
||||
system.cpu2: completed 30000 read accesses @1013014
|
||||
system.cpu5: completed 30000 read accesses @1015303
|
||||
system.cpu0: completed 30000 read accesses @1018359
|
||||
system.cpu1: completed 30000 read accesses @1021563
|
||||
system.cpu4: completed 30000 read accesses @1024489
|
||||
system.cpu6: completed 30000 read accesses @1024945
|
||||
system.cpu7: completed 30000 read accesses @1026805
|
||||
system.cpu3: completed 40000 read accesses @1337640
|
||||
system.cpu4: completed 40000 read accesses @1353749
|
||||
system.cpu5: completed 40000 read accesses @1355921
|
||||
system.cpu2: completed 40000 read accesses @1358297
|
||||
system.cpu0: completed 40000 read accesses @1365879
|
||||
system.cpu7: completed 40000 read accesses @1368402
|
||||
system.cpu6: completed 40000 read accesses @1369510
|
||||
system.cpu1: completed 40000 read accesses @1372174
|
||||
system.cpu3: completed 50000 read accesses @1687319
|
||||
system.cpu4: completed 50000 read accesses @1694511
|
||||
system.cpu7: completed 50000 read accesses @1696243
|
||||
system.cpu2: completed 50000 read accesses @1699794
|
||||
system.cpu5: completed 50000 read accesses @1700188
|
||||
system.cpu6: completed 50000 read accesses @1703368
|
||||
system.cpu0: completed 50000 read accesses @1704599
|
||||
system.cpu1: completed 50000 read accesses @1716501
|
||||
system.cpu4: completed 60000 read accesses @2030412
|
||||
system.cpu3: completed 60000 read accesses @2034929
|
||||
system.cpu2: completed 60000 read accesses @2036378
|
||||
system.cpu7: completed 60000 read accesses @2036726
|
||||
system.cpu0: completed 60000 read accesses @2038738
|
||||
system.cpu5: completed 60000 read accesses @2046852
|
||||
system.cpu1: completed 60000 read accesses @2050784
|
||||
system.cpu6: completed 60000 read accesses @2058109
|
||||
system.cpu3: completed 70000 read accesses @2359493
|
||||
system.cpu4: completed 70000 read accesses @2365063
|
||||
system.cpu2: completed 70000 read accesses @2371739
|
||||
system.cpu0: completed 70000 read accesses @2373666
|
||||
system.cpu7: completed 70000 read accesses @2373767
|
||||
system.cpu5: completed 70000 read accesses @2395804
|
||||
system.cpu1: completed 70000 read accesses @2404686
|
||||
system.cpu6: completed 70000 read accesses @2406335
|
||||
system.cpu2: completed 80000 read accesses @2701352
|
||||
system.cpu7: completed 80000 read accesses @2705729
|
||||
system.cpu3: completed 80000 read accesses @2707362
|
||||
system.cpu4: completed 80000 read accesses @2711169
|
||||
system.cpu0: completed 80000 read accesses @2718197
|
||||
system.cpu1: completed 80000 read accesses @2736476
|
||||
system.cpu6: completed 80000 read accesses @2746379
|
||||
system.cpu5: completed 80000 read accesses @2751740
|
||||
system.cpu2: completed 90000 read accesses @3041770
|
||||
system.cpu3: completed 90000 read accesses @3048359
|
||||
system.cpu7: completed 90000 read accesses @3049406
|
||||
system.cpu0: completed 90000 read accesses @3052026
|
||||
system.cpu4: completed 90000 read accesses @3061142
|
||||
system.cpu1: completed 90000 read accesses @3064341
|
||||
system.cpu6: completed 90000 read accesses @3079121
|
||||
system.cpu5: completed 90000 read accesses @3089679
|
||||
system.cpu2: completed 100000 read accesses @3377485
|
||||
system.cpu7: completed 10000 read accesses @3869056
|
||||
system.cpu6: completed 10000 read accesses @3886426
|
||||
system.cpu4: completed 10000 read accesses @3898396
|
||||
system.cpu5: completed 10000 read accesses @3918286
|
||||
system.cpu0: completed 10000 read accesses @3919696
|
||||
system.cpu1: completed 10000 read accesses @3927286
|
||||
system.cpu2: completed 10000 read accesses @3929616
|
||||
system.cpu3: completed 10000 read accesses @3936396
|
||||
system.cpu5: completed 20000 read accesses @7713766
|
||||
system.cpu7: completed 20000 read accesses @7774726
|
||||
system.cpu4: completed 20000 read accesses @7795816
|
||||
system.cpu6: completed 20000 read accesses @7798926
|
||||
system.cpu1: completed 20000 read accesses @7805792
|
||||
system.cpu0: completed 20000 read accesses @7819976
|
||||
system.cpu2: completed 20000 read accesses @7850656
|
||||
system.cpu3: completed 20000 read accesses @7872096
|
||||
system.cpu5: completed 30000 read accesses @11623576
|
||||
system.cpu6: completed 30000 read accesses @11668436
|
||||
system.cpu0: completed 30000 read accesses @11699446
|
||||
system.cpu7: completed 30000 read accesses @11704516
|
||||
system.cpu4: completed 30000 read accesses @11718806
|
||||
system.cpu1: completed 30000 read accesses @11741606
|
||||
system.cpu3: completed 30000 read accesses @11767816
|
||||
system.cpu2: completed 30000 read accesses @11813276
|
||||
system.cpu5: completed 40000 read accesses @15522846
|
||||
system.cpu0: completed 40000 read accesses @15592626
|
||||
system.cpu6: completed 40000 read accesses @15619436
|
||||
system.cpu1: completed 40000 read accesses @15624516
|
||||
system.cpu4: completed 40000 read accesses @15630786
|
||||
system.cpu7: completed 40000 read accesses @15640616
|
||||
system.cpu3: completed 40000 read accesses @15655796
|
||||
system.cpu2: completed 40000 read accesses @15680896
|
||||
system.cpu5: completed 50000 read accesses @19438476
|
||||
system.cpu0: completed 50000 read accesses @19458866
|
||||
system.cpu1: completed 50000 read accesses @19542456
|
||||
system.cpu6: completed 50000 read accesses @19543746
|
||||
system.cpu4: completed 50000 read accesses @19568206
|
||||
system.cpu7: completed 50000 read accesses @19569526
|
||||
system.cpu3: completed 50000 read accesses @19594416
|
||||
system.cpu2: completed 50000 read accesses @19626796
|
||||
system.cpu5: completed 60000 read accesses @23331176
|
||||
system.cpu0: completed 60000 read accesses @23345146
|
||||
system.cpu6: completed 60000 read accesses @23379766
|
||||
system.cpu1: completed 60000 read accesses @23400806
|
||||
system.cpu4: completed 60000 read accesses @23475225
|
||||
system.cpu3: completed 60000 read accesses @23504027
|
||||
system.cpu7: completed 60000 read accesses @23511286
|
||||
system.cpu2: completed 60000 read accesses @23548006
|
||||
system.cpu5: completed 70000 read accesses @27140516
|
||||
system.cpu0: completed 70000 read accesses @27275896
|
||||
system.cpu1: completed 70000 read accesses @27288996
|
||||
system.cpu6: completed 70000 read accesses @27292846
|
||||
system.cpu7: completed 70000 read accesses @27386426
|
||||
system.cpu3: completed 70000 read accesses @27389056
|
||||
system.cpu4: completed 70000 read accesses @27433216
|
||||
system.cpu2: completed 70000 read accesses @27451236
|
||||
system.cpu5: completed 80000 read accesses @31034206
|
||||
system.cpu6: completed 80000 read accesses @31104766
|
||||
system.cpu1: completed 80000 read accesses @31179446
|
||||
system.cpu0: completed 80000 read accesses @31203676
|
||||
system.cpu3: completed 80000 read accesses @31246486
|
||||
system.cpu7: completed 80000 read accesses @31258446
|
||||
system.cpu2: completed 80000 read accesses @31320306
|
||||
system.cpu4: completed 80000 read accesses @31334426
|
||||
system.cpu5: completed 90000 read accesses @34995346
|
||||
system.cpu6: completed 90000 read accesses @35062566
|
||||
system.cpu3: completed 90000 read accesses @35112636
|
||||
system.cpu1: completed 90000 read accesses @35134786
|
||||
system.cpu7: completed 90000 read accesses @35159686
|
||||
system.cpu2: completed 90000 read accesses @35168476
|
||||
system.cpu0: completed 90000 read accesses @35169596
|
||||
system.cpu4: completed 90000 read accesses @35260086
|
||||
system.cpu6: completed 100000 read accesses @38939096
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 20 2010 12:10:28
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:10:38
|
||||
M5 executing on SC2B0629
|
||||
M5 compiled Feb 8 2011 17:41:34
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:41:42
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3377485 because maximum number of loads reached
|
||||
Exiting @ tick 38939096 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 341856 # Number of bytes of host memory used
|
||||
host_seconds 29.56 # Real time elapsed on the host
|
||||
host_tick_rate 114257 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346560 # Number of bytes of host memory used
|
||||
host_seconds 500.03 # Real time elapsed on the host
|
||||
host_tick_rate 77873 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003377 # Number of seconds simulated
|
||||
sim_ticks 3377485 # Number of ticks simulated
|
||||
sim_seconds 0.038939 # Number of seconds simulated
|
||||
sim_ticks 38939096 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99116 # number of read accesses completed
|
||||
system.cpu0.num_writes 53019 # number of write accesses completed
|
||||
system.cpu0.num_reads 99650 # number of read accesses completed
|
||||
system.cpu0.num_writes 53465 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99151 # number of read accesses completed
|
||||
system.cpu1.num_writes 53486 # number of write accesses completed
|
||||
system.cpu1.num_reads 99886 # number of read accesses completed
|
||||
system.cpu1.num_writes 53908 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 53183 # number of write accesses completed
|
||||
system.cpu2.num_reads 99727 # number of read accesses completed
|
||||
system.cpu2.num_writes 53685 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99632 # number of read accesses completed
|
||||
system.cpu3.num_writes 54001 # number of write accesses completed
|
||||
system.cpu3.num_reads 99743 # number of read accesses completed
|
||||
system.cpu3.num_writes 53374 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99186 # number of read accesses completed
|
||||
system.cpu4.num_writes 53590 # number of write accesses completed
|
||||
system.cpu4.num_reads 99344 # number of read accesses completed
|
||||
system.cpu4.num_writes 53842 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98345 # number of read accesses completed
|
||||
system.cpu5.num_writes 53268 # number of write accesses completed
|
||||
system.cpu5.num_reads 99988 # number of read accesses completed
|
||||
system.cpu5.num_writes 53434 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99155 # number of read accesses completed
|
||||
system.cpu6.num_writes 53749 # number of write accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 54115 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99644 # number of read accesses completed
|
||||
system.cpu7.num_writes 53528 # number of write accesses completed
|
||||
system.cpu7.num_reads 99701 # number of read accesses completed
|
||||
system.cpu7.num_writes 53854 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
|
|
@ -513,10 +522,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
|
|||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -528,8 +536,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -540,8 +549,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -552,8 +562,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -564,8 +575,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -576,8 +588,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -588,8 +601,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -600,8 +614,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -612,8 +627,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -622,14 +638,6 @@ version=7
|
|||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu0: completed 10000 read accesses @257947
|
||||
system.cpu1: completed 10000 read accesses @260311
|
||||
system.cpu3: completed 10000 read accesses @264703
|
||||
system.cpu7: completed 10000 read accesses @266036
|
||||
system.cpu5: completed 10000 read accesses @266378
|
||||
system.cpu4: completed 10000 read accesses @267169
|
||||
system.cpu2: completed 10000 read accesses @267625
|
||||
system.cpu6: completed 10000 read accesses @271366
|
||||
system.cpu0: completed 20000 read accesses @515410
|
||||
system.cpu1: completed 20000 read accesses @519078
|
||||
system.cpu7: completed 20000 read accesses @528562
|
||||
system.cpu3: completed 20000 read accesses @529556
|
||||
system.cpu5: completed 20000 read accesses @531753
|
||||
system.cpu4: completed 20000 read accesses @536204
|
||||
system.cpu6: completed 20000 read accesses @537031
|
||||
system.cpu2: completed 20000 read accesses @537314
|
||||
system.cpu0: completed 30000 read accesses @772994
|
||||
system.cpu1: completed 30000 read accesses @780923
|
||||
system.cpu3: completed 30000 read accesses @794263
|
||||
system.cpu7: completed 30000 read accesses @796675
|
||||
system.cpu4: completed 30000 read accesses @797063
|
||||
system.cpu5: completed 30000 read accesses @800026
|
||||
system.cpu2: completed 30000 read accesses @802601
|
||||
system.cpu6: completed 30000 read accesses @805267
|
||||
system.cpu0: completed 40000 read accesses @1033304
|
||||
system.cpu1: completed 40000 read accesses @1040457
|
||||
system.cpu3: completed 40000 read accesses @1058903
|
||||
system.cpu7: completed 40000 read accesses @1062178
|
||||
system.cpu5: completed 40000 read accesses @1064117
|
||||
system.cpu4: completed 40000 read accesses @1065423
|
||||
system.cpu6: completed 40000 read accesses @1066744
|
||||
system.cpu2: completed 40000 read accesses @1068649
|
||||
system.cpu0: completed 50000 read accesses @1292512
|
||||
system.cpu1: completed 50000 read accesses @1299935
|
||||
system.cpu3: completed 50000 read accesses @1324981
|
||||
system.cpu5: completed 50000 read accesses @1327818
|
||||
system.cpu7: completed 50000 read accesses @1328780
|
||||
system.cpu4: completed 50000 read accesses @1329164
|
||||
system.cpu6: completed 50000 read accesses @1332786
|
||||
system.cpu2: completed 50000 read accesses @1334645
|
||||
system.cpu0: completed 60000 read accesses @1550153
|
||||
system.cpu1: completed 60000 read accesses @1559435
|
||||
system.cpu7: completed 60000 read accesses @1591474
|
||||
system.cpu3: completed 60000 read accesses @1593078
|
||||
system.cpu4: completed 60000 read accesses @1594642
|
||||
system.cpu5: completed 60000 read accesses @1595392
|
||||
system.cpu2: completed 60000 read accesses @1600002
|
||||
system.cpu6: completed 60000 read accesses @1600595
|
||||
system.cpu0: completed 70000 read accesses @1802423
|
||||
system.cpu1: completed 70000 read accesses @1829858
|
||||
system.cpu7: completed 70000 read accesses @1853648
|
||||
system.cpu5: completed 70000 read accesses @1854214
|
||||
system.cpu3: completed 70000 read accesses @1854818
|
||||
system.cpu4: completed 70000 read accesses @1855726
|
||||
system.cpu6: completed 70000 read accesses @1868528
|
||||
system.cpu2: completed 70000 read accesses @1875446
|
||||
system.cpu0: completed 80000 read accesses @2061056
|
||||
system.cpu1: completed 80000 read accesses @2090957
|
||||
system.cpu7: completed 80000 read accesses @2119055
|
||||
system.cpu4: completed 80000 read accesses @2119432
|
||||
system.cpu5: completed 80000 read accesses @2121677
|
||||
system.cpu3: completed 80000 read accesses @2123217
|
||||
system.cpu6: completed 80000 read accesses @2133942
|
||||
system.cpu2: completed 80000 read accesses @2139530
|
||||
system.cpu0: completed 90000 read accesses @2322313
|
||||
system.cpu1: completed 90000 read accesses @2351193
|
||||
system.cpu4: completed 90000 read accesses @2382901
|
||||
system.cpu7: completed 90000 read accesses @2384445
|
||||
system.cpu5: completed 90000 read accesses @2387842
|
||||
system.cpu3: completed 90000 read accesses @2390630
|
||||
system.cpu6: completed 90000 read accesses @2400244
|
||||
system.cpu2: completed 90000 read accesses @2403389
|
||||
system.cpu0: completed 100000 read accesses @2583072
|
||||
system.cpu5: completed 10000 read accesses @3921160
|
||||
system.cpu1: completed 10000 read accesses @3925580
|
||||
system.cpu0: completed 10000 read accesses @3934400
|
||||
system.cpu2: completed 10000 read accesses @3939680
|
||||
system.cpu3: completed 10000 read accesses @3944050
|
||||
system.cpu6: completed 10000 read accesses @3950830
|
||||
system.cpu7: completed 10000 read accesses @3958280
|
||||
system.cpu4: completed 10000 read accesses @3974010
|
||||
system.cpu0: completed 20000 read accesses @7820430
|
||||
system.cpu5: completed 20000 read accesses @7822630
|
||||
system.cpu1: completed 20000 read accesses @7842540
|
||||
system.cpu2: completed 20000 read accesses @7858630
|
||||
system.cpu3: completed 20000 read accesses @7865210
|
||||
system.cpu4: completed 20000 read accesses @7866290
|
||||
system.cpu6: completed 20000 read accesses @7899300
|
||||
system.cpu7: completed 20000 read accesses @7926330
|
||||
system.cpu0: completed 30000 read accesses @11730870
|
||||
system.cpu1: completed 30000 read accesses @11752380
|
||||
system.cpu5: completed 30000 read accesses @11754100
|
||||
system.cpu4: completed 30000 read accesses @11817260
|
||||
system.cpu3: completed 30000 read accesses @11833290
|
||||
system.cpu2: completed 30000 read accesses @11849820
|
||||
system.cpu6: completed 30000 read accesses @11858520
|
||||
system.cpu7: completed 30000 read accesses @11878780
|
||||
system.cpu1: completed 40000 read accesses @15666470
|
||||
system.cpu0: completed 40000 read accesses @15689570
|
||||
system.cpu5: completed 40000 read accesses @15693470
|
||||
system.cpu3: completed 40000 read accesses @15770740
|
||||
system.cpu2: completed 40000 read accesses @15801030
|
||||
system.cpu4: completed 40000 read accesses @15802680
|
||||
system.cpu6: completed 40000 read accesses @15812300
|
||||
system.cpu7: completed 40000 read accesses @15814020
|
||||
system.cpu0: completed 50000 read accesses @19587160
|
||||
system.cpu1: completed 50000 read accesses @19609890
|
||||
system.cpu5: completed 50000 read accesses @19679290
|
||||
system.cpu3: completed 50000 read accesses @19706240
|
||||
system.cpu6: completed 50000 read accesses @19738150
|
||||
system.cpu2: completed 50000 read accesses @19790350
|
||||
system.cpu4: completed 50000 read accesses @19793110
|
||||
system.cpu7: completed 50000 read accesses @19826670
|
||||
system.cpu0: completed 60000 read accesses @23442420
|
||||
system.cpu1: completed 60000 read accesses @23506570
|
||||
system.cpu5: completed 60000 read accesses @23555050
|
||||
system.cpu3: completed 60000 read accesses @23640540
|
||||
system.cpu6: completed 60000 read accesses @23651620
|
||||
system.cpu4: completed 60000 read accesses @23764590
|
||||
system.cpu2: completed 60000 read accesses @23767160
|
||||
system.cpu7: completed 60000 read accesses @23798150
|
||||
system.cpu0: completed 70000 read accesses @27346650
|
||||
system.cpu1: completed 70000 read accesses @27417040
|
||||
system.cpu5: completed 70000 read accesses @27459850
|
||||
system.cpu3: completed 70000 read accesses @27568910
|
||||
system.cpu7: completed 70000 read accesses @27679260
|
||||
system.cpu4: completed 70000 read accesses @27695210
|
||||
system.cpu2: completed 70000 read accesses @27695820
|
||||
system.cpu6: completed 70000 read accesses @27700350
|
||||
system.cpu0: completed 80000 read accesses @31228160
|
||||
system.cpu5: completed 80000 read accesses @31278826
|
||||
system.cpu1: completed 80000 read accesses @31322150
|
||||
system.cpu3: completed 80000 read accesses @31508190
|
||||
system.cpu2: completed 80000 read accesses @31596330
|
||||
system.cpu6: completed 80000 read accesses @31639000
|
||||
system.cpu4: completed 80000 read accesses @31655530
|
||||
system.cpu7: completed 80000 read accesses @31659000
|
||||
system.cpu0: completed 90000 read accesses @35134550
|
||||
system.cpu5: completed 90000 read accesses @35282690
|
||||
system.cpu1: completed 90000 read accesses @35298090
|
||||
system.cpu2: completed 90000 read accesses @35490890
|
||||
system.cpu3: completed 90000 read accesses @35500970
|
||||
system.cpu6: completed 90000 read accesses @35564170
|
||||
system.cpu7: completed 90000 read accesses @35589110
|
||||
system.cpu4: completed 90000 read accesses @35604290
|
||||
system.cpu0: completed 100000 read accesses @39098820
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 20 2010 12:14:24
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:14:33
|
||||
M5 executing on SC2B0629
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 2583072 because maximum number of loads reached
|
||||
Exiting @ tick 39098820 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 341980 # Number of bytes of host memory used
|
||||
host_seconds 25.58 # Real time elapsed on the host
|
||||
host_tick_rate 100993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346136 # Number of bytes of host memory used
|
||||
host_seconds 306.11 # Real time elapsed on the host
|
||||
host_tick_rate 127726 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.002583 # Number of seconds simulated
|
||||
sim_ticks 2583072 # Number of ticks simulated
|
||||
sim_seconds 0.039099 # Number of seconds simulated
|
||||
sim_ticks 39098820 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53663 # number of write accesses completed
|
||||
system.cpu0.num_writes 53574 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98827 # number of read accesses completed
|
||||
system.cpu1.num_writes 53487 # number of write accesses completed
|
||||
system.cpu1.num_reads 99631 # number of read accesses completed
|
||||
system.cpu1.num_writes 53502 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 96775 # number of read accesses completed
|
||||
system.cpu2.num_writes 51846 # number of write accesses completed
|
||||
system.cpu2.num_reads 99061 # number of read accesses completed
|
||||
system.cpu2.num_writes 53455 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97235 # number of read accesses completed
|
||||
system.cpu3.num_writes 52295 # number of write accesses completed
|
||||
system.cpu3.num_reads 98999 # number of read accesses completed
|
||||
system.cpu3.num_writes 53370 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 97597 # number of read accesses completed
|
||||
system.cpu4.num_writes 52429 # number of write accesses completed
|
||||
system.cpu4.num_reads 99076 # number of read accesses completed
|
||||
system.cpu4.num_writes 53347 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97329 # number of read accesses completed
|
||||
system.cpu5.num_writes 52105 # number of write accesses completed
|
||||
system.cpu5.num_reads 99631 # number of read accesses completed
|
||||
system.cpu5.num_writes 53316 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 96958 # number of read accesses completed
|
||||
system.cpu6.num_writes 52281 # number of write accesses completed
|
||||
system.cpu6.num_reads 99060 # number of read accesses completed
|
||||
system.cpu6.num_writes 53733 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97500 # number of read accesses completed
|
||||
system.cpu7.num_writes 52109 # number of write accesses completed
|
||||
system.cpu7.num_reads 99033 # number of read accesses completed
|
||||
system.cpu7.num_writes 53376 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.cpu0]
|
||||
type=MemTest
|
||||
|
|
@ -142,6 +151,7 @@ type=Directory_Controller
|
|||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
|
|
@ -538,10 +548,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
|
|||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -553,8 +562,9 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -565,8 +575,9 @@ port=system.cpu0.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl1.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -577,8 +588,9 @@ port=system.cpu1.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl2.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -589,8 +601,9 @@ port=system.cpu2.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl3.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -601,8 +614,9 @@ port=system.cpu3.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl4.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -613,8 +627,9 @@ port=system.cpu4.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl5.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -625,8 +640,9 @@ port=system.cpu5.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl6.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -637,8 +653,9 @@ port=system.cpu6.test
|
|||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl7.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
deadlock_threshold=1000000
|
||||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
|
|
@ -647,14 +664,6 @@ version=7
|
|||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu2: completed 10000 read accesses @332309
|
||||
system.cpu0: completed 10000 read accesses @332762
|
||||
system.cpu3: completed 10000 read accesses @333275
|
||||
system.cpu7: completed 10000 read accesses @334660
|
||||
system.cpu4: completed 10000 read accesses @336400
|
||||
system.cpu6: completed 10000 read accesses @336827
|
||||
system.cpu1: completed 10000 read accesses @336833
|
||||
system.cpu5: completed 10000 read accesses @339345
|
||||
system.cpu3: completed 20000 read accesses @659139
|
||||
system.cpu0: completed 20000 read accesses @662762
|
||||
system.cpu2: completed 20000 read accesses @662918
|
||||
system.cpu4: completed 20000 read accesses @663822
|
||||
system.cpu6: completed 20000 read accesses @664214
|
||||
system.cpu7: completed 20000 read accesses @673557
|
||||
system.cpu1: completed 20000 read accesses @673720
|
||||
system.cpu5: completed 20000 read accesses @675222
|
||||
system.cpu3: completed 30000 read accesses @990404
|
||||
system.cpu6: completed 30000 read accesses @991868
|
||||
system.cpu0: completed 30000 read accesses @993980
|
||||
system.cpu2: completed 30000 read accesses @994621
|
||||
system.cpu4: completed 30000 read accesses @995936
|
||||
system.cpu5: completed 30000 read accesses @1005609
|
||||
system.cpu1: completed 30000 read accesses @1008145
|
||||
system.cpu7: completed 30000 read accesses @1008840
|
||||
system.cpu6: completed 40000 read accesses @1322251
|
||||
system.cpu0: completed 40000 read accesses @1324139
|
||||
system.cpu3: completed 40000 read accesses @1324341
|
||||
system.cpu2: completed 40000 read accesses @1325019
|
||||
system.cpu4: completed 40000 read accesses @1328462
|
||||
system.cpu5: completed 40000 read accesses @1335869
|
||||
system.cpu1: completed 40000 read accesses @1336407
|
||||
system.cpu7: completed 40000 read accesses @1342910
|
||||
system.cpu6: completed 50000 read accesses @1654106
|
||||
system.cpu0: completed 50000 read accesses @1654925
|
||||
system.cpu3: completed 50000 read accesses @1657897
|
||||
system.cpu2: completed 50000 read accesses @1658205
|
||||
system.cpu1: completed 50000 read accesses @1668347
|
||||
system.cpu5: completed 50000 read accesses @1668465
|
||||
system.cpu4: completed 50000 read accesses @1670315
|
||||
system.cpu7: completed 50000 read accesses @1681232
|
||||
system.cpu6: completed 60000 read accesses @1984633
|
||||
system.cpu0: completed 60000 read accesses @1986549
|
||||
system.cpu2: completed 60000 read accesses @1989981
|
||||
system.cpu3: completed 60000 read accesses @1993690
|
||||
system.cpu1: completed 60000 read accesses @2001694
|
||||
system.cpu4: completed 60000 read accesses @2002313
|
||||
system.cpu5: completed 60000 read accesses @2005561
|
||||
system.cpu7: completed 60000 read accesses @2014675
|
||||
system.cpu6: completed 70000 read accesses @2317222
|
||||
system.cpu0: completed 70000 read accesses @2318277
|
||||
system.cpu2: completed 70000 read accesses @2322048
|
||||
system.cpu3: completed 70000 read accesses @2324750
|
||||
system.cpu4: completed 70000 read accesses @2332151
|
||||
system.cpu1: completed 70000 read accesses @2332386
|
||||
system.cpu5: completed 70000 read accesses @2332911
|
||||
system.cpu7: completed 70000 read accesses @2343337
|
||||
system.cpu0: completed 80000 read accesses @2646207
|
||||
system.cpu6: completed 80000 read accesses @2646561
|
||||
system.cpu3: completed 80000 read accesses @2652685
|
||||
system.cpu2: completed 80000 read accesses @2655532
|
||||
system.cpu5: completed 80000 read accesses @2662477
|
||||
system.cpu4: completed 80000 read accesses @2665813
|
||||
system.cpu7: completed 80000 read accesses @2668350
|
||||
system.cpu1: completed 80000 read accesses @2668666
|
||||
system.cpu6: completed 90000 read accesses @2976982
|
||||
system.cpu0: completed 90000 read accesses @2982010
|
||||
system.cpu2: completed 90000 read accesses @2983845
|
||||
system.cpu3: completed 90000 read accesses @2993125
|
||||
system.cpu5: completed 90000 read accesses @2995492
|
||||
system.cpu4: completed 90000 read accesses @2998220
|
||||
system.cpu7: completed 90000 read accesses @3003787
|
||||
system.cpu1: completed 90000 read accesses @3004322
|
||||
system.cpu6: completed 100000 read accesses @3305503
|
||||
system.cpu5: completed 10000 read accesses @3773579
|
||||
system.cpu6: completed 10000 read accesses @3800919
|
||||
system.cpu4: completed 10000 read accesses @3806319
|
||||
system.cpu7: completed 10000 read accesses @3815919
|
||||
system.cpu3: completed 10000 read accesses @3847469
|
||||
system.cpu1: completed 10000 read accesses @3858049
|
||||
system.cpu2: completed 10000 read accesses @3865769
|
||||
system.cpu0: completed 10000 read accesses @3909119
|
||||
system.cpu6: completed 20000 read accesses @7545009
|
||||
system.cpu5: completed 20000 read accesses @7578569
|
||||
system.cpu3: completed 20000 read accesses @7650419
|
||||
system.cpu4: completed 20000 read accesses @7653039
|
||||
system.cpu7: completed 20000 read accesses @7660349
|
||||
system.cpu1: completed 20000 read accesses @7666509
|
||||
system.cpu2: completed 20000 read accesses @7676969
|
||||
system.cpu0: completed 20000 read accesses @7778949
|
||||
system.cpu5: completed 30000 read accesses @11400279
|
||||
system.cpu6: completed 30000 read accesses @11403319
|
||||
system.cpu3: completed 30000 read accesses @11463329
|
||||
system.cpu4: completed 30000 read accesses @11476649
|
||||
system.cpu1: completed 30000 read accesses @11482109
|
||||
system.cpu2: completed 30000 read accesses @11515599
|
||||
system.cpu7: completed 30000 read accesses @11523379
|
||||
system.cpu0: completed 30000 read accesses @11644619
|
||||
system.cpu6: completed 40000 read accesses @15163509
|
||||
system.cpu5: completed 40000 read accesses @15247859
|
||||
system.cpu1: completed 40000 read accesses @15285159
|
||||
system.cpu4: completed 40000 read accesses @15331509
|
||||
system.cpu2: completed 40000 read accesses @15338199
|
||||
system.cpu3: completed 40000 read accesses @15352259
|
||||
system.cpu7: completed 40000 read accesses @15377169
|
||||
system.cpu0: completed 40000 read accesses @15448399
|
||||
system.cpu6: completed 50000 read accesses @18963379
|
||||
system.cpu5: completed 50000 read accesses @19066919
|
||||
system.cpu1: completed 50000 read accesses @19138729
|
||||
system.cpu3: completed 50000 read accesses @19175839
|
||||
system.cpu4: completed 50000 read accesses @19193269
|
||||
system.cpu2: completed 50000 read accesses @19229269
|
||||
system.cpu0: completed 50000 read accesses @19286699
|
||||
system.cpu7: completed 50000 read accesses @19288339
|
||||
system.cpu6: completed 60000 read accesses @22830379
|
||||
system.cpu5: completed 60000 read accesses @22876169
|
||||
system.cpu1: completed 60000 read accesses @22895139
|
||||
system.cpu4: completed 60000 read accesses @23008339
|
||||
system.cpu3: completed 60000 read accesses @23024099
|
||||
system.cpu2: completed 60000 read accesses @23042669
|
||||
system.cpu7: completed 60000 read accesses @23113989
|
||||
system.cpu0: completed 60000 read accesses @23166249
|
||||
system.cpu6: completed 70000 read accesses @26656369
|
||||
system.cpu5: completed 70000 read accesses @26704159
|
||||
system.cpu1: completed 70000 read accesses @26732409
|
||||
system.cpu4: completed 70000 read accesses @26782879
|
||||
system.cpu3: completed 70000 read accesses @26845059
|
||||
system.cpu2: completed 70000 read accesses @26884599
|
||||
system.cpu7: completed 70000 read accesses @26960819
|
||||
system.cpu0: completed 70000 read accesses @26960869
|
||||
system.cpu6: completed 80000 read accesses @30376569
|
||||
system.cpu5: completed 80000 read accesses @30517259
|
||||
system.cpu4: completed 80000 read accesses @30578729
|
||||
system.cpu1: completed 80000 read accesses @30606099
|
||||
system.cpu3: completed 80000 read accesses @30658599
|
||||
system.cpu2: completed 80000 read accesses @30711719
|
||||
system.cpu0: completed 80000 read accesses @30713219
|
||||
system.cpu7: completed 80000 read accesses @30760569
|
||||
system.cpu6: completed 90000 read accesses @34228379
|
||||
system.cpu5: completed 90000 read accesses @34328029
|
||||
system.cpu4: completed 90000 read accesses @34428059
|
||||
system.cpu1: completed 90000 read accesses @34475699
|
||||
system.cpu3: completed 90000 read accesses @34504539
|
||||
system.cpu0: completed 90000 read accesses @34548119
|
||||
system.cpu7: completed 90000 read accesses @34567549
|
||||
system.cpu2: completed 90000 read accesses @34597039
|
||||
system.cpu6: completed 100000 read accesses @38059429
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 20 2010 12:17:38
|
||||
M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 20 2010 12:17:55
|
||||
M5 executing on SC2B0629
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3305503 because maximum number of loads reached
|
||||
Exiting @ tick 38059429 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 341640 # Number of bytes of host memory used
|
||||
host_seconds 37.52 # Real time elapsed on the host
|
||||
host_tick_rate 88100 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 345444 # Number of bytes of host memory used
|
||||
host_seconds 247.62 # Real time elapsed on the host
|
||||
host_tick_rate 153698 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003306 # Number of seconds simulated
|
||||
sim_ticks 3305503 # Number of ticks simulated
|
||||
sim_seconds 0.038059 # Number of seconds simulated
|
||||
sim_ticks 38059429 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99692 # number of read accesses completed
|
||||
system.cpu0.num_writes 53673 # number of write accesses completed
|
||||
system.cpu0.num_reads 99072 # number of read accesses completed
|
||||
system.cpu0.num_writes 53787 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99062 # number of read accesses completed
|
||||
system.cpu1.num_writes 53374 # number of write accesses completed
|
||||
system.cpu1.num_reads 99360 # number of read accesses completed
|
||||
system.cpu1.num_writes 53383 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99665 # number of read accesses completed
|
||||
system.cpu2.num_writes 53906 # number of write accesses completed
|
||||
system.cpu2.num_reads 99132 # number of read accesses completed
|
||||
system.cpu2.num_writes 53677 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99457 # number of read accesses completed
|
||||
system.cpu3.num_writes 53389 # number of write accesses completed
|
||||
system.cpu3.num_reads 99402 # number of read accesses completed
|
||||
system.cpu3.num_writes 53396 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99209 # number of read accesses completed
|
||||
system.cpu4.num_writes 53779 # number of write accesses completed
|
||||
system.cpu4.num_reads 99445 # number of read accesses completed
|
||||
system.cpu4.num_writes 53699 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99375 # number of read accesses completed
|
||||
system.cpu5.num_writes 53528 # number of write accesses completed
|
||||
system.cpu5.num_reads 99752 # number of read accesses completed
|
||||
system.cpu5.num_writes 53216 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53388 # number of write accesses completed
|
||||
system.cpu6.num_writes 53289 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99219 # number of read accesses completed
|
||||
system.cpu7.num_writes 53946 # number of write accesses completed
|
||||
system.cpu7.num_reads 99050 # number of read accesses completed
|
||||
system.cpu7.num_writes 53576 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -130,6 +139,7 @@ tracer=system.ruby.tracer
|
|||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
|
|
|
|||
|
|
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/13/2011 22:36:32
|
||||
Real time: Feb/08/2011 17:31:55
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 2
|
||||
Elapsed_time_in_minutes: 0.0333333
|
||||
Elapsed_time_in_hours: 0.000555556
|
||||
Elapsed_time_in_days: 2.31481e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 2.32
|
||||
Virtual_time_in_minutes: 0.0386667
|
||||
Virtual_time_in_hours: 0.000644444
|
||||
Virtual_time_in_days: 2.68519e-05
|
||||
Virtual_time_in_seconds: 0.79
|
||||
Virtual_time_in_minutes: 0.0131667
|
||||
Virtual_time_in_hours: 0.000219444
|
||||
Virtual_time_in_days: 9.14352e-06
|
||||
|
||||
Ruby_current_time: 352261
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 352261
|
||||
|
||||
mbytes_resident: 19.4023
|
||||
mbytes_total: 155.219
|
||||
resident_ratio: 0.12505
|
||||
mbytes_resident: 33.6719
|
||||
mbytes_total: 208.004
|
||||
resident_ratio: 0.161956
|
||||
|
||||
ruby_cycles_executed: [ 352262 ]
|
||||
|
||||
|
|
@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4457 average: 0 | standa
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 2
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 5638
|
||||
page_reclaims: 9831
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 13 2011 22:36:25
|
||||
M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
|
||||
M5 started Jan 13 2011 22:36:30
|
||||
M5 executing on scamorza.cs.wisc.edu
|
||||
M5 compiled Feb 8 2011 17:31:51
|
||||
M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:31:55
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 158948 # Number of bytes of host memory used
|
||||
host_seconds 1.84 # Real time elapsed on the host
|
||||
host_tick_rate 191255 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213000 # Number of bytes of host memory used
|
||||
host_seconds 0.47 # Real time elapsed on the host
|
||||
host_tick_rate 753338 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000352 # Number of seconds simulated
|
||||
sim_ticks 352261 # Number of ticks simulated
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -52,32 +61,19 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -85,7 +81,7 @@ replacement_policy=PSEUDO_LRU
|
|||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -121,14 +117,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -138,13 +133,18 @@ randomization=true
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -160,9 +160,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
|
|
@ -224,3 +224,10 @@ num_of_sequencers=1
|
|||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:40:25
|
||||
Real time: Feb/08/2011 17:41:43
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 1.03
|
||||
Virtual_time_in_minutes: 0.0171667
|
||||
Virtual_time_in_hours: 0.000286111
|
||||
Virtual_time_in_days: 1.19213e-05
|
||||
Virtual_time_in_seconds: 0.8
|
||||
Virtual_time_in_minutes: 0.0133333
|
||||
Virtual_time_in_hours: 0.000222222
|
||||
Virtual_time_in_days: 9.25926e-06
|
||||
|
||||
Ruby_current_time: 372291
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 372291
|
||||
|
||||
mbytes_resident: 31.6016
|
||||
mbytes_total: 31.6094
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 33.7734
|
||||
mbytes_total: 208.148
|
||||
resident_ratio: 0.162313
|
||||
|
||||
ruby_cycles_executed: [ 372292 ]
|
||||
|
||||
|
|
@ -119,8 +119,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7050
|
||||
page_faults: 1907
|
||||
page_reclaims: 9846
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.174693
|
|||
outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
|
||||
--- L1Cache ---
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:34:54
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:40:24
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:41:34
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:41:42
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 210064 # Number of bytes of host memory used
|
||||
host_seconds 0.80 # Real time elapsed on the host
|
||||
host_tick_rate 465329 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213148 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 746373 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000372 # Number of seconds simulated
|
||||
sim_ticks 372291 # Number of ticks simulated
|
||||
|
|
|
|||
|
|
@ -1,13 +1,22 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
|
|
@ -55,9 +64,9 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
|
||||
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -69,24 +78,11 @@ no_mig_atomic=true
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
[system.l1_cntrl0.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -94,7 +90,7 @@ replacement_policy=PSEUDO_LRU
|
|||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
[system.l1_cntrl0.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
|
|
@ -132,14 +128,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -149,13 +144,18 @@ randomization=true
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -171,9 +171,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
name=Crossbar
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
|
|
@ -235,3 +235,10 @@ num_of_sequencers=1
|
|||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 10:45:27
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.75
|
||||
Virtual_time_in_minutes: 0.0125
|
||||
Virtual_time_in_hours: 0.000208333
|
||||
Virtual_time_in_days: 8.68056e-06
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 273851
|
||||
Ruby_current_time: 267511
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 273851
|
||||
Ruby_cycles: 267511
|
||||
|
||||
mbytes_resident: 31.5859
|
||||
mbytes_total: 31.5938
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 33.7617
|
||||
mbytes_total: 208.121
|
||||
resident_ratio: 0.162259
|
||||
|
||||
ruby_cycles_executed: [ 273852 ]
|
||||
ruby_cycles_executed: [ 267512 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -66,17 +66,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.8225 | standard deviation: 1.14181 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 902 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
|
||||
miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 6580 count: 954 average: 4444.74 | standard deviation: 1862.02 | 67 9 3 1 6 4 9 12 10 7 1 8 5 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1214 count: 48 average: 548.458 | standard deviation: 260.39 | 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6135 count: 52 average: 4940.85 | standard deviation: 1334.03 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6580 count: 854 average: 4633.53 | standard deviation: 1690.7 | 62 8 1 0 3 2 5 7 3 2 0 1 1 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 73 average: 12.8356 | standard deviation: 32.0687 | 0 17 17 15 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_L2Cache: [binsize: 8 max: 812 count: 13 average: 309.154 | standard deviation: 223.678 | 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6580 count: 868 average: 4879.41 | standard deviation: 1307.99 | 0 0 1 1 4 2 7 12 10 6 1 8 4 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -86,16 +86,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 902
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average: 4 | standard deviation: 0 | 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 868
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 108 count: 2 average: 55.5 | standard deviation: 74.2496 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 2 max: 359 count: 3 average: 181.333 | standard deviation: 165.7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1214 count: 43 average: 597 | standard deviation: 225.443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 3 average: 1.66667 | standard deviation: 0.707107 | 0 1 2 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6135 count: 49 average: 5243.24 | standard deviation: 522.306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 68 average: 12.0735 | standard deviation: 31.0217 | 0 16 15 14 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 8 max: 812 count: 10 average: 347.5 | standard deviation: 231.361 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6580 count: 776 average: 5093.73 | standard deviation: 906.859 | 0 0 0 0 1 1 3 7 3 1 0 1 0 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -127,8 +126,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7004
|
||||
page_faults: 1904
|
||||
page_reclaims: 9836
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -136,120 +135,116 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5485 43880
|
||||
total_msg_count_Response_Data: 2871 206712
|
||||
total_msg_count_ResponseL2hit_Data: 51 3672
|
||||
total_msg_count_Response_Control: 9 72
|
||||
total_msg_count_Writeback_Data: 5349 385128
|
||||
total_msg_count_Writeback_Control: 246 1968
|
||||
total_msg_count_Persistent_Control: 2292 18336
|
||||
total_msgs: 16303 total_bytes: 659768
|
||||
total_msg_count_Request_Control: 5259 42072
|
||||
total_msg_count_Response_Data: 2727 196344
|
||||
total_msg_count_ResponseL2hit_Data: 33 2376
|
||||
total_msg_count_Response_Control: 3 24
|
||||
total_msg_count_Writeback_Data: 5187 373464
|
||||
total_msg_count_Writeback_Control: 234 1872
|
||||
total_msg_count_Persistent_Control: 2388 19104
|
||||
total_msgs: 15831 total_bytes: 635256
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.115928
|
||||
links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.115486
|
||||
links_utilized_percent_switch_0_link_0: 0.0430356 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.187936 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 0 0 0 955 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0997532
|
||||
links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.0975123
|
||||
links_utilized_percent_switch_1_link_0: 0.0428627 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.152162 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 768 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.09541
|
||||
links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0934167
|
||||
links_utilized_percent_switch_2_link_0: 0.0396432 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.14719 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.167305
|
||||
links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.164909
|
||||
links_utilized_percent_switch_3_link_0: 0.164704 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.171451 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.158573 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 58
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 58
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 58 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 46 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 865
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.39306%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.6069%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.86124%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.1388%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 865 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 836 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [41 ] 41
|
||||
Ifetch [59 ] 59
|
||||
Store [901 ] 901
|
||||
Load [52 ] 52
|
||||
Ifetch [48 ] 48
|
||||
Store [855 ] 855
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [388292 ] 388292
|
||||
Data_Shared [9 ] 9
|
||||
Data_Owner [2 ] 2
|
||||
Data_All_Tokens [998 ] 998
|
||||
Ack [2 ] 2
|
||||
Ack_All_Tokens [2 ] 2
|
||||
L1_Replacement [19142 ] 19142
|
||||
Data_Shared [3 ] 3
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [976 ] 976
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
|
|
@ -259,21 +254,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
|
|||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [382 ] 382
|
||||
Request_Timeout [674 ] 674
|
||||
Own_Lock_or_Unlock [398 ] 398
|
||||
Request_Timeout [783 ] 783
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [912 ] 912
|
||||
Use_TimeoutNoStarvers [877 ] 877
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [38 ] 38
|
||||
NP Ifetch [58 ] 58
|
||||
NP Store [826 ] 826
|
||||
NP Load [49 ] 49
|
||||
NP Ifetch [46 ] 46
|
||||
NP Store [787 ] 787
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [87 ] 87
|
||||
NP Data_All_Tokens [98 ] 98
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -282,7 +277,7 @@ NP Transient_Local_GETS [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [175 ] 175
|
||||
NP Own_Lock_or_Unlock [190 ] 190
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
|
|
@ -305,10 +300,10 @@ I Persistent_GETS_Last_Token [0 ] 0
|
|||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [1 ] 1
|
||||
S Store [1 ] 1
|
||||
S Ifetch [2 ] 2
|
||||
S Store [0 ] 0
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [8 ] 8
|
||||
S L1_Replacement [3 ] 3
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
|
|
@ -348,33 +343,33 @@ M Load [0 ] 0
|
|||
M Ifetch [0 ] 0
|
||||
M Store [0 ] 0
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [83 ] 83
|
||||
M L1_Replacement [88 ] 88
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [12 ] 12
|
||||
M Own_Lock_or_Unlock [15 ] 15
|
||||
|
||||
MM Load [2 ] 2
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [64 ] 64
|
||||
MM Store [57 ] 57
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [826 ] 826
|
||||
MM L1_Replacement [786 ] 786
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [27 ] 27
|
||||
MM Own_Lock_or_Unlock [15 ] 15
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Load [1 ] 1
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [1338 ] 1338
|
||||
M_W L1_Replacement [396 ] 396
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
|
|
@ -384,35 +379,35 @@ M_W Persistent_GETS [0 ] 0
|
|||
M_W Own_Lock_or_Unlock [1 ] 1
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [85 ] 85
|
||||
M_W Use_TimeoutNoStarvers [90 ] 90
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [9 ] 9
|
||||
MM_W Store [10 ] 10
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [30069 ] 30069
|
||||
MM_W L1_Replacement [7395 ] 7395
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [26 ] 26
|
||||
MM_W Own_Lock_or_Unlock [25 ] 25
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [827 ] 827
|
||||
MM_W Use_TimeoutNoStarvers [787 ] 787
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [341249 ] 341249
|
||||
IM L1_Replacement [9791 ] 9791
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [2 ] 2
|
||||
IM Data_All_Tokens [823 ] 823
|
||||
IM Ack [2 ] 2
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [786 ] 786
|
||||
IM Ack [1 ] 1
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
|
|
@ -422,8 +417,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [124 ] 124
|
||||
IM Request_Timeout [608 ] 608
|
||||
IM Own_Lock_or_Unlock [135 ] 135
|
||||
IM Request_Timeout [709 ] 709
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
|
@ -432,7 +427,7 @@ SM Atomic [0 ] 0
|
|||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [1 ] 1
|
||||
SM Data_All_Tokens [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -454,7 +449,7 @@ OM L1_Replacement [0 ] 0
|
|||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [2 ] 2
|
||||
OM Ack_All_Tokens [0 ] 0
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
|
|
@ -464,17 +459,17 @@ OM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [1 ] 1
|
||||
OM Request_Timeout [1 ] 1
|
||||
OM Own_Lock_or_Unlock [0 ] 0
|
||||
OM Request_Timeout [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [14719 ] 14719
|
||||
IS Data_Shared [9 ] 9
|
||||
IS L1_Replacement [683 ] 683
|
||||
IS Data_Shared [3 ] 3
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [87 ] 87
|
||||
IS Data_All_Tokens [92 ] 92
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
|
|
@ -485,8 +480,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [16 ] 16
|
||||
IS Request_Timeout [65 ] 65
|
||||
IS Own_Lock_or_Unlock [17 ] 17
|
||||
IS Request_Timeout [74 ] 74
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
|
|
@ -590,50 +585,50 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
|||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 906
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 9.60265%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.3974%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.5626%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4374%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 906 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 871 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [95 ] 95
|
||||
L1_GETS_Last_Token [1 ] 1
|
||||
L1_GETX [826 ] 826
|
||||
L1_GETS_Last_Token [0 ] 0
|
||||
L1_GETX [787 ] 787
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [857 ] 857
|
||||
L2_Replacement [799 ] 799
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [8 ] 8
|
||||
Writeback_All_Tokens [908 ] 908
|
||||
Writeback_Shared_Data [3 ] 3
|
||||
Writeback_All_Tokens [874 ] 874
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [173 ] 173
|
||||
Persistent_GETS [18 ] 18
|
||||
Persistent_GETX [179 ] 179
|
||||
Persistent_GETS [20 ] 20
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [191 ] 191
|
||||
Own_Lock_or_Unlock [199 ] 199
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [87 ] 87
|
||||
NP L1_GETX [816 ] 816
|
||||
NP L1_GETS [92 ] 92
|
||||
NP L1_GETX [777 ] 777
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [7 ] 7
|
||||
NP Writeback_All_Tokens [852 ] 852
|
||||
NP Writeback_Shared_Data [3 ] 3
|
||||
NP Writeback_All_Tokens [798 ] 798
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
|
|
@ -642,7 +637,7 @@ NP Ack [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [168 ] 168
|
||||
NP Own_Lock_or_Unlock [181 ] 181
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
|
|
@ -651,10 +646,10 @@ I L1_INV [0 ] 0
|
|||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [28 ] 28
|
||||
I L2_Replacement [24 ] 24
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [1 ] 1
|
||||
I Writeback_All_Tokens [5 ] 5
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [3 ] 3
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
|
|
@ -666,13 +661,13 @@ I Persistent_GETS_Last_Token [0 ] 0
|
|||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [1 ] 1
|
||||
S L1_GETX [2 ] 2
|
||||
S L1_GETS_Last_Token [0 ] 0
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [5 ] 5
|
||||
S L2_Replacement [2 ] 2
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
|
|
@ -688,12 +683,12 @@ S Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_GETX [0 ] 0
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [7 ] 7
|
||||
O L2_Replacement [3 ] 3
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [0 ] 0
|
||||
|
|
@ -706,34 +701,34 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [8 ] 8
|
||||
M L1_GETX [7 ] 7
|
||||
M L1_GETS [3 ] 3
|
||||
M L1_GETX [8 ] 8
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [814 ] 814
|
||||
M Persistent_GETX [26 ] 26
|
||||
M L2_Replacement [768 ] 768
|
||||
M Persistent_GETX [20 ] 20
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_GETX [1 ] 1
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [3 ] 3
|
||||
I_L L2_Replacement [2 ] 2
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [51 ] 51
|
||||
I_L Writeback_All_Tokens [73 ] 73
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [147 ] 147
|
||||
I_L Persistent_GETS [18 ] 18
|
||||
I_L Own_Lock_or_Unlock [23 ] 23
|
||||
I_L Persistent_GETX [159 ] 159
|
||||
I_L Persistent_GETS [20 ] 20
|
||||
I_L Own_Lock_or_Unlock [18 ] 18
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
|
|
@ -757,93 +752,93 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
|||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1720
|
||||
memory_reads: 902
|
||||
memory_writes: 818
|
||||
memory_refreshes: 571
|
||||
memory_total_request_delays: 1302
|
||||
memory_delays_per_request: 0.756977
|
||||
memory_delays_in_input_queue: 202
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1100
|
||||
memory_stalls_for_bank_busy: 220
|
||||
memory_total_requests: 1655
|
||||
memory_reads: 869
|
||||
memory_writes: 786
|
||||
memory_refreshes: 558
|
||||
memory_total_request_delays: 1116
|
||||
memory_delays_per_request: 0.67432
|
||||
memory_delays_in_input_queue: 156
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 957
|
||||
memory_stalls_for_bank_busy: 245
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 97
|
||||
memory_stalls_for_bus: 424
|
||||
memory_stalls_for_arbitration: 76
|
||||
memory_stalls_for_bus: 363
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 268
|
||||
memory_stalls_for_read_read_turnaround: 91
|
||||
accesses_per_bank: 61 42 48 69 122 69 58 56 55 51 54 41 43 47 55 55 46 45 53 50 43 51 55 52 43 56 60 54 49 40 40 57
|
||||
memory_stalls_for_read_write_turnaround: 197
|
||||
memory_stalls_for_read_read_turnaround: 76
|
||||
accesses_per_bank: 42 44 54 72 110 62 62 43 42 53 38 40 51 47 54 42 48 54 39 56 64 58 51 54 48 46 43 52 46 43 49 48
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [828 ] 828
|
||||
GETS [87 ] 87
|
||||
Lockdown [191 ] 191
|
||||
Unlockdown [191 ] 191
|
||||
GETX [807 ] 807
|
||||
GETS [92 ] 92
|
||||
Lockdown [199 ] 199
|
||||
Unlockdown [199 ] 199
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [7 ] 7
|
||||
Data_All_Tokens [825 ] 825
|
||||
Data_Owner [3 ] 3
|
||||
Data_All_Tokens [790 ] 790
|
||||
Ack_Owner [0 ] 0
|
||||
Ack_Owner_All_Tokens [76 ] 76
|
||||
Tokens [2 ] 2
|
||||
Ack_All_Tokens [3 ] 3
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [2 ] 2
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [902 ] 902
|
||||
Memory_Ack [817 ] 817
|
||||
Memory_Data [868 ] 868
|
||||
Memory_Ack [786 ] 786
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [811 ] 811
|
||||
O GETS [83 ] 83
|
||||
O Lockdown [6 ] 6
|
||||
O GETX [773 ] 773
|
||||
O GETS [90 ] 90
|
||||
O Lockdown [5 ] 5
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [3 ] 3
|
||||
O Ack_All_Tokens [2 ] 2
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [8 ] 8
|
||||
NO GETS [4 ] 4
|
||||
NO Lockdown [168 ] 168
|
||||
NO GETX [2 ] 2
|
||||
NO GETS [2 ] 2
|
||||
NO Lockdown [180 ] 180
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [7 ] 7
|
||||
NO Data_All_Tokens [811 ] 811
|
||||
NO Data_Owner [3 ] 3
|
||||
NO Data_All_Tokens [783 ] 783
|
||||
NO Ack_Owner [0 ] 0
|
||||
NO Ack_Owner_All_Tokens [76 ] 76
|
||||
NO Tokens [1 ] 1
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [0 ] 0
|
||||
L GETX [4 ] 4
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [189 ] 189
|
||||
L Unlockdown [199 ] 199
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
L Data_All_Tokens [14 ] 14
|
||||
L Data_All_Tokens [7 ] 7
|
||||
L Ack_Owner [0 ] 0
|
||||
L Ack_Owner_All_Tokens [0 ] 0
|
||||
L Tokens [1 ] 1
|
||||
L Tokens [0 ] 0
|
||||
L DMA_READ [0 ] 0
|
||||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [9 ] 9
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W Lockdown [3 ] 3
|
||||
O_W Lockdown [1 ] 1
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
|
@ -852,16 +847,16 @@ O_W Data_All_Tokens [0 ] 0
|
|||
O_W Ack_Owner [0 ] 0
|
||||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [1 ] 1
|
||||
O_W Memory_Ack [815 ] 815
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [785 ] 785
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [0 ] 0
|
||||
L_O_W GETX [28 ] 28
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [2 ] 2
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock [0 ] 0
|
||||
L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L_O_W Data_Owner [0 ] 0
|
||||
|
|
@ -869,8 +864,8 @@ L_O_W Data_All_Tokens [0 ] 0
|
|||
L_O_W Ack_Owner [0 ] 0
|
||||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [7 ] 7
|
||||
L_O_W Memory_Ack [2 ] 2
|
||||
L_O_W Memory_Data [6 ] 6
|
||||
L_O_W Memory_Ack [1 ] 1
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
@ -886,7 +881,7 @@ L_NO_W Data_All_Tokens [0 ] 0
|
|||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [14 ] 14
|
||||
L_NO_W Memory_Data [13 ] 13
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
@ -927,7 +922,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
|||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [14 ] 14
|
||||
NO_W Lockdown [13 ] 13
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
|
@ -936,7 +931,7 @@ NO_W Data_All_Tokens [0 ] 0
|
|||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [880 ] 880
|
||||
NO_W Memory_Data [849 ] 849
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 10:41:36
|
||||
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
|
||||
M5 started Aug 5 2010 10:45:27
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 273851 because Ruby Tester completed
|
||||
Exiting @ tick 267511 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 210052 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 516678 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213120 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_tick_rate 1663377 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000274 # Number of seconds simulated
|
||||
sim_ticks 273851 # Number of ticks simulated
|
||||
sim_seconds 0.000268 # Number of seconds simulated
|
||||
sim_ticks 267511 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,29 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000
|
||||
time_sync_spin_threshold=100000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
children=dir_cntrl0 l1_cntrl0 physmem ruby tester
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
|
||||
[system.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
buffer_size=0
|
||||
directory=system.dir_cntrl0.directory
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
|
|
@ -62,17 +72,18 @@ start_index_bit=6
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
|
||||
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
|
||||
children=L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
|
||||
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=10
|
||||
issue_latency=2
|
||||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
|
|
@ -84,35 +95,6 @@ replacement_policy=PSEUDO_LRU
|
|||
size=512
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.l1_cntrl0.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=root.cpuPort[0]
|
||||
|
||||
[system.l1_cntrl0.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -121,14 +103,13 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
|
|
@ -138,13 +119,35 @@ randomization=true
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.tester.cpuPort[0]
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.cpu_ruby_ports.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=2
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -160,9 +163,9 @@ topology=system.ruby.network.topology
|
|||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
name=Crossbar
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
|
|
@ -208,3 +211,10 @@ num_of_sequencers=1
|
|||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
cpuPort=system.ruby.cpu_ruby_ports.port[0]
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ RubySystem config:
|
|||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: Crossbar
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/05/2010 14:46:32
|
||||
Real time: Feb/08/2011 17:57:03
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.69
|
||||
Virtual_time_in_minutes: 0.0115
|
||||
Virtual_time_in_hours: 0.000191667
|
||||
Virtual_time_in_days: 7.98611e-06
|
||||
Virtual_time_in_seconds: 0.4
|
||||
Virtual_time_in_minutes: 0.00666667
|
||||
Virtual_time_in_hours: 0.000111111
|
||||
Virtual_time_in_days: 4.62963e-06
|
||||
|
||||
Ruby_current_time: 213851
|
||||
Ruby_current_time: 210961
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 213851
|
||||
Ruby_cycles: 210961
|
||||
|
||||
mbytes_resident: 31.293
|
||||
mbytes_total: 31.3008
|
||||
resident_ratio: 1
|
||||
mbytes_resident: 33.4023
|
||||
mbytes_total: 207.566
|
||||
resident_ratio: 0.160961
|
||||
|
||||
ruby_cycles_executed: [ 213852 ]
|
||||
ruby_cycles_executed: [ 210962 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -65,17 +65,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016 | standard deviation: 1.14461 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 71 891 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -85,15 +85,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 854
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 859
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average: 2 | standard deviation: 0.816497 | 0 1 2 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -125,8 +124,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6929
|
||||
page_faults: 1882
|
||||
page_reclaims: 9722
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -134,117 +133,118 @@ block_outputs: 0
|
|||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 2568 20544
|
||||
total_msg_count_Response_Data: 2562 184464
|
||||
total_msg_count_Writeback_Data: 2281 164232
|
||||
total_msg_count_Writeback_Control: 5351 42808
|
||||
total_msg_count_Unblock_Control: 2559 20472
|
||||
total_msgs: 15321 total_bytes: 432520
|
||||
total_msg_count_Request_Control: 2577 20616
|
||||
total_msg_count_Response_Data: 2577 185544
|
||||
total_msg_count_Writeback_Data: 2301 165672
|
||||
total_msg_count_Writeback_Control: 5367 42936
|
||||
total_msg_count_Unblock_Control: 2574 20592
|
||||
total_msgs: 15396 total_bytes: 435360
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.13593
|
||||
links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.138684
|
||||
links_utilized_percent_switch_0_link_0: 0.0508566 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.226511 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.127495
|
||||
links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.130027
|
||||
links_utilized_percent_switch_1_link_0: 0.0566278 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.203426 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.210637
|
||||
links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.214969
|
||||
links_utilized_percent_switch_2_link_0: 0.203426 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.226511 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.icache
|
||||
system.l1_cntrl0.sequencer.icache_total_misses: 57
|
||||
system.l1_cntrl0.sequencer.icache_total_demand_misses: 57
|
||||
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
system.ruby.cpu_ruby_ports.icache_total_misses: 52
|
||||
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 52
|
||||
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100%
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 52 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.sequencer.dcache
|
||||
system.l1_cntrl0.sequencer.dcache_total_misses: 840
|
||||
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840
|
||||
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 852
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 852
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571%
|
||||
system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 5.28169%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 94.7183%
|
||||
|
||||
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 852 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 856
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 904
|
||||
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 904
|
||||
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.97788%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2699%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.75221%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 904 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [41 ] 41
|
||||
Ifetch [106 ] 106
|
||||
Store [906 ] 906
|
||||
L2_Replacement [849 ] 849
|
||||
L1_to_L2 [303164 ] 303164
|
||||
Trigger_L2_to_L1D [38 ] 38
|
||||
Trigger_L2_to_L1I [3 ] 3
|
||||
Complete_L2_to_L1 [41 ] 41
|
||||
Load [48 ] 48
|
||||
Ifetch [53 ] 53
|
||||
Store [888 ] 888
|
||||
L2_Replacement [854 ] 854
|
||||
L1_to_L2 [16074 ] 16074
|
||||
Trigger_L2_to_L1D [39 ] 39
|
||||
Trigger_L2_to_L1I [4 ] 4
|
||||
Complete_L2_to_L1 [43 ] 43
|
||||
Other_GETX [0 ] 0
|
||||
Other_GETS [0 ] 0
|
||||
Merged_GETS [0 ] 0
|
||||
Other_GETS_No_Mig [0 ] 0
|
||||
NC_DMA_GETS [0 ] 0
|
||||
Invalidate [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Data [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
Exclusive_Data [854 ] 854
|
||||
Writeback_Ack [848 ] 848
|
||||
Exclusive_Data [859 ] 859
|
||||
Writeback_Ack [852 ] 852
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [853 ] 853
|
||||
All_acks_no_sharers [859 ] 859
|
||||
|
||||
- Transitions -
|
||||
I Load [36 ] 36
|
||||
I Ifetch [54 ] 54
|
||||
I Store [766 ] 766
|
||||
I Load [44 ] 44
|
||||
I Ifetch [48 ] 48
|
||||
I Store [769 ] 769
|
||||
I L2_Replacement [0 ] 0
|
||||
I L1_to_L2 [0 ] 0
|
||||
I Trigger_L2_to_L1D [0 ] 0
|
||||
|
|
@ -252,6 +252,7 @@ I Trigger_L2_to_L1I [0 ] 0
|
|||
I Other_GETX [0 ] 0
|
||||
I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
|
|
@ -264,6 +265,7 @@ S Trigger_L2_to_L1I [0 ] 0
|
|||
S Other_GETX [0 ] 0
|
||||
S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
|
|
@ -277,46 +279,50 @@ O Other_GETX [0 ] 0
|
|||
O Other_GETS [0 ] 0
|
||||
O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [1 ] 1
|
||||
M Store [1 ] 1
|
||||
M L2_Replacement [87 ] 87
|
||||
M L1_to_L2 [88 ] 88
|
||||
M Trigger_L2_to_L1D [1 ] 1
|
||||
M Ifetch [0 ] 0
|
||||
M Store [3 ] 3
|
||||
M L2_Replacement [85 ] 85
|
||||
M L1_to_L2 [95 ] 95
|
||||
M Trigger_L2_to_L1D [9 ] 9
|
||||
M Trigger_L2_to_L1I [0 ] 0
|
||||
M Other_GETX [0 ] 0
|
||||
M Other_GETS [0 ] 0
|
||||
M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
|
||||
MM Load [5 ] 5
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [4 ] 4
|
||||
MM Store [82 ] 82
|
||||
MM L2_Replacement [762 ] 762
|
||||
MM Store [92 ] 92
|
||||
MM L2_Replacement [769 ] 769
|
||||
MM L1_to_L2 [804 ] 804
|
||||
MM Trigger_L2_to_L1D [37 ] 37
|
||||
MM Trigger_L2_to_L1I [3 ] 3
|
||||
MM Trigger_L2_to_L1D [30 ] 30
|
||||
MM Trigger_L2_to_L1I [4 ] 4
|
||||
MM Other_GETX [0 ] 0
|
||||
MM Other_GETS [0 ] 0
|
||||
MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM L2_Replacement [0 ] 0
|
||||
IM L1_to_L2 [275518 ] 275518
|
||||
IM L1_to_L2 [9842 ] 9842
|
||||
IM Other_GETX [0 ] 0
|
||||
IM Other_GETS [0 ] 0
|
||||
IM Other_GETS_No_Mig [0 ] 0
|
||||
IM NC_DMA_GETS [0 ] 0
|
||||
IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [764 ] 764
|
||||
IM Exclusive_Data [767 ] 767
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
|
@ -326,9 +332,11 @@ SM L1_to_L2 [0 ] 0
|
|||
SM Other_GETX [0 ] 0
|
||||
SM Other_GETS [0 ] 0
|
||||
SM Other_GETS_No_Mig [0 ] 0
|
||||
SM NC_DMA_GETS [0 ] 0
|
||||
SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
|
|
@ -339,6 +347,7 @@ OM Other_GETX [0 ] 0
|
|||
OM Other_GETS [0 ] 0
|
||||
OM Merged_GETS [0 ] 0
|
||||
OM Other_GETS_No_Mig [0 ] 0
|
||||
OM NC_DMA_GETS [0 ] 0
|
||||
OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
|
|
@ -354,34 +363,35 @@ ISM All_acks_no_sharers [0 ] 0
|
|||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [483 ] 483
|
||||
M_W L1_to_L2 [310 ] 310
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [89 ] 89
|
||||
M_W All_acks_no_sharers [91 ] 91
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [1 ] 1
|
||||
MM_W Store [0 ] 0
|
||||
MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [10887 ] 10887
|
||||
MM_W L1_to_L2 [4284 ] 4284
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [764 ] 764
|
||||
MM_W All_acks_no_sharers [768 ] 768
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS L2_Replacement [0 ] 0
|
||||
IS L1_to_L2 [14644 ] 14644
|
||||
IS L1_to_L2 [621 ] 621
|
||||
IS Other_GETX [0 ] 0
|
||||
IS Other_GETS [0 ] 0
|
||||
IS Other_GETS_No_Mig [0 ] 0
|
||||
IS NC_DMA_GETS [0 ] 0
|
||||
IS Invalidate [0 ] 0
|
||||
IS Ack [0 ] 0
|
||||
IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [90 ] 90
|
||||
IS Exclusive_Data [92 ] 92
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
|
|
@ -402,20 +412,22 @@ OI Other_GETX [0 ] 0
|
|||
OI Other_GETS [0 ] 0
|
||||
OI Merged_GETS [0 ] 0
|
||||
OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [36 ] 36
|
||||
MI Store [5 ] 5
|
||||
MI Ifetch [1 ] 1
|
||||
MI Store [0 ] 0
|
||||
MI L2_Replacement [0 ] 0
|
||||
MI L1_to_L2 [0 ] 0
|
||||
MI Other_GETX [0 ] 0
|
||||
MI Other_GETS [0 ] 0
|
||||
MI Merged_GETS [0 ] 0
|
||||
MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [848 ] 848
|
||||
MI Writeback_Ack [852 ] 852
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
|
|
@ -425,6 +437,7 @@ II L1_to_L2 [0 ] 0
|
|||
II Other_GETX [0 ] 0
|
||||
II Other_GETS [0 ] 0
|
||||
II Other_GETS_No_Mig [0 ] 0
|
||||
II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
|
|
@ -439,6 +452,7 @@ IT Other_GETX [0 ] 0
|
|||
IT Other_GETS [0 ] 0
|
||||
IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
|
|
@ -451,6 +465,7 @@ ST Other_GETX [0 ] 0
|
|||
ST Other_GETS [0 ] 0
|
||||
ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
|
|
@ -463,30 +478,33 @@ OT Other_GETX [0 ] 0
|
|||
OT Other_GETS [0 ] 0
|
||||
OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
MT Store [10 ] 10
|
||||
MT Store [2 ] 2
|
||||
MT L2_Replacement [0 ] 0
|
||||
MT L1_to_L2 [154 ] 154
|
||||
MT Complete_L2_to_L1 [1 ] 1
|
||||
MT L1_to_L2 [39 ] 39
|
||||
MT Complete_L2_to_L1 [9 ] 9
|
||||
MT Other_GETX [0 ] 0
|
||||
MT Other_GETS [0 ] 0
|
||||
MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [11 ] 11
|
||||
MMT Store [41 ] 41
|
||||
MMT Ifetch [0 ] 0
|
||||
MMT Store [21 ] 21
|
||||
MMT L2_Replacement [0 ] 0
|
||||
MMT L1_to_L2 [586 ] 586
|
||||
MMT Complete_L2_to_L1 [40 ] 40
|
||||
MMT L1_to_L2 [79 ] 79
|
||||
MMT Complete_L2_to_L1 [34 ] 34
|
||||
MMT Other_GETX [0 ] 0
|
||||
MMT Other_GETS [0 ] 0
|
||||
MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
|
|
@ -498,42 +516,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
|
|||
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1616
|
||||
memory_reads: 856
|
||||
memory_writes: 760
|
||||
memory_refreshes: 446
|
||||
memory_total_request_delays: 1108
|
||||
memory_delays_per_request: 0.685644
|
||||
memory_delays_in_input_queue: 161
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 945
|
||||
memory_stalls_for_bank_busy: 192
|
||||
memory_total_requests: 1626
|
||||
memory_reads: 859
|
||||
memory_writes: 767
|
||||
memory_refreshes: 440
|
||||
memory_total_request_delays: 1086
|
||||
memory_delays_per_request: 0.667897
|
||||
memory_delays_in_input_queue: 156
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 930
|
||||
memory_stalls_for_bank_busy: 238
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 83
|
||||
memory_stalls_for_bus: 395
|
||||
memory_stalls_for_arbitration: 61
|
||||
memory_stalls_for_bus: 358
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 154
|
||||
memory_stalls_for_read_read_turnaround: 121
|
||||
accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49
|
||||
memory_stalls_for_read_write_turnaround: 169
|
||||
memory_stalls_for_read_read_turnaround: 104
|
||||
accesses_per_bank: 41 42 40 76 63 66 54 43 49 56 52 46 53 60 61 57 50 44 44 42 48 49 42 47 53 52 49 52 50 47 41 57
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [770 ] 770
|
||||
GETS [91 ] 91
|
||||
PUT [909 ] 909
|
||||
GETX [767 ] 767
|
||||
GETS [93 ] 93
|
||||
PUT [907 ] 907
|
||||
Unblock [0 ] 0
|
||||
UnblockS [0 ] 0
|
||||
UnblockM [853 ] 853
|
||||
UnblockM [856 ] 856
|
||||
Writeback_Clean [0 ] 0
|
||||
Writeback_Dirty [0 ] 0
|
||||
Writeback_Exclusive_Clean [86 ] 86
|
||||
Writeback_Exclusive_Dirty [760 ] 760
|
||||
Writeback_Exclusive_Clean [85 ] 85
|
||||
Writeback_Exclusive_Dirty [767 ] 767
|
||||
Pf_Replacement [0 ] 0
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [854 ] 854
|
||||
Memory_Ack [760 ] 760
|
||||
Memory_Data [859 ] 859
|
||||
Memory_Ack [767 ] 767
|
||||
Ack [0 ] 0
|
||||
Shared_Ack [0 ] 0
|
||||
Shared_Data [0 ] 0
|
||||
|
|
@ -554,7 +572,7 @@ NX DMA_WRITE [0 ] 0
|
|||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
NO PUT [849 ] 849
|
||||
NO PUT [852 ] 852
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
|
@ -573,8 +591,8 @@ O Pf_Replacement [0 ] 0
|
|||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
|
||||
E GETX [766 ] 766
|
||||
E GETS [90 ] 90
|
||||
E GETX [767 ] 767
|
||||
E GETS [92 ] 92
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
|
|
@ -611,9 +629,9 @@ NO_R All_acks_and_data_no_sharers [0 ] 0
|
|||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
NO_B PUT [60 ] 60
|
||||
NO_B PUT [55 ] 55
|
||||
NO_B UnblockS [0 ] 0
|
||||
NO_B UnblockM [853 ] 853
|
||||
NO_B UnblockM [856 ] 856
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
|
|
@ -624,6 +642,8 @@ NO_B_X PUT [0 ] 0
|
|||
NO_B_X UnblockS [0 ] 0
|
||||
NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
|
|
@ -647,6 +667,7 @@ O_B GETX [0 ] 0
|
|||
O_B GETS [0 ] 0
|
||||
O_B PUT [0 ] 0
|
||||
O_B UnblockS [0 ] 0
|
||||
O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
|
|
@ -659,7 +680,7 @@ NO_B_W UnblockM [0 ] 0
|
|||
NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [854 ] 854
|
||||
NO_B_W Memory_Data [859 ] 859
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
|
|
@ -769,14 +790,14 @@ O_DR_B Shared_Ack [0 ] 0
|
|||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
|
||||
WB GETX [2 ] 2
|
||||
WB GETS [1 ] 1
|
||||
WB GETX [0 ] 0
|
||||
WB GETS [0 ] 0
|
||||
WB PUT [0 ] 0
|
||||
WB Unblock [0 ] 0
|
||||
WB Writeback_Clean [0 ] 0
|
||||
WB Writeback_Dirty [0 ] 0
|
||||
WB Writeback_Exclusive_Clean [86 ] 86
|
||||
WB Writeback_Exclusive_Dirty [760 ] 760
|
||||
WB Writeback_Exclusive_Clean [85 ] 85
|
||||
WB Writeback_Exclusive_Dirty [767 ] 767
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
|
|
@ -789,8 +810,8 @@ WB_O_W DMA_READ [0 ] 0
|
|||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
|
||||
WB_E_W GETX [2 ] 2
|
||||
WB_E_W GETS [0 ] 0
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [1 ] 1
|
||||
WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 5 2010 14:43:33
|
||||
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
|
||||
M5 started Aug 5 2010 14:46:32
|
||||
M5 executing on svvint09
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 213851 because Ruby Tester completed
|
||||
Exiting @ tick 210961 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 209796 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
host_tick_rate 485996 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 212552 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 1803209 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000214 # Number of seconds simulated
|
||||
sim_ticks 213851 # Number of ticks simulated
|
||||
sim_seconds 0.000211 # Number of seconds simulated
|
||||
sim_ticks 210961 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue