Regressions: Update regressions for SIMD opclass changes
This commit is contained in:
Ali Saidi
parent
0058927190
commit
371110fb0a
58 changed files with 3945 additions and 559 deletions
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@ -136,8 +136,8 @@ size=64
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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@ -231,29 +231,137 @@ opLat=1
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList
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count=0
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opList=system.cpu.fuPool.FUList5.opList
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children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
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count=4
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opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
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[system.cpu.fuPool.FUList5.opList]
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[system.cpu.fuPool.FUList5.opList00]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opClass=SimdAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList01]
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type=OpDesc
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issueLat=1
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opClass=SimdAddAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList02]
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type=OpDesc
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issueLat=1
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opClass=SimdAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList03]
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type=OpDesc
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issueLat=1
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opClass=SimdCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList04]
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type=OpDesc
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issueLat=1
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opClass=SimdCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList05]
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type=OpDesc
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issueLat=1
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opClass=SimdMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList06]
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type=OpDesc
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issueLat=1
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opClass=SimdMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList07]
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type=OpDesc
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issueLat=1
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opClass=SimdMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList08]
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type=OpDesc
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issueLat=1
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opClass=SimdShift
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opLat=1
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[system.cpu.fuPool.FUList5.opList09]
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type=OpDesc
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issueLat=1
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opClass=SimdShiftAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList10]
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type=OpDesc
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issueLat=1
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opClass=SimdSqrt
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opLat=1
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[system.cpu.fuPool.FUList5.opList11]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList12]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList13]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList14]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList15]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatDiv
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opLat=1
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[system.cpu.fuPool.FUList5.opList16]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList17]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList18]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList19]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatSqrt
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opLat=1
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[system.cpu.fuPool.FUList6]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
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children=opList
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count=0
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opList=system.cpu.fuPool.FUList6.opList
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[system.cpu.fuPool.FUList6.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList6.opList1]
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[system.cpu.fuPool.FUList6.opList]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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@ -261,11 +369,29 @@ opLat=1
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[system.cpu.fuPool.FUList7]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
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[system.cpu.fuPool.FUList7.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList7.opList1]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList8]
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type=FUDesc
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children=opList
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count=1
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opList=system.cpu.fuPool.FUList7.opList
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opList=system.cpu.fuPool.FUList8.opList
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[system.cpu.fuPool.FUList7.opList]
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[system.cpu.fuPool.FUList8.opList]
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type=OpDesc
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issueLat=3
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opClass=IprAccess
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@ -358,7 +484,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -1,5 +1,11 @@
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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warn: Prefetch instrutions is Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: Prefetch instrutions is Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: Prefetch instrutions is Alpha do not do anything
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For more information see: http://www.m5sim.org/warn/3e0eccba
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warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
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For more information see: http://www.m5sim.org/warn/5c5b547f
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hack: be nice to actually delete the event here
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@ -1,5 +1,3 @@
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Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout
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Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr
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M5 Simulator System
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Copyright (c) 2001-2008
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@ -7,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Nov 2 2010 21:30:55
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M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
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M5 started Nov 2 2010 22:21:55
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M5 executing on aus-bc2-b15
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M5 compiled Nov 15 2010 08:52:32
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M5 revision f440cdaf1c2d+ 7743+ default tip
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M5 started Nov 15 2010 08:53:40
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M5 executing on zizzer
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -1,9 +1,9 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 299092 # Simulator instruction rate (inst/s)
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host_mem_usage 240504 # Number of bytes of host memory used
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host_seconds 1890.90 # Real time elapsed on the host
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host_tick_rate 86086026 # Simulator tick rate (ticks/s)
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host_inst_rate 195051 # Simulator instruction rate (inst/s)
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host_mem_usage 206584 # Number of bytes of host memory used
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host_seconds 2899.51 # Real time elapsed on the host
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host_tick_rate 56140502 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.162780 # Number of seconds simulated
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@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.62% # Ty
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system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 73.42% # at
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system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 73.42% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::MemRead 1541723 21.73% 95.15% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::MemWrite 344447 4.85% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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@ -136,8 +136,8 @@ size=64
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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@ -231,29 +231,137 @@ opLat=1
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList
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count=0
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opList=system.cpu.fuPool.FUList5.opList
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children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
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count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -353,7 +479,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:05:23
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
M5 compiled Nov 15 2010 00:04:22
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 00:10:23
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 119996 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230000 # Number of bytes of host memory used
|
||||
host_seconds 11713.80 # Real time elapsed on the host
|
||||
host_tick_rate 51345807 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 179682 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208000 # Number of bytes of host memory used
|
||||
host_seconds 7822.74 # Real time elapsed on the host
|
||||
host_tick_rate 76885423 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1405604152 # Number of instructions simulated
|
||||
sim_seconds 0.601455 # Number of seconds simulated
|
||||
|
|
@ -270,6 +270,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 423845666 28.60% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170779885 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -287,6 +307,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2529934 77.96% 89.96% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 325689 10.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -8,12 +8,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/chips/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/chips/pd/randd/dist/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -163,8 +163,8 @@ size=64
|
|||
|
||||
[system.cpu0.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
|
||||
|
||||
[system.cpu0.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -258,29 +258,137 @@ opLat=1
|
|||
|
||||
[system.cpu0.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu0.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList]
|
||||
[system.cpu0.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu0.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList1]
|
||||
[system.cpu0.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -288,11 +396,29 @@ opLat=1
|
|||
|
||||
[system.cpu0.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu0.fuPool.FUList7.opList
|
||||
opList=system.cpu0.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList]
|
||||
[system.cpu0.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -468,8 +594,8 @@ size=64
|
|||
|
||||
[system.cpu1.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
|
||||
|
||||
[system.cpu1.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -563,29 +689,137 @@ opLat=1
|
|||
|
||||
[system.cpu1.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu1.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList]
|
||||
[system.cpu1.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu1.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu1.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList6.opList1]
|
||||
[system.cpu1.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -593,11 +827,29 @@ opLat=1
|
|||
|
||||
[system.cpu1.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu1.fuPool.FUList7.opList
|
||||
opList=system.cpu1.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList]
|
||||
[system.cpu1.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -661,7 +913,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -681,7 +933,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -807,7 +1059,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -1278,7 +1530,9 @@ SubsystemID=0
|
|||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
|
|
|
|||
|
|
@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
|
|||
For more information see: http://www.m5sim.org/warn/8742226b
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
|
||||
Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 23:00:12
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 23:04:53
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 14 2010 23:49:18
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 14 2010 23:51:27
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 118370500
|
||||
Exiting @ tick 1900844230500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 199216 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 328188 # Number of bytes of host memory used
|
||||
host_seconds 286.07 # Real time elapsed on the host
|
||||
host_tick_rate 6644616468 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 136464 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 294032 # Number of bytes of host memory used
|
||||
host_seconds 417.62 # Real time elapsed on the host
|
||||
host_tick_rate 4551611662 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 56990237 # Number of instructions simulated
|
||||
sim_seconds 1.900844 # Number of seconds simulated
|
||||
|
|
@ -390,6 +390,26 @@ system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.65% # Ty
|
|||
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::MemRead 9004352 17.71% 87.36% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645593 11.11% 98.47% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779196 1.53% 100.00% # Type of FU issued
|
||||
|
|
@ -407,6 +427,26 @@ system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.87% # at
|
|||
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.87% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::MemRead 225058 59.23% 70.10% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::MemWrite 113599 29.90% 100.00% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -943,6 +983,26 @@ system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Ty
|
|||
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.02% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282654 20.88% 83.90% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452686 13.29% 97.18% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307870 2.82% 100.00% # Type of FU issued
|
||||
|
|
@ -960,6 +1020,26 @@ system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.58% # at
|
|||
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.58% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::MemRead 93965 59.61% 62.20% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::MemWrite 59585 37.80% 100.00% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -8,12 +8,12 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/chips/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
pal=/chips/pd/randd/dist/binaries/ts_osfpal
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -163,8 +163,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -258,29 +258,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -288,11 +396,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -356,7 +482,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -376,7 +502,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -502,7 +628,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/chips/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -973,7 +1099,9 @@ SubsystemID=0
|
|||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
disks=system.disk0 system.disk2
|
||||
io_shift=0
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
|
|
|
|||
|
|
@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
|
|||
For more information see: http://www.m5sim.org/warn/8742226b
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simout
|
||||
Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 23:00:12
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 23:00:25
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 14 2010 23:49:18
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 14 2010 23:49:28
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1866702027500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 198948 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 325560 # Number of bytes of host memory used
|
||||
host_seconds 266.67 # Real time elapsed on the host
|
||||
host_tick_rate 7000163701 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 136365 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 291304 # Number of bytes of host memory used
|
||||
host_seconds 389.05 # Real time elapsed on the host
|
||||
host_tick_rate 4798136047 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 53052455 # Number of instructions simulated
|
||||
sim_seconds 1.866702 # Number of seconds simulated
|
||||
|
|
@ -388,6 +388,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 10431492 18.09% 86.80% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659819 11.55% 98.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 952981 1.65% 100.00% # Type of FU issued
|
||||
|
|
@ -405,6 +425,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.87% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 268470 61.45% 73.32% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 116580 26.68% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
opening camera file chair.camera
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 21:32:27
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:44:21
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 228388 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 246968 # Number of bytes of host memory used
|
||||
host_seconds 1644.46 # Real time elapsed on the host
|
||||
host_tick_rate 82900633 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 158570 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213052 # Number of bytes of host memory used
|
||||
host_seconds 2368.51 # Real time elapsed on the host
|
||||
host_tick_rate 57558166 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.136327 # Number of seconds simulated
|
||||
|
|
@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2961066 0.69% 51.88% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16836878 3.91% 55.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569908 0.36% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.16% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 106389727 24.72% 80.88% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82310612 19.12% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 6690 0.08% 0.91% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 1184776 13.73% 14.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 981942 11.38% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 26.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 5222594 60.52% 86.53% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1162294 13.47% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: ignoring syscall sigprocmask(0, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 21:48:16
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 08:53:40
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 223208 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 247308 # Number of bytes of host memory used
|
||||
host_seconds 8167.46 # Real time elapsed on the host
|
||||
host_tick_rate 85688066 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 221847 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213388 # Number of bytes of host memory used
|
||||
host_seconds 8217.59 # Real time elapsed on the host
|
||||
host_tick_rate 85165348 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1823043370 # Number of instructions simulated
|
||||
sim_seconds 0.699854 # Number of seconds simulated
|
||||
|
|
@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.79% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 554531536 26.62% 86.41% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 283128420 13.59% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.01% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 27783755 75.15% 75.16% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 9183701 24.84% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 22:35:53
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 245514 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 249732 # Number of bytes of host memory used
|
||||
host_seconds 324.18 # Real time elapsed on the host
|
||||
host_tick_rate 83167459 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 163173 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215808 # Number of bytes of host memory used
|
||||
host_seconds 487.78 # Real time elapsed on the host
|
||||
host_tick_rate 55274619 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.026962 # Number of seconds simulated
|
||||
|
|
@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122228 0.14% 56.85% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.85% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38521 0.05% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 21679241 25.37% 82.27% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 15152888 17.73% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.00% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 404792 44.70% 55.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 401115 44.30% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 22:41:19
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 08:53:40
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 217413 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 240500 # Number of bytes of host memory used
|
||||
host_seconds 7985.01 # Real time elapsed on the host
|
||||
host_tick_rate 90668752 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 144806 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206568 # Number of bytes of host memory used
|
||||
host_seconds 11988.72 # Real time elapsed on the host
|
||||
host_tick_rate 60389347 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.723991 # Number of seconds simulated
|
||||
|
|
@ -289,6 +289,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 139 0.00% 66.09% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 15 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 577672336 25.06% 91.15% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 204064018 8.85% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -306,6 +326,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.07% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 23.07% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 8405753 63.02% 86.09% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 1855692 13.91% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 22:27:52
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 191238 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 244496 # Number of bytes of host memory used
|
||||
host_seconds 440.18 # Real time elapsed on the host
|
||||
host_tick_rate 92306061 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 130193 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210712 # Number of bytes of host memory used
|
||||
host_seconds 646.58 # Real time elapsed on the host
|
||||
host_tick_rate 62840883 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040632 # Number of seconds simulated
|
||||
|
|
@ -281,6 +281,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2389553 2.30% 67.65% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305056 0.29% 67.95% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755116 0.73% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 25265594 24.29% 92.96% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7319262 7.04% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -298,6 +318,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 1979 0.10% 13.66% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 2355 0.12% 13.78% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 826053 42.33% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 56.11% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 733480 37.59% 93.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 122981 6.30% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -358,7 +484,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 2 2010 21:30:55
|
||||
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
|
||||
M5 started Nov 2 2010 22:53:27
|
||||
M5 executing on aus-bc2-b15
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 44712 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204968 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 86758837 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 34451 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203748 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_tick_rate 66857161 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6386 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
|
|
@ -279,6 +279,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -296,6 +316,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Prefetch instrutions is Alpha do not do anything
|
||||
For more information see: http://www.m5sim.org/warn/3e0eccba
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 11:52:05
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 101462 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 236800 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 307213198 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 60581 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202656 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 184013511 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
|
|
@ -279,6 +279,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 71.19% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -296,6 +316,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -190,8 +190,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -285,29 +285,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -315,11 +423,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:29:28
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
|
||||
M5 compiled Nov 14 2010 23:58:18
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 14 2010 23:58:34
|
||||
M5 executing on zizzer
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 25375 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223596 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 62666353 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 72923 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204488 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 179666090 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5169 # Number of instructions simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
|
|
@ -272,6 +272,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -289,6 +309,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -137,8 +137,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -232,29 +232,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -262,11 +370,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero.
|
||||
warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero.
|
||||
For more information see: http://www.m5sim.org/warn/3a2134f6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout
|
||||
Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 12:59:22
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:59:25
|
||||
M5 compiled Nov 15 2010 00:01:15
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 00:01:17
|
||||
M5 executing on zizzer
|
||||
command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
|
||||
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 8561 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202624 # Number of bytes of host memory used
|
||||
host_seconds 0.68 # Real time elapsed on the host
|
||||
host_tick_rate 17311106 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 15746 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202164 # Number of bytes of host memory used
|
||||
host_seconds 0.37 # Real time elapsed on the host
|
||||
host_tick_rate 31829526 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5800 # Number of instructions simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
|
|
@ -272,6 +272,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -289,6 +309,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 7.19% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 11:51:59
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:11:50
|
||||
M5 compiled Nov 15 2010 08:52:32
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 13:43:59
|
||||
M5 executing on zizzer
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 53800 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205552 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 59488297 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 115372 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204236 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 127463354 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 12773 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
|
|
@ -436,6 +436,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.11% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2121 21.37% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1143 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -451,6 +471,26 @@ system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.67% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdAdd 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdAddAcc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdAlu 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdCmp 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdCvt 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdMisc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdMult 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdMultAcc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdShift 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdSqrt 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMult 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::MemRead 2103 21.07% 88.75% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::MemWrite 1123 11.25% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -466,6 +506,26 @@ system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.39% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdAdd 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdAddAcc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdAlu 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdCmp 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdCvt 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdMisc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdMult 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdMultAcc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdShift 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdShiftAcc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdSqrt 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatAdd 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatAlu 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatCmp 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatCvt 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatDiv 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatMisc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatMult 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatMultAcc 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::SimdFloatSqrt 0 0.00% 67.39% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::MemRead 4224 21.22% 88.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::MemWrite 2266 11.39% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -487,6 +547,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.70% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 89 53.94% 63.64% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 60 36.36% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList]
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
[system.cpu.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList]
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:00:21
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
|
||||
M5 compiled Nov 15 2010 00:04:22
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 00:04:25
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Begining test of difficult SPARC instructions...
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 29064 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225548 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 37472433 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 33758 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203840 # Number of bytes of host memory used
|
||||
host_seconds 0.43 # Real time elapsed on the host
|
||||
host_tick_rate 43520237 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
|
|
@ -262,6 +262,26 @@ system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 74.52% # Ty
|
|||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2869 16.04% 90.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1689 9.44% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -279,6 +299,26 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 29.55% # at
|
|||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 21 23.86% 53.41% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 41 46.59% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
|
|
@ -136,8 +136,8 @@ size=64
|
|||
|
||||
[system.cpu0.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
|
||||
|
||||
[system.cpu0.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -231,29 +231,137 @@ opLat=1
|
|||
|
||||
[system.cpu0.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu0.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList]
|
||||
[system.cpu0.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu0.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList6.opList1]
|
||||
[system.cpu0.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -261,11 +369,29 @@ opLat=1
|
|||
|
||||
[system.cpu0.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu0.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu0.fuPool.FUList7.opList
|
||||
opList=system.cpu0.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu0.fuPool.FUList7.opList]
|
||||
[system.cpu0.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -455,8 +581,8 @@ size=64
|
|||
|
||||
[system.cpu1.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
|
||||
|
||||
[system.cpu1.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -550,29 +676,137 @@ opLat=1
|
|||
|
||||
[system.cpu1.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu1.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList]
|
||||
[system.cpu1.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu1.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu1.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList6.opList1]
|
||||
[system.cpu1.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -580,11 +814,29 @@ opLat=1
|
|||
|
||||
[system.cpu1.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu1.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu1.fuPool.FUList7.opList
|
||||
opList=system.cpu1.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu1.fuPool.FUList7.opList]
|
||||
[system.cpu1.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -755,8 +1007,8 @@ size=64
|
|||
|
||||
[system.cpu2.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
|
||||
|
||||
[system.cpu2.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -850,29 +1102,137 @@ opLat=1
|
|||
|
||||
[system.cpu2.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu2.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList]
|
||||
[system.cpu2.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu2.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList6.opList1]
|
||||
[system.cpu2.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -880,11 +1240,29 @@ opLat=1
|
|||
|
||||
[system.cpu2.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu2.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu2.fuPool.FUList7.opList
|
||||
opList=system.cpu2.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu2.fuPool.FUList7.opList]
|
||||
[system.cpu2.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
@ -1055,8 +1433,8 @@ size=64
|
|||
|
||||
[system.cpu3.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
|
||||
|
||||
[system.cpu3.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
|
|
@ -1150,29 +1528,137 @@ opLat=1
|
|||
|
||||
[system.cpu3.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu3.fuPool.FUList5.opList
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList]
|
||||
[system.cpu3.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
|
||||
children=opList
|
||||
count=0
|
||||
opList=system.cpu3.fuPool.FUList6.opList
|
||||
|
||||
[system.cpu3.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList6.opList1]
|
||||
[system.cpu3.fuPool.FUList6.opList]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
|
|
@ -1180,11 +1666,29 @@ opLat=1
|
|||
|
||||
[system.cpu3.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
|
||||
|
||||
[system.cpu3.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu3.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
opList=system.cpu3.fuPool.FUList7.opList
|
||||
opList=system.cpu3.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu3.fuPool.FUList7.opList]
|
||||
[system.cpu3.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:00:16
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
M5 compiled Nov 15 2010 00:04:22
|
||||
M5 revision f440cdaf1c2d+ 7743+ default tip
|
||||
M5 started Nov 15 2010 00:06:46
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Init done
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 45662 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 235748 # Number of bytes of host memory used
|
||||
host_seconds 25.27 # Real time elapsed on the host
|
||||
host_tick_rate 4652764 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 225525 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214280 # Number of bytes of host memory used
|
||||
host_seconds 5.12 # Real time elapsed on the host
|
||||
host_tick_rate 22978978 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1153797 # Number of instructions simulated
|
||||
sim_seconds 0.000118 # Number of seconds simulated
|
||||
|
|
@ -272,6 +272,26 @@ system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.97% # Ty
|
|||
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.97% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::MemRead 175866 38.63% 80.61% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88274 19.39% 100.00% # Type of FU issued
|
||||
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -289,6 +309,26 @@ system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 15.76% # at
|
|||
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::MemRead 75 40.76% 56.52% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::MemWrite 80 43.48% 100.00% # attempts to use FU when none available
|
||||
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -605,6 +645,26 @@ system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.51% # Ty
|
|||
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::MemRead 95884 36.40% 83.91% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42396 16.09% 100.00% # Type of FU issued
|
||||
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -622,6 +682,26 @@ system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.18% # at
|
|||
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.50% 33.68% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::MemWrite 128 66.32% 100.00% # attempts to use FU when none available
|
||||
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -937,6 +1017,26 @@ system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.50% # Ty
|
|||
system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.50% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::MemRead 83455 36.32% 84.81% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34899 15.19% 100.00% # Type of FU issued
|
||||
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -954,6 +1054,26 @@ system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.88% # at
|
|||
system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.67% 31.55% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::MemWrite 128 68.45% 100.00% # attempts to use FU when none available
|
||||
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -1268,6 +1388,26 @@ system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.00% # Ty
|
|||
system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::MemRead 89212 36.40% 84.40% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38247 15.60% 100.00% # Type of FU issued
|
||||
system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
|
|
@ -1285,6 +1425,26 @@ system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.21% # at
|
|||
system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::MemRead 54 28.12% 33.33% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::MemWrite 128 66.67% 100.00% # attempts to use FU when none available
|
||||
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
|
|||
Loading…
Reference in a new issue