Bus: Update the stats for the recent bus fix.
--HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
This commit is contained in:
Gabe Black
parent
ec1a4cbbc7
commit
8833b4cd44
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@ -354,6 +354,7 @@ type=Bus
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block_size=64
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bus_id=0
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clock=1000
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header_cycles=1
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responder_set=false
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width=64
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port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
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@ -383,6 +384,7 @@ type=Bus
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block_size=64
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bus_id=0
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clock=1000
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header_cycles=1
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responder_set=false
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width=64
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port=system.physmem.port[0] system.cpu.l2cache.mem_side
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@ -1,40 +1,40 @@
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 65654561 # Number of BTB hits
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global.BPredUnit.BTBLookups 73151995 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 169 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4205600 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 70082652 # Number of conditional branches predicted
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global.BPredUnit.lookups 76008681 # Number of BP lookups
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global.BPredUnit.usedRAS 1691598 # Number of times the RAS was used to get a target.
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host_inst_rate 128115 # Simulator instruction rate (inst/s)
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host_mem_usage 179076 # Number of bytes of host memory used
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host_seconds 4414.41 # Real time elapsed on the host
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host_tick_rate 36753376 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 16547976 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 11089768 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 126749521 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 43031323 # Number of stores inserted to the mem dependence unit.
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global.BPredUnit.BTBHits 65739146 # Number of BTB hits
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global.BPredUnit.BTBLookups 73253175 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4205990 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted
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global.BPredUnit.lookups 76112488 # Number of BP lookups
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global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target.
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host_inst_rate 185893 # Simulator instruction rate (inst/s)
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host_mem_usage 223968 # Number of bytes of host memory used
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host_seconds 3042.35 # Real time elapsed on the host
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host_tick_rate 54375513 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 43192001 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.162244 # Number of seconds simulated
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sim_ticks 162244431000 # Number of ticks simulated
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sim_seconds 0.165429 # Number of seconds simulated
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sim_ticks 165429421500 # Number of ticks simulated
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 20224381 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 20148945 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 314748435
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system.cpu.commit.COM:committed_per_cycle.samples 320950455
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 101194182 3215.08%
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1 100733142 3200.43%
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2 36585553 1162.37%
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3 9846995 312.85%
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4 9788938 311.01%
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5 22215967 705.83%
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6 12733844 404.57%
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7 1425433 45.29%
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8 20224381 642.56%
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0 102049912 3179.62%
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1 106118520 3306.38%
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2 36548740 1138.77%
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3 11550344 359.88%
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4 9951958 310.08%
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5 22152324 690.21%
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6 10779065 335.85%
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7 1650647 51.43%
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8 20148945 627.79%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4204974 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 4205367 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 60291190 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 61707712 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.573756 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.573756 # CPI: Total CPI of All Threads
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system.cpu.cpi 0.585019 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 111502528 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 18844.916681 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2949.400439 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 111286370 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4073479500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001939 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 216158 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 638347 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 637536500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001939 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 216158 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 37793986 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 31985.983848 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5397.978661 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37456762 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 10786441417 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.008923 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 337224 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1657335 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 1820327956 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008923 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 337224 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 1750 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 314.756278 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked
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system.cpu.dcache.ReadReq_accesses 114321557 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 26993.890628 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001892 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 216307 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001892 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 37579282 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 48790.597140 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.008975 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 337288 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008975 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 320.196392 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 500 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 7000 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 149296514 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 26852.917003 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 4441.533075 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 148743132 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 14859920917 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.003707 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 553382 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2295682 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 2457864456 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003707 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 553382 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 151900839 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 40273.937496 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.003644 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 553595 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003644 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 149296514 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 26852.917003 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 4441.533075 # average overall mshr miss latency
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system.cpu.dcache.overall_accesses 151900839 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 40273.937496 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 148743132 # number of overall hits
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system.cpu.dcache.overall_miss_latency 14859920917 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.003707 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 553382 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2295682 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 2457864456 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003707 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 553382 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 151347244 # number of overall hits
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system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.003644 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 553595 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003644 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 468726 # number of replacements
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system.cpu.dcache.sampled_refs 472822 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 468826 # number of replacements
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system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.314104 # Cycle average of tags in use
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system.cpu.dcache.total_refs 148823693 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 40784000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 334059 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 42566270 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4158683 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 688606993 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 143063088 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 123633498 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 9740149 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 1993 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5485580 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 162949466 # DTB accesses
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system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use
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system.cpu.dcache.total_refs 151427918 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 334126 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 645 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4161088 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 690019158 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 145191324 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 123829448 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 9907520 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 1984 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5507398 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 163087430 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 162906256 # DTB hits
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system.cpu.dtb.misses 43210 # DTB misses
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system.cpu.dtb.read_accesses 122197654 # DTB read accesses
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system.cpu.dtb.hits 163038163 # DTB hits
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system.cpu.dtb.misses 49267 # DTB misses
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system.cpu.dtb.read_accesses 122338189 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 122179184 # DTB read hits
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system.cpu.dtb.read_misses 18470 # DTB read misses
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system.cpu.dtb.write_accesses 40751812 # DTB write accesses
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system.cpu.dtb.read_hits 122317544 # DTB read hits
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system.cpu.dtb.read_misses 20645 # DTB read misses
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system.cpu.dtb.write_accesses 40749241 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 40727072 # DTB write hits
|
||||
system.cpu.dtb.write_misses 24740 # DTB write misses
|
||||
system.cpu.fetch.Branches 76008681 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 65896748 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 196824794 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1364007 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 697754611 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4231353 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.234241 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 65896748 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 67346159 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.150319 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 40720619 # DTB write hits
|
||||
system.cpu.dtb.write_misses 28622 # DTB write misses
|
||||
system.cpu.fetch.Branches 76112488 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 66025670 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 197184214 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1351502 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 699221634 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4235220 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230045 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 66025670 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 67431719 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.113353 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 324488585
|
||||
system.cpu.fetch.rateDist.samples 330857976
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 193560578 5965.10%
|
||||
1 10362197 319.34%
|
||||
2 15850739 488.48%
|
||||
3 14596639 449.84%
|
||||
4 12316094 379.55%
|
||||
5 14809266 456.39%
|
||||
6 6007554 185.14%
|
||||
7 3339155 102.91%
|
||||
8 53646363 1653.26%
|
||||
0 199699470 6035.81%
|
||||
1 10371896 313.48%
|
||||
2 15863038 479.45%
|
||||
3 14602598 441.36%
|
||||
4 12358229 373.52%
|
||||
5 14818818 447.89%
|
||||
6 6010699 181.67%
|
||||
7 3341156 100.98%
|
||||
8 53792072 1625.84%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 65896658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7912.777778 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 65895758 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7121500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 66025546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 10641.352550 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 900 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 4936500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 902 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 73217.508889 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 73198.053215 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 65896658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7912.777778 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 65895758 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7121500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 66025546 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 10641.352550 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 900 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 90 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 4936500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 902 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 65896658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7912.777778 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 66025546 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 10641.352550 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 65895758 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7121500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 66024644 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 900 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 90 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 4936500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 902 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,63 +229,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 33 # number of replacements
|
||||
system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 32 # number of replacements
|
||||
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 768.164023 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 65895758 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 769.239178 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 66024644 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 278 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67308634 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 42970883 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.845233 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 163887352 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41147603 # Number of stores executed
|
||||
system.cpu.idleCycles 868 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67336673 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43018581 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.810881 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 164027135 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41145337 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 489989790 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 595601295 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.806975 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 491694974 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 595952322 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.808476 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 395409527 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.835506 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 596765761 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4670315 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 16012 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 126749521 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 397523802 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.801228 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597113280 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4671395 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 85472 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 127086189 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3266921 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43031323 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 662307026 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122739749 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6453693 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 598757600 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 772 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 3259094 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43192001 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 663707703 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122881798 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6536173 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599145915 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1317 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9740149 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 3730 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9907520 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 4668 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 110 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 10032402 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 14046 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 4162 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 7269203 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 14266 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 28615 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5883 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 11700011 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3218800 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 28615 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 540218 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4130097 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.742902 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.742902 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 605211293 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 32461 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5902 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 12036679 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3379478 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 32461 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 540781 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4130614 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.709347 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.709347 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 605682088 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 438467789 72.45% # Type of FU issued
|
||||
IntMult 6519 0.00% # Type of FU issued
|
||||
IntAlu 438760030 72.44% # Type of FU issued
|
||||
IntMult 6517 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 29 0.00% # Type of FU issued
|
||||
FloatCmp 5 0.00% # Type of FU issued
|
||||
|
|
@ -293,17 +293,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 4 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 124761442 20.61% # Type of FU issued
|
||||
MemWrite 41975500 6.94% # Type of FU issued
|
||||
MemRead 124950238 20.63% # Type of FU issued
|
||||
MemWrite 41965260 6.93% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6453084 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010663 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6912738 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011413 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 5357187 83.02% # attempts to use FU when none available
|
||||
IntMult 62 0.00% # attempts to use FU when none available
|
||||
IntAlu 5342591 77.29% # attempts to use FU when none available
|
||||
IntMult 72 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 719041 11.14% # attempts to use FU when none available
|
||||
MemWrite 376794 5.84% # attempts to use FU when none available
|
||||
MemRead 924602 13.38% # attempts to use FU when none available
|
||||
MemWrite 645473 9.34% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 324488585
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 330857976
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 85242339 2626.97%
|
||||
1 67499921 2080.19%
|
||||
2 79976954 2464.71%
|
||||
3 31584556 973.36%
|
||||
4 32202311 992.40%
|
||||
5 15755227 485.54%
|
||||
6 10683294 329.23%
|
||||
7 1033211 31.84%
|
||||
8 510772 15.74%
|
||||
0 90630363 2739.25%
|
||||
1 66723730 2016.69%
|
||||
2 79382589 2399.30%
|
||||
3 36274593 1096.38%
|
||||
4 32477730 981.62%
|
||||
5 12845074 388.24%
|
||||
6 10946309 330.85%
|
||||
7 1065447 32.20%
|
||||
8 512141 15.48%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.865122 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 619336121 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605211293 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.830636 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 620689100 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605682088 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 52474081 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 8223 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 53858401 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 17774 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 28423624 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 65896787 # ITB accesses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 29864580 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 66025708 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 65896748 # ITB hits
|
||||
system.cpu.itb.misses 39 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256664 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4133.853988 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2133.853988 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1061011500 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 66025670 # ITB hits
|
||||
system.cpu.itb.misses 38 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256615 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5221.239990 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2221.239990 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1339848500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 256664 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 547683500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 256615 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 570003500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 256664 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 217058 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4373.107225 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.107225 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181264 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 156531000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.164905 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35794 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 84943000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164905 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35794 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 80561 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4159.357505 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2159.630590 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 335082000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 256615 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 217209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5324.201615 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2324.201615 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181418 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 190558500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.164777 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35791 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 83185500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164777 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35791 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 80676 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5165.743220 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2166.071694 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 416751500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 80561 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 173982000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 80676 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 174750000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 80561 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 334059 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 334059 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 80676 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 334126 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 334126 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.721530 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.724082 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 473722 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4163.136245 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2163.136245 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 181264 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1217542500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.617362 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 292458 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 473824 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5233.842671 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 181418 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1530407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.617119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 292406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 632626500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.617362 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 292458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 653189000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.617119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 292406 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 473722 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4163.136245 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2163.136245 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 473824 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5233.842671 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 181264 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1217542500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.617362 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 292458 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 181418 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1530407000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.617119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 292406 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 632626500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.617362 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 292458 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 653189000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.617119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 292406 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -418,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 85254 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100887 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 85250 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100885 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16349.255755 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 375454 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16355.319881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 375704 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63238 # number of writebacks
|
||||
system.cpu.numCycles 324488863 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 10819068 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 63237 # number of writebacks
|
||||
system.cpu.numCycles 330858844 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 11109833 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 31586159 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 150406554 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 152123 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 894972185 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 679108412 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 518438219 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 116538783 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9740149 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 36983719 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 54583330 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 312 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:IQFullEvents 34908767 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 152607206 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 316634 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 896955924 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 680550426 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 519573186 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 116670528 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9907520 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 40562533 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 55718297 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 356 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 71524705 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 79715664 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 101 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 189 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 991240 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 177788 # Number of bytes of host memory used
|
||||
host_seconds 607.18 # Real time elapsed on the host
|
||||
host_tick_rate 1262504824 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1122189 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222560 # Number of bytes of host memory used
|
||||
host_seconds 536.32 # Real time elapsed on the host
|
||||
host_tick_rate 1430957420 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_seconds 0.766562 # Number of seconds simulated
|
||||
sim_ticks 766562460000 # Number of ticks simulated
|
||||
sim_seconds 0.767457 # Number of seconds simulated
|
||||
sim_ticks 767457055000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15027.272004 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13027.272004 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16196.211338 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13196.211338 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3023968000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 3259196000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2621504000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2655500000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.984797 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.984797 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8222275000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 8880052000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7564493000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7893379000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 21214.403072 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22898.927230 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 11246243000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 12139248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10185997000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10548879000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 21214.403072 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19214.403072 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22898.927230 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 153435240 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 11246243000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 12139248000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 530123 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10185997000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10548879000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.968634 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.918042 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 342269000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 357644000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 325723 # number of writebacks
|
||||
system.cpu.dtb.accesses 153970296 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 19875000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 21465000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 18285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 19080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 19875000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 21465000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 18285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 19080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 601861103 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 19875000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 21465000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 18285000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 19080000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 673.730766 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 673.689179 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 601861898 # ITB hits
|
||||
system.cpu.itb.misses 20 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5591586000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5845749000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 765402000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 800193000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21998.527995 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22998.461086 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1643906000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1718629000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6356988000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 6645942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 167236 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6356988000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 6645942000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 288954 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 84513 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16358.690190 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 16357.683393 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63194 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1533124920 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1534914110 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||
system.cpu.num_refs 154866966 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,122 +1,122 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 185907621 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 211172077 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 181883102 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 205056000 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 84388329 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 259737867 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 259737867 # Number of BP lookups
|
||||
global.BPredUnit.condIncorrect 84375502 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 253548806 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 253548806 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 60132 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 181784 # Number of bytes of host memory used
|
||||
host_seconds 23375.38 # Real time elapsed on the host
|
||||
host_tick_rate 47481565 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 469164607 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 147914514 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 750060478 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 305538857 # Number of stores inserted to the mem dependence unit.
|
||||
host_inst_rate 116576 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 226608 # Number of bytes of host memory used
|
||||
host_seconds 12057.44 # Real time elapsed on the host
|
||||
host_tick_rate 91455071 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 445533165 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 138523488 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 741821167 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 303434180 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1405610551 # Number of instructions simulated
|
||||
sim_seconds 1.109900 # Number of seconds simulated
|
||||
sim_ticks 1109899556500 # Number of ticks simulated
|
||||
sim_insts 1405610550 # Number of instructions simulated
|
||||
sim_seconds 1.102714 # Number of seconds simulated
|
||||
sim_ticks 1102714100000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 86246390 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 8131436 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 8144258 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1976139127
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1965947566
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 1095749998 5544.90%
|
||||
1 581465878 2942.43%
|
||||
2 120709498 610.84%
|
||||
3 119935544 606.92%
|
||||
4 28050272 141.94%
|
||||
5 7339488 37.14%
|
||||
6 10411639 52.69%
|
||||
7 4345374 21.99%
|
||||
8 8131436 41.15%
|
||||
0 1089819992 5543.48%
|
||||
1 575192807 2925.78%
|
||||
2 120683737 613.87%
|
||||
3 121997081 620.55%
|
||||
4 27903521 141.93%
|
||||
5 7399306 37.64%
|
||||
6 10435277 53.08%
|
||||
7 4371587 22.24%
|
||||
8 8144258 41.43%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu.commit.COM:count 1489528974 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 402516087 # Number of loads committed
|
||||
system.cpu.commit.COM:count 1489528973 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 402516086 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 569373869 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 569373868 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 84388329 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489528974 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 84375502 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489528973 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 2243501 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1415029138 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405610551 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405610551 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.579242 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.579242 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 423053343 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15772.083502 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2729.132935 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 422816175 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3740633500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000561 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 237168 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 599122 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 647263000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000561 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 237168 # number of ReadReq MSHR misses
|
||||
system.cpu.commit.commitSquashedInsts 1379622895 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405610550 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405610550 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.569018 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.569018 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 430903803 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21506.820895 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.823732 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 430676780 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4882543000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000527 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 227023 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 610037 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 676261500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000527 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 227023 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 7087.500000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 5087.500000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 283500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 203500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 165053818 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 45542.600793 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5916.879810 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164707416 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 15776048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002099 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 346402 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1802638 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2049619000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002099 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 346402 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 165064291 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 64362.786896 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.204206 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164722312 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 22010721500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002072 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 341979 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1792165 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2651775000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002072 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 341979 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1146.620565 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1192.736607 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 588107161 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 33443.599740 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 587523591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 19516681500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000992 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 583570 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2401760 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 2696882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000992 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 583570 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 595968094 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 47263.919107 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 595399092 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 26893264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000955 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 569002 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2402202 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3328036500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000955 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 569002 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 588107161 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 33443.599740 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 4621.351337 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 595968094 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 47263.919107 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5848.901234 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 587523591 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 19516681500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000992 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 583570 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2401760 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 2696882000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000992 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 583570 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 595399092 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 26893264500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000955 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 569002 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2402202 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3328036500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000955 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 569002 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 508363 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 512459 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 495151 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 499247 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.764839 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 587596028 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 80528000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 343236 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 411423589 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3483733335 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 768911971 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 792962132 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 243659831 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2841435 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 259737867 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 358807696 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1213889868 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 12053122 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3775936768 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 90315783 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.117010 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 358807696 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 185907621 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.701026 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.tagsinuse 4095.753267 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 595470173 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 85544000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 338813 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 411958316 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3446272352 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 768408181 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 782722330 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 239479384 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2858739 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 253548806 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 356679455 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1203440686 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 10248277 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3739797008 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 90313792 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.114966 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 356679455 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 181883102 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.695724 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 2219798958
|
||||
system.cpu.fetch.rateDist.samples 2205426950
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 1364716830 6147.93%
|
||||
1 258967518 1166.63%
|
||||
2 83143428 374.55%
|
||||
3 38353275 172.78%
|
||||
4 87812104 395.59%
|
||||
5 41187584 185.55%
|
||||
6 32935987 148.37%
|
||||
7 20637545 92.97%
|
||||
8 292044687 1315.64%
|
||||
0 1358665764 6160.56%
|
||||
1 256941668 1165.04%
|
||||
2 81115553 367.80%
|
||||
3 38329197 173.79%
|
||||
4 87812032 398.16%
|
||||
5 41184299 186.74%
|
||||
6 30948569 140.33%
|
||||
7 20663338 93.69%
|
||||
8 289766530 1313.88%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 358807628 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7480.059084 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5308.714919 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 358806274 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 10128000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 356679310 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9956.762749 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6465.262380 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 356677957 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13471500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1354 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 7188000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1353 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 145 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 8747500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1354 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1353 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 264997.248154 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 263620.071693 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 358807628 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7480.059084 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 358806274 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 10128000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 356679310 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9956.762749 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 356677957 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13471500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1354 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 68 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 7188000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1353 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 145 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 8747500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1353 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 358807628 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7480.059084 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5308.714919 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 356679310 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9956.762749 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6465.262380 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 358806274 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 10128000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 356677957 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13471500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1354 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 68 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 7188000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1353 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 145 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 8747500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1353 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -222,180 +222,180 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 206 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 208 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1353 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1043.219654 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 358806274 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1040.462476 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 356677957 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 156 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 127603528 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 356521630 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.852457 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 746062439 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 207373942 # Number of stores executed
|
||||
system.cpu.idleCycles 1251 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 127605912 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 350340512 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.854314 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 751911003 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 205327510 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1493031889 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1859658958 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.962656 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1480058841 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1846013592 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.961975 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1437276141 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.837760 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1869182188 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 90142069 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 426198 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 750060478 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21374388 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 17119395 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 305538857 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2904603510 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 538688497 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 102140333 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1892283108 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 19664 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1423779046 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.837032 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1859125771 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 92169328 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 589466 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 741821167 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21373722 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 17131490 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 303434180 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2869215575 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 546583493 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 102562223 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1884127631 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 34476 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 4147 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 243659831 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 32077 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 6237 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 239479384 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 64949 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 115016780 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 46174 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 115050739 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 46193 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6167113 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 30 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 347544391 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 138681075 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6167113 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1511945 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 88630124 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.633215 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.633215 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 1994423441 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6187227 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 339305081 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 136576398 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6187227 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1512324 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 90657004 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.637341 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.637341 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 1986689854 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 1187879871 59.56% # Type of FU issued
|
||||
IntAlu 1179867838 59.39% # Type of FU issued
|
||||
IntMult 0 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2994707 0.15% # Type of FU issued
|
||||
FloatAdd 3034528 0.15% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 575372220 28.85% # Type of FU issued
|
||||
MemWrite 228176643 11.44% # Type of FU issued
|
||||
MemRead 573302529 28.86% # Type of FU issued
|
||||
MemWrite 230484959 11.60% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4059109 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002035 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3941211 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 143359 3.53% # attempts to use FU when none available
|
||||
IntAlu 143231 3.63% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 223654 5.51% # attempts to use FU when none available
|
||||
FloatAdd 224126 5.69% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
FloatCvt 0 0.00% # attempts to use FU when none available
|
||||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 3316143 81.70% # attempts to use FU when none available
|
||||
MemWrite 375953 9.26% # attempts to use FU when none available
|
||||
MemRead 3231195 81.98% # attempts to use FU when none available
|
||||
MemWrite 342659 8.69% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 2219798958
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 2205426950
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 1092127511 4919.94%
|
||||
1 592160180 2667.63%
|
||||
2 301053468 1356.22%
|
||||
3 164170369 739.57%
|
||||
4 50664484 228.24%
|
||||
5 13356785 60.17%
|
||||
6 5787626 26.07%
|
||||
7 350679 1.58%
|
||||
8 127856 0.58%
|
||||
0 1088269781 4934.51%
|
||||
1 585554812 2655.06%
|
||||
2 294018661 1333.16%
|
||||
3 167298864 758.58%
|
||||
4 47518780 215.46%
|
||||
5 16542191 75.01%
|
||||
6 5287334 23.97%
|
||||
7 801167 3.63%
|
||||
8 135360 0.61%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.898470 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2526420335 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1994423441 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21661545 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1099219582 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 637228 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19418044 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1350410508 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 275291 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4810.268044 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.268044 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1324223500 # number of ReadExReq miss cycles
|
||||
system.cpu.iq.ISSUE:rate 0.900818 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2497204504 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1986689854 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21670559 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1069656656 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 613177 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19427058 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1294993594 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 272224 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5810.711032 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2810.711032 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1581815000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 275291 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 773641500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 272224 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 765143000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 275291 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 238522 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4132.403832 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2132.403832 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 203557 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 144489500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.146590 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34965 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 74559500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146590 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34965 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 71158 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4269.526968 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2269.653447 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 303811000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 272224 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 228376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5108.225294 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.225294 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 193435 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 178486500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.152998 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34941 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73663500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.152998 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34941 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 69802 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.366465 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.524054 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 363694000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 71158 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 161504000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 69802 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154299000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 71158 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 343236 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 343236 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 69802 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 338813 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 338813 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 4.069566 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 3.927611 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 513813 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4733.874607 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 203557 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1468713000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.603831 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 310256 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 500600 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5730.801035 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 193435 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1760301500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.613594 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 307165 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 848201000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.603831 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 310256 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 838806500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.613594 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 307165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 513813 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4733.874607 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2733.874607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 500600 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5730.801035 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2730.801035 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 203557 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1468713000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.603831 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 310256 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 193435 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1760301500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.613594 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 307165 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 848201000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.603831 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 310256 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 838806500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.613594 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 307165 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -407,32 +407,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 84454 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99919 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 84439 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99904 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16408.026694 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 406627 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16410.322643 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 392384 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61955 # number of writebacks
|
||||
system.cpu.numCycles 2219799114 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14139757 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244771059 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 11 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 15246 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 833407854 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 22992244 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 4967044310 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3128619871 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2442811426 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 727931337 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 243659831 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32162189 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1198040367 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 368497990 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 22007928 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 169677376 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21764302 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 35 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.numCycles 2205428201 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14473307 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 33045 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 831088395 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 23088197 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 4934346294 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3102230072 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2427283324 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 719527974 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 239479384 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32278343 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1182512267 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 368579547 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 22008768 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 170264872 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21765105 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 5236 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -31,14 +31,14 @@ Uncompressed data compared correctly
|
|||
Tested 1MB buffer: OK!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:29
|
||||
M5 started Wed Feb 13 10:56:54 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 16:16:45 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1109899556500 because target called exit()
|
||||
Exiting @ tick 1102714100000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 679691 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179024 # Number of bytes of host memory used
|
||||
host_seconds 2191.46 # Real time elapsed on the host
|
||||
host_tick_rate 944252368 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1554729 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223840 # Number of bytes of host memory used
|
||||
host_seconds 958.05 # Real time elapsed on the host
|
||||
host_tick_rate 2160793398 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1489514761 # Number of instructions simulated
|
||||
sim_seconds 2.069290 # Number of seconds simulated
|
||||
sim_ticks 2069290262000 # Number of ticks simulated
|
||||
sim_seconds 2.070158 # Number of seconds simulated
|
||||
sim_ticks 2070157841000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15023.869951 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13023.869951 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16192.525780 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13192.525780 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 402318223 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2906593000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 3132687000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 193465 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2519663000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2552292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 193465 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 166527036 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7990150000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 8629360000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 319606 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7350938000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7670542000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 319606 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 21238.275015 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22924.794034 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 568845259 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10896743000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 11762047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 513071 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9870601000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10222834000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 513071 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 21238.275015 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19238.275015 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22924.794034 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19924.794034 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 568845259 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10896743000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 11762047000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 513071 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9870601000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10222834000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 513071 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 449114 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 453210 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.519132 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.499108 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568906446 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 358664000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 373865000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 316430 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1489519635 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24989.071038 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22989.071038 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26988.160291 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23988.160291 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1489518537 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 27438000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 29633000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 25242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 26339000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1489519635 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24989.071038 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26988.160291 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1489518537 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 27438000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 29633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 25242000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 26339000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1489519635 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24989.071038 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22989.071038 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26988.160291 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23988.160291 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1489518537 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 27438000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 29633000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1098 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 25242000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 26339000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 115 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 891.583823 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 891.563559 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1489518537 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 259745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5714390000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5974135000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 259745 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857195000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 259745 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 194563 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 160837 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 741972000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 775698000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.173342 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33726 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 370986000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173342 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33726 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 59901 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21999.265455 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232066 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1317778000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1377677000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 59901 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658911000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 454308 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 160837 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6456362000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 6749833000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.645974 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 293471 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 454308 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 160837 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6456362000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 6749833000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.645974 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 293471 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 82889 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 98333 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16360.484779 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 16360.066474 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 337247 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61877 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4138580524 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4140315682 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1489514761 # Number of instructions executed
|
||||
system.cpu.num_refs 569364430 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -31,14 +31,14 @@ Uncompressed data compared correctly
|
|||
Tested 1MB buffer: OK!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:29
|
||||
M5 started Wed Feb 13 17:45:44 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 16:16:45 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2069290262000 because target called exit()
|
||||
Exiting @ tick 2070157841000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 588725 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 293504 # Number of bytes of host memory used
|
||||
host_seconds 414.17 # Real time elapsed on the host
|
||||
host_tick_rate 875417785 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 892340 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 338704 # Number of bytes of host memory used
|
||||
host_seconds 273.25 # Real time elapsed on the host
|
||||
host_tick_rate 1330855666 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 243829010 # Number of instructions simulated
|
||||
sim_seconds 0.362567 # Number of seconds simulated
|
||||
sim_ticks 362567483000 # Number of ticks simulated
|
||||
sim_seconds 0.363652 # Number of seconds simulated
|
||||
sim_ticks 363652229000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13002.741800 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.741800 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14002.970284 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.970284 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 81326625 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11609420000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 12502468000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 892844 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9823732000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9823936000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 892844 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 200000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 216000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 184000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 192000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 22806873 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2374075000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2564001000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2184149000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2279112000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 14156.100331 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 15252.442026 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 104133498 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 13983495000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 15066469000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 987807 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 12007881000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 12103048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 987807 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 14156.100331 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12156.100331 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 15252.442026 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12252.442026 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 104133498 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 13983495000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 15066469000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 987807 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12007881000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12103048000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 987807 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 935465 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 939561 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3565.653949 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3567.172946 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 104185630 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134187537000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 134200939000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 94875 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26970.420933 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.420933 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 23707000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 20193000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 21070000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26970.420933 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 23707000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 20193000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 21070000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26970.420933 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23970.420933 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 244424462 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 23707000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 879 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 20193000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 21070000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 25 # number of replacements
|
||||
system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 716.707891 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 716.881678 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 46717 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1027774000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1074491000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46717 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513887000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46717 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 893723 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 892642 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 23782000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 24863000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1081 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11891000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1081 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 48254 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1061588000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1109842000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 48254 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530794000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 940440 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 892642 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1051556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1099354000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050825 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47798 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 940440 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 892642 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1051556000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1099354000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050825 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47798 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 877 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15560 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 8927.933046 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 8941.212243 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 802349 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 41 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 725134966 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 727304458 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 243829010 # Number of instructions executed
|
||||
system.cpu.num_refs 105710359 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -16,14 +16,14 @@ checksum : 68389
|
|||
optimal
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:29
|
||||
M5 started Wed Feb 13 18:26:14 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 16:16:46 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 362567483000 because target called exit()
|
||||
Exiting @ tick 363652229000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,113 +1,113 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 36236154 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 45185962 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1073 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 5716683 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 34971489 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 61628084 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 12361715 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 99282 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157844 # Number of bytes of host memory used
|
||||
host_seconds 3782.92 # Real time elapsed on the host
|
||||
host_tick_rate 35167352 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 72386416 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 49504127 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 123653839 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 91343872 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 37055347 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 45947414 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1096 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 5691744 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 62480259 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 155119 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205336 # Number of bytes of host memory used
|
||||
host_seconds 2421.21 # Real time elapsed on the host
|
||||
host_tick_rate 55712012 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 92782205 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574833 # Number of instructions simulated
|
||||
sim_seconds 0.133035 # Number of seconds simulated
|
||||
sim_ticks 133035205000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587535 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 13438686 # number cycles where commit BW limit reached
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.134890 # Number of seconds simulated
|
||||
sim_ticks 134890208500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587532 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 13065530 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 251297305
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 254286247
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 121146881 4820.86%
|
||||
1 48729398 1939.11%
|
||||
2 18716292 744.79%
|
||||
3 21031196 836.90%
|
||||
4 10746871 427.66%
|
||||
5 8854080 352.33%
|
||||
6 5795641 230.63%
|
||||
7 2838260 112.94%
|
||||
8 13438686 534.77%
|
||||
0 123470433 4855.57%
|
||||
1 49744073 1956.22%
|
||||
2 18820215 740.12%
|
||||
3 19293865 758.75%
|
||||
4 12510791 492.00%
|
||||
5 8575068 337.22%
|
||||
6 5688152 223.69%
|
||||
7 3118120 122.62%
|
||||
8 13065530 513.81%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu.commit.COM:count 398664608 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651996 # Number of loads committed
|
||||
system.cpu.commit.COM:count 398664594 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 100651995 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 174183399 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5712494 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 5687554 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 90429807 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574833 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.708435 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.708435 # CPI: Total CPI of All Threads
|
||||
system.cpu.commit.commitSquashedInsts 96777858 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.718313 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 94590513 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 11093.306288 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5614.604462 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94589527 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 10938000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 95885180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 15194.726166 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 986 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 502 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5536000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73513283 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23569.486405 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6046.374622 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73509973 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 78015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_accesses 73513083 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32019.486405 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 7447 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 20013500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40244.103424 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40554.006943 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168103796 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 20706.005587 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168099500 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 88953000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 169398263 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 28157.937616 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4296 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 7949 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 25549500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 168103796 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 20706.005587 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5947.276536 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 169398263 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 28157.937616 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168099500 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 88953000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 169393967 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4296 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 7949 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 25549500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -123,101 +123,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 781 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3296.752220 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168099620 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169394087 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 636 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 18878594 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4321 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11282111 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 527703627 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 131753678 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 99378321 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 14771982 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12721 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1286713 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 182322311 # DTB accesses
|
||||
system.cpu.dtb.acv 11231 # DTB access violations
|
||||
system.cpu.dtb.hits 182284581 # DTB hits
|
||||
system.cpu.dtb.misses 37730 # DTB misses
|
||||
system.cpu.dtb.read_accesses 103122587 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 11230 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 103086401 # DTB read hits
|
||||
system.cpu.dtb.read_misses 36186 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 79199724 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 79198180 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1544 # DTB write misses
|
||||
system.cpu.fetch.Branches 61628084 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 63320961 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 166618115 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1484455 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 541175943 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6060115 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.231623 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 63320961 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 48597869 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.033958 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4312 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11369096 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 533723337 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 133094788 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100949486 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15490881 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12729 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1286410 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 186077432 # DTB accesses
|
||||
system.cpu.dtb.acv 11216 # DTB access violations
|
||||
system.cpu.dtb.hits 186006805 # DTB hits
|
||||
system.cpu.dtb.misses 70627 # DTB misses
|
||||
system.cpu.dtb.read_accesses 104841123 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 11216 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 104772046 # DTB read hits
|
||||
system.cpu.dtb.read_misses 69077 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 81236309 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 81234759 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1550 # DTB write misses
|
||||
system.cpu.fetch.Branches 62480259 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 64020665 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 168778939 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1468351 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 547045642 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6042059 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.231597 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 64020665 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 49453854 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.027744 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 266069288
|
||||
system.cpu.fetch.rateDist.samples 269777129
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 162772436 6117.67%
|
||||
1 10792214 405.62%
|
||||
2 11562978 434.59%
|
||||
3 6945740 261.05%
|
||||
4 14845221 557.95%
|
||||
5 9644746 362.49%
|
||||
6 6640124 249.56%
|
||||
7 3951437 148.51%
|
||||
8 38914392 1462.57%
|
||||
0 165019149 6116.87%
|
||||
1 11208105 415.46%
|
||||
2 10970042 406.63%
|
||||
3 7809028 289.46%
|
||||
4 16007682 593.37%
|
||||
5 8770390 325.10%
|
||||
6 6686429 247.85%
|
||||
7 3981315 147.58%
|
||||
8 39324989 1457.68%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 63320771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7179.953858 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4985.644706 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 63316870 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 28009000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3901 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 190 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 19449000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000062 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 64020369 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9431.835687 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3895 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3895 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16230.933094 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16435.551733 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 63320771 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7179.953858 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 63316870 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 28009000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3901 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 190 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 19449000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000062 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 64020369 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9431.835687 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3895 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3895 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 63320771 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7179.953858 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 4985.644706 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 64020369 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9431.835687 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 63316870 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 28009000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3901 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 190 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 19449000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000062 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3901 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 64016474 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3895 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3895 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1979 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1973 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3895 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1826.105929 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 63316870 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1826.958701 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 64016474 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1124 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 50342697 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27143660 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.556730 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 189044982 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 79210411 # Number of stores executed
|
||||
system.cpu.idleCycles 3290 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51062363 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27214999 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.560789 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 192842691 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 81246989 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 284353015 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 410949767 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.699040 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 287107823 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 417299912 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.702706 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 198774253 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.544515 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 411560855 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6153520 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2291780 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 123653839 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 201752289 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.546813 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 418066212 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6311133 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2198946 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 125306666 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6328938 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 91343872 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 489095367 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 109834571 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 9454650 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 414199709 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 219457 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 6339692 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92782205 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 495443138 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 111595702 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 10411801 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 421070304 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 127438 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 24015 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 14771982 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 586141 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 23538 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15490881 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 491568 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8319023 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 12177 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8710387 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3327 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 423678 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 176362 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 23001843 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 17812469 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 423678 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 800835 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5352685 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.411562 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.411562 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 423654359 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 505299 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 175942 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 24654671 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 19250803 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 505299 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 821714 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5489419 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.392150 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.392150 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 431482105 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 33581 0.01% # Type of FU issued
|
||||
IntAlu 164699955 38.88% # Type of FU issued
|
||||
IntMult 2150553 0.51% # Type of FU issued
|
||||
IntAlu 167002612 38.70% # Type of FU issued
|
||||
IntMult 2153139 0.50% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 34423933 8.13% # Type of FU issued
|
||||
FloatCmp 7590989 1.79% # Type of FU issued
|
||||
FloatCvt 2918170 0.69% # Type of FU issued
|
||||
FloatMult 16813198 3.97% # Type of FU issued
|
||||
FloatDiv 1589024 0.38% # Type of FU issued
|
||||
FloatAdd 34874757 8.08% # Type of FU issued
|
||||
FloatCmp 7889981 1.83% # Type of FU issued
|
||||
FloatCvt 2903377 0.67% # Type of FU issued
|
||||
FloatMult 16803027 3.89% # Type of FU issued
|
||||
FloatDiv 1591666 0.37% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 112375969 26.53% # Type of FU issued
|
||||
MemWrite 81058987 19.13% # Type of FU issued
|
||||
MemRead 114230521 26.47% # Type of FU issued
|
||||
MemWrite 83999444 19.47% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 9621593 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.022711 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10446664 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.024211 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 40277 0.42% # attempts to use FU when none available
|
||||
IntAlu 32363 0.31% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 97634 1.01% # attempts to use FU when none available
|
||||
FloatCmp 3955 0.04% # attempts to use FU when none available
|
||||
FloatCvt 14420 0.15% # attempts to use FU when none available
|
||||
FloatMult 1625332 16.89% # attempts to use FU when none available
|
||||
FloatDiv 750896 7.80% # attempts to use FU when none available
|
||||
FloatAdd 95689 0.92% # attempts to use FU when none available
|
||||
FloatCmp 7492 0.07% # attempts to use FU when none available
|
||||
FloatCvt 12721 0.12% # attempts to use FU when none available
|
||||
FloatMult 1683122 16.11% # attempts to use FU when none available
|
||||
FloatDiv 1408746 13.49% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 5547187 57.65% # attempts to use FU when none available
|
||||
MemWrite 1541892 16.03% # attempts to use FU when none available
|
||||
MemRead 5941492 56.87% # attempts to use FU when none available
|
||||
MemWrite 1265039 12.11% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 266069288
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 269777129
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 96503300 3627.00%
|
||||
1 57159929 2148.31%
|
||||
2 40537288 1523.56%
|
||||
3 30901170 1161.40%
|
||||
4 22699747 853.15%
|
||||
5 10809299 406.26%
|
||||
6 4873798 183.18%
|
||||
7 2049983 77.05%
|
||||
8 534774 20.10%
|
||||
0 99508340 3688.54%
|
||||
1 57898126 2146.15%
|
||||
2 39403533 1460.60%
|
||||
3 28850583 1069.42%
|
||||
4 24598298 911.80%
|
||||
5 10625217 393.85%
|
||||
6 6146486 227.84%
|
||||
7 2145397 79.52%
|
||||
8 601149 22.28%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.592264 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 461951468 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 423654359 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.599383 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 468227900 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 431482105 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 85357325 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 903613 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 91553989 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1306748 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 69252259 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 63321261 # ITB accesses
|
||||
system.cpu.itb.acv 2 # ITB acv
|
||||
system.cpu.itb.hits 63320961 # ITB hits
|
||||
system.cpu.itb.misses 300 # ITB misses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 68680838 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 64020959 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 64020665 # ITB hits
|
||||
system.cpu.itb.misses 294 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4638.497653 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2638.497653 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 14820000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 6098.591549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3098.591549 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 19485000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8430000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9900000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4341.521020 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2341.521020 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 649 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 18382000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.867090 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4234 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 9914000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867090 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4234 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5592.080378 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2592.080378 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 647 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 23654500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.867336 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4230 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10964500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867336 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4230 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4500 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2500 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 544500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5698.347107 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2698.347107 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 689500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 302500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 326500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.128626 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.128309 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4469.242159 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 649 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 33202000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.919658 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7429 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 8072 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5810.033670 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 647 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 43139500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.919846 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7425 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18344000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.919658 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7429 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 20864500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.919846 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7425 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8078 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4469.242159 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2469.242159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 8072 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5810.033670 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 649 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 33202000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.919658 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7429 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 647 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 43139500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.919846 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7425 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18344000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.919658 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7429 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 20864500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.919846 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7425 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -419,30 +419,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4688 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4684 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3886.512098 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 603 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3884.477480 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 601 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 266070412 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 9037497 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1658142 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 136681474 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7036650 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 676869332 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 514036809 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 332594976 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 95406326 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 14771982 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 9818184 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 73062625 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 353825 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37914 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 21299684 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 252 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 417 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.numCycles 269780419 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 8898218 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1493929 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 138057394 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7378387 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 685335905 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 519882318 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 336260549 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96875532 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15490881 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10098203 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 76728208 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 356901 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37939 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 22218757 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 727 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
Eon, Version 1.1
|
||||
OO-style eon Time= 0.116667
|
||||
OO-style eon Time= 0.133333
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 850841 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157124 # Number of bytes of host memory used
|
||||
host_seconds 468.55 # Real time elapsed on the host
|
||||
host_tick_rate 1210368735 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 948947 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204452 # Number of bytes of host memory used
|
||||
host_seconds 420.11 # Real time elapsed on the host
|
||||
host_tick_rate 1349967290 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_seconds 0.567123 # Number of seconds simulated
|
||||
sim_ticks 567123353000 # Number of ticks simulated
|
||||
sim_seconds 0.567139 # Number of seconds simulated
|
||||
sim_ticks 567138642000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 23522.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21522.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 22346000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 24129000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 20446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 21279000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 82850000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 89478000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 76222000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 79536000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 24670.731707 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 26643.292683 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 105196000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 113607000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 96668000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 100815000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 24670.731707 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22670.731707 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 26643.292683 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168270956 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 105196000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 113607000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4264 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 96668000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 100815000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3289.454246 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3289.418113 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 625 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 73520730 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 23471.004628 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21471.004628 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25343.588347 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 86209000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 93087000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 78863000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 82068000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 23471.004628 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 25343.588347 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 86209000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 93087000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 78863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 82068000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 23471.004628 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21471.004628 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 25343.588347 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 398660993 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 86209000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 93087000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3673 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 78863000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 82068000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1795.369921 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1795.354000 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 398664666 # ITB hits
|
||||
system.cpu.itb.misses 173 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 70444000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 73646000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 88836000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 92874000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2464000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2576000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 159280000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 166520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 585 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 159280000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 166520000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7240 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3714.863490 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3714.818787 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1134246706 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134277284 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664609 # Number of instructions executed
|
||||
system.cpu.num_refs 174183455 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 883544 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 162840 # Number of bytes of host memory used
|
||||
host_seconds 2273.78 # Real time elapsed on the host
|
||||
host_tick_rate 1217345227 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1017888 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209744 # Number of bytes of host memory used
|
||||
host_seconds 1973.68 # Real time elapsed on the host
|
||||
host_tick_rate 1403993769 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_seconds 2.767980 # Number of seconds simulated
|
||||
sim_ticks 2767979952000 # Number of ticks simulated
|
||||
sim_seconds 2.771038 # Number of seconds simulated
|
||||
sim_ticks 2771037759000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24826.352085 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22826.352085 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 26811.881426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23811.881426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 36201588000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 39096871000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 33285204000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 34722295000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.692460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.692460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1869675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2019226000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1720101000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1794865000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 24834.823569 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 26821.043863 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 38071263000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 41116097000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 35005305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 36517160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 24834.823569 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22834.823569 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 26821.043863 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720331943 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 38071263000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 41116097000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1532979 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 35005305000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 36517160000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.361619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.350762 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 795905000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 812770000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.dtb.accesses 722298387 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15691.959230 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13691.959230 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16916.289166 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13916.289166 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 166272000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 179245000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 145080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 147457000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15691.959230 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 16916.289166 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 166272000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 179245000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 145080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 147457000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15691.959230 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13691.959230 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 16916.289166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2009410475 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 166272000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 179245000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10596 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 145080000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 147457000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1478.559454 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1478.550297 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 2009421071 # ITB hits
|
||||
system.cpu.itb.misses 105 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1582944000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1654896000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 791472000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 31668296000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 33107764000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21821.516755 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22813.403880 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 61864000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 64676000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 33251240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 34762660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 29320 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 33251240000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 34762660000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1511420 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 1473608 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31924.676313 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 31923.721558 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5535959904 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5542075518 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987605 # Number of instructions executed
|
||||
system.cpu.num_refs 722823898 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 8038204 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 14256935 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 35926 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 456185 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10553314 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 16248074 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1941559 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 107979 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 171824 # Number of bytes of host memory used
|
||||
host_seconds 737.10 # Real time elapsed on the host
|
||||
host_tick_rate 33795098 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12328057 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 11324911 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 22967030 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 16293172 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 8028209 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 16239906 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 101925 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 220292 # Number of bytes of host memory used
|
||||
host_seconds 780.89 # Real time elapsed on the host
|
||||
host_tick_rate 32150232 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.024910 # Number of seconds simulated
|
||||
sim_ticks 24910446000 # Number of ticks simulated
|
||||
sim_seconds 0.025106 # Number of seconds simulated
|
||||
sim_ticks 25105678500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 3431451 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 48556236
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 48941983
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 19632028 4043.15%
|
||||
1 11130407 2292.27%
|
||||
2 5090838 1048.44%
|
||||
3 3451952 710.92%
|
||||
4 2493473 513.52%
|
||||
5 1522245 313.50%
|
||||
6 990886 204.07%
|
||||
7 812956 167.43%
|
||||
8 3431451 706.70%
|
||||
0 20096984 4106.29%
|
||||
1 10996856 2246.92%
|
||||
2 5104227 1042.91%
|
||||
3 3459002 706.76%
|
||||
4 2556441 522.34%
|
||||
5 1507300 307.98%
|
||||
6 975853 199.39%
|
||||
7 821586 167.87%
|
||||
8 3423734 699.55%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 360457 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 8047613 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.625955 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.625955 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20358815 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14848.430668 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3932.171708 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20297292 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 913520000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003022 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 61523 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 82415 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 241919000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61523 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 13806620 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30619.646254 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5319.309194 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13656795 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4587588500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010852 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149825 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 806757 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 796965500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010852 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149825 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 20369036 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19244.510005 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.003020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 61521 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003020 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 13753160 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 50456.177120 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010893 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149819 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010893 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 165.649492 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 165.441832 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34165435 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26028.675455 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33954087 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 5501108500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006186 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 211348 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 889172 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1038884500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006186 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 211348 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 34122196 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 41370.471752 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006194 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 211340 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006194 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34165435 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26028.675455 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 4915.516116 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 34122196 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 41370.471752 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 33954087 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 5501108500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006186 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 211348 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 889172 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1038884500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006186 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 211348 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 33910856 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006194 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 211340 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006194 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 200918 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205014 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 200914 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4080.935098 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33960465 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 120644000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147759 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 965138 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 96643 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3649464 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101643368 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 27939518 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19626008 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1262570 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284543 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 25573 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 36605590 # DTB accesses
|
||||
system.cpu.dtb.acv 38 # DTB access violations
|
||||
system.cpu.dtb.hits 36432080 # DTB hits
|
||||
system.cpu.dtb.misses 173510 # DTB misses
|
||||
system.cpu.dtb.read_accesses 21546917 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 36 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21390081 # DTB read hits
|
||||
system.cpu.dtb.read_misses 156836 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15058673 # DTB write accesses
|
||||
system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33917230 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147756 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 36627367 # DTB accesses
|
||||
system.cpu.dtb.acv 39 # DTB access violations
|
||||
system.cpu.dtb.hits 36456086 # DTB hits
|
||||
system.cpu.dtb.misses 171281 # DTB misses
|
||||
system.cpu.dtb.read_accesses 21562223 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 37 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21405571 # DTB read hits
|
||||
system.cpu.dtb.read_misses 156652 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15065144 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 2 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15041999 # DTB write hits
|
||||
system.cpu.dtb.write_misses 16674 # DTB write misses
|
||||
system.cpu.fetch.Branches 16248074 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13374991 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33229665 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 154532 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103238390 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 573003 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.326130 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13374991 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9979763 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.072191 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 15050515 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14629 # DTB write misses
|
||||
system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 49818807
|
||||
system.cpu.fetch.rateDist.samples 50204254
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 29989736 6019.76%
|
||||
1 1895135 380.41%
|
||||
2 1526458 306.40%
|
||||
3 1823774 366.08%
|
||||
4 3936760 790.22%
|
||||
5 1866062 374.57%
|
||||
6 698148 140.14%
|
||||
7 1109093 222.63%
|
||||
8 6973641 1399.80%
|
||||
0 30393344 6053.94%
|
||||
1 1855009 369.49%
|
||||
2 1535971 305.94%
|
||||
3 1792342 357.01%
|
||||
4 4000264 796.80%
|
||||
5 1878750 374.22%
|
||||
6 697475 138.93%
|
||||
7 1087494 216.61%
|
||||
8 6963605 1387.05%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 13374115 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 4650.026870 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2608.921937 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13288517 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 398033000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006400 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 85598 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 876 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 223318500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006400 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85598 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 13372459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5833.169458 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 85431 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006389 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 155.243312 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 13374115 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 4650.026870 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13288517 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 398033000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006400 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 85598 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 876 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 223318500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006400 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85598 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 13372459 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5833.169458 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006389 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 85431 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006389 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 13374115 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 4650.026870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2608.921937 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 13372459 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5833.169458 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 13288517 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 398033000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006400 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 85598 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 876 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 223318500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006400 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85598 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 13287028 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006389 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 85431 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006389 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 83550 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85598 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 83382 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1922.621732 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13288517 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 21667252000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 2086 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14743916 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9378551 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.702006 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36947583 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15291466 # Number of stores executed
|
||||
system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14739955 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15298022 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 42399540 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84317145 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765160 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 32442413 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.692405 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84551587 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 401023 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 18086 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22967030 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4976 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 358113 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16293172 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 98809667 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21656117 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 536500 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84795443 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1943 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 32426009 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 166 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1262570 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2513 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 947497 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 960 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 18554 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1310 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2587631 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1448553 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 18554 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 108095 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 292928 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.597558 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.597558 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 85331943 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 47873863 56.10% # Type of FU issued
|
||||
IntMult 42967 0.05% # Type of FU issued
|
||||
IntAlu 47875288 56.09% # Type of FU issued
|
||||
IntMult 42930 0.05% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 121266 0.14% # Type of FU issued
|
||||
FloatCmp 86 0.00% # Type of FU issued
|
||||
FloatCvt 121911 0.14% # Type of FU issued
|
||||
FloatAdd 121387 0.14% # Type of FU issued
|
||||
FloatCmp 87 0.00% # Type of FU issued
|
||||
FloatCvt 121941 0.14% # Type of FU issued
|
||||
FloatMult 50 0.00% # Type of FU issued
|
||||
FloatDiv 38525 0.05% # Type of FU issued
|
||||
FloatDiv 38534 0.05% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 21762707 25.50% # Type of FU issued
|
||||
MemWrite 15370568 18.01% # Type of FU issued
|
||||
MemRead 21778158 25.51% # Type of FU issued
|
||||
MemWrite 15380330 18.02% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 973739 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011411 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 95466 9.80% # attempts to use FU when none available
|
||||
IntAlu 96046 9.70% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 447999 46.01% # attempts to use FU when none available
|
||||
MemWrite 430274 44.19% # attempts to use FU when none available
|
||||
MemRead 442273 44.69% # attempts to use FU when none available
|
||||
MemWrite 451365 45.61% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 49818807
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 14814928 2973.76%
|
||||
1 13524369 2714.71%
|
||||
2 8025078 1610.85%
|
||||
3 4803693 964.23%
|
||||
4 4680291 939.46%
|
||||
5 2123644 426.27%
|
||||
6 1156346 232.11%
|
||||
7 454785 91.29%
|
||||
8 235673 47.31%
|
||||
0 15297066 3046.97%
|
||||
1 13336776 2656.50%
|
||||
2 8168141 1626.98%
|
||||
3 4718425 939.85%
|
||||
4 4728752 941.90%
|
||||
5 2063960 411.11%
|
||||
6 1191217 237.27%
|
||||
7 451074 89.85%
|
||||
8 248843 49.57%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.712774 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89426140 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85331943 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4976 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9626821 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 45871 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 393 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6618385 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 13400594 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 13398974 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 13374991 # ITB hits
|
||||
system.cpu.itb.misses 25603 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143491 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4105.274895 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2105.274895 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 589070000 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 13373612 # ITB hits
|
||||
system.cpu.itb.misses 25362 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143491 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 302088000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143491 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 147121 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4130.611741 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2130.611741 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 102527 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 184200500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.303111 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44594 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 95012500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303111 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44594 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6346 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4217.538607 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2242.593760 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 26764500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6346 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14231500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6346 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147759 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147759 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.676534 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 290612 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4111.282133 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 102527 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 773270500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.647203 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 188085 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 397100500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.647203 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 188085 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 290612 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4111.282133 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2111.282133 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 102527 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 773270500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.647203 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 188085 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 102374 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 188067 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 397100500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.647203 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 188085 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -418,31 +418,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 148798 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 174015 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 148782 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18438.001925 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 117727 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120645 # number of writebacks
|
||||
system.cpu.numCycles 49820893 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 263970 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 120646 # number of writebacks
|
||||
system.cpu.numCycles 50211358 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 36282 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28255906 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 551452 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 121470810 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 100830627 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60670426 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19329077 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1262570 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 631100 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8123545 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 76184 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5248 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1415098 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5246 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 786 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 826490 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 170652 # Number of bytes of host memory used
|
||||
host_seconds 106.89 # Real time elapsed on the host
|
||||
host_tick_rate 1207717238 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 866615 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218536 # Number of bytes of host memory used
|
||||
host_seconds 101.94 # Real time elapsed on the host
|
||||
host_tick_rate 1271060462 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_seconds 0.129089 # Number of seconds simulated
|
||||
sim_ticks 129089084000 # Number of ticks simulated
|
||||
sim_seconds 0.129569 # Number of seconds simulated
|
||||
sim_ticks 129569130000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19821.229326 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17821.229326 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1204437000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1082907000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3744825000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3445239000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 23505.456929 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4949262000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4528146000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 23505.456929 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 21505.456929 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34679457 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4949262000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 210558 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4528146000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 200247 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4080.925680 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 736945000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.dtb.accesses 34987415 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14374.483228 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12374.483228 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1098728000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 945856000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 14374.483228 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1098728000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 945856000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 14374.483228 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 12374.483228 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88361638 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1098728000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 945856000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1876.966161 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 88438074 # ITB hits
|
||||
system.cpu.itb.misses 3934 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3158716000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 952512000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21869.026549 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 135916000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4111228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 93905 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4111228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 186874 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 147560 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18266.602159 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120634 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 258178168 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 259138260 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340673 # Number of instructions executed
|
||||
system.cpu.num_refs 35321418 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 595046 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 168184 # Number of bytes of host memory used
|
||||
host_seconds 228.79 # Real time elapsed on the host
|
||||
host_tick_rate 875480121 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 809753 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216324 # Number of bytes of host memory used
|
||||
host_seconds 168.12 # Real time elapsed on the host
|
||||
host_tick_rate 1194295397 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 136139203 # Number of instructions simulated
|
||||
sim_seconds 0.200299 # Number of seconds simulated
|
||||
sim_ticks 200299240000 # Number of ticks simulated
|
||||
sim_seconds 0.200790 # Number of seconds simulated
|
||||
sim_ticks 200790381000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20034.528231 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18034.528231 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 911551000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 820553000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2735125000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2516315000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 23541.522491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3646676000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3336868000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 23541.522491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 21541.522491 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 57940701 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3646676000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 154904 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3336868000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4089.107061 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 584692000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107271 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 13838.865600 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11838.865600 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2588200000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2214152000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 13838.865600 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2588200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2214152000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 13838.865600 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11838.865600 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 136106788 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2588200000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 187024 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2214152000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 2006.879224 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 142655430000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2313938000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 874412000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21907.172996 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 93456000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3188350000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 192777 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3188350000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 144925 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 120486 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 19343.330573 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 87413 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 400598480 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 401580762 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 136139203 # Number of instructions executed
|
||||
system.cpu.num_refs 58160249 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: ignoring syscall time(4026527848, 4026528248, ...)
|
||||
warn: ignoring syscall time(4026527400, 1375098, ...)
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:29
|
||||
M5 started Wed Feb 13 18:35:08 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 16:16:46 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 200299240000 because target called exit()
|
||||
Exiting @ tick 200790381000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 295818465 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 304122978 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 19402485 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 254075805 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 329612468 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 23323532 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 97496 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 329184 # Number of bytes of host memory used
|
||||
host_seconds 17806.38 # Real time elapsed on the host
|
||||
host_tick_rate 36626304 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 70242096 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 35756687 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 594298118 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 221596838 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 298925307 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 307254403 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 123 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 19461333 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 256954278 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 332748805 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 23332154 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 185907 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 374916 # Number of bytes of host memory used
|
||||
host_seconds 9338.25 # Real time elapsed on the host
|
||||
host_tick_rate 70823738 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 73213571 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 37308198 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 599919223 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 223513381 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.652182 # Number of seconds simulated
|
||||
sim_ticks 652181935500 # Number of ticks simulated
|
||||
sim_seconds 0.661370 # Number of seconds simulated
|
||||
sim_ticks 661369625500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 63182611 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 64339411 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1232005757
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1246869641
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 589160016 4782.12%
|
||||
1 261470532 2122.32%
|
||||
2 125479748 1018.50%
|
||||
3 79571868 645.87%
|
||||
4 48773289 395.89%
|
||||
5 29278259 237.65%
|
||||
6 23936883 194.29%
|
||||
7 11152551 90.52%
|
||||
8 63182611 512.84%
|
||||
0 606206692 4861.83%
|
||||
1 260350579 2088.03%
|
||||
2 123843780 993.24%
|
||||
3 79587483 638.30%
|
||||
4 49145226 394.15%
|
||||
5 29422011 235.97%
|
||||
6 23247922 186.45%
|
||||
7 10726537 86.03%
|
||||
8 64339411 516.01%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,80 +43,80 @@ system.cpu.commit.COM:loads 445666361 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 19401982 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 19460831 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 475043649 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 498311436 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.751343 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.751343 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.761927 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.761927 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 7500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 5500 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 6500 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 7500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 9500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 5500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 6500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 511397910 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5961.540286 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3155.891925 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 504123428 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 43367117500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.014225 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7274482 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1270693 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22957479000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014225 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7274482 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 158841743 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 13698.127588 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7375.596927 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 156593123 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 30801883656 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.014156 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2248620 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1886759 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16584914763 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.014156 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2248620 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 1503.843690 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 1667.900476 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 72.176220 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 32186 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 65110 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 48402713 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 108597000 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_accesses 513272040 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 8025.908244 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3665.501336 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 505997425 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 58385392500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.014173 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7274615 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1427526 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 26665111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014173 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7274615 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 158750545 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 19340.801620 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 156501908 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 43490442133 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.014165 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2248637 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1977957 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 22750942389 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.014165 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2248637 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2040.681665 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 2667.920935 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 72.369821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 71409 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 65111 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 145723037 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 173711000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 670239653 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7788.323716 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 4152.259816 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 660716551 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 74169001156 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.014209 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9523102 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 3157452 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 39542393763 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014209 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9523102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 672022585 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 10697.588873 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 662499333 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 101875834633 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.014171 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9523252 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 3405483 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 49416053389 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014171 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9523252 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 670239653 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7788.323716 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 4152.259816 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 672022585 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 10697.588873 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 660716551 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 74169001156 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.014209 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9523102 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 3157452 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 39542393763 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014209 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9523102 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 662499333 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 101875834633 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.014171 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9523252 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 3405483 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 49416053389 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014171 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9523252 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -128,104 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 9155159 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9159255 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9155291 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9159387 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4084.262567 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 661080401 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 6949510000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245532 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 20296019 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 568 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 51416617 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2683518542 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 684337640 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 525337430 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 72357917 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1672 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2034669 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 758199856 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4084.377148 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 662863201 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 6956358000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245548 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 25695554 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 564 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 51842469 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2704061258 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 689853878 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 528999718 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 75857193 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1673 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2320492 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 762597100 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 743488243 # DTB hits
|
||||
system.cpu.dtb.misses 14711613 # DTB misses
|
||||
system.cpu.dtb.read_accesses 558546548 # DTB read accesses
|
||||
system.cpu.dtb.hits 747387018 # DTB hits
|
||||
system.cpu.dtb.misses 15210082 # DTB misses
|
||||
system.cpu.dtb.read_accesses 561654782 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 549772416 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8774132 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 199653308 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 552717840 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8936942 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 200942318 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 193715827 # DTB write hits
|
||||
system.cpu.dtb.write_misses 5937481 # DTB write misses
|
||||
system.cpu.fetch.Branches 329612468 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 338613941 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 876004177 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8904316 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2731617625 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 26354316 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.252700 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 338613941 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 319141997 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.094214 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 194669178 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6273140 # DTB write misses
|
||||
system.cpu.fetch.Branches 332748805 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 340572268 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 882406365 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8482299 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2756699547 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 26531665 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.251560 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 340572268 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 322257461 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.084084 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 1304363675
|
||||
system.cpu.fetch.rateDist.samples 1322726835
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 766973475 5880.06%
|
||||
1 46084102 353.31%
|
||||
2 31888422 244.47%
|
||||
3 48880451 374.75%
|
||||
4 119066916 912.84%
|
||||
5 67245019 515.54%
|
||||
6 45549495 349.21%
|
||||
7 40080763 307.28%
|
||||
8 138595032 1062.55%
|
||||
0 780892776 5903.66%
|
||||
1 46232823 349.53%
|
||||
2 32110220 242.76%
|
||||
3 49083369 371.08%
|
||||
4 120415668 910.36%
|
||||
5 67469038 510.08%
|
||||
6 46013556 347.87%
|
||||
7 40168101 303.68%
|
||||
8 140341284 1061.00%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 338613861 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7795.580110 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5439.226519 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 338612956 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7055000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 340572130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 10589.900111 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6758.046615 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 340571229 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 9541500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 905 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 4922500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 138 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 905 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 374157.962431 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 377992.485017 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 338613861 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7795.580110 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5439.226519 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 338612956 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7055000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 340572130 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 10589.900111 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 340571229 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 9541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 905 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 4922500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 901 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 138 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 905 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 338613861 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7795.580110 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5439.226519 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 340572130 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 10589.900111 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 338612956 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7055000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 340571229 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 9541500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 905 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 80 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 4922500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 901 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 138 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 905 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -238,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 905 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 710.790129 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 338612956 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 708.208043 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 340571229 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 197 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 270601627 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 122950690 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.695694 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 759488153 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 199866169 # Number of stores executed
|
||||
system.cpu.idleCycles 12417 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 272957078 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 123939642 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.684042 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 763895221 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 201165010 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1476471660 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2173120671 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.814447 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1488939134 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2188676291 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.814314 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1202508134 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.666039 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2193819887 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21036346 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 890955 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 594298118 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 23367194 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 221596838 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2498495898 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 559621984 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 40950985 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2211801428 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 13541 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1212463676 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.654654 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2210006196 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21034553 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2251453 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 599919223 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 23371349 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 223513381 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2521543989 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 562730211 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 40765112 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2227547936 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 36991 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 2831 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 72357917 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 97673 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 5661 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 75857193 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 176880 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 127122 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 37060344 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 338095 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 196633 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 37920789 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 331554 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 366768 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 439987 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 148631757 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 60691856 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 366768 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 707965 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 20328381 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.330951 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.330951 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 2252752413 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 154252862 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 62608399 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 439987 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 706308 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 20328245 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.312461 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.312461 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 2268313048 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 1478789273 65.64% # Type of FU issued
|
||||
IntMult 88 0.00% # Type of FU issued
|
||||
IntAlu 1489479679 65.66% # Type of FU issued
|
||||
IntMult 80 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 219 0.00% # Type of FU issued
|
||||
FloatCmp 15 0.00% # Type of FU issued
|
||||
FloatCvt 142 0.00% # Type of FU issued
|
||||
FloatAdd 221 0.00% # Type of FU issued
|
||||
FloatCmp 17 0.00% # Type of FU issued
|
||||
FloatCvt 143 0.00% # Type of FU issued
|
||||
FloatMult 14 0.00% # Type of FU issued
|
||||
FloatDiv 24 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 570630847 25.33% # Type of FU issued
|
||||
MemWrite 203331791 9.03% # Type of FU issued
|
||||
MemRead 574434192 25.32% # Type of FU issued
|
||||
MemWrite 204398678 9.01% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 16520505 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.007333 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 16429831 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.007243 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 2435019 14.74% # attempts to use FU when none available
|
||||
IntAlu 2410991 14.67% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -319,102 +319,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 10615930 64.26% # attempts to use FU when none available
|
||||
MemWrite 3469556 21.00% # attempts to use FU when none available
|
||||
MemRead 10617024 64.62% # attempts to use FU when none available
|
||||
MemWrite 3401816 20.71% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 1304363675
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 1322726835
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 462770877 3547.87%
|
||||
1 244714532 1876.12%
|
||||
2 220402920 1689.74%
|
||||
3 136161657 1043.89%
|
||||
4 111417032 854.19%
|
||||
5 74141239 568.41%
|
||||
6 43153628 330.84%
|
||||
7 9363341 71.78%
|
||||
8 2238449 17.16%
|
||||
0 474192746 3584.96%
|
||||
1 247291499 1869.56%
|
||||
2 221816340 1676.96%
|
||||
3 137127863 1036.71%
|
||||
4 113209815 855.88%
|
||||
5 74495950 563.20%
|
||||
6 43530199 329.09%
|
||||
7 8994308 68.00%
|
||||
8 2068115 15.64%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.727089 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2375545164 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2252752413 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 626246255 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 560449 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 250981207 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 338613977 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.714860 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2397604305 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2268313048 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 649290621 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 732371 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 261741042 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 340572306 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 338613941 # ITB hits
|
||||
system.cpu.itb.misses 36 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884773 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4937.593280 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2937.593280 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9306242500 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 340572268 # ITB hits
|
||||
system.cpu.itb.misses 38 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884772 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5864.888697 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2864.888697 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 11053978000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1884773 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5536696500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 1884772 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5399662000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1884773 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7275387 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4268.742599 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2268.742599 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5387095 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8060632500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259545 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1888292 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4284048500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259545 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1888292 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 363852 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4821.983939 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2827.799490 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1754488500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1884772 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7275516 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5386.307802 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2386.307802 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5387207 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 10171013500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259543 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1888309 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4506086500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259543 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1888309 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 363870 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5746.245912 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2753.549345 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2090886500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 363852 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1028900500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 363870 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1001934000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 363852 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245532 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2245532 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 363870 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245548 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2245548 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.418007 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.418060 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9160160 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4602.856033 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2602.856033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5387095 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 17366875000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411899 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3773065 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 9160288 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5625.373932 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5387207 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 21224991500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411895 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3773081 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9820745000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411899 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3773065 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9905748500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411895 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3773081 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 9160160 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4602.856033 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2602.856033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 9160288 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5625.373932 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5387095 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 17366875000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411899 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3773065 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5387207 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 21224991500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411895 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3773081 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9820745000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411899 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3773065 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9905748500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411895 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3773081 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -427,31 +427,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 2759208 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2783807 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2783806 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25807.653410 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6731265 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 138143419000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1195675 # number of writebacks
|
||||
system.cpu.numCycles 1304363872 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 7040310 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.tagsinuse 25817.282629 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6731411 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 140102368000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1195679 # number of writebacks
|
||||
system.cpu.numCycles 1322739252 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 10423216 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2463939 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 700105266 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 8691200 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 11040 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3391931401 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2621456398 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1967699206 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 511613721 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 72357917 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 13245923 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 591496243 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 538 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 27887649 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 1183 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 3385420 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 705442707 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9460872 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 157269 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3423780434 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2645446907 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1985349974 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 515854810 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 75857193 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15148388 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 609147011 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 521 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 33326787 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 4373 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 890836 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 328448 # Number of bytes of host memory used
|
||||
host_seconds 2042.78 # Real time elapsed on the host
|
||||
host_tick_rate 1270245606 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1098189 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 373972 # Number of bytes of host memory used
|
||||
host_seconds 1657.07 # Real time elapsed on the host
|
||||
host_tick_rate 1574114309 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_seconds 2.594831 # Number of seconds simulated
|
||||
sim_ticks 2594830590000 # Number of ticks simulated
|
||||
sim_seconds 2.608424 # Number of seconds simulated
|
||||
sim_ticks 2608424230000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16114.256812 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14114.256812 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 17373.778213 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14373.778213 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 116383834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 125480619000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 101939006000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 103813377000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.842958 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.842958 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 56195050000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 60690301000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 51699446000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 53946895000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18223.331337 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 19658.571674 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 172578884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 186170920000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 153638452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 157760272000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18223.331337 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 16223.331337 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 19658.571674 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 595853949 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 172578884000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 186170920000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9470216 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 153638452000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 157760272000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4079.310460 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4079.381693 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40726989000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 40744129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244708 # number of writebacks
|
||||
system.cpu.dtb.accesses 611922547 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 20050000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 21654000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 18446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 19248000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 20050000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 21654000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 18446000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 19248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1826377708 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 20050000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 21654000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 802 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 18446000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 19248000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 611.506560 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 611.562745 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 1826378510 # ITB hits
|
||||
system.cpu.itb.misses 18 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 41565040000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 43454360000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 41253806000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 43128979000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 21978.336430 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22977.351722 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 7878838000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 8236967000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 82818846000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 86583339000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5348043 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 82818846000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 86583339000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3764493 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 2751986 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25384.669947 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 25389.772813 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 571912424000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 574940849000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1194738 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5189661180 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5216848460 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1819780127 # Number of instructions executed
|
||||
system.cpu.num_refs 613169725 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 12982100 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 16925674 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1193 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1943811 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 14569446 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 19414460 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1712096 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 78473 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156252 # Number of bytes of host memory used
|
||||
host_seconds 1072.72 # Real time elapsed on the host
|
||||
host_tick_rate 37770547 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 17082206 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 4901517 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 33850526 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 10567472 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 13021521 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 16952662 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1212 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1950052 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 19451761 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 79678 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202860 # Number of bytes of host memory used
|
||||
host_seconds 1056.50 # Real time elapsed on the host
|
||||
host_tick_rate 38578826 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 10604217 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040517 # Number of seconds simulated
|
||||
sim_ticks 40517060000 # Number of ticks simulated
|
||||
sim_seconds 0.040758 # Number of seconds simulated
|
||||
sim_ticks 40758469000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2905382 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 2850471 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73005548
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73485570
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 35921098 4920.32%
|
||||
1 18137551 2484.41%
|
||||
2 7364010 1008.69%
|
||||
3 3887256 532.46%
|
||||
4 2043377 279.89%
|
||||
5 1276568 174.86%
|
||||
6 715830 98.05%
|
||||
7 754476 103.35%
|
||||
8 2905382 397.97%
|
||||
0 36241200 4931.74%
|
||||
1 18077968 2460.07%
|
||||
2 7549008 1027.28%
|
||||
3 4015107 546.38%
|
||||
4 2030060 276.25%
|
||||
5 1302937 177.31%
|
||||
6 688676 93.72%
|
||||
7 730143 99.36%
|
||||
8 2850471 387.90%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 1931330 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 1937588 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 55735776 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 55772540 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.962632 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.962632 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.968368 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 23342837 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 8742.094862 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5367.588933 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23342331 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4423500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 23270992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 11553.149606 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 506 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2716000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_misses 508 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6494987 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 24890.835580 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5791.644205 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493132 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 46172500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1855 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6116 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 10743500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1855 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6494911 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34394.822006 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000285 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1854 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 13319.460268 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13269.579581 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 29837824 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 21429.902584 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5700.762389 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29835463 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 50596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_accesses 29765903 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 29482.218459 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2361 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6237 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 13459500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_misses 2362 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2361 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2362 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 29837824 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 21429.902584 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5700.762389 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 29765903 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 29482.218459 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 29835463 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 50596000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits 29763541 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2361 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6237 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 13459500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_misses 2362 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2361 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2362 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -121,103 +121,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 159 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1459.087304 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29835591 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29763667 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 105 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3482162 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12650 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3029893 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 162323026 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 39485043 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 29813671 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8027779 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45343 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 224673 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 31858285 # DTB accesses
|
||||
system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12627 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3048985 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 162336287 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 39537926 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 29896024 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8028470 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45209 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 189320 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 31783723 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 31399009 # DTB hits
|
||||
system.cpu.dtb.misses 459276 # DTB misses
|
||||
system.cpu.dtb.read_accesses 24667541 # DTB read accesses
|
||||
system.cpu.dtb.hits 31332689 # DTB hits
|
||||
system.cpu.dtb.misses 451034 # DTB misses
|
||||
system.cpu.dtb.read_accesses 24575603 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 24209262 # DTB read hits
|
||||
system.cpu.dtb.read_misses 458279 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7190744 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 24125563 # DTB read hits
|
||||
system.cpu.dtb.read_misses 450040 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7208120 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 7189747 # DTB write hits
|
||||
system.cpu.dtb.write_misses 997 # DTB write misses
|
||||
system.cpu.fetch.Branches 19414460 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19196880 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 50094936 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 510856 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167171428 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2080137 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.239584 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19196880 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14694196 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.062976 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 7207126 # DTB write hits
|
||||
system.cpu.dtb.write_misses 994 # DTB write misses
|
||||
system.cpu.fetch.Branches 19451761 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19219800 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 50154718 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 536931 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167137455 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2059472 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.238622 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19219800 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14743121 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.050340 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 81033328
|
||||
system.cpu.fetch.rateDist.samples 81514041
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 50135346 6187.00%
|
||||
1 3110572 383.86%
|
||||
2 2001906 247.05%
|
||||
3 3498240 431.70%
|
||||
4 4581898 565.43%
|
||||
5 1504688 185.69%
|
||||
6 2029552 250.46%
|
||||
7 1835028 226.45%
|
||||
8 12336098 1522.35%
|
||||
0 50579197 6204.97%
|
||||
1 3119637 382.71%
|
||||
2 2009848 246.56%
|
||||
3 3519871 431.81%
|
||||
4 4617609 566.48%
|
||||
5 1511564 185.44%
|
||||
6 2006119 246.11%
|
||||
7 1828029 224.26%
|
||||
8 12322167 1511.66%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 19196523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5281.475978 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3147.102526 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19186428 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 53316500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 19219343 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6740.447436 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000526 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10095 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 357 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 31770000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 10102 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10095 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10102 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1900.587221 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1901.528509 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 19196523 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5281.475978 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3147.102526 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19186428 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 53316500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 19219343 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 6740.447436 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000526 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10095 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 357 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 31770000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 10102 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10095 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 10102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 19196523 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5281.475978 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3147.102526 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 19219343 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 6740.447436 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 19186428 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 53316500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 19209241 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000526 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10095 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 357 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 31770000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 10102 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10095 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 10102 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,183 +229,183 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 8181 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10095 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8191 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10102 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1548.554006 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19186428 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1547.575549 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19209241 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 793 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12780668 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12539131 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.254771 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31909412 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7192377 # Number of stores executed
|
||||
system.cpu.idleCycles 2898 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12781978 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12589139 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.246896 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31834864 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7209747 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 90873941 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 99790534 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.723651 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 91092089 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 99774116 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.721851 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 65761001 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.231463 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100701135 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2107897 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 246665 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 33850526 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 65754876 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.223968 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100649675 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2112266 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 284242 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 33854360 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1732647 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10567472 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 147637958 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24717035 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2166845 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 101679237 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 118331 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 1723654 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10604217 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 147674740 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24625117 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2113526 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 101643128 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 120911 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8027779 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 156734 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8028470 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 165624 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 856559 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2781 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 844640 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2772 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 251777 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9738 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 13816113 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4064777 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 251777 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 201293 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1906604 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.038818 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.038818 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 103846082 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 223466 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 13819947 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4101522 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 223466 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 201477 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1910789 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.032665 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.032665 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 103756654 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 7 0.00% # Type of FU issued
|
||||
IntAlu 64291846 61.91% # Type of FU issued
|
||||
IntMult 474892 0.46% # Type of FU issued
|
||||
IntAlu 64328227 62.00% # Type of FU issued
|
||||
IntMult 474807 0.46% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2784334 2.68% # Type of FU issued
|
||||
FloatCmp 115616 0.11% # Type of FU issued
|
||||
FloatCvt 2378731 2.29% # Type of FU issued
|
||||
FloatMult 305685 0.29% # Type of FU issued
|
||||
FloatDiv 755261 0.73% # Type of FU issued
|
||||
FloatSqrt 321 0.00% # Type of FU issued
|
||||
MemRead 25423709 24.48% # Type of FU issued
|
||||
MemWrite 7315680 7.04% # Type of FU issued
|
||||
FloatAdd 2783435 2.68% # Type of FU issued
|
||||
FloatCmp 115619 0.11% # Type of FU issued
|
||||
FloatCvt 2381566 2.30% # Type of FU issued
|
||||
FloatMult 305730 0.29% # Type of FU issued
|
||||
FloatDiv 755065 0.73% # Type of FU issued
|
||||
FloatSqrt 322 0.00% # Type of FU issued
|
||||
MemRead 25279956 24.36% # Type of FU issued
|
||||
MemWrite 7331920 7.07% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1872954 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018036 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1948888 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018783 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 224469 11.98% # attempts to use FU when none available
|
||||
IntAlu 297234 15.25% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 178 0.01% # attempts to use FU when none available
|
||||
FloatAdd 492 0.03% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
FloatCvt 3554 0.19% # attempts to use FU when none available
|
||||
FloatMult 2233 0.12% # attempts to use FU when none available
|
||||
FloatDiv 827912 44.20% # attempts to use FU when none available
|
||||
FloatCvt 3359 0.17% # attempts to use FU when none available
|
||||
FloatMult 1274 0.07% # attempts to use FU when none available
|
||||
FloatDiv 828421 42.51% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 741361 39.58% # attempts to use FU when none available
|
||||
MemWrite 73247 3.91% # attempts to use FU when none available
|
||||
MemRead 745957 38.28% # attempts to use FU when none available
|
||||
MemWrite 72151 3.70% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 81033328
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 81514041
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 34942372 4312.10%
|
||||
1 18670897 2304.10%
|
||||
2 11746700 1449.61%
|
||||
3 6722042 829.54%
|
||||
4 5133527 633.51%
|
||||
5 2276322 280.91%
|
||||
6 1240213 153.05%
|
||||
7 251377 31.02%
|
||||
8 49878 6.16%
|
||||
0 35401194 4342.96%
|
||||
1 18638593 2286.55%
|
||||
2 11850080 1453.75%
|
||||
3 6738129 826.62%
|
||||
4 5072118 622.24%
|
||||
5 2314380 283.92%
|
||||
6 1219789 149.64%
|
||||
7 213656 26.21%
|
||||
8 66102 8.11%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.281511 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 135098398 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 103846082 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.272823 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 135085172 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 103756654 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 50311951 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 231214 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 50298713 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 225846 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 47101038 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 19196954 # ITB accesses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 47102449 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 19219874 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 19196880 # ITB hits
|
||||
system.cpu.itb.hits 19219800 # ITB hits
|
||||
system.cpu.itb.misses 74 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4494.812680 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2494.812680 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7798500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5751.440092 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2751.440092 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9984500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4328500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4776500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10600 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4263.499557 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2263.499557 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7211 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14449000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.319717 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 7671000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319717 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4426.829268 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2426.829268 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 544500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5363.488784 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.488784 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 18171500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.319351 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8007500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319351 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 122 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5704.918033 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2704.918033 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 696000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 298500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 122 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 330000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 122 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.151271 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.154260 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 12335 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4341.822795 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2341.822795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7211 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 22247500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.415403 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_accesses 12345 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5494.925839 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 28156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.415067 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11999500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415403 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 12784000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415067 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 12335 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4341.822795 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2341.822795 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 12345 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5494.925839 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 7211 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 22247500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.415403 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_hits 7221 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 28156000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.415067 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5124 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11999500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415403 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 12784000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415067 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -421,28 +421,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2256.522025 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7196 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2257.557113 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7206 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 81034121 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 1616502 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 81516939 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 1780351 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 794130 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 40700940 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 985111 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 202769823 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 157139154 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 115832522 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28814075 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8027779 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1869307 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47405161 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 4725 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 464 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4330333 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 453 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 1047628 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 40793393 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 942240 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 202632347 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 157116893 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 115707927 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28822360 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8028470 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 2084695 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47280566 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 4772 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 463 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4626500 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 687 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 877549 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 155412 # Number of bytes of host memory used
|
||||
host_seconds 104.73 # Real time elapsed on the host
|
||||
host_tick_rate 1132363341 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1053450 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201692 # Number of bytes of host memory used
|
||||
host_seconds 87.24 # Real time elapsed on the host
|
||||
host_tick_rate 1359521857 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_seconds 0.118589 # Number of seconds simulated
|
||||
sim_ticks 118589318000 # Number of ticks simulated
|
||||
sim_seconds 0.118605 # Number of seconds simulated
|
||||
sim_ticks 118605062000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 23658.227848 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21658.227848 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 11214000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 10266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 46475000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 42757000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 24727.389627 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22727.389627 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 57689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 53023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 24727.389627 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22727.389627 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26494968 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 57689000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2333 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 53023000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1441.456926 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 104 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16695.887192 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14695.887192 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 142082000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 125062000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 16695.887192 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 142082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 125062000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 16695.887192 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 14695.887192 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 91894580 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 142082000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 8510 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 125062000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 6681 # number of replacements
|
||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1418.474191 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 91903090 # ITB hits
|
||||
system.cpu.itb.misses 47 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 38456000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 66924000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2442000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -198,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 105380000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -212,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5942 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 105380000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 4790 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2021.711944 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 237178636 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 237210124 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 91903056 # Number of instructions executed
|
||||
system.cpu.num_refs 26537141 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 615476 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157048 # Number of bytes of host memory used
|
||||
host_seconds 314.29 # Real time elapsed on the host
|
||||
host_tick_rate 860356799 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1067073 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203488 # Number of bytes of host memory used
|
||||
host_seconds 181.28 # Real time elapsed on the host
|
||||
host_tick_rate 1491737734 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 193435005 # Number of instructions simulated
|
||||
sim_seconds 0.270398 # Number of seconds simulated
|
||||
sim_ticks 270397899000 # Number of ticks simulated
|
||||
sim_seconds 0.270417 # Number of seconds simulated
|
||||
sim_ticks 270416976000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12450000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 11454000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 18975304 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 27750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 29970000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1110 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 25530000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 26640000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1110 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 76708944 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 40200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 43416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1608 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 36984000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 38592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1608 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 76708944 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 40200000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 43416000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1608 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 36984000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 38592000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1608 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 26 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1237.402352 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1237.389513 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 23 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 193436018 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16510.596674 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14510.596674 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 17803.146397 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14803.146397 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 193423750 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 202552000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 218409000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 178016000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 181605000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 193436018 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 16510.596674 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 17803.146397 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 193423750 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 202552000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 218409000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 178016000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 181605000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 193436018 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 16510.596674 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 14510.596674 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 17803.146397 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 14803.146397 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 193423750 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 202552000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 218409000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 12268 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 178016000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 181605000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 10342 # number of replacements
|
||||
system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1591.726789 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1591.711897 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 193423750 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1087 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 23914000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 25001000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1087 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 11957000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1087 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 12766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 8679 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 89914000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 94001000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.320147 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4087 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 44957000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320147 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4087 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 550000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -192,10 +192,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 13853 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 8679 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 113828000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 119002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.373493 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -206,11 +206,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 13853 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 8679 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 113828000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 119002000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.373493 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5174 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4078 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2649.709095 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2649.681897 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8679 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 540795798 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 540833952 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 193435005 # Number of instructions executed
|
||||
system.cpu.num_refs 76733003 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 396 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7005
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -13,14 +13,16 @@ Authors: Carl Sechen, Bill Swartz
|
|||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:29
|
||||
M5 started Wed Feb 13 18:42:03 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 16:18:16 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 270397899000 because target called exit()
|
||||
Exiting @ tick 270416976000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 562 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1725 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 409 # Number of conditional branches incorrect
|
||||
global.BPredUnit.BTBHits 574 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1715 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 425 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 2029 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 61994 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 152004 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 52834669 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 124 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1236 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.lookups 2013 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 44115 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 194668 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
host_tick_rate 41555653 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 117 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1228 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5623 # Number of instructions simulated
|
||||
sim_seconds 0.000005 # Number of seconds simulated
|
||||
sim_ticks 4806000 # Number of ticks simulated
|
||||
sim_ticks 5303000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 862 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 86 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 89 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 8660
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 9365
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 6353 7336.03%
|
||||
1 1192 1376.44%
|
||||
2 402 464.20%
|
||||
3 186 214.78%
|
||||
4 132 152.42%
|
||||
5 92 106.24%
|
||||
6 109 125.87%
|
||||
7 108 124.71%
|
||||
8 86 99.31%
|
||||
0 7035 7512.01%
|
||||
1 1204 1285.64%
|
||||
2 411 438.87%
|
||||
3 192 205.02%
|
||||
4 145 154.83%
|
||||
5 90 96.10%
|
||||
6 97 103.58%
|
||||
7 102 108.92%
|
||||
8 89 95.03%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 1791 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 353 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4190 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5623 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.709586 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.709586 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1437 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1023500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.063844 # miss rate for ReadReq accesses
|
||||
system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14760.204082 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.064010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 623000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.063844 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.064010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 529 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27385.057471 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5839.080460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 442 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2382500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.164461 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_accesses 528 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 36879.310345 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.164773 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.164461 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.164773 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 11.141176 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11.111765 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18410.810811 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1879 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3406000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.089632 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2059 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25162.162162 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.089849 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 185 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 314 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1131000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.089632 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.089849 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18410.810811 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6113.513514 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 2059 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25162.162162 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1879 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3406000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.089632 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 1874 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.089849 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 185 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 314 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1131000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.089632 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.089849 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 109.245747 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1894 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1889 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 428 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 80 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 11542 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 6127 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2070 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 788 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 235 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 36 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 2656 # DTB accesses
|
||||
system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 163 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 11516 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 6794 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2076 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 792 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 231 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 2663 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 2596 # DTB hits
|
||||
system.cpu.dtb.misses 60 # DTB misses
|
||||
system.cpu.dtb.hits 2604 # DTB hits
|
||||
system.cpu.dtb.misses 59 # DTB misses
|
||||
system.cpu.dtb.read_accesses 1652 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1615 # DTB read hits
|
||||
system.cpu.dtb.read_misses 37 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 1004 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 1614 # DTB read hits
|
||||
system.cpu.dtb.read_misses 38 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 1011 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 981 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.fetch.Branches 2029 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1542 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3746 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.211068 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.302299 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 990 # DTB write hits
|
||||
system.cpu.dtb.write_misses 21 # DTB write misses
|
||||
system.cpu.fetch.Branches 2013 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1565 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 3769 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 233 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12458 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.189780 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 844 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.174507 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 9449
|
||||
system.cpu.fetch.rateDist.samples 10158
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 7275 7699.23%
|
||||
1 181 191.55%
|
||||
2 174 184.15%
|
||||
3 146 154.51%
|
||||
4 219 231.77%
|
||||
5 159 168.27%
|
||||
6 189 200.02%
|
||||
7 101 106.89%
|
||||
8 1005 1063.60%
|
||||
0 7986 7861.78%
|
||||
1 184 181.14%
|
||||
2 171 168.34%
|
||||
3 148 145.70%
|
||||
4 221 217.56%
|
||||
5 166 163.42%
|
||||
6 188 185.08%
|
||||
7 106 104.35%
|
||||
8 988 972.63%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 1520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7745.954693 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5443.365696 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1211 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2393500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.203289 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 309 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1682000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.203289 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 309 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 1530 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 10214.516129 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.202614 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 310 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.202614 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 3.919094 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.935484 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1520 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7745.954693 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1211 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2393500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.203289 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 309 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1682000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.203289 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 309 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 1530 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 10214.516129 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.202614 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 310 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.202614 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1520 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7745.954693 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5443.365696 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 1530 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 10214.516129 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1211 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2393500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.203289 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 309 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1682000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.203289 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 309 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 1220 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.202614 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 310 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.202614 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 309 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 164.253671 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1211 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 162.483905 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1220 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 164 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1199 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 72 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.833975 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1006 # Number of stores executed
|
||||
system.cpu.idleCycles 449 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1210 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 70 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.759310 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2668 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1014 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 5428 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7664 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.742815 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 5427 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7728 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.742583 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 4032 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.797254 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.WB:producers 4030 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.728575 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7840 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 420 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2030 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1236 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9996 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 185 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1228 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9927 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8017 # Number of executed instructions
|
||||
system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8054 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 788 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 792 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1051 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 424 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1034 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 416 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.584937 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.584937 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued
|
||||
system.cpu.iew.predictedNotTakenIncorrect 297 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.530122 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.530122 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8404 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 2 0.02% # Type of FU issued
|
||||
IntAlu 5559 66.31% # Type of FU issued
|
||||
IntAlu 5587 66.48% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.02% # Type of FU issued
|
||||
|
|
@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 1786 21.31% # Type of FU issued
|
||||
MemWrite 1033 12.32% # Type of FU issued
|
||||
MemRead 1774 21.11% # Type of FU issued
|
||||
MemWrite 1038 12.35% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 102 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.012167 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 103 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.012256 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 0.98% # attempts to use FU when none available
|
||||
IntAlu 1 0.97% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 66 64.71% # attempts to use FU when none available
|
||||
MemWrite 35 34.31% # attempts to use FU when none available
|
||||
MemRead 68 66.02% # attempts to use FU when none available
|
||||
MemWrite 34 33.01% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 9449
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 10158
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 6104 6459.94%
|
||||
1 1118 1183.19%
|
||||
2 813 860.41%
|
||||
3 591 625.46%
|
||||
4 460 486.82%
|
||||
5 212 224.36%
|
||||
6 105 111.12%
|
||||
7 32 33.87%
|
||||
8 14 14.82%
|
||||
0 6739 6634.18%
|
||||
1 1163 1144.91%
|
||||
2 838 824.97%
|
||||
3 636 626.11%
|
||||
4 450 443.00%
|
||||
5 195 191.97%
|
||||
6 92 90.57%
|
||||
7 30 29.53%
|
||||
8 15 14.77%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.872048 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3948 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2574 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 1572 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 0.792307 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9833 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8404 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3830 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2411 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 1597 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 1542 # ITB hits
|
||||
system.cpu.itb.misses 30 # ITB misses
|
||||
system.cpu.itb.hits 1565 # ITB hits
|
||||
system.cpu.itb.misses 32 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4548.611111 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2548.611111 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 327500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 183500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4400.246305 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2400.246305 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5733.415233 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2733.415233 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1786500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 974500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2333500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1112500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4266.666667 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2266.666667 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 64000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5433.333333 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2433.333333 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 81500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 34000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 479 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4422.594142 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5790.187891 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2114000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997912 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 478 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1158000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997912 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 478 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1336500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 479 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4422.594142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2422.594142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5790.187891 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2114000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997912 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 478 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 2773500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 479 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1158000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997912 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 478 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1336500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -415,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 218.025629 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 215.878593 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 9613 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 10607 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14101 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11035 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8205 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:IdleCycles 6962 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14001 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 10976 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8169 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 788 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 122 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4154 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 276 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 532 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 57 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:SquashCycles 792 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4118 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 79 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 15 2008 08:14:31
|
||||
M5 started Tue Jan 15 08:12:22 2008
|
||||
M5 executing on m45-034.pool
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 13:00:08 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 4806000 because target called exit()
|
||||
Exiting @ tick 5303000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -169,6 +170,7 @@ euid=100
|
|||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
|
|
@ -180,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 341217 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 196644 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1094407052 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 11324 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193960 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 38693743 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18374000 # Number of ticks simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 19285000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2300000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2116000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2175000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2001000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4475000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4117000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1612 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4475000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 179 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4117000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 102.386256 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 812 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24956.678700 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22956.678700 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6359000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24956.678700 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6359000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24956.678700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22956.678700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5375 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 277 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6359000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 128.084203 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5375 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,28 +160,28 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 5652 # ITB hits
|
||||
system.cpu.itb.misses 17 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1606000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8096000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -196,10 +196,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9702000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -210,11 +210,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9702000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 441 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 177.499846 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 36748 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 38570 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5641 # Number of instructions executed
|
||||
system.cpu.num_refs 1801 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 14 2007 17:58:14
|
||||
M5 started Tue Aug 14 17:59:07 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 12:58:22 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 18374000 because target called exit()
|
||||
Exiting @ tick 19285000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 156 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 642 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 213 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 401 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 824 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 1500 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151288 # Number of bytes of host memory used
|
||||
host_seconds 1.59 # Real time elapsed on the host
|
||||
host_tick_rate 1513804 # Simulator tick rate (ticks/s)
|
||||
global.BPredUnit.BTBHits 155 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 639 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 405 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 821 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 34209 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193660 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 38614456 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 412 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000002 # Number of seconds simulated
|
||||
sim_ticks 2410000 # Number of ticks simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2700000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 32 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 4452
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 4866
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 3491 7841.42%
|
||||
1 256 575.02%
|
||||
2 341 765.95%
|
||||
3 140 314.47%
|
||||
4 70 157.23%
|
||||
5 70 157.23%
|
||||
6 32 71.88%
|
||||
7 20 44.92%
|
||||
8 32 71.88%
|
||||
0 3922 8060.01%
|
||||
1 255 524.04%
|
||||
2 327 672.01%
|
||||
3 133 273.33%
|
||||
4 67 137.69%
|
||||
5 70 143.86%
|
||||
6 33 67.82%
|
||||
7 20 41.10%
|
||||
8 39 80.15%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.019690 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.019690 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 467 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 527000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.115530 # miss rate for ReadReq accesses
|
||||
system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 11663.934426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.114878 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 61 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.115530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.114878 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 240 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 18297.297297 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5986.486486 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 203 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 677000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.154167 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_accesses 230 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26567.567568 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.160870 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 54 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 221500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.154167 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.160870 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.035294 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 7.952941 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 768 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 12285.714286 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 670 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1204000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.127604 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 761 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 17290.816327 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.128778 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 98 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 64 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.127604 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.128778 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 768 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 12285.714286 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5780.612245 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 761 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 17290.816327 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 670 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1204000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.127604 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 663 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.128778 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 98 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 64 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 566500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.127604 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.128778 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,100 +121,100 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 47.072215 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 683 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 676 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 93 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 135 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4564 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 3475 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 283 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 303 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 931 # DTB accesses
|
||||
system.cpu.dtb.accesses 936 # DTB accesses
|
||||
system.cpu.dtb.acv 1 # DTB access violations
|
||||
system.cpu.dtb.hits 904 # DTB hits
|
||||
system.cpu.dtb.misses 27 # DTB misses
|
||||
system.cpu.dtb.read_accesses 575 # DTB read accesses
|
||||
system.cpu.dtb.hits 911 # DTB hits
|
||||
system.cpu.dtb.misses 25 # DTB misses
|
||||
system.cpu.dtb.read_accesses 578 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 563 # DTB read hits
|
||||
system.cpu.dtb.read_misses 12 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 356 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 567 # DTB read hits
|
||||
system.cpu.dtb.read_misses 11 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 358 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 341 # DTB write hits
|
||||
system.cpu.dtb.write_misses 15 # DTB write misses
|
||||
system.cpu.fetch.Branches 824 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 707 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1626 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.170919 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.092719 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 344 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14 # DTB write misses
|
||||
system.cpu.fetch.Branches 821 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 705 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 4736
|
||||
system.cpu.fetch.rateDist.samples 5157
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 3845 8118.67%
|
||||
1 38 80.24%
|
||||
2 85 179.48%
|
||||
3 63 133.02%
|
||||
4 118 249.16%
|
||||
5 55 116.13%
|
||||
6 42 88.68%
|
||||
7 48 101.35%
|
||||
8 442 933.28%
|
||||
0 4266 8272.25%
|
||||
1 34 65.93%
|
||||
2 85 164.82%
|
||||
3 67 129.92%
|
||||
4 115 223.00%
|
||||
5 55 106.65%
|
||||
6 41 79.50%
|
||||
7 48 93.08%
|
||||
8 446 864.84%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 692 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7648.351648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5370.879121 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 510 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1392000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.263006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 682 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 10041.208791 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.266862 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 182 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 977500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.263006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.266862 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 2.802198 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 692 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7648.351648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 510 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1392000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.263006 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 682 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 10041.208791 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 500 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.266862 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 182 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 977500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.263006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.266862 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 692 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7648.351648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5370.879121 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 682 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 10041.208791 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 510 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1392000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.263006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 500 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.266862 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 182 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 977500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.263006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.266862 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -230,59 +230,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 92.900452 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 510 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 500 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 85 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 538 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 274 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.658784 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 356 # Number of stores executed
|
||||
system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 542 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 277 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 358 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1781 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3084 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.794497 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1788 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3104 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1415 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.639701 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.WB:producers 1414 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 698 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 412 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4056 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 578 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 105 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3176 # Number of executed instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 283 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 118 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.495125 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.495125 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued
|
||||
system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 2319 70.68% # Type of FU issued
|
||||
IntAlu 2327 70.71% # Type of FU issued
|
||||
IntMult 1 0.03% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -291,13 +291,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 597 18.20% # Type of FU issued
|
||||
MemWrite 364 11.09% # Type of FU issued
|
||||
MemRead 599 18.20% # Type of FU issued
|
||||
MemWrite 364 11.06% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010667 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 2.86% # attempts to use FU when none available
|
||||
|
|
@ -315,57 +315,57 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 4736
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 5157
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 3384 7145.27%
|
||||
1 494 1043.07%
|
||||
2 314 663.01%
|
||||
3 237 500.42%
|
||||
4 163 344.17%
|
||||
5 88 185.81%
|
||||
6 40 84.46%
|
||||
7 12 25.34%
|
||||
8 4 8.45%
|
||||
0 3776 7322.09%
|
||||
1 540 1047.12%
|
||||
2 304 589.49%
|
||||
3 226 438.24%
|
||||
4 166 321.89%
|
||||
5 89 172.58%
|
||||
6 40 77.56%
|
||||
7 12 23.27%
|
||||
8 4 7.76%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.680564 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1238 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 742 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 735 # ITB accesses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 734 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 707 # ITB hits
|
||||
system.cpu.itb.misses 28 # ITB misses
|
||||
system.cpu.itb.hits 705 # ITB hits
|
||||
system.cpu.itb.misses 29 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4604.166667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2604.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 110500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 62500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4304.526749 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2304.526749 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1046000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4178.571429 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2178.571429 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 58500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 30500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -377,29 +377,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4331.460674 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1156500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 622500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4331.460674 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2331.460674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1156500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 267 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 622500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -416,26 +416,26 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 115.687599 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 4821 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5401 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 4989 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4410 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3154 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 808 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 283 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1386 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 84 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 28 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 15 2008 08:14:31
|
||||
M5 started Tue Jan 15 08:12:16 2008
|
||||
M5 executing on m45-034.pool
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 13:00:07 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 2410000 because target called exit()
|
||||
Exiting @ tick 2700000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -169,6 +170,7 @@ euid=100
|
|||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
|
|
@ -180,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 178240 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195696 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 641473527 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 99969 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193012 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 383001655 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000009 # Number of seconds simulated
|
||||
sim_ticks 9438000 # Number of ticks simulated
|
||||
sim_seconds 0.000010 # Number of seconds simulated
|
||||
sim_ticks 9950000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1375000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1265000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 950000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 874000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 2325000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 2139000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 616 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 2325000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 93 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 2139000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 48.838317 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 4075000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 3749000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 4075000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 3749000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2423 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 4075000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 163 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 3749000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 83.395749 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,27 +160,27 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 2586 # ITB hits
|
||||
system.cpu.itb.misses 11 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 594000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 4796000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 242000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -195,10 +195,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 5390000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -209,11 +209,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 5390000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 106.559981 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 18876 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 19900 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 14 2007 17:58:14
|
||||
M5 started Tue Aug 14 17:59:08 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 12:58:25 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 9438000 because target called exit()
|
||||
Exiting @ tick 9950000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -11,7 +11,62 @@ physmem=system.physmem
|
|||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dtb icache itb l2cache toL2Bus tracer workload
|
||||
children=dcache dtb icache itb l2cache tlb toL2Bus tracer workload
|
||||
CP0_Config=0
|
||||
CP0_Config1=0
|
||||
CP0_Config1_C2=false
|
||||
CP0_Config1_CA=false
|
||||
CP0_Config1_DA=0
|
||||
CP0_Config1_DL=0
|
||||
CP0_Config1_DS=0
|
||||
CP0_Config1_EP=false
|
||||
CP0_Config1_FP=false
|
||||
CP0_Config1_IA=0
|
||||
CP0_Config1_IL=0
|
||||
CP0_Config1_IS=0
|
||||
CP0_Config1_M=0
|
||||
CP0_Config1_MD=false
|
||||
CP0_Config1_MMU=0
|
||||
CP0_Config1_PC=false
|
||||
CP0_Config1_WR=false
|
||||
CP0_Config2=0
|
||||
CP0_Config2_M=false
|
||||
CP0_Config2_SA=0
|
||||
CP0_Config2_SL=0
|
||||
CP0_Config2_SS=0
|
||||
CP0_Config2_SU=0
|
||||
CP0_Config2_TA=0
|
||||
CP0_Config2_TL=0
|
||||
CP0_Config2_TS=0
|
||||
CP0_Config2_TU=0
|
||||
CP0_Config3=0
|
||||
CP0_Config3_DSPP=false
|
||||
CP0_Config3_LPA=false
|
||||
CP0_Config3_M=false
|
||||
CP0_Config3_MT=false
|
||||
CP0_Config3_SM=false
|
||||
CP0_Config3_SP=false
|
||||
CP0_Config3_TL=false
|
||||
CP0_Config3_VEIC=false
|
||||
CP0_Config3_VInt=false
|
||||
CP0_Config_AR=0
|
||||
CP0_Config_AT=0
|
||||
CP0_Config_BE=0
|
||||
CP0_Config_MT=0
|
||||
CP0_Config_VI=0
|
||||
CP0_EBase_CPUNum=0
|
||||
CP0_IntCtl_IPPCI=0
|
||||
CP0_IntCtl_IPTI=0
|
||||
CP0_PRId=0
|
||||
CP0_PRId_CompanyID=0
|
||||
CP0_PRId_CompanyOptions=0
|
||||
CP0_PRId_ProcessorID=1
|
||||
CP0_PRId_Revision=0
|
||||
CP0_PerfCtr_M=false
|
||||
CP0_PerfCtr_W=false
|
||||
CP0_SrsCtl_HSS=0
|
||||
CP0_WatchHi_M=false
|
||||
UnifiedTLB=true
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
|
|
@ -26,6 +81,7 @@ max_loads_any_thread=0
|
|||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tlb=system.cpu.tlb
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -69,6 +125,7 @@ mem_side=system.cpu.toL2Bus.port[1]
|
|||
|
||||
[system.cpu.dtb]
|
||||
type=MipsDTB
|
||||
size=64
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
|
|
@ -108,6 +165,7 @@ mem_side=system.cpu.toL2Bus.port[0]
|
|||
|
||||
[system.cpu.itb]
|
||||
type=MipsITB
|
||||
size=64
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
|
|
@ -145,11 +203,16 @@ write_buffers=8
|
|||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
|
||||
[system.cpu.tlb]
|
||||
type=MipsUTB
|
||||
size=64
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -167,6 +230,7 @@ euid=100
|
|||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
|
|
@ -178,6 +242,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 192479 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 197496 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 618816195 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 11117 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195308 # Number of bytes of host memory used
|
||||
host_seconds 0.51 # Real time elapsed on the host
|
||||
host_tick_rate 38035865 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5656 # Number of instructions simulated
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18463000 # Number of ticks simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 19359000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2050000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1886000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1600000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1472000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3650000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3358000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1908 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3650000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 146 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3358000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,27 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 84.706280 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24920.792079 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22920.792079 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7551000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24920.792079 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7551000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24920.792079 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22920.792079 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5355 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7551000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,34 +147,43 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 135.936693 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1100000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8426000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 308000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -180,10 +198,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9526000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -194,11 +212,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9526000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 433 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -219,14 +237,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 183.281817 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 36926 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 38718 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5656 # Number of instructions executed
|
||||
system.cpu.num_refs 2055 # Number of memory references
|
||||
system.cpu.tlb.accesses 0 # DTB accesses
|
||||
system.cpu.tlb.accesses 0 # DTB accesses
|
||||
system.cpu.tlb.hits 0 # DTB hits
|
||||
system.cpu.tlb.hits 0 # DTB hits
|
||||
system.cpu.tlb.misses 0 # DTB misses
|
||||
system.cpu.tlb.misses 0 # DTB misses
|
||||
system.cpu.tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
Hello World!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 14 2007 22:02:23
|
||||
M5 started Tue Aug 14 22:02:25 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 13:24:29
|
||||
M5 started Sun Feb 24 13:24:31 2008
|
||||
M5 executing on tater
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 18463000 because target called exit()
|
||||
Exiting @ tick 19359000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1215 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 181116 # Number of bytes of host memory used
|
||||
host_seconds 3.98 # Real time elapsed on the host
|
||||
host_tick_rate 3985160 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 153074 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195092 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 524572616 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4833 # Number of instructions simulated
|
||||
sim_seconds 0.000016 # Number of seconds simulated
|
||||
sim_ticks 15853000 # Number of ticks simulated
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16662000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24777.777778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22777.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1338000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1230000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2400000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2208000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 24920 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22920 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3738000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 24920 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22920 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1119 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3738000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 150 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3438000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 81.746424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24906.250000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22906.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6376000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 5864000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24906.250000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6376000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 5864000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24906.250000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22906.250000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4621 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6376000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 256 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 5864000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,34 +138,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 114.989412 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4621 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1782000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 6754000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 330000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -180,10 +180,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 8536000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -194,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 8536000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 388 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 133.763146 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 31706 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33324 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 4833 # Number of instructions executed
|
||||
system.cpu.num_refs 1282 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
Hello World!M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 28 2007 18:29:37
|
||||
M5 started Wed Nov 28 18:29:38 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Sun Feb 24 13:28:47 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 15853000 because target called exit()
|
||||
Exiting @ tick 16662000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -400,6 +401,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,5 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7008
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@ Hello world!
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 15 2008 08:14:31
|
||||
M5 started Tue Jan 15 08:14:22 2008
|
||||
M5 executing on m45-038.pool
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 12:58:27 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 5727000 because target called exit()
|
||||
Exiting @ tick 6363000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -354,6 +354,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -383,6 +384,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 2711 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 6964 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 2713 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 6851 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 2012 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 7659 # Number of BP lookups
|
||||
global.BPredUnit.condIncorrect 2011 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 7546 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 7546 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 42769 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 153188 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 61517406 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 35519 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195624 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_tick_rate 52488986 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 2956 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedLoads 3058 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 2926 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 10411 # Number of instructions simulated
|
||||
sim_seconds 0.000015 # Number of seconds simulated
|
||||
sim_ticks 14990500 # Number of ticks simulated
|
||||
sim_ticks 15392500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 2152 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 87 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 88 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 26989
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 27698
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 21416 7935.08%
|
||||
1 3114 1153.80%
|
||||
2 1160 429.80%
|
||||
3 589 218.24%
|
||||
4 306 113.38%
|
||||
5 84 31.12%
|
||||
6 196 72.62%
|
||||
7 37 13.71%
|
||||
8 87 32.24%
|
||||
0 22133 7990.83%
|
||||
1 3105 1121.02%
|
||||
2 1159 418.44%
|
||||
3 591 213.37%
|
||||
4 306 110.48%
|
||||
5 82 29.61%
|
||||
6 196 70.76%
|
||||
7 38 13.72%
|
||||
8 88 31.77%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,71 +43,71 @@ system.cpu.commit.COM:loads 1462 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2760 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 2012 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 2011 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 13198 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 13116 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 10411 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 10411 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.879839 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.879839 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2274 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 9734.848485 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5560.606061 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2208 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 642500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.029024 # miss rate for ReadReq accesses
|
||||
system.cpu.cpi 2.957065 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.957065 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 13053.030303 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7068.181818 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2205 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 861500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.029062 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 66 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 367000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.029024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 466500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.029062 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1171 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 16414.285714 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5623.809524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1066 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1723500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.089667 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_accesses 1167 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 21642.857143 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6966.666667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1062 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2272500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.089974 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 121 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 590500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089667 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 125 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 731500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089974 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 21.703947 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 21.657895 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 3445 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 13836.257310 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3274 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 2366000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.049637 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 3438 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 18327.485380 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3267 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3134000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.049738 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 171 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.049637 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_hits 151 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1198000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.049738 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 3445 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 13836.257310 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5599.415205 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 3438 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 18327.485380 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 3274 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 2366000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.049637 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 3267 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3134000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.049738 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 171 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 146 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 957500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.049637 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_hits 151 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1198000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.049738 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -123,85 +123,85 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 111.288485 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3299 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 110.780967 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3292 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3945 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 38084 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 12820 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 10159 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 2909 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:BlockedCycles 4065 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 37568 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 13467 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 10101 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 2901 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 7659 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4927 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 16219 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 589 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 42202 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2099 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.255453 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4927 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2711 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.407578 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.Branches 7546 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4905 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 16129 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 609 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 41611 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2098 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.245111 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4905 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2713 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.351621 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 29898
|
||||
system.cpu.fetch.rateDist.samples 30599
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 18628 6230.52%
|
||||
1 4885 1633.89%
|
||||
2 619 207.04%
|
||||
3 712 238.14%
|
||||
4 788 263.56%
|
||||
5 640 214.06%
|
||||
6 611 204.36%
|
||||
7 195 65.22%
|
||||
8 2820 943.21%
|
||||
0 19398 6339.42%
|
||||
1 4890 1598.09%
|
||||
2 619 202.29%
|
||||
3 711 232.36%
|
||||
4 788 257.52%
|
||||
5 642 209.81%
|
||||
6 612 200.01%
|
||||
7 196 64.05%
|
||||
8 2743 896.43%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 4907 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 7495.945946 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5325.675676 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4537 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2773500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.075402 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_accesses 4860 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9979.729730 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6462.162162 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4490 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3692500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.076132 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 370 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1970500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.075402 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.076132 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 12.262162 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12.135135 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4907 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 7495.945946 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4537 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.075402 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 4860 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9979.729730 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4490 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3692500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.076132 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 370 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1970500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.075402 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2391000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.076132 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 4907 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 7495.945946 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 5325.675676 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 4860 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9979.729730 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4537 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2773500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.075402 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 4490 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3692500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.076132 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 370 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 20 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1970500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.075402 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2391000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.076132 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -217,59 +217,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 233.477311 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4537 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 230.770092 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4490 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 84 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3086 # Number of branches executed
|
||||
system.cpu.idleCycles 187 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3077 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1794 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.575379 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 4543 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2116 # Number of stores executed
|
||||
system.cpu.iew.EXEC:rate 0.558825 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 4529 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2104 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 9189 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 16618 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.827620 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 9158 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 16580 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.828347 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 7605 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.554266 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 16830 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2216 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.WB:producers 7586 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.538556 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 16781 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2212 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 3077 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2973 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 2956 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 24330 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2427 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2838 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 17251 # Number of executed instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 2936 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 2926 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 24197 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2425 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2802 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 17204 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 2909 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 2901 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1615 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1658 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1596 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1628 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 695 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1521 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.347242 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.347242 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 20089 # Type of FU issued
|
||||
system.cpu.iew.predictedNotTakenIncorrect 689 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1523 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.338173 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.338173 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 20006 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 14535 72.35% # Type of FU issued
|
||||
IntAlu 14491 72.43% # Type of FU issued
|
||||
IntMult 0 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 2907 14.47% # Type of FU issued
|
||||
MemWrite 2647 13.18% # Type of FU issued
|
||||
MemRead 2890 14.45% # Type of FU issued
|
||||
MemWrite 2625 13.12% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009358 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009347 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 50 26.60% # attempts to use FU when none available
|
||||
IntAlu 51 27.27% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -296,60 +296,60 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 23 12.23% # attempts to use FU when none available
|
||||
MemWrite 115 61.17% # attempts to use FU when none available
|
||||
MemRead 24 12.83% # attempts to use FU when none available
|
||||
MemWrite 112 59.89% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 29898
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 30599
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 21040 7037.26%
|
||||
1 3621 1211.12%
|
||||
2 2127 711.42%
|
||||
3 1561 522.11%
|
||||
4 748 250.18%
|
||||
5 407 136.13%
|
||||
6 293 98.00%
|
||||
7 62 20.74%
|
||||
8 39 13.04%
|
||||
0 21747 7107.10%
|
||||
1 3624 1184.35%
|
||||
2 2137 698.39%
|
||||
3 1557 508.84%
|
||||
4 751 245.43%
|
||||
5 397 129.74%
|
||||
6 290 94.77%
|
||||
7 60 19.61%
|
||||
8 36 11.77%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.670035 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 21924 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 20089 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 0.649841 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 21791 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 20006 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 10183 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 8044 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 4424.418605 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2424.418605 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 380500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5755.813953 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2755.813953 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 495000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 208500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 237000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 4287.037037 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2287.037037 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5417.824074 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2417.824074 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1852000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2340500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 988000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4421.052632 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2421.052632 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 84000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5631.578947 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2631.578947 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 107000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 50000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -361,29 +361,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 4309.845560 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5473.938224 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 2835500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1196500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1281500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 4309.845560 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2309.845560 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5473.938224 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2232500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 2835500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 518 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1196500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1281500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -400,25 +400,25 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 259.708792 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 257.005987 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 29982 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 30786 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 14192 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:RenameLookups 51924 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 30001 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 24487 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 8874 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 2909 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:IdleCycles 14813 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:RenameLookups 51330 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 29671 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 24234 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 8843 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 2901 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 14619 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 3693 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 648 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4472 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 685 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 20 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:UndoneMaps 14366 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 3812 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 646 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4446 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 683 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -11,14 +11,14 @@ STTW: Passed
|
|||
Done
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 16 2008 04:32:20
|
||||
M5 started Wed Jan 16 04:31:23 2008
|
||||
M5 executing on m45-027.pool
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 12:17:27 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 14990500 because target called exit()
|
||||
Exiting @ tick 15392500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -181,6 +182,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2763 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 180992 # Number of bytes of host memory used
|
||||
host_seconds 3.97 # Real time elapsed on the host
|
||||
host_tick_rate 6131000 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 23807 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 194964 # Number of bytes of host memory used
|
||||
host_seconds 0.46 # Real time elapsed on the host
|
||||
host_tick_rate 54716973 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 10976 # Number of instructions simulated
|
||||
sim_seconds 0.000024 # Number of seconds simulated
|
||||
sim_ticks 24355000 # Number of ticks simulated
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 25237000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1350000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1458000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2835000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2415000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2520000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3975000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 4293000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2595 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3975000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 4293000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 159 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 100.373888 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 99.913779 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24915.194346 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22915.194346 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26908.127208 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7051000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 7615000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6485000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6766000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24915.194346 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26908.127208 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 7615000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 283 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6485000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 6766000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24915.194346 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22915.194346 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26908.127208 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 10729 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7051000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 7615000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 283 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6485000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 6766000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -140,34 +140,34 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 155.977710 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 154.924957 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 10729 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1936000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2024000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7370000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7705000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -182,10 +182,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9306000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 9729000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -196,11 +196,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9306000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 9729000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 423 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -221,12 +221,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 178.108320 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 176.975795 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 48710 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 50474 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 10976 # Number of instructions executed
|
||||
system.cpu.num_refs 2770 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7011
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -11,14 +11,14 @@ STTW: Passed
|
|||
Done
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Nov 28 2007 18:29:37
|
||||
M5 started Wed Nov 28 18:29:38 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 13:27:50
|
||||
M5 started Mon Feb 25 12:26:21 2008
|
||||
M5 executing on tater
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 24355000 because target called exit()
|
||||
Exiting @ tick 25237000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -296,6 +296,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
|
|
@ -379,6 +380,7 @@ children=responder
|
|||
block_size=64
|
||||
bus_id=1
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
|
|
@ -433,6 +435,7 @@ children=responder
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
default=system.toL2Bus.responder.pio
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,6 @@
|
|||
warn: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
Listening for system connection on port 3458
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7009
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: 469929000: Trying to launch CPU number 1!
|
||||
warn: 478619000: Trying to launch CPU number 1!
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:19
|
||||
M5 started Wed Feb 13 00:40:52 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:18:14
|
||||
M5 started Sun Feb 24 13:19:24 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1967564570000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1972679592000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -188,6 +188,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
|
|
@ -271,6 +272,7 @@ children=responder
|
|||
block_size=64
|
||||
bus_id=1
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
default=system.membus.responder.pio
|
||||
|
|
@ -325,6 +327,7 @@ children=responder
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
default=system.toL2Bus.responder.pio
|
||||
|
|
|
|||
|
|
@ -1,92 +1,92 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 696140 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 250636 # Number of bytes of host memory used
|
||||
host_seconds 86.29 # Real time elapsed on the host
|
||||
host_tick_rate 22338313409 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 827411 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 316168 # Number of bytes of host memory used
|
||||
host_seconds 72.58 # Real time elapsed on the host
|
||||
host_tick_rate 26612603617 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 60068732 # Number of instructions simulated
|
||||
sim_seconds 1.927543 # Number of seconds simulated
|
||||
sim_ticks 1927543019000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 200271 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13100.266914 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11100.266914 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 183037 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 225770000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.086053 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 17234 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191302000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086053 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 17234 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 9532729 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19595.012234 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17594.985853 # average ReadReq mshr miss latency
|
||||
sim_insts 60056349 # Number of instructions simulated
|
||||
sim_seconds 1.931640 # Number of seconds simulated
|
||||
sim_ticks 1931639667000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 200273 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14106.217767 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11106.217767 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 183016 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 243431000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.086167 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 17257 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 191660000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086167 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 17257 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 9530772 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21143.101090 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18143.074712 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_hits 7808009 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 33795909500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.180926 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1724720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 30346424000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.180926 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1724720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses 199250 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency 25002.710390 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 23002.710390 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_hits 169365 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 747206000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_rate 0.149987 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_misses 29885 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 687436000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.149987 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 29885 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6155089 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25003.901042 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23003.901042 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 7805869 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 36469798500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.180983 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1724903 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31295044000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.180983 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1724903 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 837553000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses 199252 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency 27003.604806 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 24003.604806 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_hits 169292 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_miss_latency 809028000 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_rate 0.150362 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_misses 29960 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency 719148000 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150362 # mshr miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_mshr_misses 29960 # number of StoreCondReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6154055 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27005.969289 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24005.969289 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_hits 5754555 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10014912500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.065074 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 400534 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 9213844500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065074 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 400534 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1165071500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_hits 5753421 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10819509500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.065101 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 400634 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 9617607500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065101 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 400634 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1174669000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 6.861521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.859082 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 15687818 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 20614.393385 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 18614.371976 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 13562564 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 43810822000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.135472 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2125254 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_accesses 15684827 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22248.169757 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 13559290 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 47289308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.135515 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2125537 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 39560268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.135472 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2125254 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 40912651500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.135515 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2125537 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 15687818 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 20614.393385 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 18614.371976 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 15684827 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22248.169757 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19248.148350 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 13562564 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 43810822000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.135472 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2125254 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 13559290 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 47289308000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.135515 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2125537 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 39560268500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.135472 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2125254 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 1995897500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 40912651500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.135515 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2125537 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 2012222000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
|
|
@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 2045827 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2046339 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2046082 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2046594 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 511.986919 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14040998 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 65018000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 430020 # number of writebacks
|
||||
system.cpu.dtb.accesses 1021777 # DTB accesses
|
||||
system.cpu.dtb.acv 373 # DTB access violations
|
||||
system.cpu.dtb.hits 16067843 # DTB hits
|
||||
system.cpu.dtb.misses 11527 # DTB misses
|
||||
system.cpu.dtb.read_accesses 729481 # DTB read accesses
|
||||
system.cpu.dcache.tagsinuse 511.986722 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14037756 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 66420000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 430195 # number of writebacks
|
||||
system.cpu.dtb.accesses 1020787 # DTB accesses
|
||||
system.cpu.dtb.acv 367 # DTB access violations
|
||||
system.cpu.dtb.hits 16064922 # DTB hits
|
||||
system.cpu.dtb.misses 11471 # DTB misses
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 9713362 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10376 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 292296 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 163 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 6354481 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1151 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 60080633 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 13203.991500 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11203.259450 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 59151734 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 12265174500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.015461 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 928899 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10406696500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.015461 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 928899 # number of ReadReq MSHR misses
|
||||
system.cpu.dtb.read_hits 9711464 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 6353458 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 60068188 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14221.050037 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11220.318707 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 59139059 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13213190000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.015468 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 929129 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10425123500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.015468 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 929129 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 63.690305 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 63.660961 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 60080633 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 13203.991500 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11203.259450 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 59151734 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 12265174500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.015461 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 928899 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_accesses 60068188 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 14221.050037 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 59139059 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13213190000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.015468 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 929129 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10406696500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.015461 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 928899 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_miss_latency 10425123500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.015468 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 929129 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 60080633 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 13203.991500 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11203.259450 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 60068188 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 14221.050037 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11220.318707 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 59151734 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 12265174500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.015461 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 928899 # number of overall misses
|
||||
system.cpu.icache.overall_hits 59139059 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13213190000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.015468 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 929129 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10406696500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.015461 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 928899 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_miss_latency 10425123500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.015468 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 929129 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 928229 # number of replacements
|
||||
system.cpu.icache.sampled_refs 928740 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 928458 # number of replacements
|
||||
system.cpu.icache.sampled_refs 928969 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 507.528659 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59151734 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 46711592000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tagsinuse 507.298573 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 59139059 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 48981308000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0.931443 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 4984781 # ITB accesses
|
||||
system.cpu.idle_fraction 0.929252 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 4979997 # ITB accesses
|
||||
system.cpu.itb.acv 184 # ITB acv
|
||||
system.cpu.itb.hits 4979736 # ITB hits
|
||||
system.cpu.itb.misses 5045 # ITB misses
|
||||
system.cpu.kern.callpal 192951 # number of callpals executed
|
||||
system.cpu.itb.hits 4974991 # ITB hits
|
||||
system.cpu.itb.misses 5006 # ITB misses
|
||||
system.cpu.kern.callpal 192947 # number of callpals executed
|
||||
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpctx 4179 2.17% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal_tbi 55 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpctx 4174 2.16% 2.17% # number of callpals executed
|
||||
system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpipl 175991 91.21% 93.41% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdps 6833 3.54% 96.95% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed
|
||||
system.cpu.kern.callpal_swpipl 175999 91.22% 93.41% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdps 6835 3.54% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed
|
||||
system.cpu.kern.callpal_rti 5165 2.68% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal_callsys 517 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
|
||||
system.cpu.kern.callpal_rti 5159 2.67% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.hwrei 212145 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.quiesce 6176 # number of quiesce instructions executed
|
||||
system.cpu.kern.ipl_count 183220 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_0 74917 40.89% 40.89% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_21 132 0.07% 40.96% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_22 1932 1.05% 42.02% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_31 106239 57.98% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good 149165 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_0 73550 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_21 132 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_31 73551 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks 1927542285000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1858193951000 96.40% 96.40% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_21 83622500 0.00% 96.41% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_22 547930500 0.03% 96.44% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_31 68716781000 3.56% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used_0 0.981753 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.inst.hwrei 212042 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed
|
||||
system.cpu.kern.ipl_count 183224 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_0 74910 40.88% 40.88% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_21 131 0.07% 40.96% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_22 1934 1.06% 42.01% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count_31 106249 57.99% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good 149151 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_0 73543 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good_31 73543 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks 1931638909000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_0 1859511291500 96.27% 96.27% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_21 87343500 0.00% 96.27% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_22 557262000 0.03% 96.30% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks_31 71483012000 3.70% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used_0 0.981751 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used_31 0.692316 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.mode_good_kernel 1915
|
||||
system.cpu.kern.mode_good_user 1747
|
||||
system.cpu.kern.mode_good_idle 168
|
||||
system.cpu.kern.mode_switch_kernel 5911 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_user 1747 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_idle 2099 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_good 1.404010 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_kernel 0.323972 # fraction of useful protection mode switches
|
||||
system.cpu.kern.ipl_used_31 0.692176 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.mode_good_kernel 1905
|
||||
system.cpu.kern.mode_good_user 1736
|
||||
system.cpu.kern.mode_good_idle 169
|
||||
system.cpu.kern.mode_switch_kernel 5906 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_user 1736 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_idle 2093 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch_good 1.403299 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_kernel 0.322553 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good_idle 0.080038 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks_kernel 44586957000 2.31% 2.31% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_user 4962483000 0.26% 2.57% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1877992843000 97.43% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4180 # number of times the context was actually changed
|
||||
system.cpu.kern.mode_switch_good_idle 0.080745 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks_kernel 45112475000 2.34% 2.34% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_user 5048233000 0.26% 2.60% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks_idle 1881478199000 97.40% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
|
||||
system.cpu.kern.syscall 326 # number of syscalls executed
|
||||
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
||||
|
|
@ -267,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
|
|||
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
||||
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
||||
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
||||
system.cpu.not_idle_fraction 0.068557 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3855086038 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 60068732 # Number of instructions executed
|
||||
system.cpu.num_refs 16316112 # Number of memory references
|
||||
system.cpu.not_idle_fraction 0.070748 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3863279334 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 60056349 # Number of instructions executed
|
||||
system.cpu.num_refs 16313052 # Number of memory references
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -284,55 +284,55 @@ system.disk2.dma_write_bytes 8192 # Nu
|
|||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_avg_miss_latency 111884.381503 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency 60884.381503 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_miss_latency 19355998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_avg_miss_latency 113566.462428 # average ReadReq miss latency
|
||||
system.iocache.ReadReq_avg_mshr_miss_latency 61566.462428 # average ReadReq mshr miss latency
|
||||
system.iocache.ReadReq_miss_latency 19646998 # number of ReadReq miss cycles
|
||||
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_misses 173 # number of ReadReq misses
|
||||
system.iocache.ReadReq_mshr_miss_latency 10532998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_latency 10650998 # number of ReadReq MSHR miss cycles
|
||||
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
||||
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_avg_miss_latency 105472.006305 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency 54472.006305 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_miss_latency 4382572806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_avg_miss_latency 115104.611234 # average WriteReq miss latency
|
||||
system.iocache.WriteReq_avg_mshr_miss_latency 63104.539180 # average WriteReq mshr miss latency
|
||||
system.iocache.WriteReq_miss_latency 4782826806 # number of WriteReq miss cycles
|
||||
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_mshr_miss_latency 2263420806 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_latency 2622119812 # number of WriteReq MSHR miss cycles
|
||||
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
||||
system.iocache.avg_blocked_cycles_no_mshrs 4141.477870 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles_no_mshrs 4196.454414 # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.blocked_no_mshrs 10461 # number of cycles access was blocked
|
||||
system.iocache.blocked_no_mshrs 2764 # number of cycles access was blocked
|
||||
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_mshrs 43324000 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_mshrs 11599000 # number of cycles access was blocked
|
||||
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
|
||||
system.iocache.demand_avg_miss_latency 105498.593265 # average overall miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency 54498.593265 # average overall mshr miss latency
|
||||
system.iocache.demand_avg_miss_latency 115098.233769 # average overall miss latency
|
||||
system.iocache.demand_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency
|
||||
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_miss_latency 4401928804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_latency 4802473804 # number of demand (read+write) miss cycles
|
||||
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.iocache.demand_misses 41725 # number of demand (read+write) misses
|
||||
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.iocache.demand_mshr_miss_latency 2273953804 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_latency 2632770810 # number of demand (read+write) MSHR miss cycles
|
||||
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
|
||||
system.iocache.overall_avg_miss_latency 105498.593265 # average overall miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency 54498.593265 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_miss_latency 115098.233769 # average overall miss latency
|
||||
system.iocache.overall_avg_mshr_miss_latency 63098.162013 # average overall mshr miss latency
|
||||
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.iocache.overall_hits 0 # number of overall hits
|
||||
system.iocache.overall_miss_latency 4401928804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_latency 4802473804 # number of overall miss cycles
|
||||
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.iocache.overall_misses 41725 # number of overall misses
|
||||
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.iocache.overall_mshr_miss_latency 2273953804 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_latency 2632770810 # number of overall MSHR miss cycles
|
||||
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
||||
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.iocache.replacements 41685 # number of replacements
|
||||
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
||||
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.iocache.tagsinuse 1.334772 # Cycle average of tags in use
|
||||
system.iocache.tagsinuse 1.333347 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 1762233995000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.warmup_cycle 1766149259000 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 41512 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses 304387 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency 22004.172320 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 11004.172320 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_miss_latency 6697784000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_accesses 304436 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency 23005.373872 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 11005.373872 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_miss_latency 7003664000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses 304387 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 3349527000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_misses 304436 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 3350432000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_misses 304387 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses 2670834 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency 22012.695417 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 11012.695417 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadExReq_mshr_misses 304436 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses 2671270 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency 23012.722595 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 11012.722595 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_hits 1708085 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 21192700500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate 0.360468 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 962749 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 10602461500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate 0.360468 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 962749 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_hits 1708534 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 22155176500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate 0.360404 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses 962736 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 10602344500 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate 0.360404 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 962736 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses 126032 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency 22001.392503 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 11002.963533 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_miss_latency 2772879500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_accesses 126158 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency 23005.275131 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 11006.915931 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_miss_latency 2902299500 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses 126032 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 1386725500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_misses 126158 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 1388610500 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_misses 126032 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 126158 # number of UpgradeReq MSHR misses
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 1051707500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses 430020 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 430020 # number of Writeback hits
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 1061281000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses 430195 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits 430195 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 1.742465 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 1.743066 # Average number of references to valid blocks.
|
||||
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses 2975221 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 22010.648028 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 11010.648028 # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1708085 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 27890484500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.425896 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 1267136 # number of demand (read+write) misses
|
||||
system.l2c.demand_accesses 2975706 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency 23010.957076 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency
|
||||
system.l2c.demand_hits 1708534 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 29158840500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate 0.425839 # miss rate for demand accesses
|
||||
system.l2c.demand_misses 1267172 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 13951988500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate 0.425896 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 1267136 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_miss_latency 13952776500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate 0.425839 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 1267172 # number of demand (read+write) MSHR misses
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.overall_accesses 2975221 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 22010.648028 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 11010.648028 # average overall mshr miss latency
|
||||
system.l2c.overall_accesses 2975706 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency 23010.957076 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 11010.957076 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits 1708085 # number of overall hits
|
||||
system.l2c.overall_miss_latency 27890484500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.425896 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 1267136 # number of overall misses
|
||||
system.l2c.overall_hits 1708534 # number of overall hits
|
||||
system.l2c.overall_miss_latency 29158840500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate 0.425839 # miss rate for overall accesses
|
||||
system.l2c.overall_misses 1267172 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 13951988500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate 0.425896 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 1267136 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 1801809500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_miss_latency 13952776500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate 0.425839 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 1267172 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 1811383000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
||||
|
|
@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
|
|||
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.l2c.replacements 1050150 # number of replacements
|
||||
system.l2c.sampled_refs 1081111 # Sample count of references to valid blocks.
|
||||
system.l2c.replacements 1050085 # number of replacements
|
||||
system.l2c.sampled_refs 1081030 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 30789.729249 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1883798 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 4791566000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 118721 # number of writebacks
|
||||
system.l2c.tagsinuse 30869.828292 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1884307 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 5029142000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 118653 # number of writebacks
|
||||
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
||||
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
warn: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
Listening for system connection on port 3456
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
Listening for system connection on port 3457
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 13 2008 00:33:19
|
||||
M5 started Wed Feb 13 00:39:25 2008
|
||||
M5 executing on zizzer
|
||||
M5 compiled Feb 24 2008 13:18:14
|
||||
M5 started Sun Feb 24 13:19:10 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 1927543019000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1931639667000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -152,6 +152,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
|
||||
|
|
@ -163,6 +164,8 @@ type=ExeTracer
|
|||
type=EioProcess
|
||||
chkpt=
|
||||
file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
|
||||
input=None
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
system=system
|
||||
|
||||
|
|
@ -171,6 +174,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1220265 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195724 # Number of bytes of host memory used
|
||||
host_seconds 0.41 # Real time elapsed on the host
|
||||
host_tick_rate 1720644367 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 922979 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193036 # Number of bytes of host memory used
|
||||
host_seconds 0.54 # Real time elapsed on the host
|
||||
host_tick_rate 1305530646 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500001 # Number of instructions simulated
|
||||
sim_seconds 0.000705 # Number of seconds simulated
|
||||
sim_ticks 705490000 # Number of ticks simulated
|
||||
sim_seconds 0.000708 # Number of seconds simulated
|
||||
sim_ticks 707548000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 7875000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 8505000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 7245000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 7560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7775000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 8397000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7153000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7464000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 15650000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 16902000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 15024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180149 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 15650000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 16902000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 626 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14398000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 15024000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 289.561085 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 289.353429 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 56340 # DTB write hits
|
||||
system.cpu.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 10075000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 10881000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 9269000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 9672000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 10075000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 10881000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 9269000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 9672000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 499617 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 10075000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 10881000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 403 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 9269000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 9672000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 266.630553 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 266.476324 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,27 +160,27 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 500020 # ITB hits
|
||||
system.cpu.itb.misses 13 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3058000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3197000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1529000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 15796000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 16514000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 7898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3784000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3956000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1892000 # number of UpgradeReq MSHR miss cycles
|
||||
|
|
@ -195,10 +195,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 18854000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 19711000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -209,11 +209,11 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 18854000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 19711000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 857 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
|
|
@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 373.545251 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 373.323140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1410980 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1415096 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 500001 # Number of instructions executed
|
||||
system.cpu.num_refs 182222 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
gzip: stdout: Broken pipe
|
||||
|
|
|
|||
|
|
@ -2,14 +2,14 @@ main dictionary has 1245 entries
|
|||
49508 bytes wasted
|
||||
>M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 14 2007 17:58:14
|
||||
M5 started Tue Aug 14 17:58:16 2007
|
||||
M5 executing on nacho
|
||||
M5 compiled Feb 24 2008 12:58:20
|
||||
M5 started Sun Feb 24 12:58:24 2008
|
||||
M5 executing on tater
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 705490000 because a thread reached the max instruction count
|
||||
Exiting @ tick 707548000 because a thread reached the max instruction count
|
||||
|
|
|
|||
|
|
@ -474,6 +474,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=2
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=16
|
||||
port=system.l2c.mem_side system.physmem.port[0]
|
||||
|
|
@ -491,6 +492,7 @@ type=Bus
|
|||
block_size=64
|
||||
bus_id=0
|
||||
clock=2
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=16
|
||||
port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
|
||||
|
|
|
|||
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Reference in a new issue