Regression: Fix some bugs in simple-timing-mp-ruby.py.

This commit is contained in:
Marc Orr 2012-06-11 03:16:43 -04:00
parent 754a9570f2
commit 02f8178b44

View file

@ -77,11 +77,13 @@ Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu ports to the ruby cpu ports
#
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
# -----------------------
# run simulation