Ref output: Update refs for PCState change.
This commit is contained in:
Gabe Black
parent
6f4bd2c1da
commit
b53231e7fe
9 changed files with 2151 additions and 2153 deletions
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@ -358,7 +358,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/gzip
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executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -5,10 +5,10 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:49
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 16:20:33
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M5 executing on phenom
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M5 compiled Sep 26 2010 21:00:10
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M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
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M5 started Sep 26 2010 21:05:23
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M5 executing on burrito
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command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -43,4 +43,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 1095331467500 because target called exit()
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Exiting @ tick 601454696500 because target called exit()
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@ -1,414 +1,414 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 138841 # Simulator instruction rate (inst/s)
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host_mem_usage 198176 # Number of bytes of host memory used
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host_seconds 10123.96 # Real time elapsed on the host
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host_tick_rate 108192045 # Simulator tick rate (ticks/s)
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host_inst_rate 119996 # Simulator instruction rate (inst/s)
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host_mem_usage 230000 # Number of bytes of host memory used
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host_seconds 11713.80 # Real time elapsed on the host
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host_tick_rate 51345807 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1405618374 # Number of instructions simulated
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sim_seconds 1.095331 # Number of seconds simulated
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sim_ticks 1095331467500 # Number of ticks simulated
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sim_insts 1405604152 # Number of instructions simulated
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sim_seconds 0.601455 # Number of seconds simulated
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sim_ticks 601454696500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 175591574 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 198504175 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 98804348 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 100538146 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 83489596 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 252577407 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 252577407 # Number of BP lookups
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system.cpu.BPredUnit.condIncorrect 5348299 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 105812900 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 105812900 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.commit.COM:branches 86248929 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 9068364 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 21328327 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle::samples 1951658061 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 0.763216 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.203742 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::samples 1172134111 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.270779 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 1.680126 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 1079992719 55.34% 55.34% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 573544089 29.39% 84.72% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 118996755 6.10% 90.82% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 118578034 6.08% 96.90% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 27958213 1.43% 98.33% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 7829070 0.40% 98.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 11095017 0.57% 99.30% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 4595800 0.24% 99.54% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 9068364 0.46% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::0 418023744 35.66% 35.66% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 498322579 42.51% 78.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 52995965 4.52% 82.70% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 103673250 8.84% 91.54% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 32915504 2.81% 94.35% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 8294294 0.71% 95.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 10946246 0.93% 98.18% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 21328327 1.82% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::total 1951658061 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1489537517 # Number of instructions committed
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system.cpu.commit.COM:loads 402517252 # Number of loads committed
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system.cpu.commit.COM:committed_per_cycle::total 1172134111 # Number of insts commited each cycle
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system.cpu.commit.COM:count 1489523295 # Number of instructions committed
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system.cpu.commit.COM:loads 402512844 # Number of loads committed
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system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
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system.cpu.commit.COM:refs 569375208 # Number of memory references committed
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system.cpu.commit.COM:refs 569360986 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 83489596 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489537517 # The number of committed instructions
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system.cpu.commit.branchMispredicts 5348299 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1344365389 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405618374 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405618374 # Number of Instructions Simulated
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system.cpu.cpi 1.558505 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.558505 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 428071377 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 13932.868577 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6644.344451 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 427202678 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 12103469000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002029 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 868699 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 619015 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1658986500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 249684 # number of ReadReq MSHR misses
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system.cpu.commit.commitSquashedInsts 219352878 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
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system.cpu.cpi 0.855795 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.855795 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 295701747 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 14658.100936 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.537350 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 294883428 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11995002500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 818319 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 604827 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1593832500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 213492 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 38071.428571 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35071.428571 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_avg_miss_latency 38214.285714 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35214.285714 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 266500 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_latency 267500 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 245500 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_latency 246500 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 14486.830110 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11574.912497 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 165064790 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 25958081664 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.010739 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1791840 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1512123 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3237699799 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001676 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 279717 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 15552.165643 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.834160 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 165080576 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 27468857045 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1766240 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1498175 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 3438425299 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1118.737886 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 955.148896 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 594928007 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14305.954795 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 592267468 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 38061550664 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.004472 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2660539 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2131138 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 4896686299 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000890 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 529401 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 462548563 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 15269.088284 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 459964004 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 39463859545 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2584559 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2103002 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 5032257799 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 481557 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.577700 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 594928007 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14305.954795 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 9249.484415 # average overall mshr miss latency
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system.cpu.dcache.occ_%::0 0.999860 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.424781 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 462548563 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 15269.088284 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 10449.973314 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 592267468 # number of overall hits
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system.cpu.dcache.overall_miss_latency 38061550664 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.004472 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2660539 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2131138 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 4896686299 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000890 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 529401 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 459964004 # number of overall hits
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system.cpu.dcache.overall_miss_latency 39463859545 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2584559 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2103002 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 5032257799 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 481557 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 525312 # number of replacements
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system.cpu.dcache.sampled_refs 529408 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 477468 # number of replacements
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system.cpu.dcache.sampled_refs 481564 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.577700 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 592268787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 165936000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 467492 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 419165001 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3408944329 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 761736999 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 767859019 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 238675861 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2897042 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 252577407 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 355041427 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1184621367 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 11557522 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3696750718 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 90055290 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.115297 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 355041427 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 175591574 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.687503 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 2190333922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.687757 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.837142 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.dcache.tagsinuse 4095.424781 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 459965323 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 132220000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 428419 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 393630434 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 1750728609 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 405694605 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 351105685 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 30409425 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 21703387 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 105812900 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 173095521 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 548231197 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1429406 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 1760522570 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6170035 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 173095521 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 98804348 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.463554 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 1202543536 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.699989 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 1360754025 62.13% 62.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 248782776 11.36% 73.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 79015111 3.61% 77.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 36736924 1.68% 78.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 85275355 3.89% 82.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 39319900 1.80% 84.46% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 30979848 1.41% 85.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 19612924 0.90% 86.77% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 289857059 13.23% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 827407907 68.80% 68.80% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 82886631 6.89% 75.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 45822474 3.81% 79.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 22740031 1.89% 81.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 33832186 2.81% 84.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 32824396 2.73% 86.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 14991772 1.25% 88.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 7935570 0.66% 88.85% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 134102569 11.15% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 2190333922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 355041427 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33183.081998 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34797.601744 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 355039305 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 70414500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 2122 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 746 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 47881500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1376 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 1202543536 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 173095521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35040.947075 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35056.370656 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 173093726 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 62898500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 45398000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 258210.403636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 133766.403400 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 355041427 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33183.081998 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 355039305 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 70414500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 2122 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 746 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 47881500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1376 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 173095521 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35040.947075 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35056.370656 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 173093726 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 62898500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 45398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.517160 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1059.143452 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 355041427 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33183.081998 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34797.601744 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.509837 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 1044.146064 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 173095521 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35040.947075 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35056.370656 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 355039305 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 70414500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 2122 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 746 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 47881500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1376 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 173093726 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 62898500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 45398000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 218 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1375 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 158 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1059.143452 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 355039305 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1044.146064 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173093726 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 329014 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 129329311 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 343977069 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.860181 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 750434371 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 206174463 # Number of stores executed
|
||||
system.cpu.idleCycles 365858 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 89387994 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 102270125 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.226831 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 590482453 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 169844558 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1480496045 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1847584929 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.961963 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1212155834 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1472494694 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1424182878 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.843391 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1859595547 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 91828645 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2291655 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 731683017 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21329829 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 16631995 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 299730608 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2833977471 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 544259908 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 92682608 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1884367319 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 43246 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1161633451 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.224111 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1473866323 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 5524573 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2522825 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 468103706 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 2974733 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 4542151 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 188277007 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 1708968213 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 420637895 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6158070 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1475767085 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 67059 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 5071 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 238675861 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 70086 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 30409425 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 130990 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 28836 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 116166112 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 85848 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 124904325 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 7473 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6831445 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 329165765 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 132872652 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6831445 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2781524 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 89047121 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.641641 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.641641 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 65590862 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 21428865 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 648511 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.168504 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.168504 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1175590605 59.46% 59.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.46% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2994259 0.15% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.61% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 570634170 28.86% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 227830893 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 884681338 59.70% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.87% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 423845666 28.60% 88.48% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 170779885 11.52% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1977049927 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4131140 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002090 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 1481925155 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3244981 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 148870 3.60% 3.60% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.60% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.60% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 222262 5.38% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.98% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 3423281 82.87% 91.85% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 336727 8.15% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 213199 6.57% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 2529934 77.96% 89.96% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 325689 10.04% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 2190333922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902625 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.145189 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 1202543536 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232326 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127768 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 1077130624 49.18% 49.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 581443700 26.55% 75.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 301967857 13.79% 89.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 159877963 7.30% 96.81% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 45264546 2.07% 98.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 18451049 0.84% 99.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 4794612 0.22% 99.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 1273045 0.06% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 130526 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 320551307 26.66% 26.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 511598648 42.54% 69.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 219310152 18.24% 87.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 94899047 7.89% 95.33% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 39949634 3.32% 98.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 10701892 0.89% 99.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 5167484 0.43% 99.97% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 226814 0.02% 99.99% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 138558 0.01% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 2190333922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.902489 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2468355699 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1977049927 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21644703 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1031033219 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 637277 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19401032 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1242826340 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 279724 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34530.938042 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31386.377770 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 218618 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2110047500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.218451 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 61106 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1917896000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.218451 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 61106 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 251060 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34076.007326 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.126905 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 217208 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1153541000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.134836 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33852 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1049484000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.134836 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33852 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 467492 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 467492 # number of Writeback hits
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 1202543536 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 1.231951 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 1603622713 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1481925155 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 3075375 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 200589396 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 67249 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 831704 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 279090439 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.656689 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.323632 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2080631000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893879500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 214779 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34036.266738 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958285 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1146375500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.156817 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33681 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1044278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156817 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33681 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 428419 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 428419 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 5.866131 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.114556 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 530784 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34368.757767 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 435826 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3263588500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.178901 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94958 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 482859 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34274.797931 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3227006500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.194987 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 94151 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2967380000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.178901 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94958 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2938157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.194987 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 94151 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.061469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.477467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 2014.215255 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15645.646003 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 530784 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34368.757767 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31249.394469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.060603 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 1985.832482 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 15675.625212 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 482859 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34274.797931 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.864505 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 435826 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3263588500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.178901 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94958 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 388708 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3227006500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.194987 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 94151 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2967380000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.178901 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94958 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2938157500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.194987 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 94151 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 76745 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 92262 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 75917 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 91431 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17659.861257 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 541221 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 17661.457694 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 467629 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 59365 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 443698156 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 136383139 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 731683017 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 299730608 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 2190662936 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 17189054 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244779268 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 463 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 34257 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 824291881 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 24214806 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 8 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 4869886562 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3060544953 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2396042530 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 704670101 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 238675861 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 33809858 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1151263262 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 371697167 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 21697179 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 175779479 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21533408 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 8581 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.l2cache.writebacks 59275 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 406523725 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 165664801 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 468103706 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 188277007 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 1202909394 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 123850376 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 134234500 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 443697356 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 41034725 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 2926103966 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 1732026812 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1445187078 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 329587648 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 30409425 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 217220624 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 200416626 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 57778107 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 3036469 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 385260528 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 3035800 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 11398 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simout
|
||||
Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 12:56:28
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 12:56:32
|
||||
M5 executing on zizzer
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:29:28
|
||||
M5 executing on burrito
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 14010500 because target called exit()
|
||||
Exiting @ tick 12784500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,129 +1,130 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 60755 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205968 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 164238154 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 25375 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 223596 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_tick_rate 62666353 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5169 # Number of instructions simulated
|
||||
sim_seconds 0.000014 # Number of seconds simulated
|
||||
sim_ticks 14010500 # Number of ticks simulated
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 12784500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1895 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 538 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 1522 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1584 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 2400 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.condIncorrect 378 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 1192 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 1744 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 916 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 67 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 76 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 14458 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.402960 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.127371 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 12273 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.474701 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.213395 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 11898 82.29% 82.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1218 8.42% 90.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 521 3.60% 94.32% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 296 2.05% 98.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 65 0.45% 98.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 62 0.43% 99.27% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 39 0.27% 99.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 67 0.46% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 9782 79.70% 79.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 1006 8.20% 87.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 705 5.74% 93.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 340 2.77% 96.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 169 1.38% 97.79% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 96 0.78% 98.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 67 0.55% 99.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 32 0.26% 99.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 76 0.62% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 14458 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 5826 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 1164 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2089 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 5944 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 3481 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 5169 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.421165 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.421165 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34750 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36021.978022 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2179 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4448000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.055483 # miss rate for ReadReq accesses
|
||||
system.cpu.cpi 4.946798 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 4.946798 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 36046.875000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1696 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4614000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.070175 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039445 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.049342 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27330.827068 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36160 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 659 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.287568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 266 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 216 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1808000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.054054 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 34184.971098 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.078431 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 11828000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 20.127660 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 16.134752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 3232 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 29741.116751 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2838 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 11718000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.121906 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 394 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 253 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5086000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.043626 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 2749 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34687.763713 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 16442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.172426 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5080500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.051291 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.022299 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 91.337822 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 3232 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 29741.116751 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.022390 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 91.708831 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 2749 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34687.763713 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36031.914894 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2838 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 11718000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.121906 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 394 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 253 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5086000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.043626 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 2275 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 16442000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.172426 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 474 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5080500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.051291 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 91.337822 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2838 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 91.708831 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 514 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 14307 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 10045 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 3899 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1070 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:BlockedCycles 736 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 42 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 88 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 10461 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8771 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2729 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 649 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 153 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 37 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -133,190 +134,190 @@ system.cpu.dtb.read_misses 0 # DT
|
|||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.fetch.Branches 2400 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 2213 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 6297 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 357 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 15518 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 762 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.085647 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 2213 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.553779 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 15528 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.999356 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.261429 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.432225 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 12922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.855286 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.122030 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 11461 73.81% 73.81% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1813 11.68% 85.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 195 1.26% 86.74% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 140 0.90% 87.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 320 2.06% 89.70% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 114 0.73% 90.44% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 288 1.85% 92.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 259 1.67% 93.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 938 6.04% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10085 78.05% 78.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 1182 9.15% 87.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 138 1.07% 88.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 127 0.98% 89.24% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 278 2.15% 91.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 124 0.96% 92.35% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 162 1.25% 93.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 99 0.77% 94.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 727 5.63% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15528 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 2213 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35692.399050 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34907.294833 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1792 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 15026500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.190239 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 421 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11484500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.148667 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1150 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 14691000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.260450 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 405 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 76 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 11523000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.211576 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 5.446809 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 3.495441 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2213 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35692.399050 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1792 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 15026500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.190239 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 421 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11484500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.148667 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_accesses 1555 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36274.074074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1150 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14691000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.260450 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 405 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 76 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 11523000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.211576 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.076220 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 156.098402 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 2213 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35692.399050 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.077565 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 158.853467 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 1555 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36274.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35024.316109 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1792 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 15026500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.190239 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 421 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 92 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11484500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.148667 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits 1150 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14691000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.260450 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 405 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 76 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 11523000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.211576 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 16 # number of replacements
|
||||
system.cpu.icache.replacements 15 # number of replacements
|
||||
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 156.098402 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1792 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 158.853467 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1150 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 12494 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1265 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1823 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.295232 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 3434 # number of memory reference insts executed
|
||||
system.cpu.idleCycles 12648 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1183 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1244 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.279625 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2950 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1042 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 4130 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 7520 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.704843 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 3586 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 6793 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.717513 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 2911 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.268361 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 7608 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 678 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2792 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1150 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 11774 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2392 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 540 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8273 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 2573 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.265663 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 6861 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2139 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1135 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 9313 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 223 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7150 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1070 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 649 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 66 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 19 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1628 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 225 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.184462 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.184462 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 975 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 210 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5164 58.60% 58.60% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.65% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.67% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2584 29.32% 88.02% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1056 11.98% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 4328 58.70% 58.70% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 4 0.05% 58.75% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.03% 58.78% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.03% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.81% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 1984 26.91% 85.72% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1053 14.28% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 8813 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 160 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018155 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 7373 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.019259 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 8 5.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 100 62.50% 67.50% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 52 32.50% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 7 4.93% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.93% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 83 58.45% 63.38% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 52 36.62% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 15528 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567555 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215524 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 12922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.570577 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213210 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 11574 74.54% 74.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1747 11.25% 85.79% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 792 5.10% 90.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 724 4.66% 95.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 342 2.20% 97.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 211 1.36% 99.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 94 0.61% 99.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 29 0.19% 99.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 9579 74.13% 74.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 1454 11.25% 85.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 793 6.14% 91.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 511 3.95% 95.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 304 2.35% 97.83% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 160 1.24% 99.06% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 76 0.59% 99.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.25% 99.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 15528 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.314503 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9939 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8813 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 4094 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2672 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 2456 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1522 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
|
|
@ -326,91 +327,91 @@ system.cpu.itb.read_misses 0 # DT
|
|||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34680 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31360 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1734000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.078431 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1769500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1568000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34319.711538 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14277000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34325.721154 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31134.615385 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14279500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34358.369099 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 16011000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34366.167024 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 16049000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14558000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.006586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 215.818258 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_%::0 0.006661 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 218.261856 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34358.369099 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34366.167024 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.447537 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 16011000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 466 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 16049000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 467 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14558000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 215.818258 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 218.261856 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2792 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1150 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 28022 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
|
||||
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 25570 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 10436 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 15725 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 13557 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8322 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 3509 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1070 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4912 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 104 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 12088 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 6119 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2609 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:03:47
|
||||
M5 executing on zizzer
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:00:21
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -25,4 +23,4 @@ LDTX: Passed
|
|||
LDTW: Passed
|
||||
STTW: Passed
|
||||
Done
|
||||
Exiting @ tick 27419000 because target called exit()
|
||||
Exiting @ tick 18639500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,399 +1,398 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 45017 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207928 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
host_tick_rate 85360538 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 29064 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 225548 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 37472433 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 27419000 # Number of ticks simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18639500 # Number of ticks simulated
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 9180 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 2677 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBLookups 5066 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 11474 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 11474 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condIncorrect 725 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.condPredicted 5166 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 5166 # Number of BP lookups
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.commit.COM:branches 3359 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 84 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 41984 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.361447 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 0.969782 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::samples 27536 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::mean 0.551097 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::stdev 1.189203 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 33831 80.58% 80.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 4806 11.45% 92.03% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 1719 4.09% 96.12% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 713 1.70% 97.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 414 0.99% 98.81% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 146 0.35% 99.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 193 0.46% 99.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 48 0.11% 99.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::0 19764 71.78% 71.78% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::1 4506 16.36% 88.14% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::2 1459 5.30% 93.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::3 767 2.79% 96.22% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::4 365 1.33% 97.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::5 265 0.96% 98.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::6 289 1.05% 99.56% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::7 37 0.13% 99.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::8 84 0.31% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 41984 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle::total 27536 # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:count 15175 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 2226 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 3674 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 725 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 19909 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4917 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 14449 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.795349 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.795349 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35221.238938 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35546.153846 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3980000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.029412 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2310500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 2.580109 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.580109 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 2725 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33508.064516 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35587.301587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2601 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4155000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.045505 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.023119 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 31011.029412 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35620.481928 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35792.892157 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.060241 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 12652500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 14603500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2956500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2968500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 24.938356 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 31924.184261 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 4763 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 16632500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.098600 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 521 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 373 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5267000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.028009 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 4167 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35260.338346 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3635 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 18758500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.127670 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5210500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.035037 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.026492 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 108.511216 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 31924.184261 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.occ_%::0 0.024989 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 102.354840 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses 4167 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35260.338346 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35688.356164 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 4763 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 16632500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.098600 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 521 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 373 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5267000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.028009 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 3635 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 18758500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.127670 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 532 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5210500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.035037 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 108.511216 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 102.354840 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3641 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 6598 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 51837 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 20462 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 14791 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 11474 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 7329 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 23792 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 833 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 58386 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.209231 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 7329 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.064680 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 46308 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.260819 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.406261 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.decode.DECODE:BlockedCycles 7103 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 23378 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 13089 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 7237 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1142 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 5166 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 4063 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 11559 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 23733 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 820 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.138573 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 4063 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 2677 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.636615 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist::samples 28678 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.827568 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.939691 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 29867 64.50% 64.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 7441 16.07% 80.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1110 2.40% 82.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 985 2.13% 85.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 1044 2.25% 87.34% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 1211 2.62% 89.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 663 1.43% 91.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 335 0.72% 92.11% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 3652 7.89% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 21209 73.96% 73.96% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 3590 12.52% 86.47% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 580 2.02% 88.50% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 498 1.74% 90.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 667 2.33% 92.56% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 529 1.84% 94.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 243 0.85% 95.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 178 0.62% 95.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 1184 4.13% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 46308 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 7329 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33501.855288 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6790 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 18057500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.073543 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 539 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 180 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.048983 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
|
||||
system.cpu.fetch.rateDist::total 28678 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.icache.ReadReq_accesses 4063 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 34748.459959 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34876.056338 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 3576 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 16922500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.119862 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 487 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12381000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.087374 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 355 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 18.966480 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 10.101695 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 7329 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33501.855288 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6790 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 18057500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.073543 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 539 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 180 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.048983 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 4063 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 34748.459959 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34876.056338 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 3576 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 16922500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.119862 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 487 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 12381000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.087374 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 355 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.110645 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 226.601923 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 7329 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33501.855288 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
|
||||
system.cpu.icache.occ_%::0 0.100082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 204.967174 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses 4063 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 34748.459959 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34876.056338 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 6790 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 18057500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.073543 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 539 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 180 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.048983 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 3576 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 16922500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.119862 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 487 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 132 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 12381000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.087374 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 355 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 226.601923 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6790 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 204.967174 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 3576 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 8531 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 4839 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 2088 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.453126 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2469 # Number of stores executed
|
||||
system.cpu.idleCycles 8602 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 3845 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 1083 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.467838 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 4472 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1661 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 13105 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 23892 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.824189 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 9394 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 17034 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.855972 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 10801 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.435675 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 24096 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3048 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 35165 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 4356 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 24849 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 8041 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.456921 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 17187 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 821 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2960 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 569 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1800 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 20159 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 2811 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 446 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 17441 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 1142 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 36 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 31 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 815 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.263480 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.263480 # IPC: Total IPC of All Threads
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 734 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 352 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 582 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 239 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.387580 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.387580 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 21372 73.18% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.18% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 4722 16.17% 89.35% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntAlu 13329 74.52% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 74.52% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemRead 2869 16.04% 90.56% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1689 9.44% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 29205 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:FU_type_0::total 17887 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 88 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.004920 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 44 24.86% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 24.86% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntAlu 26 29.55% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 29.55% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemRead 21 23.86% 53.41% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::MemWrite 41 46.59% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 46308 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.630669 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.289103 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::samples 28678 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623719 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.187639 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 33418 72.16% 72.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 5459 11.79% 83.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 3013 6.51% 90.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 2134 4.61% 95.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 995 2.15% 97.22% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 696 1.50% 98.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.73% 99.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 214 0.46% 99.91% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::0 19867 69.28% 69.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::1 4247 14.81% 84.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::2 1908 6.65% 90.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::3 1720 6.00% 96.74% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::4 389 1.36% 98.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::5 282 0.98% 99.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::6 171 0.60% 99.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::7 80 0.28% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 46308 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.532559 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 32304 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 29205 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 15678 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 12314 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:issued_per_cycle::total 28678 # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:rate 0.479802 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 18507 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 17887 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 569 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3884 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 94 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 3281 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34391.566265 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2854500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.144578 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31409.638554 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2866500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2607000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.380952 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 418 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34231.884058 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.038647 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990431 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 414 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12836500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990431 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 414 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.009547 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34247.514911 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 501 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34282.696177 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 17226500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 17038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992016 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15443500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992016 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 497 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_%::0 0.008034 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 263.251984 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34247.514911 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.occ_%::0 0.007304 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 239.321987 # Average occupied blocks per context
|
||||
system.cpu.l2cache.overall_accesses 501 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34282.696177 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31073.440644 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 17226500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 503 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 17038500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992016 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 497 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15620000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15443500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992016 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 497 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 419 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 263.251984 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 239.321987 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 54839 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking
|
||||
system.cpu.memDep0.insertedLoads 2960 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1800 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.numCycles 37280 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 254 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 22249 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 74810 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 42608 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 13159 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6232 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5138 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 822 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IdleCycles 13548 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 39844 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 21594 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 19316 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 7011 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1142 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 422 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 5484 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6301 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 607 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2701 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 587 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 26 2010 13:03:41
|
||||
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
|
||||
M5 started Aug 26 2010 13:03:47
|
||||
M5 executing on zizzer
|
||||
M5 compiled Sep 26 2010 21:00:10
|
||||
M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
|
||||
M5 started Sep 26 2010 21:00:16
|
||||
M5 executing on burrito
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
@ -22,68 +20,68 @@ Init done
|
|||
[Iteration 1, Thread 1] Got lock
|
||||
[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
|
||||
Iteration 1 completed
|
||||
[Iteration 2, Thread 2] Got lock
|
||||
[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 2, Thread 1] Got lock
|
||||
[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 2, Thread 2] Got lock
|
||||
[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 2, Thread 3] Got lock
|
||||
[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
|
||||
Iteration 2 completed
|
||||
[Iteration 3, Thread 1] Got lock
|
||||
[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 3, Thread 3] Got lock
|
||||
[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 3, Thread 1] Got lock
|
||||
[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 3, Thread 2] Got lock
|
||||
[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
|
||||
Iteration 3 completed
|
||||
[Iteration 4, Thread 3] Got lock
|
||||
[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 4, Thread 1] Got lock
|
||||
[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 4, Thread 2] Got lock
|
||||
[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 4, Thread 1] Got lock
|
||||
[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 4, Thread 3] Got lock
|
||||
[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
|
||||
Iteration 4 completed
|
||||
[Iteration 5, Thread 2] Got lock
|
||||
[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 5, Thread 3] Got lock
|
||||
[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 5, Thread 1] Got lock
|
||||
[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 5, Thread 2] Got lock
|
||||
[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
|
||||
Iteration 5 completed
|
||||
[Iteration 6, Thread 3] Got lock
|
||||
[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 6, Thread 1] Got lock
|
||||
[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 6, Thread 3] Got lock
|
||||
[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 6, Thread 2] Got lock
|
||||
[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
|
||||
Iteration 6 completed
|
||||
[Iteration 7, Thread 3] Got lock
|
||||
[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 7, Thread 2] Got lock
|
||||
[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 7, Thread 1] Got lock
|
||||
[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 7, Thread 2] Got lock
|
||||
[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 7, Thread 3] Got lock
|
||||
[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
|
||||
Iteration 7 completed
|
||||
[Iteration 8, Thread 1] Got lock
|
||||
[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
|
||||
[Iteration 8, Thread 2] Got lock
|
||||
[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
|
||||
[Iteration 8, Thread 3] Got lock
|
||||
[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
|
||||
[Iteration 8, Thread 2] Got lock
|
||||
[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
|
||||
Iteration 8 completed
|
||||
[Iteration 9, Thread 3] Got lock
|
||||
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 9, Thread 2] Got lock
|
||||
[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
|
||||
[Iteration 9, Thread 1] Got lock
|
||||
[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
|
||||
[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 9, Thread 2] Got lock
|
||||
[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
|
||||
Iteration 9 completed
|
||||
[Iteration 10, Thread 2] Got lock
|
||||
[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
|
||||
[Iteration 10, Thread 3] Got lock
|
||||
[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
|
||||
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
|
||||
[Iteration 10, Thread 1] Got lock
|
||||
[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
|
||||
[Iteration 10, Thread 2] Got lock
|
||||
[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
|
||||
Iteration 10 completed
|
||||
PASSED :-)
|
||||
Exiting @ tick 216428500 because target called exit()
|
||||
Exiting @ tick 117567000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue