test: Update stats for python object iteration.
Small changes in tests with data races due to new object creation order.
This commit is contained in:
Steve Reinhardt
parent
c2e1458746
commit
5577048bcf
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@ -5,3 +5,7 @@ hack: be nice to actually delete the event here
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gzip: stdout: Broken pipe
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gzip: stdout: Broken pipe
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gzip: stdout: Broken pipe
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gzip: stdout: Broken pipe
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@ -5,11 +5,11 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Feb 24 2010 23:12:40
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M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
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M5 started Feb 25 2010 02:28:17
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M5 executing on SC2B0619
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command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
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M5 compiled Jul 1 2010 14:37:40
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M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
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M5 started Jul 1 2010 14:37:50
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M5 executing on phenom
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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main dictionary has 1245 entries
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@ -1,27 +1,27 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1192031 # Simulator instruction rate (inst/s)
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host_mem_usage 196580 # Number of bytes of host memory used
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host_seconds 1.68 # Real time elapsed on the host
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host_tick_rate 440023932 # Simulator tick rate (ticks/s)
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host_inst_rate 1240283 # Simulator instruction rate (inst/s)
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host_mem_usage 197852 # Number of bytes of host memory used
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host_seconds 1.61 # Real time elapsed on the host
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host_tick_rate 457858198 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1999941 # Number of instructions simulated
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sim_seconds 0.000738 # Number of seconds simulated
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sim_ticks 738387000 # Number of ticks simulated
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system.cpu0.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_hits 124108 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_hits 56028 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
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@ -30,38 +30,38 @@ system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 #
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system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks.
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system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 180136 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
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system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
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system.cpu0.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits 180136 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles
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system.cpu0.dcache.overall_hits 180140 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 35212000 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
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system.cpu0.dcache.overall_misses 635 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -69,70 +69,70 @@ system.cpu0.dcache.overall_mshr_uncacheable_misses 0
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system.cpu0.dcache.replacements 61 # number of replacements
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system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.tagsinuse 272.914158 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 180308 # Total number of references to valid blocks.
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system.cpu0.dcache.tagsinuse 272.921161 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.writebacks 29 # number of writebacks
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system.cpu0.dtb.data_accesses 180789 # DTB accesses
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system.cpu0.dtb.data_accesses 180793 # DTB accesses
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system.cpu0.dtb.data_acv 0 # DTB access violations
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system.cpu0.dtb.data_hits 180771 # DTB hits
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system.cpu0.dtb.data_hits 180775 # DTB hits
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system.cpu0.dtb.data_misses 18 # DTB misses
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system.cpu0.dtb.fetch_accesses 0 # ITB accesses
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system.cpu0.dtb.fetch_acv 0 # ITB acv
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system.cpu0.dtb.fetch_hits 0 # ITB hits
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system.cpu0.dtb.fetch_misses 0 # ITB misses
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system.cpu0.dtb.read_accesses 124440 # DTB read accesses
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system.cpu0.dtb.read_accesses 124443 # DTB read accesses
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system.cpu0.dtb.read_acv 0 # DTB read access violations
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system.cpu0.dtb.read_hits 124432 # DTB read hits
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system.cpu0.dtb.read_hits 124435 # DTB read hits
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system.cpu0.dtb.read_misses 8 # DTB read misses
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system.cpu0.dtb.write_accesses 56349 # DTB write accesses
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system.cpu0.dtb.write_accesses 56350 # DTB write accesses
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system.cpu0.dtb.write_acv 0 # DTB write access violations
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system.cpu0.dtb.write_hits 56339 # DTB write hits
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system.cpu0.dtb.write_hits 56340 # DTB write hits
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system.cpu0.dtb.write_misses 10 # DTB write misses
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system.cpu0.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 499537 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
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system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
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system.cpu0.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
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system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
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system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
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system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks.
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system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 499537 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
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system.cpu0.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
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system.cpu0.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
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system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
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system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu0.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
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system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
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system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.occ_%::0 0.421784 # Average percentage of cache occupancy
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system.cpu0.icache.occ_blocks::0 215.953225 # Average occupied blocks per context
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system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses
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system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
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system.cpu0.icache.occ_%::0 0.421796 # Average percentage of cache occupancy
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system.cpu0.icache.occ_blocks::0 215.959580 # Average occupied blocks per context
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system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
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system.cpu0.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu0.icache.overall_hits 499537 # number of overall hits
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system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles
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system.cpu0.icache.overall_hits 499557 # number of overall hits
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system.cpu0.icache.overall_miss_latency 23479000 # number of overall miss cycles
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system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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system.cpu0.icache.overall_misses 463 # number of overall misses
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system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu0.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
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system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
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system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -140,8 +140,8 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0
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system.cpu0.icache.replacements 152 # number of replacements
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system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.icache.tagsinuse 215.953225 # Cycle average of tags in use
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system.cpu0.icache.total_refs 499537 # Total number of references to valid blocks.
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system.cpu0.icache.tagsinuse 215.959580 # Cycle average of tags in use
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system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
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system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.writebacks 0 # number of writebacks
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system.cpu0.idle_fraction 0 # Percentage of idle cycles
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@ -149,9 +149,9 @@ system.cpu0.itb.data_accesses 0 # DT
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system.cpu0.itb.data_acv 0 # DTB access violations
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system.cpu0.itb.data_hits 0 # DTB hits
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system.cpu0.itb.data_misses 0 # DTB misses
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system.cpu0.itb.fetch_accesses 500013 # ITB accesses
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system.cpu0.itb.fetch_accesses 500033 # ITB accesses
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system.cpu0.itb.fetch_acv 0 # ITB acv
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system.cpu0.itb.fetch_hits 500000 # ITB hits
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system.cpu0.itb.fetch_hits 500020 # ITB hits
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system.cpu0.itb.fetch_misses 13 # ITB misses
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.read_acv 0 # DTB read access violations
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@ -163,63 +163,63 @@ system.cpu0.itb.write_hits 0 # DT
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu0.numCycles 1476774 # number of cpu cycles simulated
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system.cpu0.num_insts 499981 # Number of instructions executed
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system.cpu0.num_refs 182218 # Number of memory references
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system.cpu0.num_insts 500001 # Number of instructions executed
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system.cpu0.num_refs 182222 # Number of memory references
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system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
system.cpu1.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_hits 124105 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
|
||||
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
|
||||
system.cpu1.dcache.ReadReq_hits 124109 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
|
||||
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
||||
system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency
|
||||
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency
|
||||
system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles
|
||||
system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_hits 180133 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_accesses 180772 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_hits 180137 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context
|
||||
system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
|
||||
system.cpu1.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context
|
||||
system.cpu1.dcache.overall_accesses 180772 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_hits 180133 # number of overall hits
|
||||
system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_hits 180137 # number of overall hits
|
||||
system.cpu1.dcache.overall_miss_latency 35229000 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_misses 635 # number of overall misses
|
||||
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_mshr_misses 635 # number of overall MSHR misses
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -227,70 +227,70 @@ system.cpu1.dcache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu1.dcache.replacements 61 # number of replacements
|
||||
system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.dcache.tagsinuse 272.910830 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 180305 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tagsinuse 272.916356 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 180309 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.writebacks 29 # number of writebacks
|
||||
system.cpu1.dtb.data_accesses 180786 # DTB accesses
|
||||
system.cpu1.dtb.data_accesses 180790 # DTB accesses
|
||||
system.cpu1.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu1.dtb.data_hits 180768 # DTB hits
|
||||
system.cpu1.dtb.data_hits 180772 # DTB hits
|
||||
system.cpu1.dtb.data_misses 18 # DTB misses
|
||||
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu1.dtb.read_accesses 124437 # DTB read accesses
|
||||
system.cpu1.dtb.read_accesses 124441 # DTB read accesses
|
||||
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu1.dtb.read_hits 124429 # DTB read hits
|
||||
system.cpu1.dtb.read_hits 124433 # DTB read hits
|
||||
system.cpu1.dtb.read_misses 8 # DTB read misses
|
||||
system.cpu1.dtb.write_accesses 56349 # DTB write accesses
|
||||
system.cpu1.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu1.dtb.write_hits 56339 # DTB write hits
|
||||
system.cpu1.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu1.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.ReadReq_hits 499531 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency
|
||||
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency
|
||||
system.cpu1.icache.ReadReq_hits 499540 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles
|
||||
system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 1078.920086 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
|
||||
system.cpu1.icache.demand_hits 499531 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.demand_accesses 500003 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
|
||||
system.cpu1.icache.demand_hits 499540 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
||||
system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.occ_%::0 0.421779 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_blocks::0 215.951034 # Average occupied blocks per context
|
||||
system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
|
||||
system.cpu1.icache.occ_%::0 0.421787 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_blocks::0 215.955045 # Average occupied blocks per context
|
||||
system.cpu1.icache.overall_accesses 500003 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_hits 499531 # number of overall hits
|
||||
system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles
|
||||
system.cpu1.icache.overall_hits 499540 # number of overall hits
|
||||
system.cpu1.icache.overall_miss_latency 23482000 # number of overall miss cycles
|
||||
system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_misses 463 # number of overall misses
|
||||
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu1.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
||||
system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
||||
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -298,8 +298,8 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu1.icache.replacements 152 # number of replacements
|
||||
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.icache.tagsinuse 215.951034 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 499531 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tagsinuse 215.955045 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 499540 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.writebacks 0 # number of writebacks
|
||||
system.cpu1.idle_fraction 0 # Percentage of idle cycles
|
||||
|
|
@ -307,9 +307,9 @@ system.cpu1.itb.data_accesses 0 # DT
|
|||
system.cpu1.itb.data_acv 0 # DTB access violations
|
||||
system.cpu1.itb.data_hits 0 # DTB hits
|
||||
system.cpu1.itb.data_misses 0 # DTB misses
|
||||
system.cpu1.itb.fetch_accesses 500007 # ITB accesses
|
||||
system.cpu1.itb.fetch_accesses 500016 # ITB accesses
|
||||
system.cpu1.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu1.itb.fetch_hits 499994 # ITB hits
|
||||
system.cpu1.itb.fetch_hits 500003 # ITB hits
|
||||
system.cpu1.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -321,23 +321,23 @@ system.cpu1.itb.write_hits 0 # DT
|
|||
system.cpu1.itb.write_misses 0 # DTB write misses
|
||||
system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu1.numCycles 1476774 # number of cpu cycles simulated
|
||||
system.cpu1.num_insts 499975 # Number of instructions executed
|
||||
system.cpu1.num_refs 182214 # Number of memory references
|
||||
system.cpu1.num_insts 499984 # Number of instructions executed
|
||||
system.cpu1.num_refs 182219 # Number of memory references
|
||||
system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.ReadReq_accesses 124432 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.ReadReq_avg_miss_latency 54932.098765 # average ReadReq miss latency
|
||||
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51932.098765 # average ReadReq mshr miss latency
|
||||
system.cpu2.dcache.ReadReq_hits 124108 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_miss_latency 17798000 # number of ReadReq miss cycles
|
||||
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_latency 16826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
||||
system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
|
||||
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
|
||||
system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
|
||||
system.cpu2.dcache.WriteReq_hits 56028 # number of WriteReq hits
|
||||
system.cpu2.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
|
||||
system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
||||
system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
|
||||
|
|
@ -346,38 +346,38 @@ system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 #
|
|||
system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
|
||||
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.avg_refs 389.434125 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
|
||||
system.cpu2.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.demand_accesses 180771 # number of demand (read+write) accesses
|
||||
system.cpu2.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_hits 180136 # number of demand (read+write) hits
|
||||
system.cpu2.dcache.demand_miss_latency 35230000 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
|
||||
system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
|
||||
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu2.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_latency 33325000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
|
||||
system.cpu2.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context
|
||||
system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
|
||||
system.cpu2.dcache.occ_%::0 0.533035 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_blocks::0 272.914158 # Average occupied blocks per context
|
||||
system.cpu2.dcache.overall_accesses 180771 # number of overall (read+write) accesses
|
||||
system.cpu2.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu2.dcache.overall_hits 180140 # number of overall hits
|
||||
system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles
|
||||
system.cpu2.dcache.overall_hits 180136 # number of overall hits
|
||||
system.cpu2.dcache.overall_miss_latency 35230000 # number of overall miss cycles
|
||||
system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_misses 635 # number of overall misses
|
||||
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu2.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_latency 33325000 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_mshr_misses 635 # number of overall MSHR misses
|
||||
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -385,70 +385,70 @@ system.cpu2.dcache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu2.dcache.replacements 61 # number of replacements
|
||||
system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu2.dcache.tagsinuse 272.921161 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tagsinuse 272.914158 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 180308 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.writebacks 29 # number of writebacks
|
||||
system.cpu2.dtb.data_accesses 180793 # DTB accesses
|
||||
system.cpu2.dtb.data_accesses 180789 # DTB accesses
|
||||
system.cpu2.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu2.dtb.data_hits 180775 # DTB hits
|
||||
system.cpu2.dtb.data_hits 180771 # DTB hits
|
||||
system.cpu2.dtb.data_misses 18 # DTB misses
|
||||
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu2.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu2.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu2.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu2.dtb.read_accesses 124443 # DTB read accesses
|
||||
system.cpu2.dtb.read_accesses 124440 # DTB read accesses
|
||||
system.cpu2.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu2.dtb.read_hits 124435 # DTB read hits
|
||||
system.cpu2.dtb.read_hits 124432 # DTB read hits
|
||||
system.cpu2.dtb.read_misses 8 # DTB read misses
|
||||
system.cpu2.dtb.write_accesses 56350 # DTB write accesses
|
||||
system.cpu2.dtb.write_accesses 56349 # DTB write accesses
|
||||
system.cpu2.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu2.dtb.write_hits 56340 # DTB write hits
|
||||
system.cpu2.dtb.write_hits 56339 # DTB write hits
|
||||
system.cpu2.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu2.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.ReadReq_hits 499557 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.ReadReq_avg_miss_latency 50723.542117 # average ReadReq miss latency
|
||||
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47723.542117 # average ReadReq mshr miss latency
|
||||
system.cpu2.icache.ReadReq_hits 499537 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_miss_latency 23485000 # number of ReadReq miss cycles
|
||||
system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
||||
system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
||||
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.avg_refs 1078.913607 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses
|
||||
system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
|
||||
system.cpu2.icache.demand_hits 499557 # number of demand (read+write) hits
|
||||
system.cpu2.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.demand_accesses 500000 # number of demand (read+write) accesses
|
||||
system.cpu2.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
|
||||
system.cpu2.icache.demand_hits 499537 # number of demand (read+write) hits
|
||||
system.cpu2.icache.demand_miss_latency 23485000 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
||||
system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
|
||||
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu2.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_latency 22096000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
||||
system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.icache.occ_%::0 0.421796 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_blocks::0 215.959580 # Average occupied blocks per context
|
||||
system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses
|
||||
system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
|
||||
system.cpu2.icache.occ_%::0 0.421784 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_blocks::0 215.953225 # Average occupied blocks per context
|
||||
system.cpu2.icache.overall_accesses 500000 # number of overall (read+write) accesses
|
||||
system.cpu2.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu2.icache.overall_hits 499557 # number of overall hits
|
||||
system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles
|
||||
system.cpu2.icache.overall_hits 499537 # number of overall hits
|
||||
system.cpu2.icache.overall_miss_latency 23485000 # number of overall miss cycles
|
||||
system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
||||
system.cpu2.icache.overall_misses 463 # number of overall misses
|
||||
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu2.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_latency 22096000 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
||||
system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
||||
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -456,8 +456,8 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu2.icache.replacements 152 # number of replacements
|
||||
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu2.icache.tagsinuse 215.959580 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 499557 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tagsinuse 215.953225 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 499537 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.writebacks 0 # number of writebacks
|
||||
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
||||
|
|
@ -465,9 +465,9 @@ system.cpu2.itb.data_accesses 0 # DT
|
|||
system.cpu2.itb.data_acv 0 # DTB access violations
|
||||
system.cpu2.itb.data_hits 0 # DTB hits
|
||||
system.cpu2.itb.data_misses 0 # DTB misses
|
||||
system.cpu2.itb.fetch_accesses 500033 # ITB accesses
|
||||
system.cpu2.itb.fetch_accesses 500013 # ITB accesses
|
||||
system.cpu2.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu2.itb.fetch_hits 500020 # ITB hits
|
||||
system.cpu2.itb.fetch_hits 500000 # ITB hits
|
||||
system.cpu2.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu2.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -479,63 +479,63 @@ system.cpu2.itb.write_hits 0 # DT
|
|||
system.cpu2.itb.write_misses 0 # DTB write misses
|
||||
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu2.numCycles 1476774 # number of cpu cycles simulated
|
||||
system.cpu2.num_insts 500001 # Number of instructions executed
|
||||
system.cpu2.num_refs 182222 # Number of memory references
|
||||
system.cpu2.num_insts 499981 # Number of instructions executed
|
||||
system.cpu2.num_refs 182218 # Number of memory references
|
||||
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
system.cpu3.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
|
||||
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
|
||||
system.cpu3.dcache.ReadReq_hits 124109 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
|
||||
system.cpu3.dcache.ReadReq_accesses 124429 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
|
||||
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
|
||||
system.cpu3.dcache.ReadReq_hits 124105 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
|
||||
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
|
||||
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
|
||||
system.cpu3.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
|
||||
system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu3.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency
|
||||
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency
|
||||
system.cpu3.dcache.WriteReq_avg_miss_latency 56041.800643 # average WriteReq miss latency
|
||||
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53041.800643 # average WriteReq mshr miss latency
|
||||
system.cpu3.dcache.WriteReq_hits 56028 # number of WriteReq hits
|
||||
system.cpu3.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles
|
||||
system.cpu3.dcache.WriteReq_miss_latency 17429000 # number of WriteReq miss cycles
|
||||
system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
|
||||
system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
|
||||
system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu3.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
|
||||
system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
|
||||
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.avg_refs 389.427646 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses
|
||||
system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency
|
||||
system.cpu3.dcache.demand_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
|
||||
system.cpu3.dcache.demand_hits 180137 # number of demand (read+write) hits
|
||||
system.cpu3.dcache.demand_miss_latency 35229000 # number of demand (read+write) miss cycles
|
||||
system.cpu3.dcache.demand_accesses 180768 # number of demand (read+write) accesses
|
||||
system.cpu3.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency
|
||||
system.cpu3.dcache.demand_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
|
||||
system.cpu3.dcache.demand_hits 180133 # number of demand (read+write) hits
|
||||
system.cpu3.dcache.demand_miss_latency 35220000 # number of demand (read+write) miss cycles
|
||||
system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
|
||||
system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
|
||||
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu3.dcache.demand_mshr_miss_latency 33324000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.dcache.demand_mshr_miss_latency 33315000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
|
||||
system.cpu3.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
|
||||
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.dcache.occ_%::0 0.533040 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_blocks::0 272.916356 # Average occupied blocks per context
|
||||
system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses
|
||||
system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency
|
||||
system.cpu3.dcache.occ_%::0 0.533029 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_blocks::0 272.910830 # Average occupied blocks per context
|
||||
system.cpu3.dcache.overall_accesses 180768 # number of overall (read+write) accesses
|
||||
system.cpu3.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu3.dcache.overall_hits 180137 # number of overall hits
|
||||
system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles
|
||||
system.cpu3.dcache.overall_hits 180133 # number of overall hits
|
||||
system.cpu3.dcache.overall_miss_latency 35220000 # number of overall miss cycles
|
||||
system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
|
||||
system.cpu3.dcache.overall_misses 635 # number of overall misses
|
||||
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu3.dcache.overall_mshr_miss_latency 33324000 # number of overall MSHR miss cycles
|
||||
system.cpu3.dcache.overall_mshr_miss_latency 33315000 # number of overall MSHR miss cycles
|
||||
system.cpu3.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
|
||||
system.cpu3.dcache.overall_mshr_misses 635 # number of overall MSHR misses
|
||||
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -543,70 +543,70 @@ system.cpu3.dcache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu3.dcache.replacements 61 # number of replacements
|
||||
system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu3.dcache.tagsinuse 272.916356 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 180309 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.tagsinuse 272.910830 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 180305 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.writebacks 29 # number of writebacks
|
||||
system.cpu3.dtb.data_accesses 180790 # DTB accesses
|
||||
system.cpu3.dtb.data_accesses 180786 # DTB accesses
|
||||
system.cpu3.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu3.dtb.data_hits 180772 # DTB hits
|
||||
system.cpu3.dtb.data_hits 180768 # DTB hits
|
||||
system.cpu3.dtb.data_misses 18 # DTB misses
|
||||
system.cpu3.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu3.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu3.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu3.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu3.dtb.read_accesses 124441 # DTB read accesses
|
||||
system.cpu3.dtb.read_accesses 124437 # DTB read accesses
|
||||
system.cpu3.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu3.dtb.read_hits 124433 # DTB read hits
|
||||
system.cpu3.dtb.read_hits 124429 # DTB read hits
|
||||
system.cpu3.dtb.read_misses 8 # DTB read misses
|
||||
system.cpu3.dtb.write_accesses 56349 # DTB write accesses
|
||||
system.cpu3.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu3.dtb.write_hits 56339 # DTB write hits
|
||||
system.cpu3.dtb.write_misses 10 # DTB write misses
|
||||
system.cpu3.icache.ReadReq_accesses 500003 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.icache.ReadReq_avg_miss_latency 50717.062635 # average ReadReq miss latency
|
||||
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47717.062635 # average ReadReq mshr miss latency
|
||||
system.cpu3.icache.ReadReq_hits 499540 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_miss_latency 23482000 # number of ReadReq miss cycles
|
||||
system.cpu3.icache.ReadReq_accesses 499994 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.icache.ReadReq_avg_miss_latency 50764.578834 # average ReadReq miss latency
|
||||
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47764.578834 # average ReadReq mshr miss latency
|
||||
system.cpu3.icache.ReadReq_hits 499531 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_miss_latency 23504000 # number of ReadReq miss cycles
|
||||
system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
|
||||
system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
|
||||
system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
|
||||
system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
|
||||
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.avg_refs 1078.900648 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses
|
||||
system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency
|
||||
system.cpu3.icache.demand_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
|
||||
system.cpu3.icache.demand_hits 499540 # number of demand (read+write) hits
|
||||
system.cpu3.icache.demand_miss_latency 23482000 # number of demand (read+write) miss cycles
|
||||
system.cpu3.icache.demand_accesses 499994 # number of demand (read+write) accesses
|
||||
system.cpu3.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency
|
||||
system.cpu3.icache.demand_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
|
||||
system.cpu3.icache.demand_hits 499531 # number of demand (read+write) hits
|
||||
system.cpu3.icache.demand_miss_latency 23504000 # number of demand (read+write) miss cycles
|
||||
system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
|
||||
system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
|
||||
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu3.icache.demand_mshr_miss_latency 22093000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.icache.demand_mshr_miss_latency 22115000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
|
||||
system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
|
||||
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.icache.occ_%::0 0.421787 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_blocks::0 215.955045 # Average occupied blocks per context
|
||||
system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses
|
||||
system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency
|
||||
system.cpu3.icache.occ_%::0 0.421779 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_blocks::0 215.951034 # Average occupied blocks per context
|
||||
system.cpu3.icache.overall_accesses 499994 # number of overall (read+write) accesses
|
||||
system.cpu3.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu3.icache.overall_hits 499540 # number of overall hits
|
||||
system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles
|
||||
system.cpu3.icache.overall_hits 499531 # number of overall hits
|
||||
system.cpu3.icache.overall_miss_latency 23504000 # number of overall miss cycles
|
||||
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
|
||||
system.cpu3.icache.overall_misses 463 # number of overall misses
|
||||
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu3.icache.overall_mshr_miss_latency 22093000 # number of overall MSHR miss cycles
|
||||
system.cpu3.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles
|
||||
system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
|
||||
system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
|
||||
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -614,8 +614,8 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0
|
|||
system.cpu3.icache.replacements 152 # number of replacements
|
||||
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu3.icache.tagsinuse 215.955045 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 499540 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.tagsinuse 215.951034 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 499531 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.writebacks 0 # number of writebacks
|
||||
system.cpu3.idle_fraction 0 # Percentage of idle cycles
|
||||
|
|
@ -623,9 +623,9 @@ system.cpu3.itb.data_accesses 0 # DT
|
|||
system.cpu3.itb.data_acv 0 # DTB access violations
|
||||
system.cpu3.itb.data_hits 0 # DTB hits
|
||||
system.cpu3.itb.data_misses 0 # DTB misses
|
||||
system.cpu3.itb.fetch_accesses 500016 # ITB accesses
|
||||
system.cpu3.itb.fetch_accesses 500007 # ITB accesses
|
||||
system.cpu3.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu3.itb.fetch_hits 500003 # ITB hits
|
||||
system.cpu3.itb.fetch_hits 499994 # ITB hits
|
||||
system.cpu3.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu3.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu3.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -637,8 +637,8 @@ system.cpu3.itb.write_hits 0 # DT
|
|||
system.cpu3.itb.write_misses 0 # DTB write misses
|
||||
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu3.numCycles 1476774 # number of cpu cycles simulated
|
||||
system.cpu3.num_insts 499984 # Number of instructions executed
|
||||
system.cpu3.num_refs 182219 # Number of memory references
|
||||
system.cpu3.num_insts 499975 # Number of instructions executed
|
||||
system.cpu3.num_refs 182214 # Number of memory references
|
||||
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -787,10 +787,10 @@ system.l2c.occ_%::1 0.005650 # Av
|
|||
system.l2c.occ_%::2 0.005650 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::3 0.005650 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::4 0.000464 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 370.294638 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 370.290796 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::2 370.305065 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::3 370.297695 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::0 370.305065 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 370.297695 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::2 370.294638 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::3 370.290796 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::4 30.383926 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
Redirecting stdout to build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
|
||||
Redirecting stderr to build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
|
|
@ -7,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 6 2010 04:01:36
|
||||
M5 revision ba1a0193c050 7448 default tip
|
||||
M5 started Jun 6 2010 04:01:52
|
||||
M5 executing on zizzer
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
M5 compiled Jul 1 2010 14:40:18
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:40:33
|
||||
M5 executing on phenom
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Init done
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:38:16
|
||||
M5 executing on SC2B0619
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
|
||||
M5 compiled Jul 1 2010 14:40:18
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:40:33
|
||||
M5 executing on phenom
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Init done
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1722968 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1115976 # Number of bytes of host memory used
|
||||
host_seconds 0.39 # Real time elapsed on the host
|
||||
host_tick_rate 222951866 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 339283 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1120212 # Number of bytes of host memory used
|
||||
host_seconds 2.00 # Real time elapsed on the host
|
||||
host_tick_rate 43931389 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 677340 # Number of instructions simulated
|
||||
sim_seconds 0.000088 # Number of seconds simulated
|
||||
sim_ticks 87713500 # Number of ticks simulated
|
||||
system.cpu0.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_hits 42192 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_misses 162 # number of ReadReq misses
|
||||
system.cpu0.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu0.dcache.SwapReq_hits 11 # number of SwapReq hits
|
||||
system.cpu0.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses
|
||||
system.cpu0.dcache.SwapReq_misses 55 # number of SwapReq misses
|
||||
system.cpu0.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_hits 15998 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_misses 109 # number of WriteReq misses
|
||||
system.cpu0.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_misses 151 # number of ReadReq misses
|
||||
system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits
|
||||
system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses
|
||||
system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses
|
||||
system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_hits 27561 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_misses 194 # number of WriteReq misses
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_refs 1206.107143 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.demand_accesses 58461 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_hits 58190 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits 81992 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_misses 271 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -42,48 +42,48 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu
|
|||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.occ_%::0 0.055509 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context
|
||||
system.cpu0.dcache.overall_accesses 58461 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.occ_%::0 0.284595 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context
|
||||
system.cpu0.dcache.overall_accesses 82337 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu0.dcache.overall_hits 58190 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits 81992 # number of overall hits
|
||||
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_misses 271 # number of overall misses
|
||||
system.cpu0.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_misses 345 # number of overall misses
|
||||
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu0.dcache.replacements 2 # number of replacements
|
||||
system.cpu0.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.replacements 9 # number of replacements
|
||||
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu0.dcache.tagsinuse 28.420699 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 33771 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use
|
||||
system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.writebacks 1 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_hits 167008 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_misses 358 # number of ReadReq misses
|
||||
system.cpu0.dcache.writebacks 6 # number of writebacks
|
||||
system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses
|
||||
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu0.icache.avg_refs 466.502793 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.demand_accesses 167366 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu0.icache.demand_hits 167008 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu0.icache.demand_miss_rate 0.002139 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_misses 358 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses
|
||||
system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -91,62 +91,62 @@ system.cpu0.icache.demand_mshr_misses 0 # nu
|
|||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.occ_%::0 0.146046 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_blocks::0 74.775474 # Average occupied blocks per context
|
||||
system.cpu0.icache.overall_accesses 167366 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.occ_%::0 0.435073 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context
|
||||
system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu0.icache.overall_hits 167008 # number of overall hits
|
||||
system.cpu0.icache.overall_hits 174934 # number of overall hits
|
||||
system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_rate 0.002139 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_misses 358 # number of overall misses
|
||||
system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses
|
||||
system.cpu0.icache.overall_misses 467 # number of overall misses
|
||||
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu0.icache.replacements 278 # number of replacements
|
||||
system.cpu0.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.replacements 215 # number of replacements
|
||||
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu0.icache.tagsinuse 74.775474 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 167008 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tagsinuse 222.757301 # Cycle average of tags in use
|
||||
system.cpu0.icache.total_refs 174934 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.writebacks 0 # number of writebacks
|
||||
system.cpu0.idle_fraction 0.045871 # Percentage of idle cycles
|
||||
system.cpu0.not_idle_fraction 0.954129 # Percentage of non-idle cycles
|
||||
system.cpu0.numCycles 173308 # number of cpu cycles simulated
|
||||
system.cpu0.num_insts 167334 # Number of instructions executed
|
||||
system.cpu0.num_refs 58537 # Number of memory references
|
||||
system.cpu0.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu0.numCycles 175428 # number of cpu cycles simulated
|
||||
system.cpu0.num_insts 175339 # Number of instructions executed
|
||||
system.cpu0.num_refs 82398 # Number of memory references
|
||||
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
|
||||
system.cpu1.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_hits 41299 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_misses 159 # number of ReadReq misses
|
||||
system.cpu1.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu1.dcache.SwapReq_hits 15 # number of SwapReq hits
|
||||
system.cpu1.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses
|
||||
system.cpu1.dcache.SwapReq_misses 55 # number of SwapReq misses
|
||||
system.cpu1.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_hits 14260 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_misses 102 # number of WriteReq misses
|
||||
system.cpu1.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_hits 40468 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_misses 176 # number of ReadReq misses
|
||||
system.cpu1.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits
|
||||
system.cpu1.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
|
||||
system.cpu1.dcache.SwapReq_misses 57 # number of SwapReq misses
|
||||
system.cpu1.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_hits 12563 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_misses 106 # number of WriteReq misses
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_refs 1045.137931 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.demand_accesses 55820 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_accesses 53313 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu1.dcache.demand_hits 55559 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits 53031 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu1.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_misses 261 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_misses 282 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -154,16 +154,16 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu
|
|||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.occ_%::0 0.053884 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context
|
||||
system.cpu1.dcache.overall_accesses 55820 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.occ_%::0 0.056783 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context
|
||||
system.cpu1.dcache.overall_accesses 53313 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu1.dcache.overall_hits 55559 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits 53031 # number of overall hits
|
||||
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu1.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_misses 261 # number of overall misses
|
||||
system.cpu1.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_misses 282 # number of overall misses
|
||||
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -171,31 +171,31 @@ system.cpu1.dcache.overall_mshr_misses 0 # nu
|
|||
system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu1.dcache.replacements 2 # number of replacements
|
||||
system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.dcache.tagsinuse 27.588376 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 30309 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use
|
||||
system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.writebacks 1 # number of writebacks
|
||||
system.cpu1.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_hits 166942 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_misses 359 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_hits 167072 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_misses 358 # number of ReadReq misses
|
||||
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.icache.avg_refs 465.019499 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.demand_accesses 167301 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses 167430 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu1.icache.demand_hits 166942 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits 167072 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu1.icache.demand_miss_rate 0.002146 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_misses 359 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_miss_rate 0.002138 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_misses 358 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -203,61 +203,61 @@ system.cpu1.icache.demand_mshr_misses 0 # nu
|
|||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.occ_%::0 0.142322 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_blocks::0 72.869097 # Average occupied blocks per context
|
||||
system.cpu1.icache.overall_accesses 167301 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.occ_%::0 0.149895 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.occ_blocks::0 76.746014 # Average occupied blocks per context
|
||||
system.cpu1.icache.overall_accesses 167430 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu1.icache.overall_hits 166942 # number of overall hits
|
||||
system.cpu1.icache.overall_hits 167072 # number of overall hits
|
||||
system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu1.icache.overall_miss_rate 0.002146 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_misses 359 # number of overall misses
|
||||
system.cpu1.icache.overall_miss_rate 0.002138 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_misses 358 # number of overall misses
|
||||
system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu1.icache.replacements 279 # number of replacements
|
||||
system.cpu1.icache.sampled_refs 359 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.replacements 278 # number of replacements
|
||||
system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.icache.tagsinuse 72.869097 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 166942 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tagsinuse 76.746014 # Cycle average of tags in use
|
||||
system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.writebacks 0 # number of writebacks
|
||||
system.cpu1.idle_fraction 0.046241 # Percentage of idle cycles
|
||||
system.cpu1.not_idle_fraction 0.953759 # Percentage of non-idle cycles
|
||||
system.cpu1.numCycles 173307 # number of cpu cycles simulated
|
||||
system.cpu1.num_insts 167269 # Number of instructions executed
|
||||
system.cpu1.num_refs 55900 # Number of memory references
|
||||
system.cpu2.dcache.ReadReq_accesses 54582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.ReadReq_hits 54431 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_miss_rate 0.002766 # miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.ReadReq_misses 151 # number of ReadReq misses
|
||||
system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu2.dcache.SwapReq_hits 15 # number of SwapReq hits
|
||||
system.cpu2.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses
|
||||
system.cpu2.dcache.SwapReq_misses 27 # number of SwapReq misses
|
||||
system.cpu2.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.dcache.WriteReq_hits 27561 # number of WriteReq hits
|
||||
system.cpu2.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses
|
||||
system.cpu2.dcache.WriteReq_misses 194 # number of WriteReq misses
|
||||
system.cpu1.idle_fraction 0.045506 # Percentage of idle cycles
|
||||
system.cpu1.not_idle_fraction 0.954494 # Percentage of non-idle cycles
|
||||
system.cpu1.numCycles 173308 # number of cpu cycles simulated
|
||||
system.cpu1.num_insts 167398 # Number of instructions executed
|
||||
system.cpu1.num_refs 53394 # Number of memory references
|
||||
system.cpu2.dcache.ReadReq_accesses 42354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.dcache.ReadReq_hits 42192 # number of ReadReq hits
|
||||
system.cpu2.dcache.ReadReq_miss_rate 0.003825 # miss rate for ReadReq accesses
|
||||
system.cpu2.dcache.ReadReq_misses 162 # number of ReadReq misses
|
||||
system.cpu2.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu2.dcache.SwapReq_hits 11 # number of SwapReq hits
|
||||
system.cpu2.dcache.SwapReq_miss_rate 0.833333 # miss rate for SwapReq accesses
|
||||
system.cpu2.dcache.SwapReq_misses 55 # number of SwapReq misses
|
||||
system.cpu2.dcache.WriteReq_accesses 16107 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.dcache.WriteReq_hits 15998 # number of WriteReq hits
|
||||
system.cpu2.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses
|
||||
system.cpu2.dcache.WriteReq_misses 109 # number of WriteReq misses
|
||||
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu2.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks.
|
||||
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.dcache.demand_accesses 82337 # number of demand (read+write) accesses
|
||||
system.cpu2.dcache.demand_accesses 58461 # number of demand (read+write) accesses
|
||||
system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu2.dcache.demand_hits 81992 # number of demand (read+write) hits
|
||||
system.cpu2.dcache.demand_hits 58190 # number of demand (read+write) hits
|
||||
system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu2.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses
|
||||
system.cpu2.dcache.demand_misses 345 # number of demand (read+write) misses
|
||||
system.cpu2.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses
|
||||
system.cpu2.dcache.demand_misses 271 # number of demand (read+write) misses
|
||||
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -265,48 +265,48 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu
|
|||
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.dcache.occ_%::0 0.284595 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context
|
||||
system.cpu2.dcache.overall_accesses 82337 # number of overall (read+write) accesses
|
||||
system.cpu2.dcache.occ_%::0 0.055509 # Average percentage of cache occupancy
|
||||
system.cpu2.dcache.occ_blocks::0 28.420699 # Average occupied blocks per context
|
||||
system.cpu2.dcache.overall_accesses 58461 # number of overall (read+write) accesses
|
||||
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu2.dcache.overall_hits 81992 # number of overall hits
|
||||
system.cpu2.dcache.overall_hits 58190 # number of overall hits
|
||||
system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu2.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_misses 345 # number of overall misses
|
||||
system.cpu2.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_misses 271 # number of overall misses
|
||||
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu2.dcache.replacements 9 # number of replacements
|
||||
system.cpu2.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.replacements 2 # number of replacements
|
||||
system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
||||
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu2.dcache.tagsinuse 145.712770 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 61599 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use
|
||||
system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks.
|
||||
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.dcache.writebacks 6 # number of writebacks
|
||||
system.cpu2.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.ReadReq_hits 174934 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses
|
||||
system.cpu2.icache.ReadReq_misses 467 # number of ReadReq misses
|
||||
system.cpu2.dcache.writebacks 1 # number of writebacks
|
||||
system.cpu2.icache.ReadReq_accesses 167366 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.icache.ReadReq_hits 167008 # number of ReadReq hits
|
||||
system.cpu2.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses
|
||||
system.cpu2.icache.ReadReq_misses 358 # number of ReadReq misses
|
||||
system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu2.icache.avg_refs 374.591006 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks.
|
||||
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.icache.demand_accesses 175401 # number of demand (read+write) accesses
|
||||
system.cpu2.icache.demand_accesses 167366 # number of demand (read+write) accesses
|
||||
system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu2.icache.demand_hits 174934 # number of demand (read+write) hits
|
||||
system.cpu2.icache.demand_hits 167008 # number of demand (read+write) hits
|
||||
system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu2.icache.demand_miss_rate 0.002662 # miss rate for demand accesses
|
||||
system.cpu2.icache.demand_misses 467 # number of demand (read+write) misses
|
||||
system.cpu2.icache.demand_miss_rate 0.002139 # miss rate for demand accesses
|
||||
system.cpu2.icache.demand_misses 358 # number of demand (read+write) misses
|
||||
system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -314,61 +314,61 @@ system.cpu2.icache.demand_mshr_misses 0 # nu
|
|||
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.icache.occ_%::0 0.435073 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_blocks::0 222.757301 # Average occupied blocks per context
|
||||
system.cpu2.icache.overall_accesses 175401 # number of overall (read+write) accesses
|
||||
system.cpu2.icache.occ_%::0 0.146046 # Average percentage of cache occupancy
|
||||
system.cpu2.icache.occ_blocks::0 74.775474 # Average occupied blocks per context
|
||||
system.cpu2.icache.overall_accesses 167366 # number of overall (read+write) accesses
|
||||
system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu2.icache.overall_hits 174934 # number of overall hits
|
||||
system.cpu2.icache.overall_hits 167008 # number of overall hits
|
||||
system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu2.icache.overall_miss_rate 0.002662 # miss rate for overall accesses
|
||||
system.cpu2.icache.overall_misses 467 # number of overall misses
|
||||
system.cpu2.icache.overall_miss_rate 0.002139 # miss rate for overall accesses
|
||||
system.cpu2.icache.overall_misses 358 # number of overall misses
|
||||
system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu2.icache.replacements 215 # number of replacements
|
||||
system.cpu2.icache.sampled_refs 467 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.replacements 278 # number of replacements
|
||||
system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu2.icache.tagsinuse 222.757301 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 174934 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.tagsinuse 74.775474 # Cycle average of tags in use
|
||||
system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks.
|
||||
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.icache.writebacks 0 # number of writebacks
|
||||
system.cpu2.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu2.numCycles 175428 # number of cpu cycles simulated
|
||||
system.cpu2.num_insts 175339 # Number of instructions executed
|
||||
system.cpu2.num_refs 82398 # Number of memory references
|
||||
system.cpu3.dcache.ReadReq_accesses 40644 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.dcache.ReadReq_hits 40468 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_miss_rate 0.004330 # miss rate for ReadReq accesses
|
||||
system.cpu3.dcache.ReadReq_misses 176 # number of ReadReq misses
|
||||
system.cpu3.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits
|
||||
system.cpu3.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses
|
||||
system.cpu3.dcache.SwapReq_misses 57 # number of SwapReq misses
|
||||
system.cpu3.dcache.WriteReq_accesses 12669 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu3.dcache.WriteReq_hits 12563 # number of WriteReq hits
|
||||
system.cpu3.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses
|
||||
system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses
|
||||
system.cpu2.idle_fraction 0.045871 # Percentage of idle cycles
|
||||
system.cpu2.not_idle_fraction 0.954129 # Percentage of non-idle cycles
|
||||
system.cpu2.numCycles 173308 # number of cpu cycles simulated
|
||||
system.cpu2.num_insts 167334 # Number of instructions executed
|
||||
system.cpu2.num_refs 58537 # Number of memory references
|
||||
system.cpu3.dcache.ReadReq_accesses 41458 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.dcache.ReadReq_hits 41299 # number of ReadReq hits
|
||||
system.cpu3.dcache.ReadReq_miss_rate 0.003835 # miss rate for ReadReq accesses
|
||||
system.cpu3.dcache.ReadReq_misses 159 # number of ReadReq misses
|
||||
system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu3.dcache.SwapReq_hits 15 # number of SwapReq hits
|
||||
system.cpu3.dcache.SwapReq_miss_rate 0.785714 # miss rate for SwapReq accesses
|
||||
system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses
|
||||
system.cpu3.dcache.WriteReq_accesses 14362 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu3.dcache.WriteReq_hits 14260 # number of WriteReq hits
|
||||
system.cpu3.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses
|
||||
system.cpu3.dcache.WriteReq_misses 102 # number of WriteReq misses
|
||||
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu3.dcache.avg_refs 960.321429 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks.
|
||||
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.dcache.demand_accesses 53313 # number of demand (read+write) accesses
|
||||
system.cpu3.dcache.demand_accesses 55820 # number of demand (read+write) accesses
|
||||
system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu3.dcache.demand_hits 53031 # number of demand (read+write) hits
|
||||
system.cpu3.dcache.demand_hits 55559 # number of demand (read+write) hits
|
||||
system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu3.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses
|
||||
system.cpu3.dcache.demand_misses 282 # number of demand (read+write) misses
|
||||
system.cpu3.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses
|
||||
system.cpu3.dcache.demand_misses 261 # number of demand (read+write) misses
|
||||
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -376,16 +376,16 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu
|
|||
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.dcache.occ_%::0 0.056783 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_blocks::0 29.073016 # Average occupied blocks per context
|
||||
system.cpu3.dcache.overall_accesses 53313 # number of overall (read+write) accesses
|
||||
system.cpu3.dcache.occ_%::0 0.053884 # Average percentage of cache occupancy
|
||||
system.cpu3.dcache.occ_blocks::0 27.588376 # Average occupied blocks per context
|
||||
system.cpu3.dcache.overall_accesses 55820 # number of overall (read+write) accesses
|
||||
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu3.dcache.overall_hits 53031 # number of overall hits
|
||||
system.cpu3.dcache.overall_hits 55559 # number of overall hits
|
||||
system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu3.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses
|
||||
system.cpu3.dcache.overall_misses 282 # number of overall misses
|
||||
system.cpu3.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses
|
||||
system.cpu3.dcache.overall_misses 261 # number of overall misses
|
||||
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -393,31 +393,31 @@ system.cpu3.dcache.overall_mshr_misses 0 # nu
|
|||
system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu3.dcache.replacements 2 # number of replacements
|
||||
system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
||||
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu3.dcache.tagsinuse 29.073016 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 26889 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use
|
||||
system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks.
|
||||
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.dcache.writebacks 1 # number of writebacks
|
||||
system.cpu3.icache.ReadReq_accesses 167430 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.icache.ReadReq_hits 167072 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses
|
||||
system.cpu3.icache.ReadReq_misses 358 # number of ReadReq misses
|
||||
system.cpu3.icache.ReadReq_accesses 167301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.icache.ReadReq_hits 166942 # number of ReadReq hits
|
||||
system.cpu3.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses
|
||||
system.cpu3.icache.ReadReq_misses 359 # number of ReadReq misses
|
||||
system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu3.icache.avg_refs 466.681564 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks.
|
||||
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.icache.demand_accesses 167430 # number of demand (read+write) accesses
|
||||
system.cpu3.icache.demand_accesses 167301 # number of demand (read+write) accesses
|
||||
system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu3.icache.demand_hits 167072 # number of demand (read+write) hits
|
||||
system.cpu3.icache.demand_hits 166942 # number of demand (read+write) hits
|
||||
system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu3.icache.demand_miss_rate 0.002138 # miss rate for demand accesses
|
||||
system.cpu3.icache.demand_misses 358 # number of demand (read+write) misses
|
||||
system.cpu3.icache.demand_miss_rate 0.002146 # miss rate for demand accesses
|
||||
system.cpu3.icache.demand_misses 359 # number of demand (read+write) misses
|
||||
system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -425,72 +425,72 @@ system.cpu3.icache.demand_mshr_misses 0 # nu
|
|||
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.icache.occ_%::0 0.149895 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_blocks::0 76.746014 # Average occupied blocks per context
|
||||
system.cpu3.icache.overall_accesses 167430 # number of overall (read+write) accesses
|
||||
system.cpu3.icache.occ_%::0 0.142322 # Average percentage of cache occupancy
|
||||
system.cpu3.icache.occ_blocks::0 72.869097 # Average occupied blocks per context
|
||||
system.cpu3.icache.overall_accesses 167301 # number of overall (read+write) accesses
|
||||
system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu3.icache.overall_hits 167072 # number of overall hits
|
||||
system.cpu3.icache.overall_hits 166942 # number of overall hits
|
||||
system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu3.icache.overall_miss_rate 0.002138 # miss rate for overall accesses
|
||||
system.cpu3.icache.overall_misses 358 # number of overall misses
|
||||
system.cpu3.icache.overall_miss_rate 0.002146 # miss rate for overall accesses
|
||||
system.cpu3.icache.overall_misses 359 # number of overall misses
|
||||
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
|
||||
system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu3.icache.replacements 278 # number of replacements
|
||||
system.cpu3.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.replacements 279 # number of replacements
|
||||
system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks.
|
||||
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu3.icache.tagsinuse 76.746014 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 167072 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.tagsinuse 72.869097 # Cycle average of tags in use
|
||||
system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks.
|
||||
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.icache.writebacks 0 # number of writebacks
|
||||
system.cpu3.idle_fraction 0.045506 # Percentage of idle cycles
|
||||
system.cpu3.not_idle_fraction 0.954494 # Percentage of non-idle cycles
|
||||
system.cpu3.numCycles 173308 # number of cpu cycles simulated
|
||||
system.cpu3.num_insts 167398 # Number of instructions executed
|
||||
system.cpu3.num_refs 53394 # Number of memory references
|
||||
system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::2 99 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu3.idle_fraction 0.046241 # Percentage of idle cycles
|
||||
system.cpu3.not_idle_fraction 0.953759 # Percentage of non-idle cycles
|
||||
system.cpu3.numCycles 173307 # number of cpu cycles simulated
|
||||
system.cpu3.num_insts 167269 # Number of instructions executed
|
||||
system.cpu3.num_refs 55900 # Number of memory references
|
||||
system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::2 99 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::0 99 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::1 13 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::2 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
|
||||
system.l2c.ReadReq_accesses::0 370 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 371 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::2 538 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::3 370 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::0 538 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 370 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::2 370 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::3 371 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits::0 367 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 368 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::2 190 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::3 301 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::0 190 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 301 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::2 367 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::3 368 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate::0 0.008108 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.008086 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::2 0.646840 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::3 0.186486 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::0 0.646840 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.186486 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::2 0.008108 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::3 0.008086 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.849521 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::2 348 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::3 69 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::0 348 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 69 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::2 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::3 3 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_accesses::0 20 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::2 48 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 106 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
|
||||
|
|
@ -498,9 +498,9 @@ system.l2c.UpgradeReq_miss_rate::1 1 # mi
|
|||
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 20 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::0 48 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::2 48 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 106 # number of UpgradeReq misses
|
||||
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -515,9 +515,9 @@ system.l2c.blocked::no_targets 0 # nu
|
|||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses::0 382 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::0 637 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 383 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::2 637 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::2 382 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::3 383 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
|
|
@ -526,21 +526,21 @@ system.l2c.demand_avg_miss_latency::2 0 # av
|
|||
system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.l2c.demand_hits::0 367 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 368 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::2 190 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::3 301 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::0 190 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 301 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::2 367 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::3 368 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1226 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.039267 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.039164 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::2 0.701727 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::3 0.214099 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::0 0.701727 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.214099 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::2 0.039267 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::3 0.039164 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.994258 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::2 447 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::3 82 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::0 447 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 82 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::2 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::3 15 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 559 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
|
|
@ -553,19 +553,19 @@ system.l2c.demand_mshr_misses 0 # nu
|
|||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.occ_%::0 0.000044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.000029 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::2 0.004314 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::3 0.001011 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::0 0.004314 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.001011 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::2 0.000044 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::3 0.000029 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::4 0.000098 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 2.865859 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 1.883074 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::2 282.753459 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::3 66.228089 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::0 282.753459 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::4 6.390048 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 382 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::2 637 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::3 383 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
|
||||
|
|
@ -575,21 +575,21 @@ system.l2c.overall_avg_miss_latency::3 0 # av
|
|||
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits::0 367 # number of overall hits
|
||||
system.l2c.overall_hits::1 368 # number of overall hits
|
||||
system.l2c.overall_hits::2 190 # number of overall hits
|
||||
system.l2c.overall_hits::3 301 # number of overall hits
|
||||
system.l2c.overall_hits::0 190 # number of overall hits
|
||||
system.l2c.overall_hits::1 301 # number of overall hits
|
||||
system.l2c.overall_hits::2 367 # number of overall hits
|
||||
system.l2c.overall_hits::3 368 # number of overall hits
|
||||
system.l2c.overall_hits::total 1226 # number of overall hits
|
||||
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.039267 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.039164 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::2 0.701727 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::3 0.214099 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::0 0.701727 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.214099 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::2 0.039267 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::3 0.039164 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.994258 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 15 # number of overall misses
|
||||
system.l2c.overall_misses::1 15 # number of overall misses
|
||||
system.l2c.overall_misses::2 447 # number of overall misses
|
||||
system.l2c.overall_misses::3 82 # number of overall misses
|
||||
system.l2c.overall_misses::0 447 # number of overall misses
|
||||
system.l2c.overall_misses::1 82 # number of overall misses
|
||||
system.l2c.overall_misses::2 15 # number of overall misses
|
||||
system.l2c.overall_misses::3 15 # number of overall misses
|
||||
system.l2c.overall_misses::total 559 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 25 2010 03:11:27
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 03:38:17
|
||||
M5 executing on SC2B0619
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
|
||||
M5 compiled Jul 1 2010 14:40:18
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:40:36
|
||||
M5 executing on phenom
|
||||
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Init done
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -22,7 +22,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports0.port[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
|
|
@ -37,7 +37,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports1.port[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
|
|
@ -52,7 +52,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports2.port[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
|
|
@ -67,7 +67,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports3.port[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
|
|
@ -82,7 +82,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports4.port[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
|
|
@ -97,7 +97,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports5.port[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
|
|
@ -112,7 +112,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports6.port[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
|
|
@ -127,7 +127,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -147,11 +147,11 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
|
|
@ -164,6 +164,102 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
|
|
@ -202,41 +298,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -254,41 +337,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -306,41 +376,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -358,41 +415,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -410,41 +454,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -462,41 +493,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -514,41 +532,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -566,41 +571,28 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu7: completed 10000 read accesses @373359
|
||||
system.cpu1: completed 10000 read accesses @375374
|
||||
system.cpu0: completed 10000 read accesses @376725
|
||||
system.cpu2: completed 10000 read accesses @380778
|
||||
system.cpu5: completed 10000 read accesses @382682
|
||||
system.cpu3: completed 10000 read accesses @383505
|
||||
system.cpu4: completed 10000 read accesses @386561
|
||||
system.cpu6: completed 10000 read accesses @389125
|
||||
system.cpu1: completed 20000 read accesses @745885
|
||||
system.cpu0: completed 20000 read accesses @748353
|
||||
system.cpu2: completed 20000 read accesses @753861
|
||||
system.cpu7: completed 20000 read accesses @758042
|
||||
system.cpu5: completed 20000 read accesses @759129
|
||||
system.cpu3: completed 20000 read accesses @764814
|
||||
system.cpu4: completed 20000 read accesses @768939
|
||||
system.cpu6: completed 20000 read accesses @774936
|
||||
system.cpu1: completed 30000 read accesses @1121924
|
||||
system.cpu2: completed 30000 read accesses @1124427
|
||||
system.cpu0: completed 30000 read accesses @1125253
|
||||
system.cpu7: completed 30000 read accesses @1139134
|
||||
system.cpu4: completed 30000 read accesses @1139334
|
||||
system.cpu3: completed 30000 read accesses @1144574
|
||||
system.cpu5: completed 30000 read accesses @1145748
|
||||
system.cpu6: completed 30000 read accesses @1147208
|
||||
system.cpu0: completed 40000 read accesses @1492239
|
||||
system.cpu1: completed 40000 read accesses @1495604
|
||||
system.cpu2: completed 40000 read accesses @1499940
|
||||
system.cpu4: completed 40000 read accesses @1518641
|
||||
system.cpu7: completed 40000 read accesses @1518771
|
||||
system.cpu5: completed 40000 read accesses @1528667
|
||||
system.cpu6: completed 40000 read accesses @1530209
|
||||
system.cpu3: completed 40000 read accesses @1537371
|
||||
system.cpu0: completed 50000 read accesses @1865558
|
||||
system.cpu1: completed 50000 read accesses @1868280
|
||||
system.cpu2: completed 50000 read accesses @1884528
|
||||
system.cpu7: completed 50000 read accesses @1899621
|
||||
system.cpu4: completed 50000 read accesses @1903698
|
||||
system.cpu5: completed 50000 read accesses @1909143
|
||||
system.cpu3: completed 50000 read accesses @1910503
|
||||
system.cpu6: completed 50000 read accesses @1915590
|
||||
system.cpu0: completed 60000 read accesses @2235441
|
||||
system.cpu1: completed 60000 read accesses @2240292
|
||||
system.cpu2: completed 60000 read accesses @2270206
|
||||
system.cpu4: completed 60000 read accesses @2278819
|
||||
system.cpu7: completed 60000 read accesses @2284397
|
||||
system.cpu5: completed 60000 read accesses @2288761
|
||||
system.cpu3: completed 60000 read accesses @2289377
|
||||
system.cpu6: completed 60000 read accesses @2312599
|
||||
system.cpu0: completed 70000 read accesses @2605926
|
||||
system.cpu1: completed 70000 read accesses @2606409
|
||||
system.cpu4: completed 70000 read accesses @2648937
|
||||
system.cpu2: completed 70000 read accesses @2655948
|
||||
system.cpu5: completed 70000 read accesses @2662046
|
||||
system.cpu3: completed 70000 read accesses @2664803
|
||||
system.cpu7: completed 70000 read accesses @2675843
|
||||
system.cpu6: completed 70000 read accesses @2704307
|
||||
system.cpu1: completed 80000 read accesses @2972591
|
||||
system.cpu0: completed 80000 read accesses @2986258
|
||||
system.cpu3: completed 80000 read accesses @3027695
|
||||
system.cpu4: completed 80000 read accesses @3034526
|
||||
system.cpu2: completed 80000 read accesses @3036101
|
||||
system.cpu5: completed 80000 read accesses @3049670
|
||||
system.cpu7: completed 80000 read accesses @3053840
|
||||
system.cpu6: completed 80000 read accesses @3088364
|
||||
system.cpu1: completed 90000 read accesses @3348204
|
||||
system.cpu0: completed 90000 read accesses @3355393
|
||||
system.cpu3: completed 90000 read accesses @3393344
|
||||
system.cpu2: completed 90000 read accesses @3410223
|
||||
system.cpu4: completed 90000 read accesses @3417605
|
||||
system.cpu5: completed 90000 read accesses @3432894
|
||||
system.cpu7: completed 90000 read accesses @3437480
|
||||
system.cpu6: completed 90000 read accesses @3470461
|
||||
system.cpu1: completed 100000 read accesses @3719757
|
||||
system.cpu5: completed 10000 read accesses @370057
|
||||
system.cpu1: completed 10000 read accesses @372602
|
||||
system.cpu0: completed 10000 read accesses @380072
|
||||
system.cpu3: completed 10000 read accesses @380676
|
||||
system.cpu4: completed 10000 read accesses @383371
|
||||
system.cpu2: completed 10000 read accesses @385679
|
||||
system.cpu6: completed 10000 read accesses @386340
|
||||
system.cpu7: completed 10000 read accesses @389231
|
||||
system.cpu5: completed 20000 read accesses @746317
|
||||
system.cpu0: completed 20000 read accesses @748763
|
||||
system.cpu3: completed 20000 read accesses @752788
|
||||
system.cpu1: completed 20000 read accesses @753263
|
||||
system.cpu4: completed 20000 read accesses @763818
|
||||
system.cpu6: completed 20000 read accesses @765866
|
||||
system.cpu2: completed 20000 read accesses @771677
|
||||
system.cpu7: completed 20000 read accesses @772771
|
||||
system.cpu0: completed 30000 read accesses @1112242
|
||||
system.cpu1: completed 30000 read accesses @1129327
|
||||
system.cpu3: completed 30000 read accesses @1129794
|
||||
system.cpu5: completed 30000 read accesses @1131833
|
||||
system.cpu2: completed 30000 read accesses @1142425
|
||||
system.cpu4: completed 30000 read accesses @1144628
|
||||
system.cpu6: completed 30000 read accesses @1153431
|
||||
system.cpu7: completed 30000 read accesses @1154016
|
||||
system.cpu0: completed 40000 read accesses @1484294
|
||||
system.cpu1: completed 40000 read accesses @1505996
|
||||
system.cpu3: completed 40000 read accesses @1507887
|
||||
system.cpu2: completed 40000 read accesses @1512800
|
||||
system.cpu4: completed 40000 read accesses @1520410
|
||||
system.cpu5: completed 40000 read accesses @1522723
|
||||
system.cpu6: completed 40000 read accesses @1538655
|
||||
system.cpu7: completed 40000 read accesses @1539216
|
||||
system.cpu0: completed 50000 read accesses @1860160
|
||||
system.cpu3: completed 50000 read accesses @1882708
|
||||
system.cpu1: completed 50000 read accesses @1883329
|
||||
system.cpu2: completed 50000 read accesses @1891575
|
||||
system.cpu4: completed 50000 read accesses @1896200
|
||||
system.cpu5: completed 50000 read accesses @1912575
|
||||
system.cpu6: completed 50000 read accesses @1917985
|
||||
system.cpu7: completed 50000 read accesses @1929708
|
||||
system.cpu0: completed 60000 read accesses @2233080
|
||||
system.cpu1: completed 60000 read accesses @2253689
|
||||
system.cpu3: completed 60000 read accesses @2259715
|
||||
system.cpu2: completed 60000 read accesses @2264515
|
||||
system.cpu4: completed 60000 read accesses @2278281
|
||||
system.cpu5: completed 60000 read accesses @2291280
|
||||
system.cpu6: completed 60000 read accesses @2305718
|
||||
system.cpu7: completed 60000 read accesses @2318114
|
||||
system.cpu0: completed 70000 read accesses @2615296
|
||||
system.cpu1: completed 70000 read accesses @2621479
|
||||
system.cpu2: completed 70000 read accesses @2635267
|
||||
system.cpu3: completed 70000 read accesses @2642310
|
||||
system.cpu4: completed 70000 read accesses @2659144
|
||||
system.cpu5: completed 70000 read accesses @2668163
|
||||
system.cpu6: completed 70000 read accesses @2691243
|
||||
system.cpu7: completed 70000 read accesses @2706192
|
||||
system.cpu0: completed 80000 read accesses @2986810
|
||||
system.cpu1: completed 80000 read accesses @2994418
|
||||
system.cpu2: completed 80000 read accesses @3009400
|
||||
system.cpu3: completed 80000 read accesses @3028789
|
||||
system.cpu4: completed 80000 read accesses @3033010
|
||||
system.cpu5: completed 80000 read accesses @3042800
|
||||
system.cpu6: completed 80000 read accesses @3071603
|
||||
system.cpu7: completed 80000 read accesses @3108423
|
||||
system.cpu0: completed 90000 read accesses @3351259
|
||||
system.cpu1: completed 90000 read accesses @3361381
|
||||
system.cpu2: completed 90000 read accesses @3381198
|
||||
system.cpu4: completed 90000 read accesses @3406636
|
||||
system.cpu3: completed 90000 read accesses @3411857
|
||||
system.cpu5: completed 90000 read accesses @3424074
|
||||
system.cpu6: completed 90000 read accesses @3457139
|
||||
system.cpu7: completed 90000 read accesses @3490206
|
||||
system.cpu0: completed 100000 read accesses @3725190
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:36:48
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:36:46
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
M5 compiled Jul 1 2010 14:38:07
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:39:45
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3719757 because maximum number of loads reached
|
||||
Exiting @ tick 3725190 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 340040 # Number of bytes of host memory used
|
||||
host_seconds 42.78 # Real time elapsed on the host
|
||||
host_tick_rate 86943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332596 # Number of bytes of host memory used
|
||||
host_seconds 35.19 # Real time elapsed on the host
|
||||
host_tick_rate 105869 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003720 # Number of seconds simulated
|
||||
sim_ticks 3719757 # Number of ticks simulated
|
||||
sim_seconds 0.003725 # Number of seconds simulated
|
||||
sim_ticks 3725190 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99860 # number of read accesses completed
|
||||
system.cpu0.num_writes 53770 # number of write accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53802 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53093 # number of write accesses completed
|
||||
system.cpu1.num_reads 99730 # number of read accesses completed
|
||||
system.cpu1.num_writes 53651 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98032 # number of read accesses completed
|
||||
system.cpu2.num_writes 52757 # number of write accesses completed
|
||||
system.cpu2.num_reads 99194 # number of read accesses completed
|
||||
system.cpu2.num_writes 53071 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98573 # number of read accesses completed
|
||||
system.cpu3.num_writes 52922 # number of write accesses completed
|
||||
system.cpu3.num_reads 98275 # number of read accesses completed
|
||||
system.cpu3.num_writes 53108 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 97812 # number of read accesses completed
|
||||
system.cpu4.num_writes 53065 # number of write accesses completed
|
||||
system.cpu4.num_reads 98291 # number of read accesses completed
|
||||
system.cpu4.num_writes 52851 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97538 # number of read accesses completed
|
||||
system.cpu5.num_writes 52364 # number of write accesses completed
|
||||
system.cpu5.num_reads 97729 # number of read accesses completed
|
||||
system.cpu5.num_writes 52263 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 96539 # number of read accesses completed
|
||||
system.cpu6.num_writes 52064 # number of write accesses completed
|
||||
system.cpu6.num_reads 97202 # number of read accesses completed
|
||||
system.cpu6.num_writes 51897 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97318 # number of read accesses completed
|
||||
system.cpu7.num_writes 52275 # number of write accesses completed
|
||||
system.cpu7.num_reads 96111 # number of read accesses completed
|
||||
system.cpu7.num_writes 51731 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports0.port[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
|
|
@ -37,7 +37,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports1.port[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
|
|
@ -52,7 +52,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports2.port[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
|
|
@ -67,7 +67,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports3.port[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
|
|
@ -82,7 +82,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports4.port[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
|
|
@ -97,7 +97,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports5.port[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
|
|
@ -112,7 +112,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports6.port[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
|
|
@ -127,7 +127,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -147,11 +147,11 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
|
|
@ -164,6 +164,102 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
|
|
@ -202,39 +298,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -252,39 +335,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -302,39 +372,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -352,39 +409,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -402,39 +446,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -452,39 +483,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -502,39 +520,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -552,39 +557,26 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read accesses @333700
|
||||
system.cpu3: completed 10000 read accesses @335770
|
||||
system.cpu4: completed 10000 read accesses @336327
|
||||
system.cpu1: completed 10000 read accesses @339698
|
||||
system.cpu2: completed 10000 read accesses @344150
|
||||
system.cpu6: completed 10000 read accesses @345138
|
||||
system.cpu7: completed 10000 read accesses @345167
|
||||
system.cpu0: completed 10000 read accesses @349190
|
||||
system.cpu6: completed 20000 read accesses @673266
|
||||
system.cpu5: completed 20000 read accesses @676289
|
||||
system.cpu7: completed 20000 read accesses @679722
|
||||
system.cpu3: completed 20000 read accesses @681408
|
||||
system.cpu4: completed 20000 read accesses @681933
|
||||
system.cpu2: completed 20000 read accesses @683973
|
||||
system.cpu0: completed 20000 read accesses @686720
|
||||
system.cpu1: completed 20000 read accesses @692941
|
||||
system.cpu4: completed 30000 read accesses @1007235
|
||||
system.cpu6: completed 30000 read accesses @1011621
|
||||
system.cpu7: completed 30000 read accesses @1013787
|
||||
system.cpu3: completed 30000 read accesses @1022376
|
||||
system.cpu1: completed 30000 read accesses @1026321
|
||||
system.cpu0: completed 30000 read accesses @1027922
|
||||
system.cpu5: completed 30000 read accesses @1030676
|
||||
system.cpu2: completed 30000 read accesses @1030823
|
||||
system.cpu6: completed 40000 read accesses @1348685
|
||||
system.cpu3: completed 40000 read accesses @1353011
|
||||
system.cpu4: completed 40000 read accesses @1356076
|
||||
system.cpu7: completed 40000 read accesses @1357286
|
||||
system.cpu1: completed 40000 read accesses @1359706
|
||||
system.cpu5: completed 40000 read accesses @1367254
|
||||
system.cpu2: completed 40000 read accesses @1373741
|
||||
system.cpu0: completed 40000 read accesses @1379957
|
||||
system.cpu4: completed 50000 read accesses @1688392
|
||||
system.cpu7: completed 50000 read accesses @1689568
|
||||
system.cpu6: completed 50000 read accesses @1689754
|
||||
system.cpu3: completed 50000 read accesses @1696699
|
||||
system.cpu1: completed 50000 read accesses @1706109
|
||||
system.cpu5: completed 50000 read accesses @1712886
|
||||
system.cpu2: completed 50000 read accesses @1716788
|
||||
system.cpu0: completed 50000 read accesses @1719320
|
||||
system.cpu7: completed 60000 read accesses @2028845
|
||||
system.cpu6: completed 60000 read accesses @2029028
|
||||
system.cpu3: completed 60000 read accesses @2030491
|
||||
system.cpu1: completed 60000 read accesses @2034867
|
||||
system.cpu4: completed 60000 read accesses @2042771
|
||||
system.cpu5: completed 60000 read accesses @2052491
|
||||
system.cpu2: completed 60000 read accesses @2054050
|
||||
system.cpu0: completed 60000 read accesses @2059964
|
||||
system.cpu1: completed 70000 read accesses @2366182
|
||||
system.cpu3: completed 70000 read accesses @2371740
|
||||
system.cpu6: completed 70000 read accesses @2378180
|
||||
system.cpu7: completed 70000 read accesses @2384422
|
||||
system.cpu4: completed 70000 read accesses @2385664
|
||||
system.cpu5: completed 70000 read accesses @2386969
|
||||
system.cpu0: completed 70000 read accesses @2391802
|
||||
system.cpu2: completed 70000 read accesses @2394315
|
||||
system.cpu1: completed 80000 read accesses @2697050
|
||||
system.cpu3: completed 80000 read accesses @2711777
|
||||
system.cpu5: completed 80000 read accesses @2712887
|
||||
system.cpu6: completed 80000 read accesses @2716967
|
||||
system.cpu7: completed 80000 read accesses @2729293
|
||||
system.cpu4: completed 80000 read accesses @2732109
|
||||
system.cpu0: completed 80000 read accesses @2735916
|
||||
system.cpu2: completed 80000 read accesses @2746698
|
||||
system.cpu5: completed 90000 read accesses @3042585
|
||||
system.cpu1: completed 90000 read accesses @3050146
|
||||
system.cpu4: completed 90000 read accesses @3051611
|
||||
system.cpu6: completed 90000 read accesses @3054450
|
||||
system.cpu3: completed 90000 read accesses @3060838
|
||||
system.cpu7: completed 90000 read accesses @3073385
|
||||
system.cpu0: completed 90000 read accesses @3084850
|
||||
system.cpu2: completed 90000 read accesses @3085570
|
||||
system.cpu6: completed 100000 read accesses @3383480
|
||||
system.cpu6: completed 10000 read accesses @325901
|
||||
system.cpu4: completed 10000 read accesses @333477
|
||||
system.cpu2: completed 10000 read accesses @337264
|
||||
system.cpu7: completed 10000 read accesses @338212
|
||||
system.cpu0: completed 10000 read accesses @341315
|
||||
system.cpu5: completed 10000 read accesses @343794
|
||||
system.cpu1: completed 10000 read accesses @347258
|
||||
system.cpu3: completed 10000 read accesses @349679
|
||||
system.cpu6: completed 20000 read accesses @662679
|
||||
system.cpu7: completed 20000 read accesses @663435
|
||||
system.cpu4: completed 20000 read accesses @670972
|
||||
system.cpu1: completed 20000 read accesses @674886
|
||||
system.cpu2: completed 20000 read accesses @675526
|
||||
system.cpu0: completed 20000 read accesses @687421
|
||||
system.cpu5: completed 20000 read accesses @695852
|
||||
system.cpu3: completed 20000 read accesses @698570
|
||||
system.cpu6: completed 30000 read accesses @1001408
|
||||
system.cpu1: completed 30000 read accesses @1004487
|
||||
system.cpu2: completed 30000 read accesses @1007345
|
||||
system.cpu4: completed 30000 read accesses @1009967
|
||||
system.cpu0: completed 30000 read accesses @1021321
|
||||
system.cpu7: completed 30000 read accesses @1025248
|
||||
system.cpu3: completed 30000 read accesses @1040400
|
||||
system.cpu5: completed 30000 read accesses @1042444
|
||||
system.cpu6: completed 40000 read accesses @1335158
|
||||
system.cpu1: completed 40000 read accesses @1341837
|
||||
system.cpu4: completed 40000 read accesses @1347757
|
||||
system.cpu2: completed 40000 read accesses @1348137
|
||||
system.cpu3: completed 40000 read accesses @1370930
|
||||
system.cpu0: completed 40000 read accesses @1372862
|
||||
system.cpu7: completed 40000 read accesses @1374480
|
||||
system.cpu5: completed 40000 read accesses @1395059
|
||||
system.cpu6: completed 50000 read accesses @1663756
|
||||
system.cpu2: completed 50000 read accesses @1676262
|
||||
system.cpu1: completed 50000 read accesses @1676376
|
||||
system.cpu4: completed 50000 read accesses @1689367
|
||||
system.cpu3: completed 50000 read accesses @1707722
|
||||
system.cpu7: completed 50000 read accesses @1715376
|
||||
system.cpu0: completed 50000 read accesses @1719053
|
||||
system.cpu5: completed 50000 read accesses @1756410
|
||||
system.cpu2: completed 60000 read accesses @1996507
|
||||
system.cpu6: completed 60000 read accesses @2009287
|
||||
system.cpu1: completed 60000 read accesses @2021631
|
||||
system.cpu4: completed 60000 read accesses @2032125
|
||||
system.cpu3: completed 60000 read accesses @2046121
|
||||
system.cpu7: completed 60000 read accesses @2054305
|
||||
system.cpu0: completed 60000 read accesses @2067865
|
||||
system.cpu5: completed 60000 read accesses @2103289
|
||||
system.cpu2: completed 70000 read accesses @2336053
|
||||
system.cpu6: completed 70000 read accesses @2351727
|
||||
system.cpu1: completed 70000 read accesses @2362242
|
||||
system.cpu3: completed 70000 read accesses @2365041
|
||||
system.cpu4: completed 70000 read accesses @2374894
|
||||
system.cpu7: completed 70000 read accesses @2393230
|
||||
system.cpu0: completed 70000 read accesses @2409417
|
||||
system.cpu5: completed 70000 read accesses @2444673
|
||||
system.cpu2: completed 80000 read accesses @2681751
|
||||
system.cpu1: completed 80000 read accesses @2695221
|
||||
system.cpu6: completed 80000 read accesses @2701603
|
||||
system.cpu3: completed 80000 read accesses @2708122
|
||||
system.cpu4: completed 80000 read accesses @2715599
|
||||
system.cpu7: completed 80000 read accesses @2739434
|
||||
system.cpu0: completed 80000 read accesses @2743943
|
||||
system.cpu5: completed 80000 read accesses @2780520
|
||||
system.cpu2: completed 90000 read accesses @3022424
|
||||
system.cpu1: completed 90000 read accesses @3030742
|
||||
system.cpu3: completed 90000 read accesses @3042635
|
||||
system.cpu6: completed 90000 read accesses @3050919
|
||||
system.cpu4: completed 90000 read accesses @3054095
|
||||
system.cpu0: completed 90000 read accesses @3084803
|
||||
system.cpu7: completed 90000 read accesses @3091274
|
||||
system.cpu5: completed 90000 read accesses @3116487
|
||||
system.cpu2: completed 100000 read accesses @3358188
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:39:50
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:38:22
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
M5 compiled Jul 1 2010 14:38:10
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:39:45
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3383480 because maximum number of loads reached
|
||||
Exiting @ tick 3358188 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 340176 # Number of bytes of host memory used
|
||||
host_seconds 30.43 # Real time elapsed on the host
|
||||
host_tick_rate 111176 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332872 # Number of bytes of host memory used
|
||||
host_seconds 24.53 # Real time elapsed on the host
|
||||
host_tick_rate 136908 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003383 # Number of seconds simulated
|
||||
sim_ticks 3383480 # Number of ticks simulated
|
||||
sim_seconds 0.003358 # Number of seconds simulated
|
||||
sim_ticks 3358188 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99022 # number of read accesses completed
|
||||
system.cpu0.num_writes 53581 # number of write accesses completed
|
||||
system.cpu0.num_reads 98036 # number of read accesses completed
|
||||
system.cpu0.num_writes 52677 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99831 # number of read accesses completed
|
||||
system.cpu1.num_writes 53533 # number of write accesses completed
|
||||
system.cpu1.num_reads 99903 # number of read accesses completed
|
||||
system.cpu1.num_writes 53671 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98646 # number of read accesses completed
|
||||
system.cpu2.num_writes 53693 # number of write accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 53360 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99440 # number of read accesses completed
|
||||
system.cpu3.num_writes 53404 # number of write accesses completed
|
||||
system.cpu3.num_reads 99545 # number of read accesses completed
|
||||
system.cpu3.num_writes 53578 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99794 # number of read accesses completed
|
||||
system.cpu4.num_writes 53954 # number of write accesses completed
|
||||
system.cpu4.num_reads 99118 # number of read accesses completed
|
||||
system.cpu4.num_writes 53226 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99737 # number of read accesses completed
|
||||
system.cpu5.num_writes 53481 # number of write accesses completed
|
||||
system.cpu5.num_reads 96991 # number of read accesses completed
|
||||
system.cpu5.num_writes 52753 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53654 # number of write accesses completed
|
||||
system.cpu6.num_reads 98713 # number of read accesses completed
|
||||
system.cpu6.num_writes 52958 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 98991 # number of read accesses completed
|
||||
system.cpu7.num_writes 53546 # number of write accesses completed
|
||||
system.cpu7.num_reads 97919 # number of read accesses completed
|
||||
system.cpu7.num_writes 52935 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports0.port[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
|
|
@ -37,7 +37,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports1.port[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
|
|
@ -52,7 +52,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports2.port[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
|
|
@ -67,7 +67,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports3.port[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
|
|
@ -82,7 +82,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports4.port[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
|
|
@ -97,7 +97,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports5.port[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
|
|
@ -112,7 +112,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports6.port[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
|
|
@ -127,7 +127,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -147,11 +147,11 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
|
|
@ -164,6 +164,102 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
|
|
@ -202,9 +298,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -215,31 +311,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -257,9 +340,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -270,31 +353,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -312,9 +382,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -325,31 +395,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -367,9 +424,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -380,31 +437,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -422,9 +466,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -435,31 +479,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -477,9 +508,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -490,31 +521,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -532,9 +550,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -545,31 +563,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
@ -587,9 +592,9 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
N_tokens=9
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
|
|
@ -600,31 +605,18 @@ l2_select_num_bits=0
|
|||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu1: completed 10000 read accesses @320533
|
||||
system.cpu0: completed 10000 read accesses @324255
|
||||
system.cpu5: completed 10000 read accesses @329816
|
||||
system.cpu4: completed 10000 read accesses @330370
|
||||
system.cpu2: completed 10000 read accesses @330850
|
||||
system.cpu3: completed 10000 read accesses @330898
|
||||
system.cpu6: completed 10000 read accesses @330981
|
||||
system.cpu7: completed 10000 read accesses @332669
|
||||
system.cpu1: completed 20000 read accesses @645951
|
||||
system.cpu6: completed 20000 read accesses @654684
|
||||
system.cpu0: completed 20000 read accesses @655122
|
||||
system.cpu5: completed 20000 read accesses @655139
|
||||
system.cpu4: completed 20000 read accesses @658112
|
||||
system.cpu7: completed 20000 read accesses @659630
|
||||
system.cpu3: completed 20000 read accesses @662399
|
||||
system.cpu2: completed 20000 read accesses @662745
|
||||
system.cpu1: completed 30000 read accesses @971498
|
||||
system.cpu0: completed 30000 read accesses @979665
|
||||
system.cpu6: completed 30000 read accesses @980753
|
||||
system.cpu4: completed 30000 read accesses @986046
|
||||
system.cpu5: completed 30000 read accesses @986992
|
||||
system.cpu7: completed 30000 read accesses @990004
|
||||
system.cpu2: completed 30000 read accesses @992746
|
||||
system.cpu3: completed 30000 read accesses @994289
|
||||
system.cpu1: completed 40000 read accesses @1295713
|
||||
system.cpu0: completed 40000 read accesses @1304844
|
||||
system.cpu6: completed 40000 read accesses @1311609
|
||||
system.cpu4: completed 40000 read accesses @1313210
|
||||
system.cpu5: completed 40000 read accesses @1315669
|
||||
system.cpu7: completed 40000 read accesses @1321203
|
||||
system.cpu3: completed 40000 read accesses @1325768
|
||||
system.cpu2: completed 40000 read accesses @1327431
|
||||
system.cpu1: completed 50000 read accesses @1620139
|
||||
system.cpu0: completed 50000 read accesses @1624207
|
||||
system.cpu6: completed 50000 read accesses @1642053
|
||||
system.cpu5: completed 50000 read accesses @1643779
|
||||
system.cpu4: completed 50000 read accesses @1647677
|
||||
system.cpu7: completed 50000 read accesses @1653016
|
||||
system.cpu3: completed 50000 read accesses @1659224
|
||||
system.cpu2: completed 50000 read accesses @1659858
|
||||
system.cpu1: completed 60000 read accesses @1944324
|
||||
system.cpu0: completed 60000 read accesses @1947039
|
||||
system.cpu5: completed 60000 read accesses @1971722
|
||||
system.cpu6: completed 60000 read accesses @1971958
|
||||
system.cpu4: completed 60000 read accesses @1978467
|
||||
system.cpu3: completed 60000 read accesses @1984371
|
||||
system.cpu7: completed 60000 read accesses @1986116
|
||||
system.cpu2: completed 60000 read accesses @1990627
|
||||
system.cpu1: completed 70000 read accesses @2268077
|
||||
system.cpu0: completed 70000 read accesses @2271308
|
||||
system.cpu6: completed 70000 read accesses @2299743
|
||||
system.cpu5: completed 70000 read accesses @2302988
|
||||
system.cpu4: completed 70000 read accesses @2306754
|
||||
system.cpu3: completed 70000 read accesses @2313390
|
||||
system.cpu7: completed 70000 read accesses @2318502
|
||||
system.cpu2: completed 70000 read accesses @2323657
|
||||
system.cpu1: completed 80000 read accesses @2590310
|
||||
system.cpu0: completed 80000 read accesses @2594700
|
||||
system.cpu5: completed 80000 read accesses @2629321
|
||||
system.cpu6: completed 80000 read accesses @2631814
|
||||
system.cpu4: completed 80000 read accesses @2636634
|
||||
system.cpu7: completed 80000 read accesses @2643921
|
||||
system.cpu2: completed 80000 read accesses @2656705
|
||||
system.cpu3: completed 80000 read accesses @2656992
|
||||
system.cpu0: completed 90000 read accesses @2911654
|
||||
system.cpu1: completed 90000 read accesses @2922192
|
||||
system.cpu5: completed 90000 read accesses @2956637
|
||||
system.cpu4: completed 90000 read accesses @2959893
|
||||
system.cpu6: completed 90000 read accesses @2961119
|
||||
system.cpu7: completed 90000 read accesses @2975550
|
||||
system.cpu2: completed 90000 read accesses @2985342
|
||||
system.cpu3: completed 90000 read accesses @2990681
|
||||
system.cpu1: completed 100000 read accesses @3238178
|
||||
system.cpu2: completed 10000 read accesses @322194
|
||||
system.cpu0: completed 10000 read accesses @322719
|
||||
system.cpu5: completed 10000 read accesses @330050
|
||||
system.cpu7: completed 10000 read accesses @330574
|
||||
system.cpu6: completed 10000 read accesses @330892
|
||||
system.cpu4: completed 10000 read accesses @331172
|
||||
system.cpu1: completed 10000 read accesses @333911
|
||||
system.cpu3: completed 10000 read accesses @335019
|
||||
system.cpu0: completed 20000 read accesses @641579
|
||||
system.cpu2: completed 20000 read accesses @642932
|
||||
system.cpu6: completed 20000 read accesses @660969
|
||||
system.cpu4: completed 20000 read accesses @661309
|
||||
system.cpu5: completed 20000 read accesses @662083
|
||||
system.cpu7: completed 20000 read accesses @664047
|
||||
system.cpu1: completed 20000 read accesses @664884
|
||||
system.cpu3: completed 20000 read accesses @668081
|
||||
system.cpu0: completed 30000 read accesses @964302
|
||||
system.cpu2: completed 30000 read accesses @967590
|
||||
system.cpu4: completed 30000 read accesses @990023
|
||||
system.cpu7: completed 30000 read accesses @990043
|
||||
system.cpu6: completed 30000 read accesses @991961
|
||||
system.cpu5: completed 30000 read accesses @993160
|
||||
system.cpu1: completed 30000 read accesses @996431
|
||||
system.cpu3: completed 30000 read accesses @1001054
|
||||
system.cpu2: completed 40000 read accesses @1287629
|
||||
system.cpu0: completed 40000 read accesses @1291802
|
||||
system.cpu4: completed 40000 read accesses @1317065
|
||||
system.cpu7: completed 40000 read accesses @1322312
|
||||
system.cpu6: completed 40000 read accesses @1324580
|
||||
system.cpu5: completed 40000 read accesses @1326928
|
||||
system.cpu1: completed 40000 read accesses @1328485
|
||||
system.cpu3: completed 40000 read accesses @1330568
|
||||
system.cpu2: completed 50000 read accesses @1610807
|
||||
system.cpu0: completed 50000 read accesses @1611621
|
||||
system.cpu4: completed 50000 read accesses @1645302
|
||||
system.cpu7: completed 50000 read accesses @1650899
|
||||
system.cpu6: completed 50000 read accesses @1654396
|
||||
system.cpu5: completed 50000 read accesses @1657056
|
||||
system.cpu1: completed 50000 read accesses @1661586
|
||||
system.cpu3: completed 50000 read accesses @1662920
|
||||
system.cpu0: completed 60000 read accesses @1928533
|
||||
system.cpu2: completed 60000 read accesses @1935763
|
||||
system.cpu4: completed 60000 read accesses @1973168
|
||||
system.cpu7: completed 60000 read accesses @1985073
|
||||
system.cpu6: completed 60000 read accesses @1987312
|
||||
system.cpu1: completed 60000 read accesses @1992182
|
||||
system.cpu5: completed 60000 read accesses @1992692
|
||||
system.cpu3: completed 60000 read accesses @1994120
|
||||
system.cpu0: completed 70000 read accesses @2251425
|
||||
system.cpu2: completed 70000 read accesses @2258967
|
||||
system.cpu4: completed 70000 read accesses @2302588
|
||||
system.cpu6: completed 70000 read accesses @2314337
|
||||
system.cpu7: completed 70000 read accesses @2315937
|
||||
system.cpu5: completed 70000 read accesses @2322183
|
||||
system.cpu1: completed 70000 read accesses @2323330
|
||||
system.cpu3: completed 70000 read accesses @2326357
|
||||
system.cpu0: completed 80000 read accesses @2576249
|
||||
system.cpu2: completed 80000 read accesses @2582991
|
||||
system.cpu4: completed 80000 read accesses @2630111
|
||||
system.cpu6: completed 80000 read accesses @2644662
|
||||
system.cpu7: completed 80000 read accesses @2648201
|
||||
system.cpu1: completed 80000 read accesses @2650725
|
||||
system.cpu5: completed 80000 read accesses @2653106
|
||||
system.cpu3: completed 80000 read accesses @2653877
|
||||
system.cpu2: completed 90000 read accesses @2907948
|
||||
system.cpu0: completed 90000 read accesses @2917526
|
||||
system.cpu4: completed 90000 read accesses @2951732
|
||||
system.cpu6: completed 90000 read accesses @2969846
|
||||
system.cpu1: completed 90000 read accesses @2970686
|
||||
system.cpu3: completed 90000 read accesses @2978760
|
||||
system.cpu5: completed 90000 read accesses @2981622
|
||||
system.cpu7: completed 90000 read accesses @2987871
|
||||
system.cpu2: completed 100000 read accesses @3229931
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:58:42
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:39:30
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
M5 compiled Jul 1 2010 14:39:47
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:40:13
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3238178 because maximum number of loads reached
|
||||
Exiting @ tick 3229931 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 340284 # Number of bytes of host memory used
|
||||
host_seconds 34.80 # Real time elapsed on the host
|
||||
host_tick_rate 93055 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332852 # Number of bytes of host memory used
|
||||
host_seconds 26.21 # Real time elapsed on the host
|
||||
host_tick_rate 123225 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003238 # Number of seconds simulated
|
||||
sim_ticks 3238178 # Number of ticks simulated
|
||||
sim_seconds 0.003230 # Number of seconds simulated
|
||||
sim_ticks 3229931 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99983 # number of read accesses completed
|
||||
system.cpu0.num_writes 54267 # number of write accesses completed
|
||||
system.cpu0.num_reads 99664 # number of read accesses completed
|
||||
system.cpu0.num_writes 53551 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53571 # number of write accesses completed
|
||||
system.cpu1.num_reads 97847 # number of read accesses completed
|
||||
system.cpu1.num_writes 52926 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 97642 # number of read accesses completed
|
||||
system.cpu2.num_writes 52892 # number of write accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 54081 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97531 # number of read accesses completed
|
||||
system.cpu3.num_writes 52364 # number of write accesses completed
|
||||
system.cpu3.num_reads 97548 # number of read accesses completed
|
||||
system.cpu3.num_writes 52843 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98570 # number of read accesses completed
|
||||
system.cpu4.num_writes 53173 # number of write accesses completed
|
||||
system.cpu4.num_reads 98335 # number of read accesses completed
|
||||
system.cpu4.num_writes 52557 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98261 # number of read accesses completed
|
||||
system.cpu5.num_writes 52643 # number of write accesses completed
|
||||
system.cpu5.num_reads 97595 # number of read accesses completed
|
||||
system.cpu5.num_writes 52679 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 98464 # number of read accesses completed
|
||||
system.cpu6.num_writes 52805 # number of write accesses completed
|
||||
system.cpu6.num_reads 97889 # number of read accesses completed
|
||||
system.cpu6.num_writes 52461 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97833 # number of read accesses completed
|
||||
system.cpu7.num_writes 52922 # number of write accesses completed
|
||||
system.cpu7.num_reads 97463 # number of read accesses completed
|
||||
system.cpu7.num_writes 51981 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[0]
|
||||
test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports0.port[0]
|
||||
|
||||
[system.cpu1]
|
||||
type=MemTest
|
||||
|
|
@ -37,7 +37,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[1]
|
||||
test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports1.port[0]
|
||||
|
||||
[system.cpu2]
|
||||
type=MemTest
|
||||
|
|
@ -52,7 +52,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[2]
|
||||
test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports2.port[0]
|
||||
|
||||
[system.cpu3]
|
||||
type=MemTest
|
||||
|
|
@ -67,7 +67,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[3]
|
||||
test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports3.port[0]
|
||||
|
||||
[system.cpu4]
|
||||
type=MemTest
|
||||
|
|
@ -82,7 +82,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[4]
|
||||
test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports4.port[0]
|
||||
|
||||
[system.cpu5]
|
||||
type=MemTest
|
||||
|
|
@ -97,7 +97,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[5]
|
||||
test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports5.port[0]
|
||||
|
||||
[system.cpu6]
|
||||
type=MemTest
|
||||
|
|
@ -112,7 +112,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[6]
|
||||
test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports6.port[0]
|
||||
|
||||
[system.cpu7]
|
||||
type=MemTest
|
||||
|
|
@ -127,7 +127,7 @@ percent_uncacheable=0
|
|||
progress_interval=10000
|
||||
trace_addr=0
|
||||
functional=system.funcmem.port[7]
|
||||
test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0]
|
||||
test=system.ruby.cpu_ruby_ports7.port[0]
|
||||
|
||||
[system.funcmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -147,11 +147,11 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort
|
||||
port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMemPort system.ruby.cpu_ruby_ports2.physMemPort system.ruby.cpu_ruby_ports3.physMemPort system.ruby.cpu_ruby_ports4.physMemPort system.ruby.cpu_ruby_ports5.physMemPort system.ruby.cpu_ruby_ports6.physMemPort system.ruby.cpu_ruby_ports7.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
|
|
@ -164,6 +164,102 @@ randomization=false
|
|||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports0]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports1]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports2]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports3]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports4]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports5]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports6]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.cpu_ruby_ports7]
|
||||
type=RubySequencer
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
|
|
@ -202,19 +298,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports0
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -222,33 +332,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu0.test
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -260,19 +343,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -280,33 +377,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -318,19 +388,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports2
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -338,33 +422,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -376,19 +433,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links3.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports3
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -396,33 +467,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -434,19 +478,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links4.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports4
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -454,33 +512,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -492,19 +523,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links5.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports5
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -512,33 +557,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -550,19 +568,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links6.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports6
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -570,33 +602,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
@ -608,19 +613,33 @@ weight=1
|
|||
|
||||
[system.ruby.network.topology.ext_links7.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
children=L1DcacheMemory L1IcacheMemory L2cacheMemory
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer
|
||||
sequencer=system.ruby.cpu_ruby_ports7
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1DcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L1IcacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
|
|
@ -628,33 +647,6 @@ latency=15
|
|||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links8]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu0: completed 10000 read accesses @427647
|
||||
system.cpu1: completed 10000 read accesses @431729
|
||||
system.cpu6: completed 10000 read accesses @433789
|
||||
system.cpu7: completed 10000 read accesses @439540
|
||||
system.cpu2: completed 10000 read accesses @440839
|
||||
system.cpu5: completed 10000 read accesses @442985
|
||||
system.cpu4: completed 10000 read accesses @444200
|
||||
system.cpu3: completed 10000 read accesses @449590
|
||||
system.cpu0: completed 20000 read accesses @865314
|
||||
system.cpu6: completed 20000 read accesses @868247
|
||||
system.cpu1: completed 20000 read accesses @868279
|
||||
system.cpu4: completed 20000 read accesses @868705
|
||||
system.cpu7: completed 20000 read accesses @876211
|
||||
system.cpu3: completed 20000 read accesses @884081
|
||||
system.cpu2: completed 20000 read accesses @890953
|
||||
system.cpu5: completed 20000 read accesses @896667
|
||||
system.cpu7: completed 30000 read accesses @1294509
|
||||
system.cpu0: completed 30000 read accesses @1300229
|
||||
system.cpu4: completed 30000 read accesses @1308389
|
||||
system.cpu6: completed 30000 read accesses @1309605
|
||||
system.cpu1: completed 30000 read accesses @1314626
|
||||
system.cpu2: completed 30000 read accesses @1319614
|
||||
system.cpu3: completed 30000 read accesses @1333112
|
||||
system.cpu5: completed 30000 read accesses @1342297
|
||||
system.cpu0: completed 40000 read accesses @1732725
|
||||
system.cpu7: completed 40000 read accesses @1734274
|
||||
system.cpu6: completed 40000 read accesses @1739223
|
||||
system.cpu4: completed 40000 read accesses @1750291
|
||||
system.cpu2: completed 40000 read accesses @1757823
|
||||
system.cpu1: completed 40000 read accesses @1760314
|
||||
system.cpu3: completed 40000 read accesses @1761490
|
||||
system.cpu5: completed 40000 read accesses @1777684
|
||||
system.cpu7: completed 50000 read accesses @2168908
|
||||
system.cpu0: completed 50000 read accesses @2178119
|
||||
system.cpu3: completed 50000 read accesses @2188628
|
||||
system.cpu1: completed 50000 read accesses @2189157
|
||||
system.cpu6: completed 50000 read accesses @2193920
|
||||
system.cpu2: completed 50000 read accesses @2194930
|
||||
system.cpu4: completed 50000 read accesses @2196927
|
||||
system.cpu5: completed 50000 read accesses @2215126
|
||||
system.cpu7: completed 60000 read accesses @2604948
|
||||
system.cpu0: completed 60000 read accesses @2616657
|
||||
system.cpu4: completed 60000 read accesses @2617534
|
||||
system.cpu1: completed 60000 read accesses @2632147
|
||||
system.cpu6: completed 60000 read accesses @2638426
|
||||
system.cpu3: completed 60000 read accesses @2639965
|
||||
system.cpu2: completed 60000 read accesses @2642221
|
||||
system.cpu5: completed 60000 read accesses @2647795
|
||||
system.cpu7: completed 70000 read accesses @3047214
|
||||
system.cpu0: completed 70000 read accesses @3049033
|
||||
system.cpu4: completed 70000 read accesses @3063601
|
||||
system.cpu1: completed 70000 read accesses @3069586
|
||||
system.cpu2: completed 70000 read accesses @3071644
|
||||
system.cpu3: completed 70000 read accesses @3075127
|
||||
system.cpu6: completed 70000 read accesses @3078550
|
||||
system.cpu5: completed 70000 read accesses @3088269
|
||||
system.cpu7: completed 80000 read accesses @3486517
|
||||
system.cpu0: completed 80000 read accesses @3492714
|
||||
system.cpu4: completed 80000 read accesses @3505717
|
||||
system.cpu2: completed 80000 read accesses @3505856
|
||||
system.cpu3: completed 80000 read accesses @3506369
|
||||
system.cpu1: completed 80000 read accesses @3507148
|
||||
system.cpu6: completed 80000 read accesses @3520617
|
||||
system.cpu5: completed 80000 read accesses @3524191
|
||||
system.cpu7: completed 90000 read accesses @3917341
|
||||
system.cpu0: completed 90000 read accesses @3926523
|
||||
system.cpu4: completed 90000 read accesses @3938478
|
||||
system.cpu1: completed 90000 read accesses @3940606
|
||||
system.cpu5: completed 90000 read accesses @3950826
|
||||
system.cpu3: completed 90000 read accesses @3954179
|
||||
system.cpu6: completed 90000 read accesses @3956200
|
||||
system.cpu2: completed 90000 read accesses @3961428
|
||||
system.cpu7: completed 100000 read accesses @4339943
|
||||
system.cpu5: completed 10000 read accesses @427588
|
||||
system.cpu7: completed 10000 read accesses @431412
|
||||
system.cpu2: completed 10000 read accesses @431662
|
||||
system.cpu0: completed 10000 read accesses @436404
|
||||
system.cpu6: completed 10000 read accesses @437826
|
||||
system.cpu3: completed 10000 read accesses @441295
|
||||
system.cpu4: completed 10000 read accesses @446537
|
||||
system.cpu1: completed 10000 read accesses @454121
|
||||
system.cpu6: completed 20000 read accesses @860243
|
||||
system.cpu5: completed 20000 read accesses @863931
|
||||
system.cpu0: completed 20000 read accesses @870865
|
||||
system.cpu7: completed 20000 read accesses @874151
|
||||
system.cpu2: completed 20000 read accesses @878670
|
||||
system.cpu1: completed 20000 read accesses @880979
|
||||
system.cpu3: completed 20000 read accesses @881568
|
||||
system.cpu4: completed 20000 read accesses @885967
|
||||
system.cpu6: completed 30000 read accesses @1296805
|
||||
system.cpu7: completed 30000 read accesses @1298533
|
||||
system.cpu0: completed 30000 read accesses @1301793
|
||||
system.cpu5: completed 30000 read accesses @1305764
|
||||
system.cpu3: completed 30000 read accesses @1313209
|
||||
system.cpu1: completed 30000 read accesses @1317956
|
||||
system.cpu4: completed 30000 read accesses @1322397
|
||||
system.cpu2: completed 30000 read accesses @1327680
|
||||
system.cpu7: completed 40000 read accesses @1724327
|
||||
system.cpu6: completed 40000 read accesses @1741883
|
||||
system.cpu3: completed 40000 read accesses @1743341
|
||||
system.cpu0: completed 40000 read accesses @1746338
|
||||
system.cpu5: completed 40000 read accesses @1749918
|
||||
system.cpu4: completed 40000 read accesses @1756944
|
||||
system.cpu1: completed 40000 read accesses @1758785
|
||||
system.cpu2: completed 40000 read accesses @1766923
|
||||
system.cpu7: completed 50000 read accesses @2153101
|
||||
system.cpu3: completed 50000 read accesses @2174455
|
||||
system.cpu6: completed 50000 read accesses @2175676
|
||||
system.cpu0: completed 50000 read accesses @2176642
|
||||
system.cpu1: completed 50000 read accesses @2195626
|
||||
system.cpu5: completed 50000 read accesses @2196192
|
||||
system.cpu4: completed 50000 read accesses @2206329
|
||||
system.cpu2: completed 50000 read accesses @2212172
|
||||
system.cpu7: completed 60000 read accesses @2597994
|
||||
system.cpu3: completed 60000 read accesses @2607264
|
||||
system.cpu6: completed 60000 read accesses @2608871
|
||||
system.cpu0: completed 60000 read accesses @2617931
|
||||
system.cpu1: completed 60000 read accesses @2626417
|
||||
system.cpu5: completed 60000 read accesses @2627919
|
||||
system.cpu2: completed 60000 read accesses @2649345
|
||||
system.cpu4: completed 60000 read accesses @2649516
|
||||
system.cpu7: completed 70000 read accesses @3041950
|
||||
system.cpu6: completed 70000 read accesses @3046421
|
||||
system.cpu3: completed 70000 read accesses @3055853
|
||||
system.cpu0: completed 70000 read accesses @3057789
|
||||
system.cpu1: completed 70000 read accesses @3060703
|
||||
system.cpu5: completed 70000 read accesses @3069601
|
||||
system.cpu4: completed 70000 read accesses @3076345
|
||||
system.cpu2: completed 70000 read accesses @3079487
|
||||
system.cpu7: completed 80000 read accesses @3472996
|
||||
system.cpu6: completed 80000 read accesses @3475066
|
||||
system.cpu3: completed 80000 read accesses @3481511
|
||||
system.cpu0: completed 80000 read accesses @3498566
|
||||
system.cpu1: completed 80000 read accesses @3506662
|
||||
system.cpu2: completed 80000 read accesses @3515589
|
||||
system.cpu5: completed 80000 read accesses @3522207
|
||||
system.cpu4: completed 80000 read accesses @3524696
|
||||
system.cpu6: completed 90000 read accesses @3905962
|
||||
system.cpu7: completed 90000 read accesses @3913222
|
||||
system.cpu3: completed 90000 read accesses @3920060
|
||||
system.cpu0: completed 90000 read accesses @3930216
|
||||
system.cpu2: completed 90000 read accesses @3948853
|
||||
system.cpu1: completed 90000 read accesses @3953559
|
||||
system.cpu5: completed 90000 read accesses @3960654
|
||||
system.cpu4: completed 90000 read accesses @3965634
|
||||
system.cpu6: completed 100000 read accesses @4329426
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 18 2010 14:59:19
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:40:34
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
M5 compiled Jul 1 2010 14:37:50
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:38:54
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 4339943 because maximum number of loads reached
|
||||
Exiting @ tick 4329426 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 339964 # Number of bytes of host memory used
|
||||
host_seconds 41.43 # Real time elapsed on the host
|
||||
host_tick_rate 104755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332624 # Number of bytes of host memory used
|
||||
host_seconds 32.19 # Real time elapsed on the host
|
||||
host_tick_rate 134514 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.004340 # Number of seconds simulated
|
||||
sim_ticks 4339943 # Number of ticks simulated
|
||||
sim_seconds 0.004329 # Number of seconds simulated
|
||||
sim_ticks 4329426 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99313 # number of read accesses completed
|
||||
system.cpu0.num_writes 53538 # number of write accesses completed
|
||||
system.cpu0.num_reads 99342 # number of read accesses completed
|
||||
system.cpu0.num_writes 53020 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99089 # number of read accesses completed
|
||||
system.cpu1.num_writes 53648 # number of write accesses completed
|
||||
system.cpu1.num_reads 98745 # number of read accesses completed
|
||||
system.cpu1.num_writes 53384 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98494 # number of read accesses completed
|
||||
system.cpu2.num_writes 52751 # number of write accesses completed
|
||||
system.cpu2.num_reads 98624 # number of read accesses completed
|
||||
system.cpu2.num_writes 53313 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98499 # number of read accesses completed
|
||||
system.cpu3.num_writes 53164 # number of write accesses completed
|
||||
system.cpu3.num_reads 99274 # number of read accesses completed
|
||||
system.cpu3.num_writes 53327 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99037 # number of read accesses completed
|
||||
system.cpu4.num_writes 53407 # number of write accesses completed
|
||||
system.cpu4.num_reads 98083 # number of read accesses completed
|
||||
system.cpu4.num_writes 52520 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99159 # number of read accesses completed
|
||||
system.cpu5.num_writes 53566 # number of write accesses completed
|
||||
system.cpu5.num_reads 98306 # number of read accesses completed
|
||||
system.cpu5.num_writes 52893 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 98888 # number of read accesses completed
|
||||
system.cpu6.num_writes 53164 # number of write accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53622 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 54267 # number of write accesses completed
|
||||
system.cpu7.num_reads 99389 # number of read accesses completed
|
||||
system.cpu7.num_writes 53486 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu3: completed 10000 read accesses @26226880
|
||||
system.cpu6: completed 10000 read accesses @26416342
|
||||
system.cpu2: completed 10000 read accesses @26427251
|
||||
system.cpu5: completed 10000 read accesses @26798889
|
||||
system.cpu0: completed 10000 read accesses @26886521
|
||||
system.cpu4: completed 10000 read accesses @26226880
|
||||
system.cpu0: completed 10000 read accesses @26416342
|
||||
system.cpu3: completed 10000 read accesses @26427251
|
||||
system.cpu2: completed 10000 read accesses @26798889
|
||||
system.cpu5: completed 10000 read accesses @26886521
|
||||
system.cpu7: completed 10000 read accesses @27109446
|
||||
system.cpu1: completed 10000 read accesses @27197408
|
||||
system.cpu4: completed 10000 read accesses @27318359
|
||||
system.cpu3: completed 20000 read accesses @53279230
|
||||
system.cpu6: completed 20000 read accesses @53417084
|
||||
system.cpu2: completed 20000 read accesses @53757092
|
||||
system.cpu0: completed 20000 read accesses @53888320
|
||||
system.cpu5: completed 20000 read accesses @53947132
|
||||
system.cpu4: completed 20000 read accesses @54390092
|
||||
system.cpu1: completed 20000 read accesses @54397720
|
||||
system.cpu6: completed 10000 read accesses @27197408
|
||||
system.cpu1: completed 10000 read accesses @27318359
|
||||
system.cpu4: completed 20000 read accesses @53279230
|
||||
system.cpu0: completed 20000 read accesses @53417084
|
||||
system.cpu3: completed 20000 read accesses @53757092
|
||||
system.cpu5: completed 20000 read accesses @53888320
|
||||
system.cpu2: completed 20000 read accesses @53947132
|
||||
system.cpu1: completed 20000 read accesses @54390092
|
||||
system.cpu6: completed 20000 read accesses @54397720
|
||||
system.cpu7: completed 20000 read accesses @54632966
|
||||
system.cpu6: completed 30000 read accesses @80144176
|
||||
system.cpu3: completed 30000 read accesses @80518264
|
||||
system.cpu0: completed 30000 read accesses @80638600
|
||||
system.cpu5: completed 30000 read accesses @80869702
|
||||
system.cpu1: completed 30000 read accesses @81289158
|
||||
system.cpu2: completed 30000 read accesses @81358716
|
||||
system.cpu0: completed 30000 read accesses @80144176
|
||||
system.cpu4: completed 30000 read accesses @80518264
|
||||
system.cpu5: completed 30000 read accesses @80638600
|
||||
system.cpu2: completed 30000 read accesses @80869702
|
||||
system.cpu6: completed 30000 read accesses @81289158
|
||||
system.cpu3: completed 30000 read accesses @81358716
|
||||
system.cpu7: completed 30000 read accesses @81981296
|
||||
system.cpu4: completed 30000 read accesses @82043104
|
||||
system.cpu6: completed 40000 read accesses @107087547
|
||||
system.cpu0: completed 40000 read accesses @107662142
|
||||
system.cpu3: completed 40000 read accesses @107722516
|
||||
system.cpu5: completed 40000 read accesses @107884124
|
||||
system.cpu1: completed 40000 read accesses @107981413
|
||||
system.cpu1: completed 30000 read accesses @82043104
|
||||
system.cpu0: completed 40000 read accesses @107087547
|
||||
system.cpu5: completed 40000 read accesses @107662142
|
||||
system.cpu4: completed 40000 read accesses @107722516
|
||||
system.cpu2: completed 40000 read accesses @107884124
|
||||
system.cpu6: completed 40000 read accesses @107981413
|
||||
system.cpu7: completed 40000 read accesses @108415286
|
||||
system.cpu2: completed 40000 read accesses @108655120
|
||||
system.cpu4: completed 40000 read accesses @109427858
|
||||
system.cpu6: completed 50000 read accesses @133583246
|
||||
system.cpu0: completed 50000 read accesses @133832383
|
||||
system.cpu5: completed 50000 read accesses @134755386
|
||||
system.cpu1: completed 50000 read accesses @134792594
|
||||
system.cpu3: completed 40000 read accesses @108655120
|
||||
system.cpu1: completed 40000 read accesses @109427858
|
||||
system.cpu0: completed 50000 read accesses @133583246
|
||||
system.cpu5: completed 50000 read accesses @133832383
|
||||
system.cpu2: completed 50000 read accesses @134755386
|
||||
system.cpu6: completed 50000 read accesses @134792594
|
||||
system.cpu7: completed 50000 read accesses @134914312
|
||||
system.cpu3: completed 50000 read accesses @134993978
|
||||
system.cpu2: completed 50000 read accesses @135362549
|
||||
system.cpu4: completed 50000 read accesses @135394370
|
||||
system.cpu0: completed 60000 read accesses @160410176
|
||||
system.cpu6: completed 60000 read accesses @160667590
|
||||
system.cpu4: completed 50000 read accesses @134993978
|
||||
system.cpu3: completed 50000 read accesses @135362549
|
||||
system.cpu1: completed 50000 read accesses @135394370
|
||||
system.cpu5: completed 60000 read accesses @160410176
|
||||
system.cpu0: completed 60000 read accesses @160667590
|
||||
system.cpu7: completed 60000 read accesses @161466346
|
||||
system.cpu1: completed 60000 read accesses @161592434
|
||||
system.cpu5: completed 60000 read accesses @161656374
|
||||
system.cpu4: completed 60000 read accesses @161882626
|
||||
system.cpu2: completed 60000 read accesses @162062631
|
||||
system.cpu3: completed 60000 read accesses @162154299
|
||||
system.cpu6: completed 70000 read accesses @187592265
|
||||
system.cpu1: completed 70000 read accesses @188138542
|
||||
system.cpu6: completed 60000 read accesses @161592434
|
||||
system.cpu2: completed 60000 read accesses @161656374
|
||||
system.cpu1: completed 60000 read accesses @161882626
|
||||
system.cpu3: completed 60000 read accesses @162062631
|
||||
system.cpu4: completed 60000 read accesses @162154299
|
||||
system.cpu0: completed 70000 read accesses @187592265
|
||||
system.cpu6: completed 70000 read accesses @188138542
|
||||
system.cpu7: completed 70000 read accesses @188373105
|
||||
system.cpu0: completed 70000 read accesses @188690782
|
||||
system.cpu3: completed 70000 read accesses @189309687
|
||||
system.cpu2: completed 70000 read accesses @189360790
|
||||
system.cpu4: completed 70000 read accesses @189391126
|
||||
system.cpu5: completed 70000 read accesses @189902895
|
||||
system.cpu6: completed 80000 read accesses @214739574
|
||||
system.cpu1: completed 80000 read accesses @215665444
|
||||
system.cpu0: completed 80000 read accesses @216021457
|
||||
system.cpu5: completed 70000 read accesses @188690782
|
||||
system.cpu4: completed 70000 read accesses @189309687
|
||||
system.cpu3: completed 70000 read accesses @189360790
|
||||
system.cpu1: completed 70000 read accesses @189391126
|
||||
system.cpu2: completed 70000 read accesses @189902895
|
||||
system.cpu0: completed 80000 read accesses @214739574
|
||||
system.cpu6: completed 80000 read accesses @215665444
|
||||
system.cpu5: completed 80000 read accesses @216021457
|
||||
system.cpu7: completed 80000 read accesses @216394344
|
||||
system.cpu3: completed 80000 read accesses @216537382
|
||||
system.cpu4: completed 80000 read accesses @216775798
|
||||
system.cpu2: completed 80000 read accesses @216868662
|
||||
system.cpu5: completed 80000 read accesses @217401619
|
||||
system.cpu6: completed 90000 read accesses @241415090
|
||||
system.cpu1: completed 90000 read accesses @242558992
|
||||
system.cpu0: completed 90000 read accesses @242897388
|
||||
system.cpu4: completed 80000 read accesses @216537382
|
||||
system.cpu1: completed 80000 read accesses @216775798
|
||||
system.cpu3: completed 80000 read accesses @216868662
|
||||
system.cpu2: completed 80000 read accesses @217401619
|
||||
system.cpu0: completed 90000 read accesses @241415090
|
||||
system.cpu6: completed 90000 read accesses @242558992
|
||||
system.cpu5: completed 90000 read accesses @242897388
|
||||
system.cpu7: completed 90000 read accesses @243372191
|
||||
system.cpu3: completed 90000 read accesses @243630762
|
||||
system.cpu5: completed 90000 read accesses @243633950
|
||||
system.cpu4: completed 90000 read accesses @243710816
|
||||
system.cpu2: completed 90000 read accesses @243974160
|
||||
system.cpu6: completed 100000 read accesses @268915439
|
||||
system.cpu4: completed 90000 read accesses @243630762
|
||||
system.cpu2: completed 90000 read accesses @243633950
|
||||
system.cpu1: completed 90000 read accesses @243710816
|
||||
system.cpu3: completed 90000 read accesses @243974160
|
||||
system.cpu0: completed 100000 read accesses @268915439
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 24 2010 23:12:40
|
||||
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
|
||||
M5 started Feb 25 2010 02:22:18
|
||||
M5 executing on SC2B0619
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
|
||||
M5 compiled Jul 1 2010 14:37:40
|
||||
M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
|
||||
M5 started Jul 1 2010 14:37:50
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 268915439 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,529 +1,529 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 316880 # Number of bytes of host memory used
|
||||
host_seconds 287.16 # Real time elapsed on the host
|
||||
host_tick_rate 936456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318132 # Number of bytes of host memory used
|
||||
host_seconds 165.43 # Real time elapsed on the host
|
||||
host_tick_rate 1625594 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000269 # Number of seconds simulated
|
||||
sim_ticks 268915439 # Number of ticks simulated
|
||||
system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency
|
||||
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency
|
||||
system.cpu0.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency
|
||||
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency
|
||||
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits
|
||||
system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles
|
||||
system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses
|
||||
system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses
|
||||
system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
|
||||
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency
|
||||
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency
|
||||
system.cpu0.l1c.ReadReq_hits 7473 # number of ReadReq hits
|
||||
system.cpu0.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles
|
||||
system.cpu0.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses
|
||||
system.cpu0.l1c.ReadReq_misses 37586 # number of ReadReq misses
|
||||
system.cpu0.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses
|
||||
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency
|
||||
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency
|
||||
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits
|
||||
system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles
|
||||
system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses
|
||||
system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses
|
||||
system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses
|
||||
system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses
|
||||
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked
|
||||
system.cpu0.l1c.WriteReq_hits 923 # number of WriteReq hits
|
||||
system.cpu0.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles
|
||||
system.cpu0.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses
|
||||
system.cpu0.l1c.WriteReq_misses 23387 # number of WriteReq misses
|
||||
system.cpu0.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses
|
||||
system.cpu0.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses
|
||||
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked
|
||||
system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks.
|
||||
system.cpu0.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked
|
||||
system.cpu0.l1c.avg_refs 0.403583 # Average number of references to valid blocks.
|
||||
system.cpu0.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked
|
||||
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked
|
||||
system.cpu0.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked
|
||||
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses
|
||||
system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency
|
||||
system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
|
||||
system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits
|
||||
system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles
|
||||
system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses
|
||||
system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses
|
||||
system.cpu0.l1c.demand_accesses 69369 # number of demand (read+write) accesses
|
||||
system.cpu0.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency
|
||||
system.cpu0.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
|
||||
system.cpu0.l1c.demand_hits 8396 # number of demand (read+write) hits
|
||||
system.cpu0.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles
|
||||
system.cpu0.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses
|
||||
system.cpu0.l1c.demand_misses 60973 # number of demand (read+write) misses
|
||||
system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses
|
||||
system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses
|
||||
system.cpu0.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses
|
||||
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context
|
||||
system.cpu0.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context
|
||||
system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses
|
||||
system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency
|
||||
system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
|
||||
system.cpu0.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy
|
||||
system.cpu0.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context
|
||||
system.cpu0.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context
|
||||
system.cpu0.l1c.overall_accesses 69369 # number of overall (read+write) accesses
|
||||
system.cpu0.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency
|
||||
system.cpu0.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
|
||||
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu0.l1c.overall_hits 8674 # number of overall hits
|
||||
system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles
|
||||
system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses
|
||||
system.cpu0.l1c.overall_misses 60767 # number of overall misses
|
||||
system.cpu0.l1c.overall_hits 8396 # number of overall hits
|
||||
system.cpu0.l1c.overall_miss_latency 2453091767 # number of overall miss cycles
|
||||
system.cpu0.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses
|
||||
system.cpu0.l1c.overall_misses 60973 # number of overall misses
|
||||
system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles
|
||||
system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses
|
||||
system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses
|
||||
system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles
|
||||
system.cpu0.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses
|
||||
system.cpu0.l1c.overall_mshr_misses 60973 # number of overall MSHR misses
|
||||
system.cpu0.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu0.l1c.replacements 28158 # number of replacements
|
||||
system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks.
|
||||
system.cpu0.l1c.replacements 28139 # number of replacements
|
||||
system.cpu0.l1c.sampled_refs 28470 # Sample count of references to valid blocks.
|
||||
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use
|
||||
system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks.
|
||||
system.cpu0.l1c.tagsinuse 343.673683 # Cycle average of tags in use
|
||||
system.cpu0.l1c.total_refs 11490 # Total number of references to valid blocks.
|
||||
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.l1c.writebacks 11054 # number of writebacks
|
||||
system.cpu0.l1c.writebacks 11130 # number of writebacks
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99578 # number of read accesses completed
|
||||
system.cpu0.num_writes 53795 # number of write accesses completed
|
||||
system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency
|
||||
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 54239 # number of write accesses completed
|
||||
system.cpu1.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency
|
||||
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency
|
||||
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits
|
||||
system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles
|
||||
system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses
|
||||
system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses
|
||||
system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses
|
||||
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency
|
||||
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency
|
||||
system.cpu1.l1c.ReadReq_hits 7462 # number of ReadReq hits
|
||||
system.cpu1.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles
|
||||
system.cpu1.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses
|
||||
system.cpu1.l1c.ReadReq_misses 37225 # number of ReadReq misses
|
||||
system.cpu1.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles
|
||||
system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu1.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses
|
||||
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu1.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu1.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency
|
||||
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency
|
||||
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits
|
||||
system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles
|
||||
system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses
|
||||
system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses
|
||||
system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses
|
||||
system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses
|
||||
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked
|
||||
system.cpu1.l1c.WriteReq_hits 973 # number of WriteReq hits
|
||||
system.cpu1.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles
|
||||
system.cpu1.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses
|
||||
system.cpu1.l1c.WriteReq_misses 23193 # number of WriteReq misses
|
||||
system.cpu1.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles
|
||||
system.cpu1.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses
|
||||
system.cpu1.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses
|
||||
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked
|
||||
system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks.
|
||||
system.cpu1.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked
|
||||
system.cpu1.l1c.avg_refs 0.411354 # Average number of references to valid blocks.
|
||||
system.cpu1.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked
|
||||
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked
|
||||
system.cpu1.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked
|
||||
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses
|
||||
system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency
|
||||
system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
|
||||
system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits
|
||||
system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles
|
||||
system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses
|
||||
system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses
|
||||
system.cpu1.l1c.demand_accesses 68853 # number of demand (read+write) accesses
|
||||
system.cpu1.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency
|
||||
system.cpu1.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
|
||||
system.cpu1.l1c.demand_hits 8435 # number of demand (read+write) hits
|
||||
system.cpu1.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles
|
||||
system.cpu1.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses
|
||||
system.cpu1.l1c.demand_misses 60418 # number of demand (read+write) misses
|
||||
system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses
|
||||
system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu1.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses
|
||||
system.cpu1.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses
|
||||
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context
|
||||
system.cpu1.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context
|
||||
system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses
|
||||
system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency
|
||||
system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
|
||||
system.cpu1.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy
|
||||
system.cpu1.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context
|
||||
system.cpu1.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context
|
||||
system.cpu1.l1c.overall_accesses 68853 # number of overall (read+write) accesses
|
||||
system.cpu1.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency
|
||||
system.cpu1.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
|
||||
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu1.l1c.overall_hits 8551 # number of overall hits
|
||||
system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles
|
||||
system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses
|
||||
system.cpu1.l1c.overall_misses 60450 # number of overall misses
|
||||
system.cpu1.l1c.overall_hits 8435 # number of overall hits
|
||||
system.cpu1.l1c.overall_miss_latency 2449625152 # number of overall miss cycles
|
||||
system.cpu1.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses
|
||||
system.cpu1.l1c.overall_misses 60418 # number of overall misses
|
||||
system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles
|
||||
system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses
|
||||
system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses
|
||||
system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles
|
||||
system.cpu1.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses
|
||||
system.cpu1.l1c.overall_mshr_misses 60418 # number of overall MSHR misses
|
||||
system.cpu1.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles
|
||||
system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu1.l1c.replacements 27563 # number of replacements
|
||||
system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks.
|
||||
system.cpu1.l1c.replacements 27721 # number of replacements
|
||||
system.cpu1.l1c.sampled_refs 28078 # Sample count of references to valid blocks.
|
||||
system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use
|
||||
system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks.
|
||||
system.cpu1.l1c.tagsinuse 344.718702 # Cycle average of tags in use
|
||||
system.cpu1.l1c.total_refs 11550 # Total number of references to valid blocks.
|
||||
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.l1c.writebacks 10923 # number of writebacks
|
||||
system.cpu1.l1c.writebacks 10846 # number of writebacks
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99680 # number of read accesses completed
|
||||
system.cpu1.num_writes 54175 # number of write accesses completed
|
||||
system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency
|
||||
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency
|
||||
system.cpu1.num_reads 99301 # number of read accesses completed
|
||||
system.cpu1.num_writes 53586 # number of write accesses completed
|
||||
system.cpu2.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu2.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency
|
||||
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency
|
||||
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits
|
||||
system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles
|
||||
system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses
|
||||
system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses
|
||||
system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses
|
||||
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency
|
||||
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency
|
||||
system.cpu2.l1c.ReadReq_hits 7472 # number of ReadReq hits
|
||||
system.cpu2.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles
|
||||
system.cpu2.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses
|
||||
system.cpu2.l1c.ReadReq_misses 37075 # number of ReadReq misses
|
||||
system.cpu2.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles
|
||||
system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses
|
||||
system.cpu2.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses
|
||||
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu2.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu2.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency
|
||||
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency
|
||||
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits
|
||||
system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles
|
||||
system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses
|
||||
system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses
|
||||
system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses
|
||||
system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses
|
||||
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked
|
||||
system.cpu2.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles
|
||||
system.cpu2.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses
|
||||
system.cpu2.l1c.WriteReq_misses 23395 # number of WriteReq misses
|
||||
system.cpu2.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles
|
||||
system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses
|
||||
system.cpu2.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses
|
||||
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked
|
||||
system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks.
|
||||
system.cpu2.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked
|
||||
system.cpu2.l1c.avg_refs 0.410620 # Average number of references to valid blocks.
|
||||
system.cpu2.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked
|
||||
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked
|
||||
system.cpu2.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked
|
||||
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses
|
||||
system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency
|
||||
system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
|
||||
system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits
|
||||
system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles
|
||||
system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses
|
||||
system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses
|
||||
system.cpu2.l1c.demand_accesses 68832 # number of demand (read+write) accesses
|
||||
system.cpu2.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency
|
||||
system.cpu2.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
|
||||
system.cpu2.l1c.demand_hits 8362 # number of demand (read+write) hits
|
||||
system.cpu2.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles
|
||||
system.cpu2.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses
|
||||
system.cpu2.l1c.demand_misses 60470 # number of demand (read+write) misses
|
||||
system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses
|
||||
system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu2.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses
|
||||
system.cpu2.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses
|
||||
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu2.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context
|
||||
system.cpu2.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context
|
||||
system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses
|
||||
system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency
|
||||
system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
|
||||
system.cpu2.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy
|
||||
system.cpu2.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context
|
||||
system.cpu2.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context
|
||||
system.cpu2.l1c.overall_accesses 68832 # number of overall (read+write) accesses
|
||||
system.cpu2.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency
|
||||
system.cpu2.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
|
||||
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu2.l1c.overall_hits 8437 # number of overall hits
|
||||
system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles
|
||||
system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses
|
||||
system.cpu2.l1c.overall_misses 60562 # number of overall misses
|
||||
system.cpu2.l1c.overall_hits 8362 # number of overall hits
|
||||
system.cpu2.l1c.overall_miss_latency 2452523238 # number of overall miss cycles
|
||||
system.cpu2.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses
|
||||
system.cpu2.l1c.overall_misses 60470 # number of overall misses
|
||||
system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles
|
||||
system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses
|
||||
system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses
|
||||
system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles
|
||||
system.cpu2.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles
|
||||
system.cpu2.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses
|
||||
system.cpu2.l1c.overall_mshr_misses 60470 # number of overall MSHR misses
|
||||
system.cpu2.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles
|
||||
system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu2.l1c.replacements 27725 # number of replacements
|
||||
system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks.
|
||||
system.cpu2.l1c.replacements 27632 # number of replacements
|
||||
system.cpu2.l1c.sampled_refs 27965 # Sample count of references to valid blocks.
|
||||
system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use
|
||||
system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks.
|
||||
system.cpu2.l1c.tagsinuse 343.014216 # Cycle average of tags in use
|
||||
system.cpu2.l1c.total_refs 11483 # Total number of references to valid blocks.
|
||||
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu2.l1c.writebacks 10868 # number of writebacks
|
||||
system.cpu2.l1c.writebacks 10950 # number of writebacks
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99153 # number of read accesses completed
|
||||
system.cpu2.num_writes 52976 # number of write accesses completed
|
||||
system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency
|
||||
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency
|
||||
system.cpu2.num_reads 99024 # number of read accesses completed
|
||||
system.cpu2.num_writes 53903 # number of write accesses completed
|
||||
system.cpu3.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu3.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency
|
||||
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency
|
||||
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits
|
||||
system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles
|
||||
system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses
|
||||
system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses
|
||||
system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses
|
||||
system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses
|
||||
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency
|
||||
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency
|
||||
system.cpu3.l1c.ReadReq_hits 7547 # number of ReadReq hits
|
||||
system.cpu3.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles
|
||||
system.cpu3.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses
|
||||
system.cpu3.l1c.ReadReq_misses 37391 # number of ReadReq misses
|
||||
system.cpu3.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles
|
||||
system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses
|
||||
system.cpu3.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses
|
||||
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu3.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu3.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency
|
||||
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency
|
||||
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits
|
||||
system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles
|
||||
system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses
|
||||
system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses
|
||||
system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles
|
||||
system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses
|
||||
system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses
|
||||
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked
|
||||
system.cpu3.l1c.WriteReq_hits 890 # number of WriteReq hits
|
||||
system.cpu3.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles
|
||||
system.cpu3.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses
|
||||
system.cpu3.l1c.WriteReq_misses 23171 # number of WriteReq misses
|
||||
system.cpu3.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles
|
||||
system.cpu3.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses
|
||||
system.cpu3.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses
|
||||
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked
|
||||
system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks.
|
||||
system.cpu3.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked
|
||||
system.cpu3.l1c.avg_refs 0.410349 # Average number of references to valid blocks.
|
||||
system.cpu3.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked
|
||||
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked
|
||||
system.cpu3.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked
|
||||
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses
|
||||
system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency
|
||||
system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
|
||||
system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits
|
||||
system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles
|
||||
system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses
|
||||
system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses
|
||||
system.cpu3.l1c.demand_accesses 68999 # number of demand (read+write) accesses
|
||||
system.cpu3.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency
|
||||
system.cpu3.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
|
||||
system.cpu3.l1c.demand_hits 8437 # number of demand (read+write) hits
|
||||
system.cpu3.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles
|
||||
system.cpu3.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses
|
||||
system.cpu3.l1c.demand_misses 60562 # number of demand (read+write) misses
|
||||
system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses
|
||||
system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses
|
||||
system.cpu3.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu3.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses
|
||||
system.cpu3.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses
|
||||
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu3.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context
|
||||
system.cpu3.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context
|
||||
system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses
|
||||
system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency
|
||||
system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
|
||||
system.cpu3.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy
|
||||
system.cpu3.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context
|
||||
system.cpu3.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context
|
||||
system.cpu3.l1c.overall_accesses 68999 # number of overall (read+write) accesses
|
||||
system.cpu3.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency
|
||||
system.cpu3.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency
|
||||
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu3.l1c.overall_hits 8535 # number of overall hits
|
||||
system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles
|
||||
system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses
|
||||
system.cpu3.l1c.overall_misses 60533 # number of overall misses
|
||||
system.cpu3.l1c.overall_hits 8437 # number of overall hits
|
||||
system.cpu3.l1c.overall_miss_latency 2458156635 # number of overall miss cycles
|
||||
system.cpu3.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses
|
||||
system.cpu3.l1c.overall_misses 60562 # number of overall misses
|
||||
system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles
|
||||
system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses
|
||||
system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses
|
||||
system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles
|
||||
system.cpu3.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles
|
||||
system.cpu3.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses
|
||||
system.cpu3.l1c.overall_mshr_misses 60562 # number of overall MSHR misses
|
||||
system.cpu3.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles
|
||||
system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu3.l1c.replacements 27562 # number of replacements
|
||||
system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks.
|
||||
system.cpu3.l1c.replacements 27725 # number of replacements
|
||||
system.cpu3.l1c.sampled_refs 28081 # Sample count of references to valid blocks.
|
||||
system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use
|
||||
system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks.
|
||||
system.cpu3.l1c.tagsinuse 346.450009 # Cycle average of tags in use
|
||||
system.cpu3.l1c.total_refs 11523 # Total number of references to valid blocks.
|
||||
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu3.l1c.writebacks 10850 # number of writebacks
|
||||
system.cpu3.l1c.writebacks 10868 # number of writebacks
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99282 # number of read accesses completed
|
||||
system.cpu3.num_writes 53764 # number of write accesses completed
|
||||
system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency
|
||||
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency
|
||||
system.cpu3.num_reads 99153 # number of read accesses completed
|
||||
system.cpu3.num_writes 52976 # number of write accesses completed
|
||||
system.cpu4.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu4.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency
|
||||
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency
|
||||
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits
|
||||
system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles
|
||||
system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses
|
||||
system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses
|
||||
system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles
|
||||
system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses
|
||||
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency
|
||||
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency
|
||||
system.cpu4.l1c.ReadReq_hits 7629 # number of ReadReq hits
|
||||
system.cpu4.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles
|
||||
system.cpu4.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses
|
||||
system.cpu4.l1c.ReadReq_misses 37136 # number of ReadReq misses
|
||||
system.cpu4.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles
|
||||
system.cpu4.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses
|
||||
system.cpu4.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses
|
||||
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu4.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu4.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency
|
||||
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency
|
||||
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits
|
||||
system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles
|
||||
system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses
|
||||
system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses
|
||||
system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles
|
||||
system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses
|
||||
system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses
|
||||
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked
|
||||
system.cpu4.l1c.WriteReq_hits 906 # number of WriteReq hits
|
||||
system.cpu4.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles
|
||||
system.cpu4.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses
|
||||
system.cpu4.l1c.WriteReq_misses 23397 # number of WriteReq misses
|
||||
system.cpu4.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles
|
||||
system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses
|
||||
system.cpu4.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses
|
||||
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked
|
||||
system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks.
|
||||
system.cpu4.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked
|
||||
system.cpu4.l1c.avg_refs 0.418843 # Average number of references to valid blocks.
|
||||
system.cpu4.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked
|
||||
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu4.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked
|
||||
system.cpu4.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked
|
||||
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses
|
||||
system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency
|
||||
system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
|
||||
system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits
|
||||
system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles
|
||||
system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses
|
||||
system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses
|
||||
system.cpu4.l1c.demand_accesses 69068 # number of demand (read+write) accesses
|
||||
system.cpu4.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency
|
||||
system.cpu4.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
|
||||
system.cpu4.l1c.demand_hits 8535 # number of demand (read+write) hits
|
||||
system.cpu4.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles
|
||||
system.cpu4.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses
|
||||
system.cpu4.l1c.demand_misses 60533 # number of demand (read+write) misses
|
||||
system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses
|
||||
system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses
|
||||
system.cpu4.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu4.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses
|
||||
system.cpu4.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses
|
||||
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu4.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context
|
||||
system.cpu4.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context
|
||||
system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses
|
||||
system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency
|
||||
system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency
|
||||
system.cpu4.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy
|
||||
system.cpu4.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context
|
||||
system.cpu4.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context
|
||||
system.cpu4.l1c.overall_accesses 69068 # number of overall (read+write) accesses
|
||||
system.cpu4.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency
|
||||
system.cpu4.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency
|
||||
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu4.l1c.overall_hits 8435 # number of overall hits
|
||||
system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles
|
||||
system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses
|
||||
system.cpu4.l1c.overall_misses 60418 # number of overall misses
|
||||
system.cpu4.l1c.overall_hits 8535 # number of overall hits
|
||||
system.cpu4.l1c.overall_miss_latency 2459294321 # number of overall miss cycles
|
||||
system.cpu4.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses
|
||||
system.cpu4.l1c.overall_misses 60533 # number of overall misses
|
||||
system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles
|
||||
system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses
|
||||
system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses
|
||||
system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles
|
||||
system.cpu4.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles
|
||||
system.cpu4.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses
|
||||
system.cpu4.l1c.overall_mshr_misses 60533 # number of overall MSHR misses
|
||||
system.cpu4.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles
|
||||
system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu4.l1c.replacements 27721 # number of replacements
|
||||
system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks.
|
||||
system.cpu4.l1c.replacements 27562 # number of replacements
|
||||
system.cpu4.l1c.sampled_refs 27915 # Sample count of references to valid blocks.
|
||||
system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use
|
||||
system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks.
|
||||
system.cpu4.l1c.tagsinuse 345.337496 # Cycle average of tags in use
|
||||
system.cpu4.l1c.total_refs 11692 # Total number of references to valid blocks.
|
||||
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu4.l1c.writebacks 10846 # number of writebacks
|
||||
system.cpu4.l1c.writebacks 10850 # number of writebacks
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99301 # number of read accesses completed
|
||||
system.cpu4.num_writes 53586 # number of write accesses completed
|
||||
system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency
|
||||
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency
|
||||
system.cpu4.num_reads 99282 # number of read accesses completed
|
||||
system.cpu4.num_writes 53764 # number of write accesses completed
|
||||
system.cpu5.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu5.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency
|
||||
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency
|
||||
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits
|
||||
system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles
|
||||
system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses
|
||||
system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses
|
||||
system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles
|
||||
system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses
|
||||
system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses
|
||||
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency
|
||||
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency
|
||||
system.cpu5.l1c.ReadReq_hits 7762 # number of ReadReq hits
|
||||
system.cpu5.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles
|
||||
system.cpu5.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses
|
||||
system.cpu5.l1c.ReadReq_misses 37405 # number of ReadReq misses
|
||||
system.cpu5.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles
|
||||
system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses
|
||||
system.cpu5.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses
|
||||
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu5.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu5.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency
|
||||
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency
|
||||
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits
|
||||
system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles
|
||||
system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses
|
||||
system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses
|
||||
system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles
|
||||
system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses
|
||||
system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses
|
||||
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked
|
||||
system.cpu5.l1c.WriteReq_hits 912 # number of WriteReq hits
|
||||
system.cpu5.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles
|
||||
system.cpu5.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses
|
||||
system.cpu5.l1c.WriteReq_misses 23362 # number of WriteReq misses
|
||||
system.cpu5.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles
|
||||
system.cpu5.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses
|
||||
system.cpu5.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses
|
||||
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked
|
||||
system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks.
|
||||
system.cpu5.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked
|
||||
system.cpu5.l1c.avg_refs 0.412252 # Average number of references to valid blocks.
|
||||
system.cpu5.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked
|
||||
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu5.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked
|
||||
system.cpu5.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked
|
||||
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses
|
||||
system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency
|
||||
system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
|
||||
system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits
|
||||
system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles
|
||||
system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses
|
||||
system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses
|
||||
system.cpu5.l1c.demand_accesses 69441 # number of demand (read+write) accesses
|
||||
system.cpu5.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency
|
||||
system.cpu5.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
|
||||
system.cpu5.l1c.demand_hits 8674 # number of demand (read+write) hits
|
||||
system.cpu5.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles
|
||||
system.cpu5.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses
|
||||
system.cpu5.l1c.demand_misses 60767 # number of demand (read+write) misses
|
||||
system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses
|
||||
system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses
|
||||
system.cpu5.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu5.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses
|
||||
system.cpu5.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses
|
||||
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu5.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context
|
||||
system.cpu5.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context
|
||||
system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses
|
||||
system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency
|
||||
system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency
|
||||
system.cpu5.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy
|
||||
system.cpu5.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context
|
||||
system.cpu5.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context
|
||||
system.cpu5.l1c.overall_accesses 69441 # number of overall (read+write) accesses
|
||||
system.cpu5.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency
|
||||
system.cpu5.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency
|
||||
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu5.l1c.overall_hits 8362 # number of overall hits
|
||||
system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles
|
||||
system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses
|
||||
system.cpu5.l1c.overall_misses 60470 # number of overall misses
|
||||
system.cpu5.l1c.overall_hits 8674 # number of overall hits
|
||||
system.cpu5.l1c.overall_miss_latency 2449640896 # number of overall miss cycles
|
||||
system.cpu5.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses
|
||||
system.cpu5.l1c.overall_misses 60767 # number of overall misses
|
||||
system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles
|
||||
system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses
|
||||
system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses
|
||||
system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles
|
||||
system.cpu5.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles
|
||||
system.cpu5.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses
|
||||
system.cpu5.l1c.overall_mshr_misses 60767 # number of overall MSHR misses
|
||||
system.cpu5.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles
|
||||
system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu5.l1c.replacements 27632 # number of replacements
|
||||
system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks.
|
||||
system.cpu5.l1c.replacements 28158 # number of replacements
|
||||
system.cpu5.l1c.sampled_refs 28502 # Sample count of references to valid blocks.
|
||||
system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use
|
||||
system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks.
|
||||
system.cpu5.l1c.tagsinuse 346.020042 # Cycle average of tags in use
|
||||
system.cpu5.l1c.total_refs 11750 # Total number of references to valid blocks.
|
||||
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu5.l1c.writebacks 10950 # number of writebacks
|
||||
system.cpu5.l1c.writebacks 11054 # number of writebacks
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99024 # number of read accesses completed
|
||||
system.cpu5.num_writes 53903 # number of write accesses completed
|
||||
system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency
|
||||
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency
|
||||
system.cpu5.num_reads 99578 # number of read accesses completed
|
||||
system.cpu5.num_writes 53795 # number of write accesses completed
|
||||
system.cpu6.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu6.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency
|
||||
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency
|
||||
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits
|
||||
system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles
|
||||
system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses
|
||||
system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses
|
||||
system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles
|
||||
system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses
|
||||
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency
|
||||
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency
|
||||
system.cpu6.l1c.ReadReq_hits 7617 # number of ReadReq hits
|
||||
system.cpu6.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles
|
||||
system.cpu6.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses
|
||||
system.cpu6.l1c.ReadReq_misses 37080 # number of ReadReq misses
|
||||
system.cpu6.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles
|
||||
system.cpu6.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses
|
||||
system.cpu6.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses
|
||||
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu6.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu6.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency
|
||||
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency
|
||||
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits
|
||||
system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles
|
||||
system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses
|
||||
system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses
|
||||
system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles
|
||||
system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses
|
||||
system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses
|
||||
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked
|
||||
system.cpu6.l1c.WriteReq_hits 934 # number of WriteReq hits
|
||||
system.cpu6.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles
|
||||
system.cpu6.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses
|
||||
system.cpu6.l1c.WriteReq_misses 23370 # number of WriteReq misses
|
||||
system.cpu6.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles
|
||||
system.cpu6.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses
|
||||
system.cpu6.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses
|
||||
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked
|
||||
system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks.
|
||||
system.cpu6.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked
|
||||
system.cpu6.l1c.avg_refs 0.415709 # Average number of references to valid blocks.
|
||||
system.cpu6.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked
|
||||
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu6.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked
|
||||
system.cpu6.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked
|
||||
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
|
||||
system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses
|
||||
system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency
|
||||
system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
|
||||
system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits
|
||||
system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles
|
||||
system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses
|
||||
system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses
|
||||
system.cpu6.l1c.demand_accesses 69001 # number of demand (read+write) accesses
|
||||
system.cpu6.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency
|
||||
system.cpu6.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
|
||||
system.cpu6.l1c.demand_hits 8551 # number of demand (read+write) hits
|
||||
system.cpu6.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles
|
||||
system.cpu6.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses
|
||||
system.cpu6.l1c.demand_misses 60450 # number of demand (read+write) misses
|
||||
system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses
|
||||
system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses
|
||||
system.cpu6.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu6.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses
|
||||
system.cpu6.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses
|
||||
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
|
||||
system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu6.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context
|
||||
system.cpu6.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context
|
||||
system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses
|
||||
system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency
|
||||
system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency
|
||||
system.cpu6.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy
|
||||
system.cpu6.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context
|
||||
system.cpu6.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context
|
||||
system.cpu6.l1c.overall_accesses 69001 # number of overall (read+write) accesses
|
||||
system.cpu6.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency
|
||||
system.cpu6.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency
|
||||
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu6.l1c.overall_hits 8396 # number of overall hits
|
||||
system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles
|
||||
system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses
|
||||
system.cpu6.l1c.overall_misses 60973 # number of overall misses
|
||||
system.cpu6.l1c.overall_hits 8551 # number of overall hits
|
||||
system.cpu6.l1c.overall_miss_latency 2447852326 # number of overall miss cycles
|
||||
system.cpu6.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses
|
||||
system.cpu6.l1c.overall_misses 60450 # number of overall misses
|
||||
system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles
|
||||
system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses
|
||||
system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses
|
||||
system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles
|
||||
system.cpu6.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles
|
||||
system.cpu6.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses
|
||||
system.cpu6.l1c.overall_mshr_misses 60450 # number of overall MSHR misses
|
||||
system.cpu6.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles
|
||||
system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu6.l1c.replacements 28139 # number of replacements
|
||||
system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks.
|
||||
system.cpu6.l1c.replacements 27563 # number of replacements
|
||||
system.cpu6.l1c.sampled_refs 27921 # Sample count of references to valid blocks.
|
||||
system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use
|
||||
system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks.
|
||||
system.cpu6.l1c.tagsinuse 342.745179 # Cycle average of tags in use
|
||||
system.cpu6.l1c.total_refs 11607 # Total number of references to valid blocks.
|
||||
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu6.l1c.writebacks 11130 # number of writebacks
|
||||
system.cpu6.l1c.writebacks 10923 # number of writebacks
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 54239 # number of write accesses completed
|
||||
system.cpu6.num_reads 99680 # number of read accesses completed
|
||||
system.cpu6.num_writes 54175 # number of write accesses completed
|
||||
system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency
|
||||
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
Loading…
Reference in a new issue