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X86: Update the stats for the new aux vectors in the ruby regression.

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I forgot to turn on ruby when updating the stats before.
This commit is contained in:
Gabe Black 2010-05-06 13:41:08 -07:00
parent 8b0c83008e
commit 81e68287bb
4 changed files with 116 additions and 127 deletions
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11
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
View file

@ -6,7 +6,7 @@ dummy=0
[system]
type=System
children=cpu physmem ruby
mem_mode=atomic
mem_mode=timing
physmem=system.physmem
[system.cpu]
@ -54,7 +54,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/x86/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -83,11 +83,11 @@ clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tech_nm=45
tracer=system.ruby.tracer
[system.ruby.debug]
@ -101,7 +101,7 @@ verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=true
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
@ -182,7 +182,10 @@ version=0
[system.ruby.network.topology.ext_links1.ext_node.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=0
size=134217728
use_map=false
version=0
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]

202
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
View file

@ -4,16 +4,11 @@
RubySystem config:
random_seed: 1234
randomization: 0
tech_nm: 45
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 134217728
total memory size bits: 27
Network Configuration
---------------------
@ -23,9 +18,9 @@ topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@ -39,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/21/2010 12:14:46
Real time: May/06/2010 00:07:43
Profiler Stats
--------------
@ -48,31 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.32
Virtual_time_in_minutes: 0.00533333
Virtual_time_in_hours: 8.88889e-05
Virtual_time_in_days: 3.7037e-06
Virtual_time_in_seconds: 0.2
Virtual_time_in_minutes: 0.00333333
Virtual_time_in_hours: 5.55556e-05
Virtual_time_in_days: 2.31481e-06
Ruby_current_time: 287334
Ruby_current_time: 276484
Ruby_start_time: 0
Ruby_cycles: 287334
Ruby_cycles: 276484
mbytes_resident: 34.1406
mbytes_total: 34.3242
resident_ratio: 0.994879
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
ruby_cycles_executed: 287335 [ 287335 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
mbytes_resident: 35.2148
mbytes_total: 226.969
resident_ratio: 0.15517
ruby_cycles_executed: [ 276485 ]
Busy Controller Counts:
L1Cache-0:0
@ -81,14 +65,14 @@ Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8874 average: 1 | standard deviation: 0 | 0 8874 ]
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8901 average: 1 | standard deviation: 0 | 0 8901 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 373 count: 8873 average: 31.383 | standard deviation: 65.1247 | 0 7435 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 6 5 6 6 3 335 255 166 323 190 5 5 4 3 1 12 13 5 9 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 13 16 13 8 0 3 3 2 2 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
miss_latency_1: [binsize: 2 max: 287 count: 6886 average: 19.1856 | standard deviation: 51.0326 | 0 6248 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 1 3 2 158 129 57 116 103 3 1 2 2 1 4 7 1 5 4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 6 4 3 5 5 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 2 max: 373 count: 1053 average: 91.7255 | standard deviation: 89.279 | 0 521 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 5 2 1 109 51 79 167 65 1 3 0 1 0 4 5 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 11 8 2 0 0 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 2 max: 281 count: 934 average: 53.2784 | standard deviation: 80.2311 | 0 666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 68 75 30 40 22 1 1 2 0 0 4 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 2 0 1 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
miss_latency_1: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_2: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -102,11 +86,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1438 average: 0 | standard deviation: 0 | 1438 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1434 average: 0 | standard deviation: 0 | 1434 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average: 0 | standard deviation: 0 | 1377 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average: 0 | standard deviation: 0 | 1373 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -120,138 +104,140 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7403
page_faults: 2289
page_reclaims: 10025
page_faults: 1
swaps: 0
block_inputs: 0
block_outputs: 0
block_inputs: 96
block_outputs: 72
Network Stats
-------------
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.156073
links_utilized_percent_switch_0_link_0: 0.0625405 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.249605 bw: 160000 base_latency: 1
links_utilized_percent_switch_0: 0.155303
links_utilized_percent_switch_0_link_0: 0.0622369 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.248369 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.156282
links_utilized_percent_switch_1_link_0: 0.0624012 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.250162 bw: 160000 base_latency: 1
links_utilized_percent_switch_1: 0.15552
links_utilized_percent_switch_1_link_0: 0.0620922 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.248947 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.249883
links_utilized_percent_switch_2_link_0: 0.250162 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.249605 bw: 160000 base_latency: 1
links_utilized_percent_switch_2: 0.248658
links_utilized_percent_switch_2_link_0: 0.248947 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.248369 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1438
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1438
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1377
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1377
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 36.9958%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 18.637%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 44.3672%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 36.3108%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 18.4459%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 45.2433%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1438 100%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1438 average: 7.26912 | standard deviation: 1.85842 | 0 71 3 0 134 0 0 0 1230 ]
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1377 100%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1377 average: 7.33842 | standard deviation: 1.77003 | 0 57 6 0 119 0 0 0 1195 ]
--- L1Cache 0 ---
- Event Counts -
Load 1053
Ifetch 6886
Load 1056
Ifetch 6910
Store 934
Data 1438
Data 1377
Fwd_GETX 0
Inv 0
Replacement 1434
Writeback_Ack 1434
Replacement 1373
Writeback_Ack 1373
Writeback_Nack 0
- Transitions -
I Load 532
I Ifetch 638
I Store 268
I Load 500
I Ifetch 623
I Store 254
I Inv 0 <--
I Replacement 0 <--
II Writeback_Nack 0 <--
M Load 521
M Ifetch 6248
M Store 666
M Load 556
M Ifetch 6287
M Store 680
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 1434
M Replacement 1373
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 1434
MI Writeback_Ack 1373
MI Writeback_Nack 0 <--
IS Data 1170
MII Fwd_GETX 0 <--
IM Data 268
IS Data 1123
IM Data 254
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
memory_total_requests: 2872
memory_reads: 1438
memory_writes: 1434
memory_refreshes: 599
memory_total_request_delays: 3924
memory_delays_per_request: 1.3663
memory_delays_in_input_queue: 1431
memory_delays_behind_head_of_bank_queue: 7
memory_delays_stalled_at_head_of_bank_queue: 2486
memory_stalls_for_bank_busy: 841
memory_total_requests: 2750
memory_reads: 1377
memory_writes: 1373
memory_refreshes: 576
memory_total_request_delays: 3664
memory_delays_per_request: 1.33236
memory_delays_in_input_queue: 1372
memory_delays_behind_head_of_bank_queue: 6
memory_delays_stalled_at_head_of_bank_queue: 2286
memory_stalls_for_bank_busy: 791
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 109
memory_stalls_for_bus: 1466
memory_stalls_for_arbitration: 78
memory_stalls_for_bus: 1373
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 70
memory_stalls_for_read_write_turnaround: 44
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 162 142 210 172 216 84 102 44 22 20 146 276 148 116 62 30 84 8 8 14 116 56 12 60 34 58 82 64 44 122 104 54
accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54
--- Directory 0 ---
- Event Counts -
GETX 1438
GETX 1377
GETS 0
PUTX 1434
PUTX 1373
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 1438
Memory_Ack 1434
Memory_Data 1377
Memory_Ack 1373
- Transitions -
I GETX 1438
I GETX 1377
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
M GETX 0 <--
M PUTX 1434
M PUTX 1373
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
@ -274,7 +260,7 @@ IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 1438
IM Memory_Data 1377
MI GETX 0 <--
MI GETS 0 <--
@ -282,7 +268,7 @@ MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 1434
MI Memory_Ack 1373
ID GETX 0 <--
ID GETS 0 <--

10
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 21 2010 12:13:38
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
M5 started Jan 21 2010 12:14:46
M5 executing on svvint07
M5 compiled May 6 2010 00:07:42
M5 revision e46d048f7e69 7074 default tip
M5 started May 6 2010 00:07:43
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 287334 because target called exit()
Exiting @ tick 276484 because target called exit()

20
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 52882 # Simulator instruction rate (inst/s)
host_mem_usage 349184 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_tick_rate 1596256 # Simulator tick rate (ticks/s)
host_inst_rate 108748 # Simulator instruction rate (inst/s)
host_mem_usage 232420 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 3137478 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 9519 # Number of instructions simulated
sim_seconds 0.000287 # Number of seconds simulated
sim_ticks 287334 # Number of ticks simulated
sim_insts 9561 # Number of instructions simulated
sim_seconds 0.000276 # Number of seconds simulated
sim_ticks 276484 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 287334 # number of cpu cycles simulated
system.cpu.num_insts 9519 # Number of instructions executed
system.cpu.num_refs 1987 # Number of memory references
system.cpu.numCycles 276484 # number of cpu cycles simulated
system.cpu.num_insts 9561 # Number of instructions executed
system.cpu.num_refs 1990 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------