merge regression updates
This commit is contained in:
Korey Sewell
commit
08c1a6f41b
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@ -204,7 +204,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -1,12 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 11 2011 02:50:17
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gem5 started Jun 11 2011 02:50:25
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gem5 compiled Jun 19 2011 23:40:02
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gem5 started Jun 20 2011 08:26:33
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gem5 executing on zooks
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command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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Hello world!
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Exiting @ tick 21139000 because target called exit()
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Exiting @ tick 21228000 because target called exit()
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@ -1,33 +1,33 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000021 # Number of seconds simulated
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sim_ticks 21139000 # Number of ticks simulated
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sim_ticks 21228000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 46714 # Simulator instruction rate (inst/s)
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host_tick_rate 154158882 # Simulator tick rate (ticks/s)
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host_mem_usage 159872 # Number of bytes of host memory used
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host_inst_rate 45998 # Simulator instruction rate (inst/s)
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host_tick_rate 152436103 # Simulator tick rate (ticks/s)
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host_mem_usage 157012 # Number of bytes of host memory used
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host_seconds 0.14 # Real time elapsed on the host
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sim_insts 6404 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1188 # DTB read hits
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system.cpu.dtb.read_hits 1186 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1195 # DTB read accesses
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system.cpu.dtb.write_hits 899 # DTB write hits
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system.cpu.dtb.read_accesses 1193 # DTB read accesses
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system.cpu.dtb.write_hits 898 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 902 # DTB write accesses
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system.cpu.dtb.data_hits 2087 # DTB hits
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system.cpu.dtb.write_accesses 901 # DTB write accesses
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system.cpu.dtb.data_hits 2084 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 2097 # DTB accesses
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system.cpu.itb.fetch_hits 955 # ITB hits
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system.cpu.dtb.data_accesses 2094 # DTB accesses
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system.cpu.itb.fetch_hits 932 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 972 # ITB accesses
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system.cpu.itb.fetch_accesses 949 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 42279 # number of cpu cycles simulated
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system.cpu.numCycles 42457 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 11424 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.threadCycles 11420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 34857 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 7422 # Number of cycles cpu stages are processed.
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system.cpu.activity 17.554814 # Percentage of cycles cpu is active
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system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 35048 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 7409 # Number of cycles cpu stages are processed.
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system.cpu.activity 17.450597 # Percentage of cycles cpu is active
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system.cpu.comLoads 1185 # Number of Load instructions committed
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system.cpu.comStores 865 # Number of Store instructions committed
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system.cpu.comBranches 1051 # Number of Branches instructions committed
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@ -61,79 +61,79 @@ system.cpu.comFloats 2 # Nu
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system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
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system.cpu.cpi 6.601968 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi 6.629763 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.601968 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.151470 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.cpi_total 6.629763 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.150835 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.151470 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 1673 # Number of BP lookups
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system.cpu.ipc_total 0.150835 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 1674 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 702 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1421 # Number of BTB lookups
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system.cpu.branch_predictor.condIncorrect 720 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1422 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 29.486277 # BTB Hit Percentage
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system.cpu.branch_predictor.BTBHitPct 29.465541 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 1103 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5160 # Number of Reads from Int. Register File
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system.cpu.branch_predictor.predictedNotTaken 1104 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5167 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9740 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9747 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 2133 # Number of Address Generations
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system.cpu.agen_unit.agens 2137 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 4442 # Number of Instructions Executed.
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system.cpu.execution_unit.executions 4444 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 37253 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 5026 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 11.887698 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 38359 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3920 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 9.271742 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 38092 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 4187 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 9.903262 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 40935 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 1344 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 3.178883 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 37801 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.idleCycles 37460 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4997 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 11.769555 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 38535 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3922 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 9.237582 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 38269 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 4188 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 9.864098 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 41117 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 3.156134 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 37979 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 10.591547 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.utilization 10.547142 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 139.199781 # Cycle average of tags in use
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system.cpu.icache.total_refs 583 # Total number of references to valid blocks.
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system.cpu.icache.tagsinuse 138.808044 # Cycle average of tags in use
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system.cpu.icache.total_refs 584 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1.936877 # Average number of references to valid blocks.
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system.cpu.icache.avg_refs 1.940199 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 139.199781 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.067969 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 583 # number of ReadReq hits
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system.cpu.icache.demand_hits 583 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 583 # number of overall hits
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system.cpu.icache.ReadReq_misses 372 # number of ReadReq misses
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system.cpu.icache.demand_misses 372 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 372 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 20556000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 20556000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 20556000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.389529 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.389529 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.389529 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55258.064516 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55258.064516 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55258.064516 # average overall miss latency
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system.cpu.icache.occ_blocks::0 138.808044 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.067777 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 584 # number of ReadReq hits
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system.cpu.icache.demand_hits 584 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 584 # number of overall hits
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system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses
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system.cpu.icache.demand_misses 348 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 348 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 19242000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 19242000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 19242000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 932 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 932 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 932 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.373391 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.373391 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.373391 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 55293.103448 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 55293.103448 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 55293.103448 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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@ -143,102 +143,102 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
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||||
system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
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||||
system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits
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||||
system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits
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||||
system.cpu.icache.ReadReq_mshr_misses 302 # number of ReadReq MSHR misses
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||||
system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses
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||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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||||
system.cpu.icache.ReadReq_mshr_miss_latency 16052500 # number of ReadReq MSHR miss cycles
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||||
system.cpu.icache.demand_mshr_miss_latency 16052500 # number of demand (read+write) MSHR miss cycles
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||||
system.cpu.icache.overall_mshr_miss_latency 16052500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency 16050000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 16050000 # number of demand (read+write) MSHR miss cycles
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||||
system.cpu.icache.overall_mshr_miss_latency 16050000 # number of overall MSHR miss cycles
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||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.316230 # mshr miss rate for ReadReq accesses
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||||
system.cpu.icache.demand_mshr_miss_rate 0.316230 # mshr miss rate for demand accesses
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||||
system.cpu.icache.overall_mshr_miss_rate 0.316230 # mshr miss rate for overall accesses
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||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.973510 # average ReadReq mshr miss latency
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||||
system.cpu.icache.demand_avg_mshr_miss_latency 53153.973510 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53153.973510 # average overall mshr miss latency
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system.cpu.icache.ReadReq_mshr_miss_rate 0.324034 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.324034 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.324034 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53145.695364 # average ReadReq mshr miss latency
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||||
system.cpu.icache.demand_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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||||
system.cpu.dcache.replacements 0 # number of replacements
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||||
system.cpu.dcache.tagsinuse 102.923226 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1704 # Total number of references to valid blocks.
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||||
system.cpu.dcache.tagsinuse 102.626911 # Cycle average of tags in use
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||||
system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
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||||
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.142857 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 102.923226 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.025128 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits
|
||||
system.cpu.dcache.occ_blocks::0 102.626911 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.025055 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 1704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 1704 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 251 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 349 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 349 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 5567500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 13605500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 19173000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 19173000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 1187 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 866 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 2053 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 2053 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.082561 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.289838 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.169995 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.169995 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56811.224490 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54205.179283 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 54936.962751 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 54936.962751 # average overall miss latency
|
||||
system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 1703 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 97 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 250 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 347 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 13555000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 19063500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 19063500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.081857 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.289017 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 54220 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 54938.040346 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 54938.040346 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1656500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 46013.888889 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 178 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 181 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 181 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 177 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 179 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 179 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5121500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3908500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9030000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9030000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3909500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9023500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9023500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084296 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.081831 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.081831 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53910.526316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53541.095890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53750 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.794521 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 195.664492 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 195.111607 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 195.664492 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.005971 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::0 195.111607 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.005954 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
|
|
@ -246,10 +246,10 @@ system.cpu.l2cache.ReadReq_misses 396 # nu
|
|||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 20706500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3820500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 24527000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 24527000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 20702500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3821500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
|
||||
|
|
@ -258,10 +258,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997481 # mi
|
|||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52289.141414 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52335.616438 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52296.375267 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52296.375267 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52279.040404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52349.315068 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -278,19 +278,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 73 # nu
|
|||
system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15879000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2941000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18820000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18820000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15876500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18819000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40098.484848 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40287.671233 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40127.931770 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40127.931770 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40092.171717 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
|
|
|
|||
Loading…
Reference in a new issue