Stats: Update stats for RAS and LRU fixes.
This commit is contained in:
Ali Saidi
parent
af2b14a362
commit
3965ecc36b
236 changed files with 34322 additions and 34511 deletions
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@ -1,13 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 11:50:11
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gem5 started Jun 4 2012 14:31:55
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gem5 compiled Jun 28 2012 22:05:18
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gem5 started Jun 28 2012 22:47:55
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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info: Launching CPU 1 @ 107002000
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Exiting @ tick 1899401490000 because m5_exit instruction encountered
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info: Launching CPU 1 @ 106801000
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Exiting @ tick 1896395899500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -1,12 +1,11 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 11:50:11
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gem5 started Jun 4 2012 14:16:04
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gem5 compiled Jun 28 2012 22:05:18
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gem5 started Jun 28 2012 22:47:37
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux
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0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 1858684403000 because m5_exit instruction encountered
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Exiting @ tick 1858879782500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -22,6 +22,7 @@ machine_type=RealView_PBX
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mem_mode=timing
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memories=system.realview.nvmem system.physmem
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midr_regval=890224640
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multi_proc=true
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num_work_ids=16
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readfile=tests/halt.sh
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symbolfile=
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@ -10,17 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr dccimvac' unimplemented
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warn: instruction 'mcr dccmvau' unimplemented
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warn: instruction 'mcr icimvau' unimplemented
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warn: 5654850500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
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warn: 5664849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
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warn: 5704830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
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warn: 5721485500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
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warn: 6170779000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
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warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
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warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
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warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
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warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
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warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
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warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
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warn: LCD dual screen mode not supported
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warn: 53396857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
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warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80d0, checker: 0xc71f6fc8
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warn: 55147144000: Instruction results do not match! (Values may not actually be integers) Inst: 0x71ef0, checker: 0x60000013
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warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr bpiallis' unimplemented
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warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
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warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
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warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
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warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
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warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
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warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
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warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
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hack: be nice to actually delete the event here
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@ -1,12 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 12:14:06
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gem5 started Jun 4 2012 18:58:44
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gem5 compiled Jun 28 2012 22:10:14
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gem5 started Jun 29 2012 01:32:52
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gem5 executing on zizzer
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
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command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
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info: Using bootloader at address 0x80000000
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 2501685689500 because m5_exit instruction encountered
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Exiting @ tick 2500827052500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -22,6 +22,7 @@ machine_type=RealView_PBX
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mem_mode=timing
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memories=system.physmem system.realview.nvmem
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midr_regval=890224640
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multi_proc=true
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num_work_ids=16
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readfile=tests/halt.sh
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symbolfile=
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@ -10,9 +10,11 @@ warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr dccimvac' unimplemented
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warn: instruction 'mcr dccmvau' unimplemented
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warn: instruction 'mcr icimvau' unimplemented
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: instruction 'mcr bpiallis' unimplemented
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warn: LCD dual screen mode not supported
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr icialluis' unimplemented
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hack: be nice to actually delete the event here
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@ -1,12 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 12:14:06
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gem5 started Jun 4 2012 18:58:50
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gem5 compiled Jun 28 2012 22:10:14
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gem5 started Jun 29 2012 01:33:16
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gem5 executing on zizzer
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
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command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
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info: Using bootloader at address 0x80000000
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 2570833934500 because m5_exit instruction encountered
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Exiting @ tick 2569716290500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -22,6 +22,7 @@ machine_type=RealView_PBX
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mem_mode=timing
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memories=system.realview.nvmem system.physmem
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midr_regval=890224640
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multi_proc=true
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num_work_ids=16
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readfile=tests/halt.sh
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symbolfile=
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@ -12,6 +12,8 @@ warn: instruction 'mcr dccmvau' unimplemented
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warn: instruction 'mcr icimvau' unimplemented
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warn: LCD dual screen mode not supported
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
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warn: instruction 'mcr icialluis' unimplemented
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warn: instruction 'mcr bpiallis' unimplemented
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hack: be nice to actually delete the event here
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@ -1,12 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 12:14:06
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gem5 started Jun 4 2012 18:55:16
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gem5 compiled Jun 28 2012 22:10:14
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gem5 started Jun 29 2012 01:31:55
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gem5 executing on zizzer
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
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command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
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info: Using bootloader at address 0x80000000
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 2501685689500 because m5_exit instruction encountered
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Exiting @ tick 2500827052500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -1,13 +1,12 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 13:44:28
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gem5 started Jun 4 2012 17:03:49
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gem5 compiled Jun 28 2012 22:08:09
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gem5 started Jun 29 2012 00:25:59
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gem5 executing on zizzer
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command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
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command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
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warning: add_child('terminal'): child 'terminal' already has parent
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
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0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 5157514159500 because m5_exit instruction encountered
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Exiting @ tick 5147413032500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -191,7 +191,7 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
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cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
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egid=100
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env=
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errout=cerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 4 2012 11:50:11
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gem5 started Jun 4 2012 13:43:43
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gem5 compiled Jun 28 2012 22:05:18
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gem5 started Jun 28 2012 22:10:24
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gem5 executing on zizzer
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command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
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command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -39,4 +39,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 274300226500 because target called exit()
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Exiting @ tick 271948359500 because target called exit()
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.274300 # Number of seconds simulated
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sim_ticks 274300226500 # Number of ticks simulated
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final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.271948 # Number of seconds simulated
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sim_ticks 271948359500 # Number of ticks simulated
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final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 112537 # Simulator instruction rate (inst/s)
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host_op_rate 112537 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 51289289 # Simulator tick rate (ticks/s)
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host_mem_usage 215256 # Number of bytes of host memory used
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host_seconds 5348.10 # Real time elapsed on the host
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host_inst_rate 167086 # Simulator instruction rate (inst/s)
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host_op_rate 167086 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 75497413 # Simulator tick rate (ticks/s)
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host_mem_usage 219024 # Number of bytes of host memory used
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host_seconds 3602.09 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 54720 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
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system.physmem.bytes_read::total 5894080 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 54720 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 54720 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3798144 # Number of bytes written to this memory
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system.physmem.bytes_written::total 3798144 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 855 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 92095 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59346 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 59346 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 199489 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 21288207 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 21487696 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 199489 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 199489 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 13846667 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 13846667 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 13846667 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 199489 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 21288207 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 35334364 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory
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system.physmem.bytes_written::total 57024 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
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||||
system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 114517577 # DTB read hits
|
||||
system.cpu.dtb.read_hits 114517207 # DTB read hits
|
||||
system.cpu.dtb.read_misses 2631 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 114520208 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39666608 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 114519838 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 39661898 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 39668910 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 154184185 # DTB hits
|
||||
system.cpu.dtb.write_accesses 39664200 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 154179105 # DTB hits
|
||||
system.cpu.dtb.data_misses 4933 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 154189118 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25020502 # ITB hits
|
||||
system.cpu.dtb.data_accesses 154184038 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25013413 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 25020524 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 25013435 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 548600454 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 543896720 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits
|
||||
system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups
|
||||
system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted
|
||||
system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect
|
||||
system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups
|
||||
system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits
|
||||
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
||||
system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage
|
||||
system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 155051949 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed.
|
||||
system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 155049936 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted
|
||||
system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts
|
||||
system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed.
|
||||
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 89.936283 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
||||
system.cpu.comStores 39451321 # Number of Store instructions committed
|
||||
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
||||
|
|
@ -114,72 +114,72 @@ system.cpu.committedInsts 601856964 # Nu
|
|||
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 30 # number of replacements
|
||||
system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25019479 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1021 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1021 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1021 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56709500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 56709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25012389 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1022 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55543.095005 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55543.095005 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,70 +188,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53526.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53526.315789 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.124914 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 334.641827 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38273706 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152394215 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152394215 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152394215 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152394215 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1571148 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1571148 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8150462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25247540000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33398002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33398002000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles
|
||||
system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 152406141 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1559222 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data 153965363
|
|||
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.029850 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010205 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010205 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010205 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010205 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.000094 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.000094 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 21439.553674 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21257.069353 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 12006000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4323.370544 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408190 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 923452 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1115753 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1115753 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1115753 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits
|
||||
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436902 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3562095500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466864500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466864500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9028960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9028960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9028960000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -318,65 +318,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17701.436650 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21509.285380 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19826.655980 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73798 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17696.811171 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 445686 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89684 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.969515 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 917 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22852.415153 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 538842 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.284159 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16057.614667 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 28.392088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1610.804416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.490040 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000866 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.049158 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540064 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170049 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364155 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364155 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364155 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60076 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60076 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92095 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92095 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21652.224350 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 719.469676 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 480.721127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660773 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.021956 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.014670 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.697400 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197093 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197107 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232986 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232986 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 430093 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 4120 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4961 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 21196 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 21196 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 25316 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 26157 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44029000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214315000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 258344000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1104963500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1104963500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 44029000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1319278500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1363307500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 44029000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1319278500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1363307500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
||||
|
|
@ -385,82 +388,82 @@ system.cpu.l2cache.demand_accesses::total 456250 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.158457 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236350 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.201852 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.201852 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52310.393829 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52174.395765 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52221.678701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52221.678701 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.024551 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083389 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083389 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 766500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9462.962963 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59346 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158457 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236350 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201852 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201852 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40008.338799 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40063.993941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40044.644117 # average overall mshr miss latency
|
||||
system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 891 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33775500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164851000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198626500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 849849500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 849849500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33775500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014700500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1048476000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -489,7 +489,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:45
|
||||
gem5 compiled Jun 28 2012 22:05:18
|
||||
gem5 started Jun 28 2012 22:10:29
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -39,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 134621123500 because target called exit()
|
||||
Exiting @ tick 133563007500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -158,7 +158,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:36
|
||||
gem5 compiled Jun 28 2012 22:05:18
|
||||
gem5 started Jun 28 2012 22:10:37
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -39,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 765623032000 because target called exit()
|
||||
Exiting @ tick 762853846000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.765623 # Number of seconds simulated
|
||||
sim_ticks 765623032000 # Number of ticks simulated
|
||||
final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.762854 # Number of seconds simulated
|
||||
sim_ticks 762853846000 # Number of ticks simulated
|
||||
final_tick 762853846000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1675799 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1675799 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2131786057 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214908 # Number of bytes of host memory used
|
||||
host_seconds 359.15 # Real time elapsed on the host
|
||||
host_inst_rate 2331221 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2331221 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2954822927 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219024 # Number of bytes of host memory used
|
||||
host_seconds 258.17 # Real time elapsed on the host
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 50880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5839104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5889984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 50880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 50880 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3797824 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3797824 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 795 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91236 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92031 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59341 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59341 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 66456 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 7626604 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7693060 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 66456 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 66456 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4960436 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4960436 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4960436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 66456 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 7626604 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12653496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1620160 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1670272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 56512 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 56512 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 25315 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 26098 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 883 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 883 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 65690 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2123814 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2189505 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 65690 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 65690 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 74080 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 74080 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 74080 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 65690 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2123814 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2263584 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1525707692 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 601856964 # Number of instructions committed
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.num_mem_refs 153970296 # nu
|
|||
system.cpu.num_load_insts 114516673 # Number of load instructions
|
||||
system.cpu.num_store_insts 39453623 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1531246064 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1525707692 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 673.337154 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 673.359193 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.337154 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328778 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 673.359193 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.328789 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.328789 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 601861103 # number of demand (read+write) hits
|
||||
|
|
@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 795 # n
|
|||
system.cpu.icache.demand_misses::total 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 795 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44016000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44016000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44016000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44016000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 601861898 # number of demand (read+write) accesses
|
||||
|
|
@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55366.037736 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55366.037736 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 795
|
|||
system.cpu.icache.demand_mshr_misses::total 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 795 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41631000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41631000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41631000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41631000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41631000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41631000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.170317 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.177385 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 578392000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.170317 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.warmup_cycle 571210000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.177385 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999555 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999555 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
|
||||
|
|
@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 455395 # n
|
|||
system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 455395 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4126262000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6081180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10207442000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10207442000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2990372000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2990372000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4448388000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4448388000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7438760000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7438760000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7438760000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7438760000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20504.999205 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23926.299265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22414.479737 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16334.742367 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16334.742367 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 408190 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 436902 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3522566000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5318691000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8841257000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8841257000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386676000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3685899000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3685899000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6072575000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6072575000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6072575000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6072575000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -258,65 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.999205 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20926.299265 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19414.479737 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 73734 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17823.514890 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 445709 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89622 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.973210 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 903 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22842.001450 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 538870 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23085 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 23.342863 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 364159 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92031 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21648.658638 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 668.310399 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 525.032413 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.660665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.020395 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016023 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.697083 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 197110 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 197122 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 232970 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 232970 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 430080 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 430092 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 430080 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 430092 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 783 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 4122 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4905 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 21193 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 21193 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 25315 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 26098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 25315 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 26098 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40716000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214344000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 255060000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1102036000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1102036000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40716000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1316380000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1357096000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40716000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1316380000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1357096000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
|
||||
|
|
@ -325,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 456190 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.158207 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.236340 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.201738 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.201738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984906 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.024279 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083383 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083383 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984906 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055589 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.057209 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055589 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.057209 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -355,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59341 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.158207 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.236340 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.201738 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.201738 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.writebacks::writebacks 883 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 883 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4122 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4905 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21193 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 21193 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 25315 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 26098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 25315 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 26098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 196200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1012600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1043920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1012600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1043920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020484 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024279 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083383 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083383 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057209 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055589 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057209 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -507,7 +507,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:39
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:37:13
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 164248292500 because target called exit()
|
||||
Exiting @ tick 163291004000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -95,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:49
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:38:20
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 301191370000 because target called exit()
|
||||
Exiting @ tick 301191365000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,38 +1,38 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.301191 # Number of seconds simulated
|
||||
sim_ticks 301191370000 # Number of ticks simulated
|
||||
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 301191365000 # Number of ticks simulated
|
||||
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2291609 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2421488 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1210789798 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221260 # Number of bytes of host memory used
|
||||
host_seconds 248.76 # Real time elapsed on the host
|
||||
sim_insts 570051644 # Number of instructions simulated
|
||||
sim_ops 602359851 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2280298136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 399862021 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2680160157 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2280298136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2280298136 # Number of instructions bytes read from this memory
|
||||
host_inst_rate 3330708 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3519478 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1759805795 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224176 # Number of bytes of host memory used
|
||||
host_seconds 171.15 # Real time elapsed on the host
|
||||
sim_insts 570051636 # Number of instructions simulated
|
||||
sim_ops 602359842 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 399862020 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2680160120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2280298100 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2280298100 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 236359611 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 236359611 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 570074534 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147793179 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 717867713 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 570074525 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147793178 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 717867703 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 69418858 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 69418858 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7570927866 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1327601189 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8898529055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7570927866 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7570927866 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 784748949 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 784748949 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7570927866 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2112350138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9683278004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7570927872 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1327601208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8898529080 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7570927872 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7570927872 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 784748962 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 784748962 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 602382741 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 602382731 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 570051644 # Number of instructions committed
|
||||
system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 570051636 # Number of instructions committed
|
||||
system.cpu.committedOps 602359842 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_func_calls 1995305 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522631 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_mem_refs 219173606 # number of memory refs
|
||||
system.cpu.num_load_insts 148952593 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 602382731 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:27:51
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:38:23
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 796762926000 because target called exit()
|
||||
Exiting @ tick 794147534000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.796763 # Number of seconds simulated
|
||||
sim_ticks 796762926000 # Number of ticks simulated
|
||||
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.794148 # Number of seconds simulated
|
||||
sim_ticks 794147534000 # Number of ticks simulated
|
||||
final_tick 794147534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1154549 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1219245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618008338 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230404 # Number of bytes of host memory used
|
||||
host_seconds 492.43 # Real time elapsed on the host
|
||||
sim_insts 568539343 # Number of instructions simulated
|
||||
sim_ops 600398281 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5720064 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5759488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3704704 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3704704 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 89376 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 89992 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57886 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 57886 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 49480 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 7179129 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7228609 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49480 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49480 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4649694 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4649694 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4649694 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 7179129 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11878304 # Total bandwidth to/from this memory (bytes/s)
|
||||
host_inst_rate 1549107 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1635914 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2163825213 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232760 # Number of bytes of host memory used
|
||||
host_seconds 367.01 # Real time elapsed on the host
|
||||
sim_insts 568539335 # Number of instructions simulated
|
||||
sim_ops 600398272 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1735040 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1774144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39104 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39104 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 194752 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 194752 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 611 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 27110 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 27721 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 3043 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 3043 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 49240 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2184783 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2234023 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 245234 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 245234 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 245234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49240 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2184783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2479257 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1588295068 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 568539343 # Number of instructions committed
|
||||
system.cpu.committedOps 600398281 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 568539335 # Number of instructions committed
|
||||
system.cpu.committedOps 600398272 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017095 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_func_calls 1995305 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522631 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470972 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_mem_refs 219173606 # number of memory refs
|
||||
system.cpu.num_load_insts 148952593 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1588295068 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 577.753136 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073883 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.576983 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.728532 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 570073892 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 570073892 # number of overall hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 577.753136 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.282106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.282106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 570073883 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 570073883 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 570073883 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 570073883 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 570073883 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 570073883 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 643 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 643 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 643 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34664000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34664000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34664000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34664000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34664000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34664000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 570074526 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 570074526 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 570074526 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 570074526 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 570074526 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 570074526 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53909.797823 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53909.797823 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 643
|
|||
system.cpu.icache.demand_mshr_misses::total 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 643 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32735000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32735000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32735000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4094.217417 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.222434 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 536853000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.217417 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999565 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999565 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 216771819 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 216771819 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
|
||||
|
|
@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 437564 # n
|
|||
system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2865114000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2865114000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4399402000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4399402000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7264516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7264516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7264516000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7264516000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002014
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16602.179338 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16602.179338 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 392392 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 392392 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 418219 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 418219 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 437564
|
|||
system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2295666000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2295666000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3656158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3656158000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5951824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5951824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5951824000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5951824000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71804 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 3963 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21581.956920 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 495400 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 24559 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 20.171831 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20942.700989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 130.076740 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 509.179191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.639121 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015539 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.658629 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 184871 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 184903 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 418219 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 418219 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 225583 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 225583 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 410454 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 410486 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 410454 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 410486 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 611 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 4945 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 5556 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 22165 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 22165 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 611 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 27110 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 27721 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 611 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 27110 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27721 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31772000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 257140000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 288912000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1152580000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1152580000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 31772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1409720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1441492000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 31772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1409720000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1441492000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 418219 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 418219 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
|
||||
|
|
@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 438207 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.165605 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.205364 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.205364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.950233 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026052 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.029172 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089466 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089466 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.950233 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.061957 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.063260 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.950233 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.061957 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.063260 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57886 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.205364 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.205364 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.writebacks::writebacks 3043 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 3043 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 611 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4945 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 5556 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22165 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 22165 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 611 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 27110 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 27721 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 611 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 27110 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27721 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 197800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 886600000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 886600000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1084400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1108840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1084400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1108840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.029172 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089466 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089466 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063260 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.950233 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.061957 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -489,7 +489,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:45:35
|
||||
gem5 compiled Jun 28 2012 22:06:58
|
||||
gem5 started Jun 28 2012 22:54:22
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 388554296500 because target called exit()
|
||||
Exiting @ tick 387353399000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -158,7 +158,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:45:45
|
||||
gem5 compiled Jun 28 2012 22:06:58
|
||||
gem5 started Jun 28 2012 22:54:27
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -38,4 +38,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2064258667000 because target called exit()
|
||||
Exiting @ tick 2061521023000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.064259 # Number of seconds simulated
|
||||
sim_ticks 2064258667000 # Number of ticks simulated
|
||||
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.061521 # Number of seconds simulated
|
||||
sim_ticks 2061521023000 # Number of ticks simulated
|
||||
final_tick 2061521023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1371910 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1375988 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1906915769 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223048 # Number of bytes of host memory used
|
||||
host_seconds 1082.51 # Real time elapsed on the host
|
||||
host_inst_rate 2065708 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2071849 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2867468443 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221124 # Number of bytes of host memory used
|
||||
host_seconds 718.93 # Real time elapsed on the host
|
||||
sim_insts 1485108101 # Number of instructions simulated
|
||||
sim_ops 1489523295 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 70592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5839360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5909952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3778240 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3778240 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1103 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 91240 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 92343 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 59035 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 59035 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 34197 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2828793 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2862990 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 34197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 34197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1830313 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1830313 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1830313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 34197 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2828793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4693303 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 65728 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 65728 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 161472 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 161472 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1027 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 26134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 27161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 2523 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 2523 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 31883 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 811331 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 843214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 31883 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 31883 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 78327 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 78327 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 78327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 31883 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 811331 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 921541 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4123042046 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1485108101 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 569365767 # nu
|
|||
system.cpu.num_load_insts 402515346 # Number of load instructions
|
||||
system.cpu.num_store_insts 166850421 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4128517334 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4123042046 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 118 # number of replacements
|
||||
system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 906.456939 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442603 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 906.456939 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.442606 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.442606 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 1107 # n
|
|||
system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1107 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58632000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 58632000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 58632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 58632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 58632000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 58632000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000001
|
|||
system.cpu.icache.demand_miss_rate::total 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52964.769648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52964.769648 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1107
|
|||
system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 55311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55311000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 55311000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55311000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 55311000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.226004 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.226955 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.warmup_cycle 566952000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4095.226004 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999811 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
|
||||
|
|
@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 453214 # n
|
|||
system.cpu.dcache.demand_misses::total 453214 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 453214 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 453214 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4019834000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 6156948000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 392000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10176782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10176782000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2888312000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2888312000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4554270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4554270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 140000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 140000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7442582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7442582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7442582000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7442582000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000796
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20775.839079 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23705.368693 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22454.694692 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 20000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16421.783087 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16421.783087 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 407009 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 407009 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 435341 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 259728 # number of WriteReq MSHR misses
|
||||
|
|
@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 453214
|
|||
system.cpu.dcache.demand_mshr_misses::total 453214 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3439376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5377764000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 371000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775086000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082940000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6082940000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082940000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6082940000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17775.839079 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20705.368693 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19454.694692 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 74112 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2614 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22186.870278 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 72.801131 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.540872 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 162271 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 162275 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 407009 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 199710 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 361981 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 361985 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 361981 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 361985 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1103 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 32318 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 60025 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1103 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 92343 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1103 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 92343 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57356000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1680536000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3121300000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4744480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4801836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4744480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4801836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.occ_blocks::writebacks 20830.127393 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 857.488075 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 499.254810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.635685 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.026168 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.015236 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.677090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 80 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 189212 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 189292 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 435341 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 435341 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 237875 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 237875 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 80 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 427087 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 427167 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 80 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 427087 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 427167 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1027 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 4274 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 5301 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 21860 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 21860 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 26134 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 27161 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 26134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27161 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 53404000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 222248000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 275652000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1136720000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1136720000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 53404000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1358968000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1412372000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 53404000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1358968000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1412372000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1107 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 193486 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 407009 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 435341 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 435341 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1107 # number of demand (read+write) accesses
|
||||
|
|
@ -316,17 +316,17 @@ system.cpu.l2cache.demand_accesses::total 454328 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 1107 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 453221 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996387 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.161330 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.166080 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.231101 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996387 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.201315 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.203252 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996387 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.203252 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.927733 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.022089 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.027241 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.084163 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.084163 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.927733 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.057663 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.059783 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.927733 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.057663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.059783 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -346,41 +346,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 59035 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1103 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 32318 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 60025 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1103 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 92343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1103 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 92343 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 44120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1292720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2401000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3693720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3693720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.161330 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.166080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231101 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.203252 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.203252 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.writebacks::writebacks 2523 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 2523 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1027 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4274 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 5301 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21860 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 21860 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 26134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 27161 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 26134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 41080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 170960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 874400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 874400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 41080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1045360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1086440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 41080000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1045360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1086440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022089 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027241 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.084163 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.084163 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.059783 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.927733 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.057663 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059783 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -510,7 +510,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:07:25
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:06:37
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -21,7 +21,6 @@ Uncompressed data compared correctly
|
|||
Compressing Input Data, level 3
|
||||
Compressed data 97831 bytes in length
|
||||
Uncompressing Data
|
||||
info: Increasing stack size by one page.
|
||||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Compressing Input Data, level 5
|
||||
|
|
@ -40,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 636988382500 because target called exit()
|
||||
Exiting @ tick 636762784500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:13:02
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:10:36
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
@ -39,4 +39,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1803258587000 because target called exit()
|
||||
Exiting @ tick 1800635309000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.803259 # Number of seconds simulated
|
||||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.800635 # Number of seconds simulated
|
||||
sim_ticks 1800635309000 # Number of ticks simulated
|
||||
final_tick 1800635309000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 587265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1082068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1203364849 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225604 # Number of bytes of host memory used
|
||||
host_seconds 1498.51 # Real time elapsed on the host
|
||||
host_inst_rate 904173 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1665987 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1850044030 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228536 # Number of bytes of host memory used
|
||||
host_seconds 973.29 # Real time elapsed on the host
|
||||
sim_insts 880025313 # Number of instructions simulated
|
||||
sim_ops 1621493983 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5679744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5725952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3712448 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3712448 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 160640 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 160640 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 722 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 88746 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 89468 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 58007 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 58007 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 25625 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3149711 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3175336 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 25625 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 25625 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2058744 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2058744 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2058744 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 25625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3149711 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5234080 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 26287 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 27009 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 2510 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 2510 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 25662 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 934319 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 959981 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 25662 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 25662 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 89213 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 89213 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 89213 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 25662 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 934319 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1049194 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3601270618 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 880025313 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 607228182 # nu
|
|||
system.cpu.num_load_insts 419042125 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3601270618 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 660.189072 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 660.189072 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.322358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.322358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
|
||||
|
|
@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.895332 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.895332 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 442048 # n
|
|||
system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2943878000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2943878000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4348848000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4348848000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7292726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7292726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7292726000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7292726000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000728
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 16497.588497 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 16497.588497 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 396372 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 422980 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 442048
|
|||
system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3614682000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3614682000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5966582000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5966582000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5966582000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5966582000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71208 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2581 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 22163.019096 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 353302 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 353302 # number of overall hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21019.596332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 596.850673 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 546.572092 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.016680 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.676362 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 193009 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 193009 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 422980 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 422980 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 222752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 222752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 415761 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 415761 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 415761 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 415761 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 30493 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 4317 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 5039 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 21970 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 21970 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 88746 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 26287 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 27009 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 88746 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 89468 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 26287 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27009 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1585636000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 224484000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 262028000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1142440000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1142440000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 37544000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1366924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1404468000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 37544000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4614792000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 4652336000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1366924000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1404468000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 422980 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 422980 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses
|
||||
|
|
@ -294,16 +294,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 722
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 442048 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.157613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021878 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.025443 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.089775 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.089775 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.202064 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.059466 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.061000 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.202064 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059466 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.061000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 58007 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 2510 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 2510 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4317 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 5039 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21970 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 21970 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 26287 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 27009 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 26287 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27009 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 878800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 878800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1051480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1080360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1051480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1080360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.157613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021878 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.025443 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089775 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089775 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.202064 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061000 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.202064 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059466 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061000 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -507,7 +507,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:32:09
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:41:22
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 25988864000 because target called exit()
|
||||
Exiting @ tick 25878583500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -95,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:36:14
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:44:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 54240666000 because target called exit()
|
||||
Exiting @ tick 54240661000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,38 +1,38 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.054241 # Number of seconds simulated
|
||||
sim_ticks 54240666000 # Number of ticks simulated
|
||||
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 54240661000 # Number of ticks simulated
|
||||
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2223712 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2239678 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1331261387 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354056 # Number of bytes of host memory used
|
||||
host_seconds 40.74 # Real time elapsed on the host
|
||||
sim_insts 90602415 # Number of instructions simulated
|
||||
sim_ops 91252969 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 431323116 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 90016599 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 521339715 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 431323116 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 431323116 # Number of instructions bytes read from this memory
|
||||
host_inst_rate 3184418 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3207282 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1906403630 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 357244 # Number of bytes of host memory used
|
||||
host_seconds 28.45 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91252960 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 107830779 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 22553295 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 130384074 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7952024704 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1659577687 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9611602391 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7952024704 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7952024704 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 348597084 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 348597084 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7952024704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2008174771 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9960199475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 108481333 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 108481323 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90602415 # Number of instructions committed
|
||||
system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 90602407 # Number of instructions committed
|
||||
system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525682 # number of integer instructions
|
||||
system.cpu.num_func_calls 112245 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525674 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27318811 # number of memory refs
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_mem_refs 27318810 # number of memory refs
|
||||
system.cpu.num_load_insts 22573966 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 108481333 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 108481323 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:37:05
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:44:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 148086239000 because target called exit()
|
||||
Exiting @ tick 148083373000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,39 +1,32 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.148086 # Number of seconds simulated
|
||||
sim_ticks 148086239000 # Number of ticks simulated
|
||||
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.148083 # Number of seconds simulated
|
||||
sim_ticks 148083373000 # Number of ticks simulated
|
||||
final_tick 148083373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1056603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1064179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1727464138 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 363220 # Number of bytes of host memory used
|
||||
host_seconds 85.72 # Real time elapsed on the host
|
||||
sim_insts 90576869 # Number of instructions simulated
|
||||
sim_ops 91226321 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1433979 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1444261 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2344399916 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 365828 # Number of bytes of host memory used
|
||||
host_seconds 63.16 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91226312 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 949120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 986112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 2048 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 2048 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14830 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15408 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 32 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 32 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 249800 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6409238 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6659039 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 249800 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 249800 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 13830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 13830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 13830 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 249800 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6409238 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6672869 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 249805 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6379974 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6629779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 249805 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 249805 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 249805 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6379974 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6629779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,43 +70,43 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 296172478 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 296166746 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90576869 # Number of instructions committed
|
||||
system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 90576861 # Number of instructions committed
|
||||
system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15548926 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525682 # number of integer instructions
|
||||
system.cpu.num_func_calls 112245 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525674 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27318811 # number of memory refs
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_mem_refs 27318810 # number of memory refs
|
||||
system.cpu.num_load_insts 22573966 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 296172478 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 296166746 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 510.334547 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 510.334547 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 107830181 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 107830172 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
|
||||
|
|
@ -126,12 +119,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 32662000
|
|||
system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
|
||||
|
|
@ -178,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3568.539568 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54479146000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3568.539568 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.871225 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.871225 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26337591 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
|
||||
|
|
@ -206,26 +199,26 @@ system.cpu.dcache.demand_misses::cpu.data 946798 # n
|
|||
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12611634000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12611634000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13875176000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13875176000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13875176000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13875176000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
|
||||
|
|
@ -234,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034701
|
|||
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14654.842955 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -250,8 +243,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 942309 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 942309 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 942334 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
|
||||
|
|
@ -260,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946798
|
|||
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,68 +269,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 634 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9598.880462 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1827210 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 119.246231 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8910.209882 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 165.071875 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 160.025936 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.271918 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005038 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004884 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.281839 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8910.241595 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 495.387120 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 193.251747 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.271919 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.015118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.005898 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.292935 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899907 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899928 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 931968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 931989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 931968 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 931989 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 932057 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14830 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14830 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15408 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 44720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 771160000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 801216000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 771160000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 801216000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 942334 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 942334 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses
|
||||
|
|
@ -347,16 +340,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 599
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000313 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015663 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016264 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016264 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -376,41 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 32 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 282 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14830 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14830 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 593200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 616320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 593200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 616320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000313 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000955 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015663 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:01:47
|
||||
gem5 started Jun 4 2012 14:55:10
|
||||
gem5 compiled Jun 28 2012 22:06:58
|
||||
gem5 started Jun 28 2012 22:55:42
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
|
||||
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 362430887000 because target called exit()
|
||||
Exiting @ tick 362428997000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.362431 # Number of seconds simulated
|
||||
sim_ticks 362430887000 # Number of ticks simulated
|
||||
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.362429 # Number of seconds simulated
|
||||
sim_ticks 362428997000 # Number of ticks simulated
|
||||
final_tick 362428997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1267775 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1267827 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1884467398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 355400 # Number of bytes of host memory used
|
||||
host_seconds 192.33 # Real time elapsed on the host
|
||||
host_inst_rate 1801112 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1801186 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2677225778 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 354292 # Number of bytes of host memory used
|
||||
host_seconds 135.37 # Real time elapsed on the host
|
||||
sim_insts 243825163 # Number of instructions simulated
|
||||
sim_ops 243835278 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 945216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1001472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 2560 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 2560 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14769 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15648 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 40 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 40 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 155219 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2607990 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2763208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2600057 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2755276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155219 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155219 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7063 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7063 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7063 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2607990 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2770272 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2600057 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2755276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 724861774 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 724857994 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825163 # Number of instructions committed
|
||||
|
|
@ -54,16 +47,16 @@ system.cpu.num_mem_refs 105711442 # nu
|
|||
system.cpu.num_load_insts 82803522 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 724861774 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 724857994 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 25 # number of replacements
|
||||
system.cpu.icache.tagsinuse 725.567632 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 725.567220 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 725.567220 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
|
||||
|
|
@ -136,12 +129,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3563.821484 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3563.821484 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
|
||||
|
|
@ -164,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
|
|||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12508482000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12508482000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12506592000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12506592000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1265712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1265712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 98000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 98000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13774194000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13774194000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13774194000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13774194000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13772304000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13772304000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13772304000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13772304000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -194,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.502082 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 24500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 24500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14660.150899 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14658.139334 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -212,8 +205,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 935237 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 935237 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 935266 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
|
||||
|
|
@ -224,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9829911000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9829911000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10955493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10955493000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10955493000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10955493000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -244,70 +237,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.502082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11660.150899 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 865 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9236.752232 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1585884 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15631 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 101.457616 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9744.405217 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8861.245791 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 244.574580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 130.931861 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007464 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.003996 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.281883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::writebacks 8861.272475 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 738.802087 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 144.330654 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.270425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.297376 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892655 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892658 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935237 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935237 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924802 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924805 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14769 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15648 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14769 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15648 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10504000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 56212000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767988000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 813696000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767988000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 813696000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935237 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935237 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
||||
|
|
@ -317,16 +310,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 882
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000226 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015719 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016639 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015719 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016639 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -346,41 +339,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 40 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 40 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1081 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14769 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15648 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14769 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15648 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016639 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016639 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -510,7 +510,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:14:48
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:13:04
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -24,4 +24,4 @@ flow value : 3080014995
|
|||
info: Increasing stack size by one page.
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 67388458000 because target called exit()
|
||||
Exiting @ tick 66545720000 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:22:27
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:17:22
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -23,4 +23,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 370010840000 because target called exit()
|
||||
Exiting @ tick 368062166000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.370011 # Number of seconds simulated
|
||||
sim_ticks 370010840000 # Number of ticks simulated
|
||||
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.368062 # Number of seconds simulated
|
||||
sim_ticks 368062166000 # Number of ticks simulated
|
||||
final_tick 368062166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 564351 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 993732 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1321716509 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 360832 # Number of bytes of host memory used
|
||||
host_seconds 279.95 # Real time elapsed on the host
|
||||
host_inst_rate 915530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1612102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2132888263 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 362628 # Number of bytes of host memory used
|
||||
host_seconds 172.57 # Real time elapsed on the host
|
||||
sim_insts 157988583 # Number of instructions simulated
|
||||
sim_ops 278192520 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 4849088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 4900800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 1885440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1885440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 14528 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 14528 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 808 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 75767 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 76575 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 29460 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 29460 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 139758 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13105259 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13245017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 139758 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 139758 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 5095634 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 5095634 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 5095634 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 139758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13105259 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 18340652 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 29370 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 30178 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140498 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5106963 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5247461 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140498 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140498 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 39472 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 39472 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 39472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140498 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5106963 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5286933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 740021680 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 736124332 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988583 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 122219139 # nu
|
|||
system.cpu.num_load_insts 90779388 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 740021680 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 736124332 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 665.896557 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 665.896557 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
|
||||
|
|
@ -136,14 +136,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4076.559519 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.661903 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4076.559519 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.995254 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.995254 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
|
|||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 27464486000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 27464486000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2704691000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2704691000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 30169177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 30169177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 30169177000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 30169177000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14596.842313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14596.842313 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1437080 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1437080 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 2061794 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2061794 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
|
|||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21582326000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21582326000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386362500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386362500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23968688500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23968688500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23968688500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23968688500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,65 +226,65 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.727544 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.727544 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.841587 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.841587 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 49212 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1081 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 19721.209952 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 12062.804989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 196.794797 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 6355.003474 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.368128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006006 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.193939 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.568073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1991062 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1991062 # number of overall hits
|
||||
system.cpu.l2cache.occ_blocks::writebacks 19369.116114 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 209.759091 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 142.334747 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.591099 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.006401 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.601844 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960377 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960377 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2061794 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2061794 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 77082 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 77082 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037459 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037459 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037459 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037459 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 33309 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 34117 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 343 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1151 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29027 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29027 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 75767 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 76575 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29370 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30178 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 75767 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 76575 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29370 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30178 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42016000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1732068000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1774084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17836000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 59852000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1509433500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42016000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 3939913500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 3981929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1527269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1569285500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42016000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 3939913500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 3981929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1527269500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1569285500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2061794 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2061794 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
||||
|
|
@ -294,27 +294,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 808
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.016988 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.017393 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000175 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000587 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273558 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273558 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.036659 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.037035 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014210 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.036659 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.037035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014210 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014595 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.016295 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.016295 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.977533 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.004426 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.977533 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -323,41 +323,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 29460 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 29460 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 227 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 227 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 343 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1151 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29027 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29027 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29370 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30178 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29370 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30178 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 46040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1161080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1161080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1174800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1207120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1174800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1207120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000175 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273558 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273558 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.037035 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.037035 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014210 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -507,7 +507,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:38:42
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:45:14
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 233057542500 because target called exit()
|
||||
Exiting @ tick 210036334500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -95,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:42:59
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:45:54
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 290498972000 because target called exit()
|
||||
Exiting @ tick 290498967000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,38 +1,38 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.290499 # Number of seconds simulated
|
||||
sim_ticks 290498972000 # Number of ticks simulated
|
||||
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 290498967000 # Number of ticks simulated
|
||||
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2223848 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1275264214 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224628 # Number of bytes of host memory used
|
||||
host_seconds 227.80 # Real time elapsed on the host
|
||||
sim_insts 506581615 # Number of instructions simulated
|
||||
sim_ops 570968176 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory
|
||||
host_inst_rate 3026360 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3411010 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1735464120 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228428 # Number of bytes of host memory used
|
||||
host_seconds 167.39 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 570968167 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 580997945 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 580997935 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506581615 # Number of instructions committed
|
||||
system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 506581607 # Number of instructions committed
|
||||
system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727695 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_mem_refs 182890034 # number of memory refs
|
||||
system.cpu.num_load_insts 126029555 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 580997945 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 580997935 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:46:58
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:48:24
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 722234364000 because target called exit()
|
||||
Exiting @ tick 718982756000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,39 +1,39 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.722234 # Number of seconds simulated
|
||||
sim_ticks 722234364000 # Number of ticks simulated
|
||||
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.718983 # Number of seconds simulated
|
||||
sim_ticks 718982756000 # Number of ticks simulated
|
||||
final_tick 718982756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1114772 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1594352181 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 233804 # Number of bytes of host memory used
|
||||
host_seconds 453.00 # Real time elapsed on the host
|
||||
sim_insts 504986861 # Number of instructions simulated
|
||||
sim_ops 569034848 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s)
|
||||
host_inst_rate 1474104 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1661066 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2098778351 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237008 # Number of bytes of host memory used
|
||||
host_seconds 342.57 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 248084 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 13441034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13689118 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 248084 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 248084 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 9144475 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 9144475 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 9144475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 248084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 13441034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 22833594 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1437965512 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986861 # Number of instructions committed
|
||||
system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 504986853 # Number of instructions committed
|
||||
system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727695 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_mem_refs 182890034 # number of memory refs
|
||||
system.cpu.num_load_insts 126029555 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1437965512 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 983.088334 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 516599864 # number of overall hits
|
||||
system.cpu.icache.occ_blocks::cpu.inst 983.088334 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.480024 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.480024 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 516599855 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 278348000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 278348000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 278348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 278348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 278348000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 278348000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24160.055551 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24160.055551 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
|||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243785000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243785000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243785000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243785000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243785000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243785000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4065.352134 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889977000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4065.352134 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.992518 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.992518 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176840705 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176840704 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
||||
|
|
@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n
|
|||
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12960486000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12960486000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9326282000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9326282000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22286768000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22286768000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22286768000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22286768000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
||||
|
|
@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19568.369277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19568.369277 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1025440 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1061444 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
||||
|
|
@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918
|
|||
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10612512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10612512000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257502000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257502000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870014000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18870014000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870014000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18870014000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 212089 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 919235 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.replacements 122482 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 26935.750905 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 344124821000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 23223.605882 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 246.683502 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 3465.461521 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.708728 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.007528 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.105757 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.822014 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 252959 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8734 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 987920 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 996654 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8734 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 987920 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 996654 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2787 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 47697 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 50484 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 103301 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 103301 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2787 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 150998 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 153785 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153785 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144924000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480244000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2625168000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5371652000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7851896000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7996820000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144924000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7851896000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7996820000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1061444 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1061444 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
|
||||
|
|
@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 1150439 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.132580 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.133675 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 172302 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.139985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.200970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.200970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.writebacks::writebacks 102730 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 102730 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2787 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 47697 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 50484 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103301 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 103301 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2787 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 150998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 153785 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111480000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1907880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6039920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6151400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6039920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6151400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.289960 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.289960 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -510,7 +510,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,15 +1,28 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:27:18
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:20:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: ***********************info: Increasing stack size by one page.
|
||||
**************************
|
||||
********************info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
******
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
|
|
@ -19,8 +32,6 @@ Welcome to the Link Parser -- Version 2.1
|
|||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
|
|
@ -64,19 +75,9 @@ Echoing of input sentence turned on.
|
|||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 459937575500 because target called exit()
|
||||
Exiting @ tick 455813328500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -179,7 +179,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 13:44:28
|
||||
gem5 started Jun 4 2012 15:45:58
|
||||
gem5 compiled Jun 28 2012 22:08:09
|
||||
gem5 started Jun 28 2012 23:33:45
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -69,4 +69,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 1658729604000 because target called exit()
|
||||
Exiting @ tick 1652422044000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.658730 # Number of seconds simulated
|
||||
sim_ticks 1658729604000 # Number of ticks simulated
|
||||
final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.652422 # Number of seconds simulated
|
||||
sim_ticks 1652422044000 # Number of ticks simulated
|
||||
final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 615589 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1234881669 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229524 # Number of bytes of host memory used
|
||||
host_seconds 1343.23 # Real time elapsed on the host
|
||||
host_inst_rate 1001096 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2000579398 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 231692 # Number of bytes of host memory used
|
||||
host_seconds 825.97 # Real time elapsed on the host
|
||||
sim_insts 826877145 # Number of instructions simulated
|
||||
sim_ops 1528988757 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3304844088 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877145 # Number of instructions committed
|
||||
|
|
@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262345 # nu
|
|||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3304844088 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
|
||||
|
|
@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
|
|||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
|
||||
|
|
@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
|
|||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
|
|||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n
|
|||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2223170 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2297113 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
|
|
@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458
|
|||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -226,68 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 568906 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 331576 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 579609 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17241952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles
|
||||
system.cpu.l2cache.replacements 403150 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 29113.171325 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 772998682000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 21035.686564 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 79.698096 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 7997.786666 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.641958 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.244073 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.888463 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 883 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1509854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1510737 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2297113 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2297113 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 581106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 581106 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 883 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2090960 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2091843 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 883 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2090960 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2091843 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 1931 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 217560 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 219491 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 209938 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 209938 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1931 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 427498 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 429429 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1931 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 427498 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 429429 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100412000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11313120000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11413532000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10916779000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10916779000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 100412000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22229899000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22330311000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 100412000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22229899000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22330311000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2297113 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2297113 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
|
||||
|
|
@ -296,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.170322 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.686212 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.169746 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.170322 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.014290 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.014290 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.006986 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.007018 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.006986 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -326,41 +326,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 411709 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.191637 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.229888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.229888 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.writebacks::writebacks 323570 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 323570 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1931 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 217560 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 219491 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 209938 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 209938 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1931 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 427498 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 429429 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1931 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 427498 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 429429 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 77240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8702400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8779640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8397520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8397520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 77240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17099920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17177160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 77240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17099920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17177160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:42:58
|
||||
gem5 compiled Jun 28 2012 22:05:18
|
||||
gem5 started Jun 28 2012 22:10:46
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.133333
|
||||
Exiting @ tick 141175129500 because target called exit()
|
||||
Exiting @ tick 141174877500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,32 +1,32 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.141175 # Number of seconds simulated
|
||||
sim_ticks 141175129500 # Number of ticks simulated
|
||||
final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 141174877500 # Number of ticks simulated
|
||||
final_tick 141174877500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110841 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 110841 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39251086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 221340 # Number of bytes of host memory used
|
||||
host_seconds 3596.72 # Real time elapsed on the host
|
||||
host_inst_rate 165783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 165783 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 58706881 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225068 # Number of bytes of host memory used
|
||||
host_seconds 2404.74 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 468608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 214592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 214592 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3353 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1520041 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1802017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3322058 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1520041 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1520041 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1520041 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1802017 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3322058 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7322 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1520044 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1799300 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 3319344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1520044 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1520044 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1520044 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1799300 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3319344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 282350260 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 282349756 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups
|
||||
|
|
@ -93,9 +93,9 @@ system.cpu.contextSwitches 1 # Nu
|
|||
system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.idleCycles 13475470 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 95.227214 # Percentage of cycles cpu is active
|
||||
system.cpu.activity 95.227384 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
||||
system.cpu.comStores 73520729 # Number of Store instructions committed
|
||||
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
||||
|
|
@ -107,34 +107,34 @@ system.cpu.committedInsts 398664595 # Nu
|
|||
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
||||
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
||||
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
||||
system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.cpi 0.708239 # CPI: Cycles Per Instruction (Per-Thread)
|
||||
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
||||
system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.cpi_total 0.708239 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.411953 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.ipc_total 1.411953 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 78535818 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.utilization 72.184917 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 108863135 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.utilization 61.443871 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 104640369 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.utilization 62.939451 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 183568295 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.utilization 34.985495 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 92657161 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.utilization 67.183552 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1974 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1829.918683 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1829.918683 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits
|
||||
|
|
@ -213,12 +213,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3284.843876 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.843893 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3284.843876 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.801964 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.801964 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753265 # number of ReadReq hits
|
||||
|
|
@ -237,14 +237,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n
|
|||
system.cpu.dcache.demand_misses::total 13259 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 13259 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 13259 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 63819000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 63819000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 63567000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 63567000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 626556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 626556000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 690375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 690375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 690375000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 690375000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 690123000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 690123000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 690123000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 690123000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -261,14 +261,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000079
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000079 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000079 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000079 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52139.705882 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 52139.705882 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52068.406365 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52068.406365 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52049.400407 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52049.400407 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 82410500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46180000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 46180000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45925000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45925000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 169537000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 169537000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215717000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 215717000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215717000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 215717000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215462000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 215462000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 215462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -311,63 +311,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48610.526316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48610.526316 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51954.961464 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51954.961464 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 13 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3896.685167 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 736 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.156031 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3900.421280 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 754 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4711 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.160051 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.518693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2902.345937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 623.820537 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 370.518684 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2902.345910 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 627.556686 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011307 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.088573 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019037 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.118917 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.119031 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 548 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 665 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 671 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 548 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 725 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 731 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 548 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 725 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 731 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3353 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 830 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4177 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3353 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7322 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3353 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7322 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175438000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43622500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 219060500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43307500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 218745500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164970500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 164970500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 175438000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 208593000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 384031000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 208278000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 383716000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 175438000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 208593000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 384031000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 208278000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 383716000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4848 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -382,27 +382,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3901
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 8053 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859523 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.862830 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.861592 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859523 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.909971 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.909226 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859523 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909971 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.909226 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.228916 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.232608 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52405.977074 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.226415 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52405.977074 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,49 +412,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3353 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4177 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3353 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3353 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7322 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33277500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160035000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 294626000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160035000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 294626000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862830 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861592 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909971 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909226 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909971 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909226 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.501076 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.264192 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -489,7 +489,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:46:44
|
||||
gem5 compiled Jun 28 2012 22:05:18
|
||||
gem5 started Jun 28 2012 22:10:52
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.066667
|
||||
Exiting @ tick 80257421500 because target called exit()
|
||||
Exiting @ tick 80278875500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -158,7 +158,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
|
||||
cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 11:50:11
|
||||
gem5 started Jun 4 2012 13:47:31
|
||||
gem5 compiled Jun 28 2012 22:05:18
|
||||
gem5 started Jun 28 2012 22:12:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Eon, Version 1.1
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.566667
|
||||
Exiting @ tick 567343170000 because target called exit()
|
||||
Exiting @ tick 567342918000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,32 +1,32 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567343 # Number of seconds simulated
|
||||
sim_ticks 567343170000 # Number of ticks simulated
|
||||
final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 567342918000 # Number of ticks simulated
|
||||
final_tick 567342918000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1377504 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1377504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1960338494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220796 # Number of bytes of host memory used
|
||||
host_seconds 289.41 # Real time elapsed on the host
|
||||
host_inst_rate 2055836 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2055836 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2925676505 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224040 # Number of bytes of host memory used
|
||||
host_seconds 193.92 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 459520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3975 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7180 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 361545 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 448406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809951 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447729 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809274 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 448406 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809951 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447729 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809274 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 1134686340 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134685836 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
|
|
@ -79,16 +79,16 @@ system.cpu.num_mem_refs 168275276 # nu
|
|||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134686340 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1134685836 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1795.131074 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1795.131072 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1795.131072 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
|
|
@ -161,12 +161,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3288.912598 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3288.912595 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3288.912598 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3288.912595 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.802957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.802957 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
|
|
@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n
|
|||
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 48286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 48286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 48034000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 48034000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 176792000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 176792000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 225078000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 225078000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 225078000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 225078000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 224826000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 224826000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 224826000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 224826000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50827.368421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54209.537572 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54209.537572 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54148.843931 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212622000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212622000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212622000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212622000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -251,63 +251,63 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47827.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51209.537572 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 13 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3768.712262 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 656 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4572 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.143482 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3772.462815 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 674 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.147613 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 371.536808 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2770.454482 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 626.720973 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 371.536806 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2770.454477 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 630.471532 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019126 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.115012 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.115126 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 117 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 585 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 177 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 645 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 177 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 645 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 833 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4038 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7180 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7180 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43316000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 209976000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 206700000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 373360000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 206700000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 373360000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -322,16 +322,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 3673
|
|||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.873459 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.917572 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.917572 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -352,38 +352,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.873459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.917572 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.917572 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
|
|
@ -507,7 +507,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 17:54:41
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:48:53
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.070000
|
||||
Exiting @ tick 71774859500 because target called exit()
|
||||
Exiting @ tick 71244143500 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -95,7 +95,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
|
||||
cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:01:26
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:54:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.210000
|
||||
Exiting @ tick 212344048000 because target called exit()
|
||||
Exiting @ tick 212344043000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,38 +1,38 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.212344 # Number of seconds simulated
|
||||
sim_ticks 212344048000 # Number of ticks simulated
|
||||
final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 212344043000 # Number of ticks simulated
|
||||
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1586428 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1233780581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229108 # Number of bytes of host memory used
|
||||
host_seconds 172.11 # Real time elapsed on the host
|
||||
sim_insts 273037671 # Number of instructions simulated
|
||||
sim_ops 349065408 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory
|
||||
host_inst_rate 2237295 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2860273 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1739965936 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232696 # Number of bytes of host memory used
|
||||
host_seconds 122.04 # Real time elapsed on the host
|
||||
sim_insts 273037663 # Number of instructions simulated
|
||||
sim_ops 349065399 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 424688097 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 424688087 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037671 # Number of instructions committed
|
||||
system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 273037663 # Number of instructions committed
|
||||
system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584926 # number of integer instructions
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584918 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 177024357 # number of memory refs
|
||||
system.cpu.num_load_insts 94648758 # Number of load instructions
|
||||
system.cpu.num_mem_refs 177024356 # number of memory refs
|
||||
system.cpu.num_load_insts 94648757 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 424688097 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 424688087 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
|
||||
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
|
||||
cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 4 2012 12:14:06
|
||||
gem5 started Jun 4 2012 18:04:29
|
||||
gem5 compiled Jun 28 2012 22:10:14
|
||||
gem5 started Jun 29 2012 00:56:30
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
|
||||
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
|
|
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
|
|||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
OO-style eon Time= 0.520000
|
||||
Exiting @ tick 525854475000 because target called exit()
|
||||
Exiting @ tick 525854423000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,32 +1,32 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.525854 # Number of seconds simulated
|
||||
sim_ticks 525854475000 # Number of ticks simulated
|
||||
final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 525854423000 # Number of ticks simulated
|
||||
final_tick 525854423000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 697015 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 891108 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1343878935 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238268 # Number of bytes of host memory used
|
||||
host_seconds 391.30 # Real time elapsed on the host
|
||||
sim_insts 272739291 # Number of instructions simulated
|
||||
sim_ops 348687131 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 167040 # Number of bytes read from this memory
|
||||
host_inst_rate 1009014 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1289987 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1945426950 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241152 # Number of bytes of host memory used
|
||||
host_seconds 270.30 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 437312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2610 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6833 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 317654 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 317533 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 513967 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 831622 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 317654 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 317654 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 317654 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 831500 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 317533 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 317533 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 317533 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 513967 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831622 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831500 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -70,73 +70,73 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1051708950 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1051708846 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739291 # Number of instructions committed
|
||||
system.cpu.committedOps 348687131 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 272739283 # Number of instructions committed
|
||||
system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584925 # number of integer instructions
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584917 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 177024357 # number of memory refs
|
||||
system.cpu.num_load_insts 94648758 # Number of load instructions
|
||||
system.cpu.num_mem_refs 177024356 # number of memory refs
|
||||
system.cpu.num_load_insts 94648757 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1051708846 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1765.984191 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1765.984158 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1765.984191 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.862297 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.862297 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644756 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644756 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644756 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 348644756 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 348644756 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 348644756 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 348644747 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 328062000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 328062000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 328062000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 328062000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 328062000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 328062000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660359 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660359 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660359 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 348660359 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 348660359 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 348660359 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 328020000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 328020000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 328020000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 328020000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 328020000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 328020000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21025.572005 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21025.572005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21025.572005 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21022.880215 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -151,46 +151,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
|||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281253000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281253000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281253000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281253000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281253000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281253000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18025.572005 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18025.572005 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3078.396294 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3078.396238 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3078.396294 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.751562 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.751562 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570005 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570005 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176619810 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176619810 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176619810 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176619810 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
|
||||
|
|
@ -207,18 +207,18 @@ system.cpu.dcache.demand_miss_latency::cpu.data 240058000
|
|||
system.cpu.dcache.demand_miss_latency::total 240058000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 240058000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 240058000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94571611 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94571611 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 176624288 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 176624288 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 176624288 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 176624288 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
|
||||
|
|
@ -278,54 +278,54 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 48 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3487.701804 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 341.613277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2408.384377 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 737.704150 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.073498 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.106436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
|
||||
system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -339,17 +339,17 @@ system.cpu.l2cache.demand_accesses::total 20081 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.231100 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.340272 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340272 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
|
|
@ -369,39 +369,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231100 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340272 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340272 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
|
|
|
|||
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Reference in a new issue