469 lines
53 KiB
Text
469 lines
53 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.271948 # Number of seconds simulated
|
|
sim_ticks 271948359500 # Number of ticks simulated
|
|
final_tick 271948359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 167086 # Simulator instruction rate (inst/s)
|
|
host_op_rate 167086 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 75497413 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 219024 # Number of bytes of host memory used
|
|
host_seconds 3602.09 # Real time elapsed on the host
|
|
sim_insts 601856964 # Number of instructions simulated
|
|
sim_ops 601856964 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 1620224 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 1674048 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 57024 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 57024 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 25316 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 26157 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 891 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 197920 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 5957837 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 6155757 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 197920 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 197920 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 209687 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 209687 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 209687 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 197920 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 5957837 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 6365444 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 114517207 # DTB read hits
|
|
system.cpu.dtb.read_misses 2631 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 114519838 # DTB read accesses
|
|
system.cpu.dtb.write_hits 39661898 # DTB write hits
|
|
system.cpu.dtb.write_misses 2302 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 39664200 # DTB write accesses
|
|
system.cpu.dtb.data_hits 154179105 # DTB hits
|
|
system.cpu.dtb.data_misses 4933 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 154184038 # DTB accesses
|
|
system.cpu.itb.fetch_hits 25013413 # ITB hits
|
|
system.cpu.itb.fetch_misses 22 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 25013435 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 17 # Number of system calls
|
|
system.cpu.numCycles 543896720 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.lookups 86316674 # Number of BP lookups
|
|
system.cpu.branch_predictor.condPredicted 81371545 # Number of conditional branches predicted
|
|
system.cpu.branch_predictor.condIncorrect 36360802 # Number of conditional branches incorrect
|
|
system.cpu.branch_predictor.BTBLookups 52676212 # Number of BTB lookups
|
|
system.cpu.branch_predictor.BTBHits 34326876 # Number of BTB hits
|
|
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
|
|
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
|
|
system.cpu.branch_predictor.BTBHitPct 65.165802 # BTB Hit Percentage
|
|
system.cpu.branch_predictor.predictedTaken 36904283 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 49412391 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 541655345 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 1005510191 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 254971320 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 155049936 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 33767521 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 2588294 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 36355815 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 26192089 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 58.124753 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 412333421 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 538321020 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 407697 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 54736228 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 489160492 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 89.936283 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 114514042 # Number of Load instructions committed
|
|
system.cpu.comStores 39451321 # Number of Store instructions committed
|
|
system.cpu.comBranches 62547159 # Number of Branches instructions committed
|
|
system.cpu.comNops 36304520 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 349039879 # Number of Integer instructions committed
|
|
system.cpu.comFloats 24 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.903698 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.903698 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.106565 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.106565 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 205017879 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 338878841 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 62.305734 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 233023029 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 310873691 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 57.156750 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 202072445 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 341824275 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 62.847276 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 432365235 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 111531485 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 20.506004 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 196896047 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 347000673 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 63.799001 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 30 # number of replacements
|
|
system.cpu.icache.tagsinuse 728.555018 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 25012389 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 29254.256140 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 728.555018 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.355740 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.355740 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25012389 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25012389 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25012389 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25012389 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25012389 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25012389 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1022 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1022 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1022 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1022 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1022 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56014500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 56014500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 56014500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 56014500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 56014500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 56014500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25013411 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25013411 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25013411 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25013411 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25013411 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25013411 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 54808.708415 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 54808.708415 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45159500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 45159500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45159500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 45159500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45159500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 45159500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 451299 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.146809 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 152406141 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 334.668016 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 260481000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.146809 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999548 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999548 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114120507 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114120507 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 38285634 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 38285634 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 152406141 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 152406141 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 152406141 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 152406141 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 393535 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 393535 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1165687 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1165687 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1559222 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1559222 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1559222 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1559222 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5944936500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5944936500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18222826500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 18222826500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 24167763000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 24167763000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 24167763000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 24167763000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003437 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029547 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.029547 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.010127 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.010127 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.010127 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.010127 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 15499.885841 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 15499.885841 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 10505000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 2188634000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2561 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 211460 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4101.913315 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 436902 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192303 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 192303 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911524 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 911524 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1103827 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1103827 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1103827 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1103827 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2433186000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2433186000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3829787500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3829787500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6262973500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6262973500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6262973500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6262973500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 917 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22852.415153 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 538842 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 23.284159 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21652.224350 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 719.469676 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 480.721127 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.660773 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.021956 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.014670 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.697400 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 197093 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 197107 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 436902 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 436902 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 232986 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 232986 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 430079 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 430093 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 430079 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 430093 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4120 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4961 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21196 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21196 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 25316 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26157 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26157 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44029000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214315000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 258344000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1104963500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1104963500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 44029000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1319278500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1363307500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 44029000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1319278500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1363307500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 436902 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 436902 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020476 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024551 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083389 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083389 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055591 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.057330 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 766500 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9462.962963 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 891 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 891 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4120 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4961 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21196 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21196 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25316 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26157 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25316 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26157 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33775500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 164851000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198626500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 849849500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 849849500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33775500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014700500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1048476000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33775500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014700500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1048476000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020476 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024551 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083389 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083389 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057330 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|