X86: Update the stats on the ruby x86 regressions for the new CMOVcc implementation.
This commit is contained in:
Gabe Black
parent
c5fae51774
commit
33b063a2a7
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@ -81,7 +81,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=RubyMemory
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clock=1
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config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
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config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
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debug=false
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debug_file=ruby.debug
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file=
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@ -2,7 +2,7 @@
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 30545
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random_seed: 1234
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randomization: 0
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tech_nm: 45
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freq_mhz: 3000
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@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0
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version: 0
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buffer_size: 32
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dma_sequencer: DMASequencer_0
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number_of_TBEs: 128
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number_of_TBEs: 256
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recycle_latency: 10
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request_latency: 6
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transitions_per_cycle: 32
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Directory_Controller config: DirectoryController_0
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version: 0
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buffer_size: 32
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directory_latency: 6
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directory_name: DirectoryMemory_0
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dma_select_low_bit: 6
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dma_select_num_bits: 0
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memory_controller_name: MemoryControl_0
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memory_latency: 158
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number_of_TBEs: 128
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number_of_TBEs: 256
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recycle_latency: 10
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to_mem_ctrl_latency: 1
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_0
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version: 0
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@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0
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cache: l1u_0
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 128
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number_of_TBEs: 256
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recycle_latency: 10
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sequencer: Sequencer_0
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transitions_per_cycle: 32
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Cache config: l1u_0
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@ -103,80 +106,40 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Jul/06/2009 11:11:42
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Real time: Aug/09/2009 03:58:51
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.28
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Virtual_time_in_minutes: 0.00466667
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Virtual_time_in_hours: 7.77778e-05
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Virtual_time_in_days: 7.77778e-05
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Virtual_time_in_seconds: 0.34
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Virtual_time_in_minutes: 0.00566667
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Virtual_time_in_hours: 9.44444e-05
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Virtual_time_in_days: 3.93519e-06
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Ruby_current_time: 5491501
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Ruby_current_time: 5504001
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Ruby_start_time: 1
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Ruby_cycles: 5491500
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Ruby_cycles: 5504000
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mbytes_resident: 144.855
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mbytes_total: 1330.54
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resident_ratio: 0.108873
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mbytes_resident: 144.359
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mbytes_total: 1352.23
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resident_ratio: 0.106763
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Total_misses: 0
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total_misses: 0 [ 0 ]
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user_misses: 0 [ 0 ]
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supervisor_misses: 0 [ 0 ]
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instruction_executed: 1 [ 1 ]
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ruby_cycles_executed: 5491501 [ 5491501 ]
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cycles_per_instruction: 5.4915e+06 [ 5.4915e+06 ]
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misses_per_thousand_instructions: 0 [ 0 ]
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ruby_cycles_executed: 5504001 [ 5504001 ]
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transactions_started: 0 [ 0 ]
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transactions_ended: 0 [ 0 ]
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instructions_per_transaction: 0 [ 0 ]
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cycles_per_transaction: 0 [ 0 ]
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misses_per_transaction: 0 [ 0 ]
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L1D_cache cache stats:
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L1D_cache_total_misses: 0
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L1D_cache_total_demand_misses: 0
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L1D_cache_total_prefetches: 0
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L1D_cache_total_sw_prefetches: 0
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L1D_cache_total_hw_prefetches: 0
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L1D_cache_misses_per_transaction: 0
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L1D_cache_misses_per_instruction: 0
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L1D_cache_instructions_per_misses: NaN
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L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L1I_cache cache stats:
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L1I_cache_total_misses: 0
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L1I_cache_total_demand_misses: 0
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L1I_cache_total_prefetches: 0
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L1I_cache_total_sw_prefetches: 0
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L1I_cache_total_hw_prefetches: 0
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L1I_cache_misses_per_transaction: 0
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L1I_cache_misses_per_instruction: 0
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L1I_cache_instructions_per_misses: NaN
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L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L2_cache cache stats:
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L2_cache_total_misses: 0
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L2_cache_total_demand_misses: 0
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L2_cache_total_prefetches: 0
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L2_cache_total_sw_prefetches: 0
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L2_cache_total_hw_prefetches: 0
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L2_cache_misses_per_transaction: 0
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L2_cache_misses_per_instruction: 0
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L2_cache_instructions_per_misses: NaN
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L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Busy Controller Counts:
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L1Cache-0:0
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@ -185,27 +148,16 @@ DMA-0:0
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Busy Bank Count:0
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L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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@ -228,11 +180,11 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 37781
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page_faults: 0
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page_reclaims: 38267
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page_faults: 1
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swaps: 0
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block_inputs: 0
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block_outputs: 40
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block_outputs: 0
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Network Stats
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-------------
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@ -266,7 +218,17 @@ links_utilized_percent_switch_3: 0
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links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
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--- DMA ---
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l1u_0 cache stats:
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l1u_0_total_misses: 0
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l1u_0_total_demand_misses: 0
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l1u_0_total_prefetches: 0
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l1u_0_total_sw_prefetches: 0
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l1u_0_total_hw_prefetches: 0
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l1u_0_misses_per_transaction: nan
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l1u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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--- DMA 0 ---
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- Event Counts -
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ReadRequest 0
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WriteRequest 0
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@ -281,7 +243,7 @@ BUSY_RD Data 0 <--
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BUSY_WR Ack 0 <--
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--- Directory ---
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--- Directory 0 ---
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- Event Counts -
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GETX 0
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GETS 0
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@ -344,7 +306,7 @@ ID_W DMA_READ 0 <--
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ID_W DMA_WRITE 0 <--
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ID_W Memory_Ack 0 <--
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--- L1Cache ---
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--- L1Cache 0 ---
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- Event Counts -
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Load 0
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Ifetch 0
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@ -1,23 +1,7 @@
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["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
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Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
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Solution: Re-compile with RUBY_DEBUG set to true.
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print config: 1
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Creating new MessageBuffer for 0 0
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Creating new MessageBuffer for 0 1
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Creating new MessageBuffer for 0 2
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Creating new MessageBuffer for 0 3
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Creating new MessageBuffer for 0 4
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Creating new MessageBuffer for 0 5
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Creating new MessageBuffer for 1 0
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Creating new MessageBuffer for 1 1
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Creating new MessageBuffer for 1 2
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Creating new MessageBuffer for 1 3
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Creating new MessageBuffer for 1 4
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Creating new MessageBuffer for 1 5
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Creating new MessageBuffer for 2 0
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Creating new MessageBuffer for 2 1
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Creating new MessageBuffer for 2 2
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Creating new MessageBuffer for 2 3
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Creating new MessageBuffer for 2 4
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Creating new MessageBuffer for 2 5
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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warn: instruction 'fnstcw_Mw' unimplemented
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@ -5,13 +5,12 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jul 6 2009 11:09:41
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M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
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M5 started Jul 6 2009 11:11:41
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M5 executing on maize
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby
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M5 compiled Aug 9 2009 03:58:47
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M5 revision 33faa9915d16 6486 default tip
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M5 started Aug 9 2009 03:58:49
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M5 executing on tater
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command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby
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Global frequency set at 1000000000000 ticks per second
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Debug: Adding to filter: 'q' (Queue)
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info: Entering event queue @ 0. Starting simulation...
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Hello world!
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Exiting @ tick 5491500 because target called exit()
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Exiting @ tick 5504000 because target called exit()
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@ -1,17 +1,17 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 70231 # Simulator instruction rate (inst/s)
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host_mem_usage 1362472 # Number of bytes of host memory used
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host_seconds 0.14 # Real time elapsed on the host
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host_tick_rate 40570791 # Simulator tick rate (ticks/s)
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host_inst_rate 7886 # Simulator instruction rate (inst/s)
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host_mem_usage 1384684 # Number of bytes of host memory used
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host_seconds 1.21 # Real time elapsed on the host
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host_tick_rate 4559114 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 9494 # Number of instructions simulated
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sim_seconds 0.000005 # Number of seconds simulated
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sim_ticks 5491500 # Number of ticks simulated
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sim_insts 9519 # Number of instructions simulated
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sim_seconds 0.000006 # Number of seconds simulated
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sim_ticks 5504000 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 10984 # number of cpu cycles simulated
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system.cpu.num_insts 9494 # Number of instructions executed
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system.cpu.numCycles 11009 # number of cpu cycles simulated
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system.cpu.num_insts 9519 # Number of instructions executed
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system.cpu.num_refs 1987 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
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@ -78,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=RubyMemory
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clock=1
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config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
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config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
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debug=false
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debug_file=ruby.debug
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file=
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@ -2,7 +2,7 @@
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 184716
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random_seed: 1234
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randomization: 0
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tech_nm: 45
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freq_mhz: 3000
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@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0
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version: 0
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buffer_size: 32
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dma_sequencer: DMASequencer_0
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number_of_TBEs: 128
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number_of_TBEs: 256
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recycle_latency: 10
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request_latency: 6
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transitions_per_cycle: 32
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Directory_Controller config: DirectoryController_0
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version: 0
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buffer_size: 32
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directory_latency: 6
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directory_name: DirectoryMemory_0
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dma_select_low_bit: 6
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dma_select_num_bits: 0
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memory_controller_name: MemoryControl_0
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memory_latency: 158
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number_of_TBEs: 128
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number_of_TBEs: 256
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recycle_latency: 10
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to_mem_ctrl_latency: 1
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_0
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version: 0
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@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0
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cache: l1u_0
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cache_response_latency: 12
|
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issue_latency: 2
|
||||
number_of_TBEs: 128
|
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number_of_TBEs: 256
|
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recycle_latency: 10
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sequencer: Sequencer_0
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transitions_per_cycle: 32
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Cache config: l1u_0
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@ -103,82 +106,42 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Jul/06/2009 11:11:44
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Real time: Aug/09/2009 04:00:22
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Profiler Stats
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--------------
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||||
Elapsed_time_in_seconds: 1
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||||
Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 4
|
||||
Elapsed_time_in_minutes: 0.0666667
|
||||
Elapsed_time_in_hours: 0.00111111
|
||||
Elapsed_time_in_days: 4.62963e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.87
|
||||
Virtual_time_in_minutes: 0.0145
|
||||
Virtual_time_in_hours: 0.000241667
|
||||
Virtual_time_in_days: 0.000241667
|
||||
Virtual_time_in_seconds: 1.19
|
||||
Virtual_time_in_minutes: 0.0198333
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Virtual_time_in_hours: 0.000330556
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Virtual_time_in_days: 1.37731e-05
|
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Ruby_current_time: 26617001
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Ruby_start_time: 1
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Ruby_cycles: 26617000
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||||
|
||||
mbytes_resident: 145.273
|
||||
mbytes_total: 1330.63
|
||||
resident_ratio: 0.109179
|
||||
mbytes_resident: 144.777
|
||||
mbytes_total: 1352.41
|
||||
resident_ratio: 0.107057
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 26617001 [ 26617001 ]
|
||||
cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Memory control:
|
||||
Memory control MemoryControl_0:
|
||||
memory_total_requests: 1082
|
||||
memory_reads: 557
|
||||
memory_writes: 525
|
||||
|
|
@ -205,30 +168,19 @@ DMA-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 1 count: 1082 average: 0.485213 | standard deviation: 0.500693 | 557 525 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 279 count: 8873 average: 12.5938 | standard deviation: 41.1326 | 0 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 279 count: 6886 average: 9.86669 | standard deviation: 35.7801 | 0 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 279 count: 1053 average: 24.4786 | standard deviation: 57.8541 | 0 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 259 count: 934 average: 19.3009 | standard deviation: 51.067 | 0 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency: [binsize: 2 max: 277 count: 8873 average: 11.531 | standard deviation: 40.8912 | 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 277 count: 6886 average: 8.82021 | standard deviation: 35.5704 | 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 277 count: 1053 average: 23.3457 | standard deviation: 57.517 | 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 257 count: 934 average: 18.197 | standard deviation: 50.763 | 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
|
@ -249,13 +201,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standa
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
user_time: 1
|
||||
system_time: 0
|
||||
page_reclaims: 37883
|
||||
page_reclaims: 38363
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 48
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -301,7 +253,22 @@ links_utilized_percent_switch_3: 0.000135502
|
|||
outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
--- DMA ---
|
||||
l1u_0 cache stats:
|
||||
l1u_0_total_misses: 557
|
||||
l1u_0_total_demand_misses: 557
|
||||
l1u_0_total_prefetches: 0
|
||||
l1u_0_total_sw_prefetches: 0
|
||||
l1u_0_total_hw_prefetches: 0
|
||||
l1u_0_misses_per_transaction: inf
|
||||
|
||||
l1u_0_request_type_LD: 25.1346%
|
||||
l1u_0_request_type_ST: 17.4147%
|
||||
l1u_0_request_type_IFETCH: 57.4506%
|
||||
|
||||
l1u_0_access_mode_type_SupervisorMode: 557 100%
|
||||
l1u_0_request_size: [binsize: log2 max: 8 count: 557 average: 7.5368 | standard deviation: 1.45496 | 0 12 1 42 502 ]
|
||||
|
||||
--- DMA 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
|
|
@ -316,7 +283,7 @@ BUSY_RD Data 0 <--
|
|||
|
||||
BUSY_WR Ack 0 <--
|
||||
|
||||
--- Directory ---
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 557
|
||||
GETS 0
|
||||
|
|
@ -379,7 +346,7 @@ ID_W DMA_READ 0 <--
|
|||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 1053
|
||||
Ifetch 6886
|
||||
|
|
|
|||
|
|
@ -1,23 +1,7 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
|
||||
Solution: Re-compile with RUBY_DEBUG set to true.
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
|
|
|
|||
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:09:41
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:43
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
M5 compiled Aug 9 2009 04:00:16
|
||||
M5 revision 33faa9915d16+ 6486+ default tip
|
||||
M5 started Aug 9 2009 04:00:18
|
||||
M5 executing on tater
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 26617000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,17 +1,17 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 12919 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1362572 # Number of bytes of host memory used
|
||||
host_seconds 0.74 # Real time elapsed on the host
|
||||
host_tick_rate 36211191 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2962 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1384872 # Number of bytes of host memory used
|
||||
host_seconds 3.21 # Real time elapsed on the host
|
||||
host_tick_rate 8282962 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9494 # Number of instructions simulated
|
||||
sim_insts 9519 # Number of instructions simulated
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 26617000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 53234 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 9494 # Number of instructions executed
|
||||
system.cpu.num_insts 9519 # Number of instructions executed
|
||||
system.cpu.num_refs 1987 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue