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Update stats for new prefetching fixes.

Browse source 
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
This commit is contained in:
Steve Reinhardt 2009-02-16 12:09:45 -05:00
parent 89a7fb0393
commit 89ea323250
261 changed files with 2357 additions and 2445 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
View file

@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

2
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -5,14 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:25:12
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes

35
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4206850 # Nu
global.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted
global.BPredUnit.lookups 76039018 # Number of BP lookups
global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
host_inst_rate 193677 # Simulator instruction rate (inst/s)
host_mem_usage 202220 # Number of bytes of host memory used
host_seconds 2920.07 # Real time elapsed on the host
host_tick_rate 57217081 # Simulator tick rate (ticks/s)
host_inst_rate 244512 # Simulator instruction rate (inst/s)
host_mem_usage 204148 # Number of bytes of host memory used
host_seconds 2312.99 # Real time elapsed on the host
host_tick_rate 72234766 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit.
@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.003628 # ms
system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 468828 # number of replacements
system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000014 # ms
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 34 # number of replacements
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # m
system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 85262 # number of replacements
system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

2
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,14 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:21:47
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-atomic
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py long/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes

8
tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3417919 # Simulator instruction rate (inst/s)
host_mem_usage 193752 # Number of bytes of host memory used
host_seconds 176.09 # Real time elapsed on the host
host_tick_rate 1708971531 # Simulator tick rate (ticks/s)
host_inst_rate 6175770 # Simulator instruction rate (inst/s)
host_mem_usage 195684 # Number of bytes of host memory used
host_seconds 97.45 # Real time elapsed on the host
host_tick_rate 3087904278 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.300931 # Number of seconds simulated

12
tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

2
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
View file

@ -5,14 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:21:45
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/alpha/tru64/simple-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
spec_init
Loading Input Data
Duplicating 262144 bytes

35
tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1797646 # Simulator instruction rate (inst/s)
host_mem_usage 201208 # Number of bytes of host memory used
host_seconds 334.80 # Real time elapsed on the host
host_tick_rate 2323765799 # Simulator tick rate (ticks/s)
host_inst_rate 1969135 # Simulator instruction rate (inst/s)
host_mem_usage 203124 # Number of bytes of host memory used
host_seconds 305.65 # Real time elapsed on the host
host_tick_rate 2545444210 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
sim_seconds 0.778004 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.003443 # ms
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000001 # ms
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # m
system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 84513 # number of replacements
system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

12
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

3
tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
View file

@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

9
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:55:58
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:45:29
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/o3-timing
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

35
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 83681535 # Nu
global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
global.BPredUnit.lookups 254458067 # Number of BP lookups
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
host_inst_rate 116972 # Simulator instruction rate (inst/s)
host_mem_usage 204276 # Number of bytes of host memory used
host_seconds 12016.73 # Real time elapsed on the host
host_tick_rate 91760367 # Simulator tick rate (ticks/s)
host_inst_rate 104414 # Simulator instruction rate (inst/s)
host_mem_usage 206176 # Number of bytes of host memory used
host_seconds 13461.92 # Real time elapsed on the host
host_tick_rate 81909485 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
@ -119,15 +119,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.001012 # ms
system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 523278 # number of replacements
system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -213,15 +204,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000004 # ms
system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 222 # number of replacements
system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -398,15 +380,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # m
system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 84497 # number of replacements
system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

3
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
View file

@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

9
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:45:38
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:46:25
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-atomic
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2833353 # Simulator instruction rate (inst/s)
host_mem_usage 195884 # Number of bytes of host memory used
host_seconds 525.71 # Real time elapsed on the host
host_tick_rate 1416680719 # Simulator tick rate (ticks/s)
host_inst_rate 3714547 # Simulator instruction rate (inst/s)
host_mem_usage 197792 # Number of bytes of host memory used
host_seconds 401.00 # Real time elapsed on the host
host_tick_rate 1857278454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 0.744764 # Number of seconds simulated

12
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

3
tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
View file

@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

9
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:41:13
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:50:17
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/00.gzip/sparc/linux/simple-timing
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

35
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2121797 # Simulator instruction rate (inst/s)
host_mem_usage 203340 # Number of bytes of host memory used
host_seconds 702.01 # Real time elapsed on the host
host_tick_rate 2963511011 # Simulator tick rate (ticks/s)
host_inst_rate 1502574 # Simulator instruction rate (inst/s)
host_mem_usage 205236 # Number of bytes of host memory used
host_seconds 991.31 # Real time elapsed on the host
host_tick_rate 2098643273 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
sim_seconds 2.080416 # Number of seconds simulated
@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000901 # ms
system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000001 # ms
system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # m
system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 82905 # number of replacements
system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -49,7 +52,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
egid=100
env=
errout=cerr

10
tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
View file

@ -1,9 +1,15 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
warn: Increasing stack size by one page.
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here

12
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 26 2008 18:29:56
M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
M5 commit date Fri Dec 26 18:25:21 2008 -0800
M5 started Dec 26 2008 19:19:42
M5 executing on fajita
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:00:03
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -21,6 +20,7 @@ Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3

8
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 717061 # Simulator instruction rate (inst/s)
host_mem_usage 197184 # Number of bytes of host memory used
host_seconds 2258.34 # Real time elapsed on the host
host_tick_rate 426391006 # Simulator tick rate (ticks/s)
host_inst_rate 1622364 # Simulator instruction rate (inst/s)
host_mem_usage 197488 # Number of bytes of host memory used
host_seconds 998.15 # Real time elapsed on the host
host_tick_rate 964717823 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 0.962935 # Number of seconds simulated

14
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -155,7 +155,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr

10
tests/long/00.gzip/ref/x86/linux/simple-timing/simerr
View file

@ -1,9 +1,15 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'prefetch_t0' unimplemented
warn: Increasing stack size by one page.
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here

12
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 26 2008 18:29:56
M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
M5 commit date Fri Dec 26 18:25:21 2008 -0800
M5 started Dec 26 2008 19:22:06
M5 executing on fajita
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:02:02
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -21,6 +20,7 @@ Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3

35
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 511923 # Simulator instruction rate (inst/s)
host_mem_usage 204640 # Number of bytes of host memory used
host_seconds 3163.30 # Real time elapsed on the host
host_tick_rate 807415286 # Simulator tick rate (ticks/s)
host_inst_rate 1065301 # Simulator instruction rate (inst/s)
host_mem_usage 204932 # Number of bytes of host memory used
host_seconds 1520.10 # Real time elapsed on the host
host_tick_rate 1680214432 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619365942 # Number of instructions simulated
sim_seconds 2.554098 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000834 # ms
system.cpu.dcache.overall_mshr_misses 506099 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 439707 # number of replacements
system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000000 # ms
system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.635970 # m
system.cpu.l2cache.overall_mshr_misses 282704 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 82097 # number of replacements
system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

34
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -46,6 +46,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -135,12 +136,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -309,12 +309,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -354,6 +353,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -443,12 +443,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -617,12 +616,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -660,6 +658,7 @@ image=system.disk0.image
type=CowDiskImage
children=child
child=system.disk0.image.child
image_file=
read_only=false
table_size=65536
@ -679,6 +678,7 @@ image=system.disk2.image
type=CowDiskImage
children=child
child=system.disk2.image.child
image_file=
read_only=false
table_size=65536
@ -713,12 +713,11 @@ latency=50000
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -746,12 +745,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -881,16 +879,22 @@ pio=system.iobus.port[1]
[system.tsunami.ethernet]
type=NSGigE
BAR0=1
BAR0LegacyIO=false
BAR0Size=256
BAR1=0
BAR1LegacyIO=false
BAR1Size=4096
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
@ -1259,16 +1263,22 @@ pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0

6
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
View file

@ -1,5 +1,7 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: 125740500: Trying to launch CPU number 1!
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/8f7d2563
hack: be nice to actually delete the event here

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 14 2008 21:47:07
M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
M5 commit date Sun Dec 14 21:45:15 2008 -0800
M5 started Dec 14 2008 21:47:53
M5 executing on tater
M5 compiled Feb 16 2009 00:15:24
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:44:44
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1907705384500 because m5_exit instruction encountered

62
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -16,10 +16,10 @@ global.BPredUnit.lookups 10093436 # Nu
global.BPredUnit.lookups 5538388 # Number of BP lookups
global.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target.
global.BPredUnit.usedRAS 417429 # Number of times the RAS was used to get a target.
host_inst_rate 132487 # Simulator instruction rate (inst/s)
host_mem_usage 294244 # Number of bytes of host memory used
host_seconds 424.12 # Real time elapsed on the host
host_tick_rate 4498020766 # Simulator tick rate (ticks/s)
host_inst_rate 133092 # Simulator instruction rate (inst/s)
host_mem_usage 294856 # Number of bytes of host memory used
host_seconds 422.19 # Real time elapsed on the host
host_tick_rate 4518571306 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 2050532 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 906322 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 1832540 # Number of conflicting stores.
@ -146,15 +146,6 @@ system.cpu0.dcache.overall_mshr_miss_rate 0.091715 # m
system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.replacements 922726 # number of replacements
system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -256,15 +247,6 @@ system.cpu0.icache.overall_mshr_miss_rate 0.096077 # m
system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.icache.replacements 619753 # number of replacements
system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -600,15 +582,6 @@ system.cpu1.dcache.overall_mshr_miss_rate 0.098495 # m
system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 824622000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.replacements 531784 # number of replacements
system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -710,15 +683,6 @@ system.cpu1.icache.overall_mshr_miss_rate 0.144757 # m
system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.icache.replacements 446606 # number of replacements
system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -985,15 +949,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms
system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41697 # number of replacements
system.iocache.sampled_refs 41713 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -1072,15 +1027,6 @@ system.l2c.overall_mshr_miss_rate 0.248969 # ms
system.l2c.overall_mshr_misses 627840 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 2264236498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 402142 # number of replacements
system.l2c.sampled_refs 433669 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

27
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -46,6 +46,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -135,12 +136,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -309,12 +309,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=4
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -352,6 +351,7 @@ image=system.disk0.image
type=CowDiskImage
children=child
child=system.disk0.image.child
image_file=
read_only=false
table_size=65536
@ -371,6 +371,7 @@ image=system.disk2.image
type=CowDiskImage
children=child
child=system.disk2.image.child
image_file=
read_only=false
table_size=65536
@ -405,12 +406,11 @@ latency=50000
max_miss_count=0
mem_side_filter_ranges=0:18446744073709551615
mshrs=20
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -438,12 +438,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=92
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -573,16 +572,22 @@ pio=system.iobus.port[1]
[system.tsunami.ethernet]
type=NSGigE
BAR0=1
BAR0LegacyIO=false
BAR0Size=256
BAR1=0
BAR1LegacyIO=false
BAR1Size=4096
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
@ -951,16 +956,22 @@ pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0

5
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
View file

@ -1,4 +1,5 @@
warn: kernel located at: /dist/m5/system/binaries/vmlinux
warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 14 2008 21:47:07
M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
M5 commit date Sun Dec 14 21:45:15 2008 -0800
M5 started Dec 14 2008 21:47:52
M5 executing on tater
M5 compiled Feb 16 2009 00:15:24
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:42:11
M5 executing on zizzer
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1867363148500 because m5_exit instruction encountered

44
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 828629 # Nu
global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted
global.BPredUnit.lookups 14570242 # Number of BP lookups
global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target.
host_inst_rate 133323 # Simulator instruction rate (inst/s)
host_mem_usage 292856 # Number of bytes of host memory used
host_seconds 398.21 # Real time elapsed on the host
host_tick_rate 4689394624 # Simulator tick rate (ticks/s)
host_inst_rate 209657 # Simulator instruction rate (inst/s)
host_mem_usage 292968 # Number of bytes of host memory used
host_seconds 253.23 # Real time elapsed on the host
host_tick_rate 7374290880 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit.
@ -134,15 +134,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.095592 # ms
system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 1401991 # number of replacements
system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -244,15 +235,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.110520 # ms
system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 994847 # number of replacements
system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -536,15 +518,6 @@ system.iocache.overall_mshr_miss_rate 1 # ms
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -623,15 +596,6 @@ system.l2c.overall_mshr_miss_rate 0.255051 # ms
system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 396031 # number of replacements
system.l2c.sampled_refs 427707 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

3
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
View file

@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

9
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:56:43
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:51:47
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-atomic
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2390204 # Simulator instruction rate (inst/s)
host_mem_usage 328072 # Number of bytes of host memory used
host_seconds 102.01 # Real time elapsed on the host
host_tick_rate 1198022319 # Simulator tick rate (ticks/s)
host_inst_rate 2414989 # Simulator instruction rate (inst/s)
host_mem_usage 329980 # Number of bytes of host memory used
host_seconds 100.97 # Real time elapsed on the host
host_tick_rate 1210444801 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.122216 # Number of seconds simulated

12
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

3
tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
View file

@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

9
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:52:55
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:53:06
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/sparc/linux/simple-timing
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

35
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1337728 # Simulator instruction rate (inst/s)
host_mem_usage 335528 # Number of bytes of host memory used
host_seconds 182.28 # Real time elapsed on the host
host_tick_rate 2010386962 # Simulator tick rate (ticks/s)
host_inst_rate 1327795 # Simulator instruction rate (inst/s)
host_mem_usage 337424 # Number of bytes of host memory used
host_seconds 183.64 # Real time elapsed on the host
host_tick_rate 1995461602 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
sim_seconds 0.366446 # Number of seconds simulated
@ -74,15 +74,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.009397 # ms
system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -136,15 +127,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000004 # ms
system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -219,15 +201,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # m
system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 891 # number of replacements
system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

5
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -49,7 +52,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr

5
tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
View file

@ -1,4 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here

11
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 26 2008 18:29:56
M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
M5 commit date Fri Dec 26 18:25:21 2008 -0800
M5 started Dec 26 2008 19:05:48
M5 executing on fajita
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:06:25
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 687504 # Simulator instruction rate (inst/s)
host_mem_usage 331712 # Number of bytes of host memory used
host_seconds 392.27 # Real time elapsed on the host
host_tick_rate 422480782 # Simulator tick rate (ticks/s)
host_inst_rate 1454099 # Simulator instruction rate (inst/s)
host_mem_usage 332016 # Number of bytes of host memory used
host_seconds 185.47 # Real time elapsed on the host
host_tick_rate 893563512 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.165726 # Number of seconds simulated

14
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -155,7 +155,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr

5
tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
View file

@ -1,4 +1,7 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fnstcw_Mw' unimplemented
For more information see: http://www.m5sim.org/warn/437d5238
warn: instruction 'fldcw_Mw' unimplemented
warn: be nice to actually delete the event here
For more information see: http://www.m5sim.org/warn/437d5238
hack: be nice to actually delete the event here

11
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,12 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 26 2008 18:29:56
M5 revision 5818:e9a95a3440197489c28a655f2de72dc8e98259b9
M5 commit date Fri Dec 26 18:25:21 2008 -0800
M5 started Dec 26 2008 20:14:49
M5 executing on fajita
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:06:48
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

35
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 422356 # Simulator instruction rate (inst/s)
host_mem_usage 339176 # Number of bytes of host memory used
host_seconds 638.53 # Real time elapsed on the host
host_tick_rate 775808629 # Simulator tick rate (ticks/s)
host_inst_rate 939339 # Simulator instruction rate (inst/s)
host_mem_usage 339456 # Number of bytes of host memory used
host_seconds 287.10 # Real time elapsed on the host
host_tick_rate 1725433923 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 269686773 # Number of instructions simulated
sim_seconds 0.495377 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.017832 # ms
system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 2049944 # number of replacements
system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000002 # ms
system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.093846 # m
system.cpu.l2cache.overall_mshr_misses 192840 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 108885 # number of replacements
system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

8
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 1 2009 00:35:14
M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase
M5 started Feb 1 2009 01:31:23
M5 executing on fajita
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:09:31
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

8
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 942344 # Simulator instruction rate (inst/s)
host_mem_usage 199592 # Number of bytes of host memory used
host_seconds 1586.98 # Real time elapsed on the host
host_tick_rate 547379933 # Simulator tick rate (ticks/s)
host_inst_rate 1649324 # Simulator instruction rate (inst/s)
host_mem_usage 201208 # Number of bytes of host memory used
host_seconds 906.72 # Real time elapsed on the host
host_tick_rate 958044415 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 0.868682 # Number of seconds simulated

9
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -46,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -83,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -120,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

8
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 1 2009 00:35:14
M5 revision ddc342563140 5849 default qtip upconfaultstats.patch tip qbase
M5 started Feb 1 2009 01:51:40
M5 executing on fajita
M5 compiled Feb 16 2009 00:19:15
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 01:11:36
M5 executing on zizzer
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

35
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 856633 # Simulator instruction rate (inst/s)
host_mem_usage 207060 # Number of bytes of host memory used
host_seconds 1745.77 # Real time elapsed on the host
host_tick_rate 1369809690 # Simulator tick rate (ticks/s)
host_inst_rate 1421036 # Simulator instruction rate (inst/s)
host_mem_usage 208620 # Number of bytes of host memory used
host_seconds 1052.39 # Real time elapsed on the host
host_tick_rate 2272325062 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495482356 # Number of instructions simulated
sim_seconds 2.391370 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.005988 # ms
system.cpu.dcache.overall_mshr_misses 3192961 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 2513875 # number of replacements
system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -126,15 +117,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000002 # ms
system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -209,15 +191,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.480279 # m
system.cpu.l2cache.overall_mshr_misses 1210680 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 663512 # number of replacements
system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

12
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini
View file

@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

3
tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,11 +1,10 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
warn: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065

11
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:21:46
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333

35
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5781170 # Nu
global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
global.BPredUnit.lookups 62209737 # Number of BP lookups
global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
host_inst_rate 151728 # Simulator instruction rate (inst/s)
host_mem_usage 209656 # Number of bytes of host memory used
host_seconds 2475.31 # Real time elapsed on the host
host_tick_rate 54537175 # Simulator tick rate (ticks/s)
host_inst_rate 183215 # Simulator instruction rate (inst/s)
host_mem_usage 211568 # Number of bytes of host memory used
host_seconds 2049.91 # Real time elapsed on the host
host_tick_rate 65854919 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.
@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms
system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 782 # number of replacements
system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000061 # ms
system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1975 # number of replacements
system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # m
system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 14 # number of replacements
system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

3
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,11 +1,10 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
warn: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065

11
tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:26:02
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-atomic
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py long/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.183333

8
tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3407773 # Simulator instruction rate (inst/s)
host_mem_usage 201328 # Number of bytes of host memory used
host_seconds 116.99 # Real time elapsed on the host
host_tick_rate 1703884563 # Simulator tick rate (ticks/s)
host_inst_rate 3515833 # Simulator instruction rate (inst/s)
host_mem_usage 203260 # Number of bytes of host memory used
host_seconds 113.39 # Real time elapsed on the host
host_tick_rate 1757913715 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664595 # Number of instructions simulated
sim_seconds 0.199332 # Number of seconds simulated

12
tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

3
tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,11 +1,10 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
warn: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065

11
tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
View file

@ -5,13 +5,14 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:22:18
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:52
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/30.eon/alpha/tru64/simple-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667

35
tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1526276 # Simulator instruction rate (inst/s)
host_mem_usage 208780 # Number of bytes of host memory used
host_seconds 261.20 # Real time elapsed on the host
host_tick_rate 2172088412 # Simulator tick rate (ticks/s)
host_inst_rate 1674592 # Simulator instruction rate (inst/s)
host_mem_usage 210700 # Number of bytes of host memory used
host_seconds 238.07 # Real time elapsed on the host
host_tick_rate 2383160323 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
sim_seconds 0.567352 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.000025 # ms
system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000009 # ms
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # m
system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 15 # number of replacements
system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

12
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
View file

@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

4
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/5c5b547f

11
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -5,14 +5,15 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:21:45
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

35
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 29107758 # Nu
global.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted
global.BPredUnit.lookups 349424731 # Number of BP lookups
global.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target.
host_inst_rate 157306 # Simulator instruction rate (inst/s)
host_mem_usage 209560 # Number of bytes of host memory used
host_seconds 11589.17 # Real time elapsed on the host
host_tick_rate 60846406 # Simulator tick rate (ticks/s)
host_inst_rate 217689 # Simulator instruction rate (inst/s)
host_mem_usage 211464 # Number of bytes of host memory used
host_seconds 8374.52 # Real time elapsed on the host
host_tick_rate 84202937 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 118847053 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 21034746 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit.
@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.002268 # ms
system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 1526847 # number of replacements
system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000028 # ms
system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 8097 # number of replacements
system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # m
system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 1474251 # number of replacements
system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

4
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/5c5b547f

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,14 +5,15 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:26:39
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:27:51
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py long/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

8
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3237524 # Simulator instruction rate (inst/s)
host_mem_usage 200500 # Number of bytes of host memory used
host_seconds 620.53 # Real time elapsed on the host
host_tick_rate 1619110797 # Simulator tick rate (ticks/s)
host_inst_rate 3467416 # Simulator instruction rate (inst/s)
host_mem_usage 202428 # Number of bytes of host memory used
host_seconds 579.39 # Real time elapsed on the host
host_tick_rate 1734081372 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 1.004711 # Number of seconds simulated

12
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

4
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,4 +1,4 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(1, 0, ...)
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/5c5b547f

11
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
View file

@ -5,14 +5,15 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:21:44
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:29:29
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
1375000: 2038431008
1374000: 3487365506
1373000: 4184770123

35
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1407375 # Simulator instruction rate (inst/s)
host_mem_usage 207960 # Number of bytes of host memory used
host_seconds 1427.47 # Real time elapsed on the host
host_tick_rate 1971983298 # Simulator tick rate (ticks/s)
host_inst_rate 2199489 # Simulator instruction rate (inst/s)
host_mem_usage 209876 # Number of bytes of host memory used
host_seconds 913.39 # Real time elapsed on the host
host_tick_rate 3081877276 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
sim_seconds 2.814951 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.002124 # ms
system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000005 # ms
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # m
system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 1473608 # number of replacements
system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

12
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini
View file

@ -22,6 +22,7 @@ SSITSize=1024
activity=0
backComSize=5
cachePorts=200
checker=Null
choiceCtrBits=2
choicePredictorSize=8192
clock=500
@ -36,6 +37,8 @@ decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
@ -107,12 +110,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -281,12 +283,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -318,12 +319,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

2
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:27:20
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:29:46
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/o3-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

35
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 452707 # Nu
global.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted
global.BPredUnit.lookups 16249463 # Number of BP lookups
global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
host_inst_rate 155507 # Simulator instruction rate (inst/s)
host_mem_usage 212996 # Number of bytes of host memory used
host_seconds 511.82 # Real time elapsed on the host
host_tick_rate 53016132 # Simulator tick rate (ticks/s)
host_inst_rate 207814 # Simulator instruction rate (inst/s)
host_mem_usage 214944 # Number of bytes of host memory used
host_seconds 382.99 # Real time elapsed on the host
host_tick_rate 70849023 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit.
@ -111,15 +111,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.006031 # ms
system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200933 # number of replacements
system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -220,15 +211,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.006420 # ms
system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 83888 # number of replacements
system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -409,15 +391,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # m
system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 148779 # number of replacements
system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

2
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:24:43
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:31:50
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-atomic
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py long/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

8
tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 3156054 # Simulator instruction rate (inst/s)
host_mem_usage 203904 # Number of bytes of host memory used
host_seconds 27.99 # Real time elapsed on the host
host_tick_rate 1579824710 # Simulator tick rate (ticks/s)
host_inst_rate 5386925 # Simulator instruction rate (inst/s)
host_mem_usage 205832 # Number of bytes of host memory used
host_seconds 16.40 # Real time elapsed on the host
host_tick_rate 2696520513 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.044221 # Number of seconds simulated

12
tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
@ -43,12 +46,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -80,12 +82,11 @@ latency=1000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
@ -117,12 +118,11 @@ latency=10000
max_miss_count=0
mem_side_filter_ranges=
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_miss=false
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false

2
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
View file

@ -1,2 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
warn: Increasing stack size by one page.
For more information see: http://www.m5sim.org/warn/d946bea6

10
tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 4 2008 21:21:43
M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
M5 commit date Thu Dec 04 18:04:32 2008 -0500
M5 started Dec 4 2008 21:28:00
M5 compiled Feb 16 2009 00:22:05
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:32:07
M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/alpha/tru64/simple-timing
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

35
tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1655989 # Simulator instruction rate (inst/s)
host_mem_usage 211348 # Number of bytes of host memory used
host_seconds 53.35 # Real time elapsed on the host
host_tick_rate 2533794438 # Simulator tick rate (ticks/s)
host_inst_rate 2514121 # Simulator instruction rate (inst/s)
host_mem_usage 213276 # Number of bytes of host memory used
host_seconds 35.14 # Real time elapsed on the host
host_tick_rate 3846798027 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
sim_seconds 0.135169 # Number of seconds simulated
@ -64,15 +64,6 @@ system.cpu.dcache.overall_mshr_miss_rate 0.006035 # ms
system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -138,15 +129,6 @@ system.cpu.icache.overall_mshr_miss_rate 0.000864 # ms
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 74391 # number of replacements
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -225,15 +207,6 @@ system.cpu.l2cache.overall_mshr_miss_rate 0.665557 # m
system.cpu.l2cache.overall_mshr_misses 186875 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 147561 # number of replacements
system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -12,9 +12,12 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0

565
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
View file

File diff suppressed because it is too large Load diff

10
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 5 2008 22:40:47
M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
M5 commit date Wed Nov 05 16:19:17 2008 -0500
M5 started Nov 5 2008 22:55:47
M5 compiled Feb 16 2009 00:17:12
M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase
M5 started Feb 16 2009 00:53:28
M5 executing on zizzer
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py long/50.vortex/sparc/linux/simple-atomic
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 68148678500 because target called exit()

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