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tests: new ref outputs for new cache model

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--HG--
extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
This commit is contained in:
Steve Reinhardt 2007-08-03 18:04:30 -04:00
parent 851e3c852b
commit bb3f7dc83b
57 changed files with 2963 additions and 3486 deletions
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45
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -86,6 +86,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -95,12 +96,9 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -118,12 +116,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -139,11 +135,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -217,11 +213,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -229,11 +225,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -259,11 +255,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -271,12 +267,9 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -294,12 +287,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -310,12 +301,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -333,12 +321,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -356,6 +342,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

517
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 522 # Number of BTB hits
global.BPredUnit.BTBLookups 1584 # Number of BTB lookups
global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1088 # Number of conditional branches predicted
global.BPredUnit.lookups 1837 # Number of BP lookups
global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target.
host_inst_rate 39303 # Simulator instruction rate (inst/s)
host_mem_usage 153768 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_tick_rate 32016268 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 127 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1874 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1142 # Number of stores inserted to the mem dependence unit.
global.BPredUnit.BTBHits 543 # Number of BTB hits
global.BPredUnit.BTBLookups 1720 # Number of BTB lookups
global.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 1175 # Number of conditional branches predicted
global.BPredUnit.lookups 2025 # Number of BP lookups
global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target.
host_inst_rate 29843 # Simulator instruction rate (inst/s)
host_mem_usage 154572 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_tick_rate 22095832 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 133 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1967 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 1200 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5623 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4589500 # Number of ticks simulated
sim_seconds 0.000004 # Number of seconds simulated
sim_ticks 4170500 # Number of ticks simulated
system.cpu.commit.COM:branches 862 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 8521
system.cpu.commit.COM:committed_per_cycle.samples 7614
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 6200 7276.14%
1 1160 1361.34%
2 469 550.40%
3 177 207.72%
4 131 153.74%
5 98 115.01%
6 109 127.92%
7 73 85.67%
8 104 122.05%
0 5315 6980.56%
1 1182 1552.40%
2 399 524.03%
3 192 252.17%
4 125 164.17%
5 99 130.02%
6 130 170.74%
7 67 88.00%
8 105 137.90%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 979 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1791 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 349 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3571 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 3957 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5623 # Number of Instructions Simulated
system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
system.cpu.cpi 1.636315 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.636315 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1470 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5932.330827 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5380 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1337 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 789000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.090476 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 538000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.068027 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 4504.373178 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1545000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.cpi 1.483372 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.483372 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 8188.118812 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5495.049505 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1386 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 827000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.067922 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 555000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.067922 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 561 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 18316.091954 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5068.965517 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 474 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1593500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.155080 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 251 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 441000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.155080 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 10.439306 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 10.770115 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2282 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 4903.361345 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1806 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2334000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.208589 # miss rate for demand accesses
system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 911500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.075811 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 12875 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1860 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2420500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.091797 # miss rate for demand accesses
system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 996000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.091797 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 2282 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 4903.361345 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5268.786127 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 12875 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5297.872340 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1806 # number of overall hits
system.cpu.dcache.overall_miss_latency 2334000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.208589 # miss rate for overall accesses
system.cpu.dcache.overall_misses 476 # number of overall misses
system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 911500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.075811 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
system.cpu.dcache.overall_hits 1860 # number of overall hits
system.cpu.dcache.overall_miss_latency 2420500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.091797 # miss rate for overall accesses
system.cpu.dcache.overall_misses 188 # number of overall misses
system.cpu.dcache.overall_mshr_hits 285 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 996000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.091797 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -119,91 +119,91 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 112.669258 # Cycle average of tags in use
system.cpu.dcache.total_refs 1806 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 112.600183 # Cycle average of tags in use
system.cpu.dcache.total_refs 1874 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 143 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 10466 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1855 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 679 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:BlockedCycles 391 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 82 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 164 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 11387 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 5174 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 2002 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 726 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1837 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1469 # Number of cache lines fetched
system.cpu.fetch.Cycles 3456 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 11417 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.199652 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1469 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 763 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.240843 # Number of inst fetches per cycle
system.cpu.fetch.Branches 2025 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1529 # Number of cache lines fetched
system.cpu.fetch.Cycles 3690 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 212 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12463 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 457 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.242777 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1529 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 820 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.494185 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 9201
system.cpu.fetch.rateDist.samples 8341
system.cpu.fetch.rateDist.min_value 0
0 7216 7842.63%
1 168 182.59%
2 148 160.85%
3 136 147.81%
4 214 232.58%
5 138 149.98%
6 177 192.37%
7 95 103.25%
8 909 987.94%
0 6181 7410.38%
1 173 207.41%
2 174 208.61%
3 151 181.03%
4 219 262.56%
5 157 188.23%
6 179 214.60%
7 102 122.29%
8 1005 1204.89%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 1469 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5381.818182 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4530.448718 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1139 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1776000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.224643 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses
system.cpu.icache.ReadReq_accesses 1511 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5621.019108 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4464.968153 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1197 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1765000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.207809 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 314 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 1413500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.212389 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency 1402000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.207809 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.650641 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 3.812102 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1469 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5381.818182 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency
system.cpu.icache.demand_hits 1139 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1776000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.224643 # miss rate for demand accesses
system.cpu.icache.demand_misses 330 # number of demand (read+write) misses
system.cpu.icache.demand_accesses 1511 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5621.019108 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
system.cpu.icache.demand_hits 1197 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1765000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.207809 # miss rate for demand accesses
system.cpu.icache.demand_misses 314 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 1413500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.212389 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_miss_latency 1402000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.207809 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 1469 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5381.818182 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4530.448718 # average overall mshr miss latency
system.cpu.icache.overall_accesses 1511 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5621.019108 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4464.968153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1139 # number of overall hits
system.cpu.icache.overall_miss_latency 1776000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.224643 # miss rate for overall accesses
system.cpu.icache.overall_misses 330 # number of overall misses
system.cpu.icache.overall_hits 1197 # number of overall hits
system.cpu.icache.overall_miss_latency 1765000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.207809 # miss rate for overall accesses
system.cpu.icache.overall_misses 314 # number of overall misses
system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 1413500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.212389 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses
system.cpu.icache.overall_mshr_miss_latency 1402000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.207809 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -216,76 +216,76 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 165.921810 # Cycle average of tags in use
system.cpu.icache.total_refs 1139 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 167.838424 # Cycle average of tags in use
system.cpu.icache.total_refs 1197 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2474 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1144 # Number of branches executed
system.cpu.iew.EXEC:nop 40 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.835018 # Inst execution rate
system.cpu.iew.EXEC:refs 2519 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 977 # Number of stores executed
system.cpu.idleCycles 1997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1159 # Number of branches executed
system.cpu.iew.EXEC:nop 43 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.933581 # Inst execution rate
system.cpu.iew.EXEC:refs 2561 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 971 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 5193 # num instructions consuming a value
system.cpu.iew.WB:count 7387 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.742923 # average fanout of values written-back
system.cpu.iew.WB:consumers 5329 # num instructions consuming a value
system.cpu.iew.WB:count 7480 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.739351 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 3858 # num instructions producing a value
system.cpu.iew.WB:rate 0.802848 # insts written-back per cycle
system.cpu.iew.WB:sent 7452 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 373 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 3940 # num instructions producing a value
system.cpu.iew.WB:rate 0.896775 # insts written-back per cycle
system.cpu.iew.WB:sent 7559 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 402 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1874 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1142 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9228 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1542 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 285 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7683 # Number of executed instructions
system.cpu.iew.iewDispLoadInsts 1967 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1200 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 9614 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1590 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 364 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 7787 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 679 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 70 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 895 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 330 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.611129 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.611129 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 7968 # Type of FU issued
system.cpu.iew.lsq.thread.0.squashedLoads 988 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 388 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 70 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 115 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.674140 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.674140 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8151 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 2 0.03% # Type of FU issued
IntAlu 5314 66.69% # Type of FU issued
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5422 66.52% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 2 0.03% # Type of FU issued
FloatAdd 2 0.02% # Type of FU issued
FloatCmp 0 0.00% # Type of FU issued
FloatCvt 0 0.00% # Type of FU issued
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 1659 20.82% # Type of FU issued
MemWrite 990 12.42% # Type of FU issued
MemRead 1720 21.10% # Type of FU issued
MemWrite 1004 12.32% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.013178 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_cnt 104 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.012759 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
@ -297,77 +297,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 70 66.67% # attempts to use FU when none available
MemWrite 35 33.33% # attempts to use FU when none available
MemRead 70 67.31% # attempts to use FU when none available
MemWrite 34 32.69% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 9201
system.cpu.iq.ISSUE:issued_per_cycle.samples 8341
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 5952 6468.86%
1 1111 1207.48%
2 928 1008.59%
3 433 470.60%
4 378 410.82%
5 251 272.80%
6 111 120.64%
7 27 29.34%
8 10 10.87%
0 5104 6119.17%
1 1084 1299.60%
2 829 993.89%
3 533 639.01%
4 366 438.80%
5 258 309.32%
6 126 151.06%
7 28 33.57%
8 13 15.59%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.865993 # Inst issue rate
system.cpu.iq.iqInstsAdded 9166 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 7968 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3154 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.ISSUE:rate 0.977221 # Inst issue rate
system.cpu.iq.iqInstsAdded 9548 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8151 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3578 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2035 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4644.927536 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2467.908903 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 2243500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1192000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 2360 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 3643.835616 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2643.835616 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 266000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 193000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3406.779661 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.779661 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1407000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995181 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 994000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995181 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 3392.857143 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2392.857143 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 47500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 33500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4644.927536 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2243500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 488 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3442.386831 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1673000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995902 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 486 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 1192000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 1187000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995902 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 486 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4644.927536 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2467.908903 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 488 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3442.386831 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2442.386831 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2243500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 483 # number of overall misses
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1673000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995902 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 486 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 1192000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 1187000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995902 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 486 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -380,29 +399,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 278.204751 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 223.758944 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 9201 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking
system.cpu.numCycles 8341 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 6382 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 12837 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10018 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 7477 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1754 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 679 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3426 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:IdleCycles 5339 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 71 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 13891 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 10852 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8114 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1888 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 726 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 102 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4063 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 272 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
system.cpu.timesIdled 26 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:skidInsts 382 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 21 2007 21:25:27
M5 started Fri Jun 22 00:04:38 2007
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:12 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4589500 because target called exit()
Exiting @ tick 4170500 because target called exit()

6
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
children=tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -25,11 +25,15 @@ phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

7
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
View file

@ -1,8 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 93019 # Simulator instruction rate (inst/s)
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 46199079 # Simulator tick rate (ticks/s)
host_inst_rate 109073 # Simulator instruction rate (inst/s)
host_mem_usage 148564 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 54123810 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:34 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:12 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2820500 because target called exit()

24
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,17 +24,16 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -52,12 +51,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -90,12 +85,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -128,12 +119,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +140,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

148
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
View file

@ -1,12 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 54390 # Simulator instruction rate (inst/s)
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 126525357 # Simulator tick rate (ticks/s)
host_inst_rate 65923 # Simulator instruction rate (inst/s)
host_mem_usage 154180 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 155349854 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13168000 # Number of ticks simulated
sim_ticks 13359000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
@ -20,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 92 # nu
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1218000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1131000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks.
@ -38,14 +39,14 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses
system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses
system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2506000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 2327000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -53,14 +54,14 @@ system.cpu.dcache.overall_accesses 1791 # nu
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1626 # number of overall hits
system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
system.cpu.dcache.overall_misses 165 # number of overall misses
system.cpu.dcache.overall_hits 1612 # number of overall hits
system.cpu.dcache.overall_miss_latency 2506000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses
system.cpu.dcache.overall_misses 179 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 2327000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -75,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 103.895955 # Cycle average of tags in use
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13992.779783 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12992.779783 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 3876000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 3599000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -98,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13992.779783 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 3876000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses
system.cpu.icache.demand_misses 277 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 3599000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13992.779783 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12992.779783 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 5366 # number of overall hits
system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 3876000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses
system.cpu.icache.overall_misses 277 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 3599000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -137,53 +138,72 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use
system.cpu.icache.tagsinuse 129.745202 # Cycle average of tags in use
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 876000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 4416000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5292000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5292000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 441 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -197,14 +217,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 179.464793 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 13168000 # number of cpu cycles simulated
system.cpu.numCycles 13359000 # number of cpu cycles simulated
system.cpu.num_insts 5642 # Number of instructions executed
system.cpu.num_refs 1792 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

10
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:35 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:13 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 13168000 because target called exit()
Exiting @ tick 13359000 because target called exit()

45
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload
children=dcache fuPool icache l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -86,6 +86,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -95,12 +96,9 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -118,12 +116,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -139,11 +135,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -217,11 +213,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -229,11 +225,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -259,11 +255,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -271,12 +267,9 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -294,12 +287,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -310,12 +301,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -333,12 +321,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -356,6 +342,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

478
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits 132 # Number of BTB hits
global.BPredUnit.BTBLookups 584 # Number of BTB lookups
global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 376 # Number of conditional branches predicted
global.BPredUnit.lookups 738 # Number of BP lookups
global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target.
host_inst_rate 39805 # Simulator instruction rate (inst/s)
host_mem_usage 153128 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 34110715 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
global.BPredUnit.BTBHits 146 # Number of BTB hits
global.BPredUnit.BTBLookups 613 # Number of BTB lookups
global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect
global.BPredUnit.condPredicted 393 # Number of conditional branches predicted
global.BPredUnit.lookups 777 # Number of BP lookups
global.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target.
host_inst_rate 24407 # Simulator instruction rate (inst/s)
host_mem_usage 153952 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 19202153 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit.
memdepunit.memDep.insertedLoads 635 # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores 367 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated
sim_ticks 2055000 # Number of ticks simulated
sim_ticks 1884000 # Number of ticks simulated
system.cpu.commit.COM:branches 396 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 33 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples 3910
system.cpu.commit.COM:committed_per_cycle.samples 3543
system.cpu.commit.COM:committed_per_cycle.min_value 0
0 2950 7544.76%
1 266 680.31%
2 336 859.34%
3 131 335.04%
4 76 194.37%
5 65 166.24%
6 27 69.05%
7 18 46.04%
8 41 104.86%
0 2580 7281.96%
1 265 747.95%
2 337 951.17%
3 138 389.50%
4 67 189.11%
5 69 194.75%
6 32 90.32%
7 22 62.09%
8 33 93.14%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 415 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 709 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 1118 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 1.723083 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.723083 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5391.304348 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4669.491525 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 372000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses
system.cpu.cpi 1.578969 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.578969 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 518 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 6583.333333 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4891.666667 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 395000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.115830 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 275500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency 293500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.115830 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 239 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14216.216216 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5202.702703 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 202 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 526000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.154812 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 55 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 192500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.154812 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 7.905882 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 5532.142857 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 774500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses
system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 401000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 757 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 9494.845361 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
system.cpu.dcache.demand_hits 660 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 921000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.128137 # miss rate for demand accesses
system.cpu.dcache.demand_misses 97 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 486000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.128137 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 97 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 5532.142857 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
system.cpu.dcache.overall_accesses 757 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 9494.845361 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 668 # number of overall hits
system.cpu.dcache.overall_miss_latency 774500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses
system.cpu.dcache.overall_misses 140 # number of overall misses
system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 401000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses
system.cpu.dcache.overall_hits 660 # number of overall hits
system.cpu.dcache.overall_miss_latency 921000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.128137 # miss rate for overall accesses
system.cpu.dcache.overall_misses 97 # number of overall misses
system.cpu.dcache.overall_mshr_hits 65 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 486000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.128137 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 97 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -119,89 +119,90 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 51.873008 # Cycle average of tags in use
system.cpu.dcache.total_refs 668 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 51.399169 # Cycle average of tags in use
system.cpu.dcache.total_refs 672 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 771 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode
system.cpu.fetch.Branches 738 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 654 # Number of cache lines fetched
system.cpu.fetch.Cycles 1444 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.179431 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.139071 # Number of inst fetches per cycle
system.cpu.decode.DECODE:BlockedCycles 87 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 125 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 4218 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 2648 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 808 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 777 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 686 # Number of cache lines fetched
system.cpu.fetch.Cycles 1528 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 107 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 4951 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.206155 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 686 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 299 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.313611 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples 4113
system.cpu.fetch.rateDist.samples 3769
system.cpu.fetch.rateDist.min_value 0
0 3325 8084.12%
1 32 77.80%
2 80 194.51%
3 50 121.57%
4 99 240.70%
5 52 126.43%
6 39 94.82%
7 35 85.10%
8 401 974.96%
0 2929 7771.29%
1 36 95.52%
2 88 233.48%
3 54 143.27%
4 108 286.55%
5 55 145.93%
6 40 106.13%
7 42 111.44%
8 417 1106.39%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5298.507463 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4556.451613 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1065000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 847500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_accesses 676 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 5629.032258 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4489.247312 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 490 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1047000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.275148 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 835000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.275148 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 2.634409 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5298.507463 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
system.cpu.icache.demand_hits 453 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1065000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses
system.cpu.icache.demand_misses 201 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 847500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses
system.cpu.icache.demand_accesses 676 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 5629.032258 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
system.cpu.icache.demand_hits 490 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1047000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.275148 # miss rate for demand accesses
system.cpu.icache.demand_misses 186 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 835000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.275148 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5298.507463 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
system.cpu.icache.overall_accesses 676 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 5629.032258 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 453 # number of overall hits
system.cpu.icache.overall_miss_latency 1065000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses
system.cpu.icache.overall_misses 201 # number of overall misses
system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 847500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses
system.cpu.icache.overall_hits 490 # number of overall hits
system.cpu.icache.overall_miss_latency 1047000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.275148 # miss rate for overall accesses
system.cpu.icache.overall_misses 186 # number of overall misses
system.cpu.icache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 835000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.275148 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -217,59 +218,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 106.293956 # Cycle average of tags in use
system.cpu.icache.total_refs 453 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 104.691657 # Cycle average of tags in use
system.cpu.icache.total_refs 490 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 501 # Number of branches executed
system.cpu.iew.EXEC:nop 234 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.726477 # Inst execution rate
system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 333 # Number of stores executed
system.cpu.idleCycles 998 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 516 # Number of branches executed
system.cpu.iew.EXEC:nop 242 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.810295 # Inst execution rate
system.cpu.iew.EXEC:refs 894 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 334 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 1652 # num instructions consuming a value
system.cpu.iew.WB:count 2914 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back
system.cpu.iew.WB:consumers 1725 # num instructions consuming a value
system.cpu.iew.WB:count 2987 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.794203 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1321 # num instructions producing a value
system.cpu.iew.WB:rate 0.708485 # insts written-back per cycle
system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute
system.cpu.iew.WB:producers 1370 # num instructions producing a value
system.cpu.iew.WB:rate 0.792518 # insts written-back per cycle
system.cpu.iew.WB:sent 3007 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 146 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions
system.cpu.iew.iewDispLoadInsts 635 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 92 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 367 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 3711 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 560 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 3054 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing
system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.forwLoads 24 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
system.cpu.iew.lsq.thread.0.squashedLoads 220 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 73 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.580355 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.580355 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued
system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly
system.cpu.ipc 0.633324 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.633324 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3165 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
No_OpClass 0 0.00% # Type of FU issued
IntAlu 2178 70.83% # Type of FU issued
IntAlu 2243 70.87% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 0 0.00% # Type of FU issued
@ -278,16 +279,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
FloatMult 0 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
MemRead 561 18.24% # Type of FU issued
MemWrite 335 10.89% # Type of FU issued
MemRead 581 18.36% # Type of FU issued
MemWrite 340 10.74% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate 0.011058 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 2 5.71% # attempts to use FU when none available
IntAlu 1 2.86% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
@ -297,41 +298,60 @@ system.cpu.iq.ISSUE:fu_full.start_dist
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
MemRead 12 34.29% # attempts to use FU when none available
MemWrite 21 60.00% # attempts to use FU when none available
MemWrite 22 62.86% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples 4113
system.cpu.iq.ISSUE:issued_per_cycle.samples 3769
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
0 2848 6924.39%
1 479 1164.60%
2 276 671.04%
3 213 517.87%
4 158 384.15%
5 86 209.09%
6 34 82.66%
7 13 31.61%
8 6 14.59%
0 2469 6550.81%
1 494 1310.69%
2 274 726.98%
3 234 620.85%
4 152 403.29%
5 87 230.83%
6 40 106.13%
7 14 37.15%
8 5 13.27%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
system.cpu.iq.ISSUE:rate 0.747629 # Inst issue rate
system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 4509.259259 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 1217500 # number of ReadReq miss cycles
system.cpu.iq.ISSUE:rate 0.839745 # Inst issue rate
system.cpu.iq.iqInstsAdded 3463 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3165 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 947 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 468 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 25 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 3720 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2720 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 93000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 25 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 25 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 3357.723577 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.723577 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 826000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 580000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 3230.769231 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2230.769231 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 42000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 29000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@ -340,32 +360,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 4509.259259 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 3391.143911 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1217500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 919000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 648000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 4509.259259 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 3391.143911 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1217500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 919000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 270 # number of overall misses
system.cpu.l2cache.overall_misses 271 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 648000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -378,28 +398,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 158.313436 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 129.636467 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 4113 # number of cpu cycles simulated
system.cpu.numCycles 3769 # number of cpu cycles simulated
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle
system.cpu.rename.RENAME:IdleCycles 2724 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 700 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed
system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:RenameLookups 4613 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 4068 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2909 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 733 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1141 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 80 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 21 2007 21:25:27
M5 started Fri Jun 22 00:04:44 2007
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:13 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2055000 because target called exit()
Exiting @ tick 1884000 because target called exit()

6
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
children=tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -25,11 +25,15 @@ phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

7
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,8 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 111994 # Simulator instruction rate (inst/s)
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 55017079 # Simulator tick rate (ticks/s)
host_inst_rate 34280 # Simulator instruction rate (inst/s)
host_mem_usage 147884 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
host_tick_rate 17043200 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:37 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:14 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1288500 because target called exit()

24
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,17 +24,16 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -52,12 +51,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -90,12 +85,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -128,12 +119,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +140,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello

101
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,12 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 51133 # Simulator instruction rate (inst/s)
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 127514531 # Simulator tick rate (ticks/s)
host_inst_rate 43962 # Simulator instruction rate (inst/s)
host_mem_usage 153564 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 112042683 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 6472000 # Number of ticks simulated
sim_seconds 0.000007 # Number of seconds simulated
sim_ticks 6615000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
@ -20,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 55 # nu
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 532000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 494000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
@ -38,14 +39,14 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1302000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 1209000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -53,14 +54,14 @@ system.cpu.dcache.overall_accesses 709 # nu
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 627 # number of overall hits
system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
system.cpu.dcache.overall_misses 82 # number of overall misses
system.cpu.dcache.overall_hits 616 # number of overall hits
system.cpu.dcache.overall_miss_latency 1302000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
system.cpu.dcache.overall_misses 93 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 1209000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -75,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 50.044147 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@ -137,20 +138,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use
system.cpu.icache.tagsinuse 86.205303 # Cycle average of tags in use
system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 324000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency 2616000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 132000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
@ -160,10 +179,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 2940000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -174,11 +193,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 2940000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 245 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -197,14 +216,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 109.774164 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 6472000 # number of cpu cycles simulated
system.cpu.numCycles 6615000 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
system.cpu.num_refs 710 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls

10
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:37 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:14 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 6472000 because target called exit()
Exiting @ tick 6615000 because target called exit()

8
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
children=tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -25,11 +25,15 @@ phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
@ -53,7 +57,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory

8
tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 535701 # Simulator instruction rate (inst/s)
host_mem_usage 148368 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 257653061 # Simulator tick rate (ticks/s)
host_inst_rate 25511 # Simulator instruction rate (inst/s)
host_mem_usage 149560 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
host_tick_rate 12728361 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

4
tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
View file

@ -6,8 +6,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 12:54:05
M5 started Tue May 15 12:54:07 2007
M5 compiled Aug 3 2007 04:06:41
M5 started Fri Aug 3 04:31:09 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

32
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,17 +24,16 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -44,7 +43,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +51,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -82,7 +77,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +85,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -120,7 +111,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +119,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +140,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
@ -174,7 +166,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

108
tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 273338 # Simulator instruction rate (inst/s)
host_mem_usage 153844 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 633390216 # Simulator tick rate (ticks/s)
host_inst_rate 45085 # Simulator instruction rate (inst/s)
host_mem_usage 155088 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 101545982 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13362000 # Number of ticks simulated
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13544000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
@ -21,13 +21,13 @@ system.cpu.dcache.ReadReq_mshr_misses 82 # nu
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 896000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 832000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks.
@ -39,14 +39,14 @@ system.cpu.dcache.cache_copies 0 # nu
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses
system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2044000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 1898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
@ -54,14 +54,14 @@ system.cpu.dcache.overall_accesses 2054 # nu
system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1922 # number of overall hits
system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses
system.cpu.dcache.overall_misses 132 # number of overall misses
system.cpu.dcache.overall_hits 1908 # number of overall hits
system.cpu.dcache.overall_miss_latency 2044000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
system.cpu.dcache.overall_misses 146 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 1898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 85.440937 # Cycle average of tags in use
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
@ -138,34 +138,52 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use
system.cpu.icache.tagsinuse 136.727640 # Cycle average of tags in use
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 600000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_miss_latency 4596000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 168000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.004619 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency 5196000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
@ -176,11 +194,11 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency 5196000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 433 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
@ -199,14 +217,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 184.077317 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 13362000 # number of cpu cycles simulated
system.cpu.numCycles 13544000 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls

6
tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 12:54:05
M5 started Tue May 15 12:54:07 2007
M5 compiled Aug 3 2007 04:06:41
M5 started Fri Aug 3 04:31:10 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 13362000 because target called exit()
Exiting @ tick 13544000 because target called exit()

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=workload
children=tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -25,11 +25,15 @@ phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
@ -53,7 +57,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 439375 # Simulator instruction rate (inst/s)
host_mem_usage 149124 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 211870315 # Simulator tick rate (ticks/s)
host_inst_rate 15625 # Simulator instruction rate (inst/s)
host_mem_usage 149968 # Number of bytes of host memory used
host_seconds 0.31 # Real time elapsed on the host
host_tick_rate 7799892 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000002 # Number of seconds simulated

4
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 17:00:05 2007
M5 compiled Aug 3 2007 04:11:25
M5 started Fri Aug 3 04:31:18 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

32
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
children=dcache icache l2cache toL2Bus tracer workload
clock=500
cpu_id=0
defer_registration=false
@ -24,17 +24,16 @@ max_loads_any_thread=0
phase=0
progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -44,7 +43,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -52,12 +51,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -68,11 +65,9 @@ mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -82,7 +77,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -90,12 +85,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -106,11 +99,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -120,7 +111,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -128,12 +119,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -151,6 +140,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
@ -174,7 +166,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

165
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 239687 # Simulator instruction rate (inst/s)
host_mem_usage 154512 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 542234464 # Simulator tick rate (ticks/s)
host_inst_rate 36222 # Simulator instruction rate (inst/s)
host_mem_usage 155556 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 84966253 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11221000 # Number of ticks simulated
sim_ticks 11443000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 13962.962963 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12962.962963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency 754000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 700000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_hits 562 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 1386000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.149773 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 99 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 1287000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.149773 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 99 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
@ -37,31 +37,31 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
system.cpu.dcache.demand_avg_miss_latency 13986.928105 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1116 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 2140000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.120567 # miss rate for demand accesses
system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 1987000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.120567 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency
system.cpu.dcache.overall_avg_miss_latency 13986.928105 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12986.928105 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1131 # number of overall hits
system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
system.cpu.dcache.overall_misses 138 # number of overall misses
system.cpu.dcache.overall_hits 1116 # number of overall hits
system.cpu.dcache.overall_miss_latency 2140000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.120567 # miss rate for overall accesses
system.cpu.dcache.overall_misses 153 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_miss_latency 1987000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.120567 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 83.865949 # Cycle average of tags in use
system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_miss_latency 13984.375000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12984.375000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency 3580000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 3324000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency
system.cpu.icache.demand_avg_miss_latency 13984.375000 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency 3580000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 3324000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency
system.cpu.icache.overall_avg_miss_latency 13984.375000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 12984.375000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4608 # number of overall hits
system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency 3580000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 3324000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@ -138,53 +138,72 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use
system.cpu.icache.tagsinuse 114.646434 # Cycle average of tags in use
system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_accesses 84 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 12000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 1008000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 84 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 924000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 84 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 12000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 3684000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 12000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency 180000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 4692000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 12000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_hits 3 # number of overall hits
system.cpu.l2cache.overall_miss_latency 4692000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
@ -198,14 +217,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 133.135118 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 11221000 # number of cpu cycles simulated
system.cpu.numCycles 11443000 # number of cpu cycles simulated
system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls

6
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 13:02:31
M5 started Tue May 15 17:00:05 2007
M5 compiled Aug 3 2007 04:11:25
M5 started Fri Aug 3 04:31:19 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 11221000 because target called exit()
Exiting @ tick 11443000 because target called exit()

45
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
View file

@ -11,7 +11,7 @@ physmem=system.physmem
[system.cpu]
type=DerivO3CPU
children=dcache fuPool icache l2cache toL2Bus workload0 workload1
children=dcache fuPool icache l2cache toL2Bus tracer workload0 workload1
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@ -86,6 +86,7 @@ smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
system=system
tracer=system.cpu.tracer
trapLatency=13
wbDepth=1
wbWidth=8
@ -95,12 +96,9 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -118,12 +116,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -139,11 +135,11 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList0
children=opList
count=6
opList=system.cpu.fuPool.FUList0.opList0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList0]
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
@ -217,11 +213,11 @@ opLat=24
[system.cpu.fuPool.FUList4]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList4.opList0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList0]
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
@ -229,11 +225,11 @@ opLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList0
children=opList
count=0
opList=system.cpu.fuPool.FUList5.opList0
opList=system.cpu.fuPool.FUList5.opList
[system.cpu.fuPool.FUList5.opList0]
[system.cpu.fuPool.FUList5.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
@ -259,11 +255,11 @@ opLat=1
[system.cpu.fuPool.FUList7]
type=FUDesc
children=opList0
children=opList
count=1
opList=system.cpu.fuPool.FUList7.opList0
opList=system.cpu.fuPool.FUList7.opList
[system.cpu.fuPool.FUList7.opList0]
[system.cpu.fuPool.FUList7.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@ -271,12 +267,9 @@ opLat=3
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -294,12 +287,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=20
trace_addr=0
@ -310,12 +301,9 @@ mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -333,12 +321,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
@ -356,6 +342,9 @@ responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload0]
type=LiveProcess
cmd=hello

732
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 21 2007 21:25:27
M5 started Fri Jun 22 00:04:51 2007
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:15 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 5491500 because target called exit()
Exiting @ tick 5126000 because target called exit()

68
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -35,7 +35,7 @@ side_b=system.membus.port[0]
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
@ -55,18 +55,16 @@ profile=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu0.tracer
width=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -84,12 +82,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -98,23 +94,15 @@ write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu0.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu0.dtb]
type=AlphaDTB
size=64
[system.cpu0.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -132,12 +120,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -146,18 +132,16 @@ write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu0.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu0.itb]
type=AlphaITB
size=48
[system.cpu0.tracer]
type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=1
defer_registration=false
@ -177,18 +161,16 @@ profile=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu1.tracer
width=1
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -206,12 +188,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -220,23 +200,15 @@ write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
[system.cpu1.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1.dtb]
type=AlphaDTB
size=64
[system.cpu1.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -254,12 +226,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -268,15 +238,13 @@ write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
[system.cpu1.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1.itb]
type=AlphaITB
size=48
[system.cpu1.tracer]
type=ExeTracer
[system.disk0]
type=IdeDisk
children=image
@ -331,11 +299,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.l2c]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -353,12 +319,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=4194304
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
@ -922,7 +886,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=system.tsunami
system=system
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]

242
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
View file

@ -1,20 +1,29 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1418499 # Simulator instruction rate (inst/s)
host_seconds 44.50 # Real time elapsed on the host
host_tick_rate 42028043491 # Simulator tick rate (ticks/s)
host_inst_rate 1258571 # Simulator instruction rate (inst/s)
host_mem_usage 256444 # Number of bytes of host memory used
host_seconds 50.16 # Real time elapsed on the host
host_tick_rate 37289409683 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63125943 # Number of instructions simulated
sim_seconds 1.870335 # Number of seconds simulated
sim_ticks 1870335101500 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits 7464198 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate 0.185482 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 1699743 # number of ReadReq misses
system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits 5646722 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 286674 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses
system.cpu0.dcache.ReadReq_accesses 8975658 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_hits 7292076 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_rate 0.187572 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 1683582 # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_hits 159819 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_rate 0.146827 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses 27504 # number of StoreCondReq misses
system.cpu0.dcache.WriteReq_accesses 5746073 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_hits 5372266 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses 373807 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 6.625567 # Average number of references to valid blocks.
@ -23,13 +32,13 @@ system.cpu0.dcache.blocked_no_targets 0 # nu
system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses 14721731 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu0.dcache.demand_hits 13110920 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits 12664342 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate 0.131574 # miss rate for demand accesses
system.cpu0.dcache.demand_misses 1986417 # number of demand (read+write) misses
system.cpu0.dcache.demand_miss_rate 0.139752 # miss rate for demand accesses
system.cpu0.dcache.demand_misses 2057389 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -37,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses 14721731 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits 13110920 # number of overall hits
system.cpu0.dcache.overall_hits 12664342 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate 0.131574 # miss rate for overall accesses
system.cpu0.dcache.overall_misses 1986417 # number of overall misses
system.cpu0.dcache.overall_miss_rate 0.139752 # miss rate for overall accesses
system.cpu0.dcache.overall_misses 2057389 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -60,39 +69,13 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued 0
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu0.dcache.protocol.read_invalid 1699743 # read misses to invalid blocks
system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks
system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks
system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks
system.cpu0.dcache.protocol.snoop_read_owned 121 # read snoops on owned blocks
system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks
system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks
system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks
system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks
system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks
system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks
system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks
system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu0.dcache.protocol.write_invalid 282338 # write misses to invalid blocks
system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks
system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks
system.cpu0.dcache.replacements 1978980 # number of replacements
system.cpu0.dcache.sampled_refs 1979492 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13115256 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 0 # number of writebacks
system.cpu0.dcache.writebacks 396796 # number of writebacks
system.cpu0.dtb.accesses 698037 # DTB accesses
system.cpu0.dtb.acv 251 # DTB access violations
system.cpu0.dtb.hits 15082969 # DTB hits
@ -154,32 +137,6 @@ system.cpu0.icache.prefetcher.num_hwpf_issued 0
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks
system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu0.icache.protocol.snoop_read_exclusive 25832 # read snoops on exclusive blocks
system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks
system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks
system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks
system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks
system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks
system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu0.icache.replacements 884276 # number of replacements
system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -285,14 +242,22 @@ system.cpu0.not_idle_fraction 0.015290 # Pe
system.cpu0.numCycles 57193784 # number of cpu cycles simulated
system.cpu0.num_insts 57190172 # Number of instructions executed
system.cpu0.num_refs 15322419 # Number of memory references
system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses
system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses
system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses
system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks.
@ -301,13 +266,13 @@ system.cpu1.dcache.blocked_no_targets 0 # nu
system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses
system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses
system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -315,14 +280,14 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits 1847506 # number of overall hits
system.cpu1.dcache.overall_hits 1812115 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 69527 # number of overall misses
system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses
system.cpu1.dcache.overall_misses 72155 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -338,39 +303,13 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued 0
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks
system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks
system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks
system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks
system.cpu1.dcache.protocol.snoop_read_shared 61772 # read snoops on shared blocks
system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks
system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks
system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks
system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks
system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks
system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks
system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks
system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks
system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks
system.cpu1.dcache.replacements 62341 # number of replacements
system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 0 # number of writebacks
system.cpu1.dcache.writebacks 30850 # number of writebacks
system.cpu1.dtb.accesses 323622 # DTB accesses
system.cpu1.dtb.acv 116 # DTB access violations
system.cpu1.dtb.hits 1914885 # DTB hits
@ -432,32 +371,6 @@ system.cpu1.icache.prefetcher.num_hwpf_issued 0
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks
system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu1.icache.protocol.snoop_read_exclusive 17317 # read snoops on exclusive blocks
system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks
system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks
system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks
system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks
system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks
system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu1.icache.replacements 103097 # number of replacements
system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
@ -559,30 +472,33 @@ system.disk2.dma_write_bytes 8192 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits 181108 # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate 0.408619 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses
system.l2c.ReadReq_accesses 2724166 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits 1782863 # number of ReadReq hits
system.l2c.ReadReq_miss_rate 0.345538 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 941303 # number of ReadReq misses
system.l2c.Writeback_accesses 427634 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 427634 # number of Writeback hits
system.l2c.ReadReq_hits 1625506 # number of ReadReq hits
system.l2c.ReadReq_miss_rate 0.403301 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 1098660 # number of ReadReq misses
system.l2c.UpgradeReq_accesses 125013 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 125013 # number of UpgradeReq misses
system.l2c.Writeback_accesses 427646 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.l2c.Writeback_misses 427646 # number of Writeback misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_refs 2.242879 # Average number of references to valid blocks.
system.l2c.avg_refs 1.720013 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2724166 # number of demand (read+write) accesses
system.l2c.demand_accesses 3030412 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.demand_hits 1782863 # number of demand (read+write) hits
system.l2c.demand_hits 1625506 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.345538 # miss rate for demand accesses
system.l2c.demand_misses 941303 # number of demand (read+write) misses
system.l2c.demand_miss_rate 0.463602 # miss rate for demand accesses
system.l2c.demand_misses 1404906 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -590,14 +506,14 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 3151800 # number of overall (read+write) accesses
system.l2c.overall_accesses 3030412 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.l2c.overall_hits 2210497 # number of overall hits
system.l2c.overall_hits 1625506 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate 0.298656 # miss rate for overall accesses
system.l2c.overall_misses 941303 # number of overall misses
system.l2c.overall_miss_rate 0.463602 # miss rate for overall accesses
system.l2c.overall_misses 1404906 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -613,12 +529,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 1000779 # number of replacements
system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks.
system.l2c.replacements 947869 # number of replacements
system.l2c.sampled_refs 966791 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 65517.575356 # Cycle average of tags in use
system.l2c.total_refs 2391266 # Total number of references to valid blocks.
system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit.
system.l2c.tagsinuse 15587.342424 # Cycle average of tags in use
system.l2c.total_refs 1662893 # Total number of references to valid blocks.
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!

11
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:04:58 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:22:43 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1870335097000 because m5_exit instruction encountered
Exiting @ tick 1870335101500 because m5_exit instruction encountered

38
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -35,7 +35,7 @@ side_b=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
@ -55,18 +55,16 @@ profile=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -84,12 +82,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -98,23 +94,15 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -132,12 +120,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -146,15 +132,13 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.disk0]
type=IdeDisk
children=image
@ -209,11 +193,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.l2c]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -231,12 +213,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=4194304
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
@ -800,7 +780,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=system.tsunami
system=system
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]

184
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
View file

@ -1,35 +1,44 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1403977 # Simulator instruction rate (inst/s)
host_seconds 42.74 # Real time elapsed on the host
host_tick_rate 42777462102 # Simulator tick rate (ticks/s)
host_inst_rate 1294756 # Simulator instruction rate (inst/s)
host_mem_usage 255900 # Number of bytes of host memory used
host_seconds 46.35 # Real time elapsed on the host
host_tick_rate 39449403667 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60007317 # Number of instructions simulated
sim_seconds 1.828355 # Number of seconds simulated
sim_ticks 1828355486000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 7984498 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1738835 # number of ReadReq misses
system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses
sim_ticks 1828355476000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200279 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 183119 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 17160 # number of LoadLockedReq misses
system.cpu.dcache.ReadReq_accesses 9523054 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 7801377 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_rate 0.180790 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1721677 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses 199258 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits 169392 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_rate 0.149886 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 29866 # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses 6150189 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_hits 5750772 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_rate 0.064944 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 399417 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.866566 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 6.866558 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses 15673243 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.demand_hits 14029591 # number of demand (read+write) hits
system.cpu.dcache.demand_hits 13552149 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2043189 # number of demand (read+write) misses
system.cpu.dcache.demand_miss_rate 0.135332 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2121094 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -37,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses 0 # nu
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses 15673243 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 14029591 # number of overall hits
system.cpu.dcache.overall_hits 13552149 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2043189 # number of overall misses
system.cpu.dcache.overall_miss_rate 0.135332 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2121094 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -60,39 +69,13 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu.dcache.protocol.read_invalid 1738835 # read misses to invalid blocks
system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks
system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks
system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks
system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks
system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks
system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks
system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks
system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks
system.cpu.dcache.replacements 2042664 # number of replacements
system.cpu.dcache.sampled_refs 2043176 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 2042666 # number of replacements
system.cpu.dcache.sampled_refs 2043178 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use
system.cpu.dcache.total_refs 14029603 # Total number of references to valid blocks.
system.cpu.dcache.total_refs 14029601 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.writebacks 428885 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
system.cpu.dtb.hits 16053818 # DTB hits
@ -106,12 +89,12 @@ system.cpu.dtb.write_acv 157 # DT
system.cpu.dtb.write_hits 6349968 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits
system.cpu.icache.ReadReq_hits 59087260 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses
system.cpu.icache.ReadReq_misses 920057 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 64.229332 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
@ -120,10 +103,10 @@ system.cpu.icache.cache_copies 0 # nu
system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits
system.cpu.icache.demand_hits 59087260 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses
system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses
system.cpu.icache.demand_misses 920057 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -135,10 +118,10 @@ system.cpu.icache.overall_accesses 60007317 # nu
system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 59087263 # number of overall hits
system.cpu.icache.overall_hits 59087260 # number of overall hits
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses
system.cpu.icache.overall_misses 920054 # number of overall misses
system.cpu.icache.overall_misses 920057 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -154,37 +137,11 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks
system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks
system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks
system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks
system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks
system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks
system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks
system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks
system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu.icache.replacements 919427 # number of replacements
system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks.
system.cpu.icache.replacements 919430 # number of replacements
system.cpu.icache.sampled_refs 919942 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use
system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks.
system.cpu.icache.total_refs 59087260 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.983588 # Percentage of idle cycles
@ -222,8 +179,8 @@ system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # nu
system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1828355278500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1811087547500 99.06% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks 1828355268500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1811087537500 99.06% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl
@ -243,7 +200,7 @@ system.cpu.kern.mode_switch_good_user 1 # fr
system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1800056182000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1800056172000 98.45% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
@ -293,30 +250,33 @@ system.disk2.dma_write_bytes 8192 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits
system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses
system.l2c.ReadReq_accesses 2658872 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits 1717828 # number of ReadReq hits
system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 941044 # number of ReadReq misses
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304342 # number of ReadExReq misses
system.l2c.ReadReq_accesses 2658877 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_hits 1558398 # number of ReadReq hits
system.l2c.ReadReq_miss_rate 0.413889 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 1100479 # number of ReadReq misses
system.l2c.UpgradeReq_accesses 124941 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 124941 # number of UpgradeReq misses
system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 428885 # number of Writeback hits
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.l2c.Writeback_misses 428885 # number of Writeback misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_refs 2.205901 # Average number of references to valid blocks.
system.l2c.avg_refs 1.644070 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2658872 # number of demand (read+write) accesses
system.l2c.demand_accesses 2963219 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.demand_hits 1717828 # number of demand (read+write) hits
system.l2c.demand_hits 1558398 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses
system.l2c.demand_misses 941044 # number of demand (read+write) misses
system.l2c.demand_miss_rate 0.474086 # miss rate for demand accesses
system.l2c.demand_misses 1404821 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@ -324,14 +284,14 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 3087757 # number of overall (read+write) accesses
system.l2c.overall_accesses 2963219 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.l2c.overall_hits 2146713 # number of overall hits
system.l2c.overall_hits 1558398 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses
system.l2c.overall_misses 941044 # number of overall misses
system.l2c.overall_miss_rate 0.474086 # miss rate for overall accesses
system.l2c.overall_misses 1404821 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@ -347,12 +307,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 992432 # number of replacements
system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks.
system.l2c.replacements 947436 # number of replacements
system.l2c.sampled_refs 965232 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use
system.l2c.total_refs 2333446 # Total number of references to valid blocks.
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tagsinuse 15309.548937 # Cycle average of tags in use
system.l2c.total_refs 1586909 # Total number of references to valid blocks.
system.l2c.warmup_cycle 789998500 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...

11
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 00:55:45 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:21:55 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1828355481500 because m5_exit instruction encountered
Exiting @ tick 1828355476000 because m5_exit instruction encountered

68
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -35,7 +35,7 @@ side_b=system.membus.port[0]
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
@ -54,17 +54,15 @@ phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu0.tracer
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -82,12 +80,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -96,23 +92,15 @@ write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu0.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu0.dtb]
type=AlphaDTB
size=64
[system.cpu0.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -130,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -144,18 +130,16 @@ write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu0.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu0.itb]
type=AlphaITB
size=48
[system.cpu0.tracer]
type=ExeTracer
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=1
defer_registration=false
@ -174,17 +158,15 @@ phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu1.tracer
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -202,12 +184,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -216,23 +196,15 @@ write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.port[4]
[system.cpu1.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1.dtb]
type=AlphaDTB
size=64
[system.cpu1.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -250,12 +222,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -264,15 +234,13 @@ write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
[system.cpu1.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1.itb]
type=AlphaITB
size=48
[system.cpu1.tracer]
type=ExeTracer
[system.disk0]
type=IdeDisk
children=image
@ -327,11 +295,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.l2c]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -349,12 +315,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=4194304
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
@ -918,7 +882,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=system.tsunami
system=system
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]

1036
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: 423901000: Trying to launch CPU number 1!
warn: 427086000: Trying to launch CPU number 1!

11
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:30:38 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:25:10 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1951129131000 because m5_exit instruction encountered
Exiting @ tick 1951367346000 because m5_exit instruction encountered

38
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -35,7 +35,7 @@ side_b=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache itb
children=dcache dtb icache itb tracer
clock=500
cpu_id=0
defer_registration=false
@ -54,17 +54,15 @@ phase=0
profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -82,12 +80,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu.dcache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -96,23 +92,15 @@ write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.toL2Bus.port[2]
[system.cpu.dcache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu.dtb]
type=AlphaDTB
size=64
[system.cpu.icache]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=1
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -130,12 +118,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu.icache.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -144,15 +130,13 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.toL2Bus.port[1]
[system.cpu.icache.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu.itb]
type=AlphaITB
size=48
[system.cpu.tracer]
type=ExeTracer
[system.disk0]
type=IdeDisk
children=image
@ -207,11 +191,9 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst
[system.l2c]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -229,12 +211,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=4194304
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0
@ -798,7 +778,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=system.tsunami
system=system
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.port[23]

474
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
View file

@ -1,74 +1,93 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 62427 # Simulator instruction rate (inst/s)
host_seconds 961.73 # Real time elapsed on the host
host_tick_rate 1983042717 # Simulator tick rate (ticks/s)
host_inst_rate 631972 # Simulator instruction rate (inst/s)
host_mem_usage 219140 # Number of bytes of host memory used
host_seconds 95.00 # Real time elapsed on the host
host_tick_rate 20109299069 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60037406 # Number of instructions simulated
sim_seconds 1.907146 # Number of seconds simulated
sim_ticks 1907146437000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles
system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles
sim_insts 60034774 # Number of instructions simulated
sim_seconds 1.910310 # Number of seconds simulated
sim_ticks 1910309711000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses 200211 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits 182851 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_miss_latency 242357000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_rate 0.086709 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 17360 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 224997000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086709 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 17360 # number of LoadLockedReq MSHR misses
system.cpu.dcache.ReadReq_accesses 9525872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_hits 7801048 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 22837453500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.181067 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1724824 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 21112583500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.181067 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1724824 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 830826000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.StoreCondReq_accesses 199189 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_hits 169131 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_miss_latency 420836000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_rate 0.150902 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_misses 30058 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_mshr_miss_latency 390778000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150902 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_misses 30058 # number of StoreCondReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6151132 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_hits 5750801 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 5605013500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.065082 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 400331 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 5204682500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.065082 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 400331 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1164414500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 6.854770 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency
system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses
system.cpu.dcache.demand_accesses 15677004 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 13383.714129 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
system.cpu.dcache.demand_hits 13551849 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 28442467000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.135559 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2125155 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_miss_latency 26317266000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.135559 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2125155 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 14030883 # number of overall hits
system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2046000 # number of overall misses
system.cpu.dcache.overall_accesses 15677004 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 13383.714129 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 13551849 # number of overall hits
system.cpu.dcache.overall_miss_latency 28442467000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.135559 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2125155 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_miss_latency 26317266000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.135559 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2125155 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 1995240500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@ -78,95 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks
system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks
system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks
system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks
system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks
system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks
system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks
system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks
system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks
system.cpu.dcache.replacements 2045476 # number of replacements
system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 2046194 # number of replacements
system.cpu.dcache.sampled_refs 2046706 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use
system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 429989 # number of writebacks
system.cpu.dcache.tagsinuse 511.987834 # Cycle average of tags in use
system.cpu.dcache.total_refs 14029698 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58297000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 429991 # number of writebacks
system.cpu.dtb.accesses 1020787 # DTB accesses
system.cpu.dtb.acv 367 # DTB access violations
system.cpu.dtb.hits 16057425 # DTB hits
system.cpu.dtb.hits 16056951 # DTB hits
system.cpu.dtb.misses 11471 # DTB misses
system.cpu.dtb.read_accesses 728856 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_hits 9706740 # DTB read hits
system.cpu.dtb.read_hits 9706492 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_hits 6350685 # DTB write hits
system.cpu.dtb.write_hits 6350459 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_accesses 60034775 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 12033.060657 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 59106935 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 11164755000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.015455 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 927840 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 10236233500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.015455 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 927840 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 63.714789 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency
system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses
system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses
system.cpu.icache.demand_accesses 60034775 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 12033.060657 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
system.cpu.icache.demand_hits 59106935 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 11164755000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.015455 # miss rate for demand accesses
system.cpu.icache.demand_misses 927840 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_miss_latency 10236233500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.015455 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 927840 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency
system.cpu.icache.overall_accesses 60034775 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 12033.060657 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 59110217 # number of overall hits
system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses
system.cpu.icache.overall_misses 927190 # number of overall misses
system.cpu.icache.overall_hits 59106935 # number of overall hits
system.cpu.icache.overall_miss_latency 11164755000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.015455 # miss rate for overall accesses
system.cpu.icache.overall_misses 927840 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses
system.cpu.icache.overall_mshr_miss_latency 10236233500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.015455 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 927840 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -178,45 +171,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks
system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks
system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks
system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks
system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks
system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks
system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks
system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks
system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks
system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks
system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks
system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks
system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks
system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks
system.cpu.icache.replacements 926519 # number of replacements
system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks.
system.cpu.icache.replacements 927169 # number of replacements
system.cpu.icache.sampled_refs 927680 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use
system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tagsinuse 508.749374 # Cycle average of tags in use
system.cpu.icache.total_refs 59106935 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 35000367000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0.940784 # Percentage of idle cycles
system.cpu.itb.accesses 4977586 # ITB accesses
system.cpu.idle_fraction 0.939637 # Percentage of idle cycles
system.cpu.itb.accesses 4978395 # ITB accesses
system.cpu.itb.acv 184 # ITB acv
system.cpu.itb.hits 4972580 # ITB hits
system.cpu.itb.hits 4973389 # ITB hits
system.cpu.itb.misses 5006 # ITB misses
system.cpu.kern.callpal 192752 # number of callpals executed
system.cpu.kern.callpal 192813 # number of callpals executed
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
@ -224,50 +191,50 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu
system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal_swpipl 175877 91.22% 93.42% # number of callpals executed
system.cpu.kern.callpal_rdps 6828 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_rti 5152 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed
system.cpu.kern.inst.hwrei 211901 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed
system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl
system.cpu.kern.ipl_count 183088 # number of times we switched to this ipl
system.cpu.kern.ipl_count_0 74875 40.90% 40.90% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_count_22 1927 1.05% 42.02% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31 106155 57.98% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good 149074 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0 73508 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_good_22 1927 1.29% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31 73508 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks 1910308997000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0 1853401678500 97.02% 97.02% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21 78202500 0.00% 97.03% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22 538133000 0.03% 97.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31 56290983000 2.95% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used_0 0.981743 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1910
system.cpu.kern.mode_good_user 1740
system.cpu.kern.ipl_used_31 0.692459 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel 1908
system.cpu.kern.mode_good_user 1738
system.cpu.kern.mode_good_idle 170
system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches
system.cpu.kern.mode_switch_user 1740 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches
system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_kernel 5896 # number of protection mode switches
system.cpu.kern.mode_switch_user 1738 # number of protection mode switches
system.cpu.kern.mode_switch_idle 2098 # number of protection mode switches
system.cpu.kern.mode_switch_good 1.404639 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel 0.323609 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode
system.cpu.kern.mode_switch_good_idle 0.081030 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel 43115749000 2.26% 2.26% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user 4716926000 0.25% 2.50% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle 1862476320000 97.50% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.kern.syscall 326 # number of syscalls executed
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
@ -300,10 +267,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles
system.cpu.numCycles 1907146437000 # number of cpu cycles simulated
system.cpu.num_insts 60037406 # Number of instructions executed
system.cpu.num_refs 16305563 # Number of memory references
system.cpu.not_idle_fraction 0.060363 # Percentage of non-idle cycles
system.cpu.numCycles 1910309711000 # number of cpu cycles simulated
system.cpu.num_insts 60034774 # Number of instructions executed
system.cpu.num_refs 16305091 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
@ -316,70 +283,79 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits 1727874 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 940980 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable
system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable
system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles
system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits 429989 # number of Writeback hits
system.l2c.ReadExReq_accesses 304522 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency 12000.719160 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_miss_latency 3654483000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses 304522 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 3349961000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 304522 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses 2670005 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency 12000.233269 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits 1568273 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 13221041000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate 0.412633 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses 1101732 # number of ReadReq misses
system.l2c.ReadReq_mshr_miss_latency 12119309000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate 0.412633 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 1101732 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 750102000 # number of ReadReq MSHR uncacheable cycles
system.l2c.UpgradeReq_accesses 125867 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency 11999.892744 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_miss_latency 1510390500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses 125867 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 1384631500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses 125867 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 1051110500 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses 429991 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses
system.l2c.Writeback_misses 429991 # number of Writeback misses
system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
system.l2c.Writeback_mshr_misses 429991 # number of Writeback MSHR misses
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.l2c.avg_refs 2.216875 # Average number of references to valid blocks.
system.l2c.avg_refs 1.660842 # Average number of references to valid blocks.
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency
system.l2c.demand_hits 1727874 # number of demand (read+write) hits
system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses
system.l2c.demand_misses 940980 # number of demand (read+write) misses
system.l2c.demand_accesses 2974527 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency 12000.338488 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
system.l2c.demand_hits 1568273 # number of demand (read+write) hits
system.l2c.demand_miss_latency 16875524000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate 0.472766 # miss rate for demand accesses
system.l2c.demand_misses 1406254 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_miss_latency 15469270000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate 0.472766 # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses 1406254 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
system.l2c.overall_hits 2157863 # number of overall hits
system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles
system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses
system.l2c.overall_misses 940980 # number of overall misses
system.l2c.overall_accesses 2974527 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency 12000.338488 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 11000.338488 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.overall_hits 1568273 # number of overall hits
system.l2c.overall_miss_latency 16875524000 # number of overall miss cycles
system.l2c.overall_miss_rate 0.472766 # miss rate for overall accesses
system.l2c.overall_misses 1406254 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_miss_latency 15469270000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate 0.472766 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 1406254 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 1801212500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
@ -389,13 +365,13 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu
system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.l2c.replacements 992369 # number of replacements
system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks.
system.l2c.replacements 947259 # number of replacements
system.l2c.sampled_refs 965538 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use
system.l2c.total_refs 2345243 # Total number of references to valid blocks.
system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 74072 # number of writebacks
system.l2c.tagsinuse 15874.904757 # Cycle average of tags in use
system.l2c.total_refs 1603606 # Total number of references to valid blocks.
system.l2c.warmup_cycle 4106790000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post

4
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
warn: Entering event queue @ 0. Starting simulation...

11
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
View file

@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:14:34 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:23:34 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1907146437000 because m5_exit instruction encountered
Exiting @ tick 1910309711000 because m5_exit instruction encountered

102
tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
View file

@ -27,12 +27,9 @@ test=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -50,12 +47,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu0.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -64,11 +59,6 @@ write_buffers=8
cpu_side=system.cpu0.test
mem_side=system.toL2Bus.port[1]
[system.cpu0.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu1]
type=MemTest
children=l1c
@ -87,12 +77,9 @@ test=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -110,12 +97,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu1.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -124,11 +109,6 @@ write_buffers=8
cpu_side=system.cpu1.test
mem_side=system.toL2Bus.port[2]
[system.cpu1.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu2]
type=MemTest
children=l1c
@ -147,12 +127,9 @@ test=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -170,12 +147,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu2.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -184,11 +159,6 @@ write_buffers=8
cpu_side=system.cpu2.test
mem_side=system.toL2Bus.port[3]
[system.cpu2.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu3]
type=MemTest
children=l1c
@ -207,12 +177,9 @@ test=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -230,12 +197,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu3.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -244,11 +209,6 @@ write_buffers=8
cpu_side=system.cpu3.test
mem_side=system.toL2Bus.port[4]
[system.cpu3.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu4]
type=MemTest
children=l1c
@ -267,12 +227,9 @@ test=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -290,12 +247,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu4.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -304,11 +259,6 @@ write_buffers=8
cpu_side=system.cpu4.test
mem_side=system.toL2Bus.port[5]
[system.cpu4.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu5]
type=MemTest
children=l1c
@ -327,12 +277,9 @@ test=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -350,12 +297,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu5.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -364,11 +309,6 @@ write_buffers=8
cpu_side=system.cpu5.test
mem_side=system.toL2Bus.port[6]
[system.cpu5.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu6]
type=MemTest
children=l1c
@ -387,12 +327,9 @@ test=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -410,12 +347,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu6.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -424,11 +359,6 @@ write_buffers=8
cpu_side=system.cpu6.test
mem_side=system.toL2Bus.port[7]
[system.cpu6.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.cpu7]
type=MemTest
children=l1c
@ -447,12 +377,9 @@ test=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
type=BaseCache
children=protocol
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=4
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=1000
lifo=false
@ -470,12 +397,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=system.cpu7.l1c.protocol
repl=Null
size=32768
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=8
trace_addr=0
@ -484,11 +409,6 @@ write_buffers=8
cpu_side=system.cpu7.test
mem_side=system.toL2Bus.port[8]
[system.cpu7.l1c.protocol]
type=CoherenceProtocol
do_upgrades=true
protocol=moesi
[system.funcmem]
type=PhysicalMemory
file=
@ -499,11 +419,9 @@ port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system
[system.l2c]
type=BaseCache
adaptive_compression=false
addr_range=0:18446744073709551615
assoc=8
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
latency=10000
lifo=false
@ -521,12 +439,10 @@ prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=65536
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=16
trace_addr=0

1299
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
View file

File diff suppressed because it is too large Load diff

146
tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
View file

@ -1,74 +1,74 @@
warn: Entering event queue @ 0. Starting simulation...
system.cpu7: completed 10000 read accesses @8253930
system.cpu1: completed 10000 read accesses @8325085
system.cpu6: completed 10000 read accesses @8427313
system.cpu4: completed 10000 read accesses @8438233
system.cpu2: completed 10000 read accesses @8458126
system.cpu5: completed 10000 read accesses @8549800
system.cpu3: completed 10000 read accesses @8559995
system.cpu0: completed 10000 read accesses @8593654
system.cpu7: completed 20000 read accesses @16744182
system.cpu1: completed 20000 read accesses @16774744
system.cpu4: completed 20000 read accesses @16786220
system.cpu3: completed 20000 read accesses @16787358
system.cpu5: completed 20000 read accesses @16795808
system.cpu6: completed 20000 read accesses @16836913
system.cpu2: completed 20000 read accesses @17031052
system.cpu0: completed 20000 read accesses @17126654
system.cpu5: completed 30000 read accesses @24892576
system.cpu6: completed 30000 read accesses @24903300
system.cpu3: completed 30000 read accesses @24935860
system.cpu4: completed 30000 read accesses @25020642
system.cpu1: completed 30000 read accesses @25031726
system.cpu7: completed 30000 read accesses @25112091
system.cpu2: completed 30000 read accesses @25235960
system.cpu0: completed 30000 read accesses @25505209
system.cpu5: completed 40000 read accesses @33191203
system.cpu6: completed 40000 read accesses @33273684
system.cpu4: completed 40000 read accesses @33345526
system.cpu3: completed 40000 read accesses @33406412
system.cpu7: completed 40000 read accesses @33509130
system.cpu1: completed 40000 read accesses @33509218
system.cpu2: completed 40000 read accesses @33664822
system.cpu0: completed 40000 read accesses @33869626
system.cpu5: completed 50000 read accesses @41488848
system.cpu4: completed 50000 read accesses @41582702
system.cpu7: completed 50000 read accesses @41828988
system.cpu3: completed 50000 read accesses @41829496
system.cpu1: completed 50000 read accesses @41849534
system.cpu6: completed 50000 read accesses @41982608
system.cpu2: completed 50000 read accesses @42197798
system.cpu0: completed 50000 read accesses @42443468
system.cpu5: completed 60000 read accesses @49751344
system.cpu4: completed 60000 read accesses @49783100
system.cpu1: completed 60000 read accesses @49918062
system.cpu7: completed 60000 read accesses @49929008
system.cpu3: completed 60000 read accesses @50173996
system.cpu6: completed 60000 read accesses @50351766
system.cpu2: completed 60000 read accesses @50352657
system.cpu0: completed 60000 read accesses @50789771
system.cpu4: completed 70000 read accesses @58352386
system.cpu5: completed 70000 read accesses @58394758
system.cpu7: completed 70000 read accesses @58570698
system.cpu1: completed 70000 read accesses @58764169
system.cpu3: completed 70000 read accesses @58764648
system.cpu2: completed 70000 read accesses @58921714
system.cpu6: completed 70000 read accesses @58929984
system.cpu0: completed 70000 read accesses @59567320
system.cpu1: completed 80000 read accesses @67092786
system.cpu5: completed 80000 read accesses @67153667
system.cpu4: completed 80000 read accesses @67153760
system.cpu7: completed 80000 read accesses @67207042
system.cpu3: completed 80000 read accesses @67238507
system.cpu2: completed 80000 read accesses @67633112
system.cpu6: completed 80000 read accesses @67664637
system.cpu0: completed 80000 read accesses @68437288
system.cpu1: completed 90000 read accesses @75679048
system.cpu4: completed 90000 read accesses @75680280
system.cpu7: completed 90000 read accesses @75751053
system.cpu5: completed 90000 read accesses @75781514
system.cpu3: completed 90000 read accesses @75844118
system.cpu2: completed 90000 read accesses @76346671
system.cpu6: completed 90000 read accesses @76491728
system.cpu0: completed 90000 read accesses @77376872
system.cpu1: completed 100000 read accesses @84350509
system.cpu7: completed 10000 read accesses @15607088
system.cpu1: completed 10000 read accesses @15686239
system.cpu5: completed 10000 read accesses @15771479
system.cpu4: completed 10000 read accesses @15772513
system.cpu0: completed 10000 read accesses @15778178
system.cpu6: completed 10000 read accesses @15791633
system.cpu2: completed 10000 read accesses @15841990
system.cpu3: completed 10000 read accesses @15878600
system.cpu2: completed 20000 read accesses @31878727
system.cpu7: completed 20000 read accesses @32026154
system.cpu6: completed 20000 read accesses @32057190
system.cpu1: completed 20000 read accesses @32240417
system.cpu0: completed 20000 read accesses @32270672
system.cpu3: completed 20000 read accesses @32335938
system.cpu5: completed 20000 read accesses @32480722
system.cpu4: completed 20000 read accesses @32490454
system.cpu2: completed 30000 read accesses @48060100
system.cpu6: completed 30000 read accesses @48167196
system.cpu4: completed 30000 read accesses @48520588
system.cpu7: completed 30000 read accesses @48646309
system.cpu0: completed 30000 read accesses @48740616
system.cpu1: completed 30000 read accesses @48766857
system.cpu3: completed 30000 read accesses @48959010
system.cpu5: completed 30000 read accesses @49028132
system.cpu6: completed 40000 read accesses @64421948
system.cpu4: completed 40000 read accesses @64637670
system.cpu2: completed 40000 read accesses @64868400
system.cpu1: completed 40000 read accesses @64925788
system.cpu0: completed 40000 read accesses @64956331
system.cpu3: completed 40000 read accesses @65406565
system.cpu5: completed 40000 read accesses @65517578
system.cpu7: completed 40000 read accesses @65556693
system.cpu6: completed 50000 read accesses @80917227
system.cpu2: completed 50000 read accesses @80917444
system.cpu4: completed 50000 read accesses @81159816
system.cpu1: completed 50000 read accesses @81373401
system.cpu3: completed 50000 read accesses @81540449
system.cpu0: completed 50000 read accesses @81577912
system.cpu5: completed 50000 read accesses @81975441
system.cpu7: completed 50000 read accesses @82285501
system.cpu2: completed 60000 read accesses @96985412
system.cpu4: completed 60000 read accesses @97174738
system.cpu6: completed 60000 read accesses @97530786
system.cpu0: completed 60000 read accesses @97671589
system.cpu3: completed 60000 read accesses @97821937
system.cpu1: completed 60000 read accesses @97822818
system.cpu5: completed 60000 read accesses @98044596
system.cpu7: completed 60000 read accesses @98812006
system.cpu2: completed 70000 read accesses @113400661
system.cpu4: completed 70000 read accesses @113949415
system.cpu1: completed 70000 read accesses @114120869
system.cpu3: completed 70000 read accesses @114207385
system.cpu0: completed 70000 read accesses @114307850
system.cpu6: completed 70000 read accesses @114393410
system.cpu5: completed 70000 read accesses @114714609
system.cpu7: completed 70000 read accesses @115286783
system.cpu2: completed 80000 read accesses @130149084
system.cpu0: completed 80000 read accesses @130494872
system.cpu4: completed 80000 read accesses @130604588
system.cpu6: completed 80000 read accesses @130741327
system.cpu1: completed 80000 read accesses @130791488
system.cpu3: completed 80000 read accesses @130805400
system.cpu5: completed 80000 read accesses @130975948
system.cpu7: completed 80000 read accesses @131555733
system.cpu2: completed 90000 read accesses @146468442
system.cpu6: completed 90000 read accesses @146616353
system.cpu1: completed 90000 read accesses @146926939
system.cpu3: completed 90000 read accesses @147059543
system.cpu0: completed 90000 read accesses @147067458
system.cpu5: completed 90000 read accesses @147440946
system.cpu4: completed 90000 read accesses @147560717
system.cpu7: completed 90000 read accesses @148115904
system.cpu6: completed 100000 read accesses @163182312

10
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:51 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
M5 compiled Aug 3 2007 03:56:47
M5 started Fri Aug 3 04:17:16 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 84350509 because Maximum number of loads reached!
Exiting @ tick 163182312 because maximum number of loads reached

20
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
View file

@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
@ -35,7 +35,7 @@ side_b=drivesys.membus.port[0]
[drivesys.cpu]
type=AtomicSimpleCPU
children=dtb itb
children=dtb itb tracer
clock=1
cpu_id=0
defer_registration=false
@ -55,6 +55,7 @@ profile=0
progress_interval=0
simulate_stalls=false
system=drivesys
tracer=drivesys.cpu.tracer
width=1
dcache_port=drivesys.membus.port[3]
icache_port=drivesys.membus.port[2]
@ -67,6 +68,9 @@ size=64
type=AlphaITB
size=48
[drivesys.cpu.tracer]
type=ExeTracer
[drivesys.disk0]
type=IdeDisk
children=image
@ -647,7 +651,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=drivesys.tsunami
system=drivesys
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=drivesys.tsunami
year_is_bcd=false
pio=drivesys.iobus.port[23]
@ -704,7 +708,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS
readfile=/z/stever/hg/m5.stever/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
@ -725,7 +729,7 @@ side_b=testsys.membus.port[0]
[testsys.cpu]
type=AtomicSimpleCPU
children=dtb itb
children=dtb itb tracer
clock=1
cpu_id=0
defer_registration=false
@ -745,6 +749,7 @@ profile=0
progress_interval=0
simulate_stalls=false
system=testsys
tracer=testsys.cpu.tracer
width=1
dcache_port=testsys.membus.port[3]
icache_port=testsys.membus.port[2]
@ -757,6 +762,9 @@ size=64
type=AlphaITB
size=48
[testsys.cpu.tracer]
type=ExeTracer
[testsys.disk0]
type=IdeDisk
children=image
@ -1337,7 +1345,7 @@ pio_addr=8804615847936
pio_latency=1000
platform=testsys.tsunami
system=testsys
time=2009 1 1 0 0 0 3 1
time=Thu Jan 1 00:00:00 2009
tsunami=testsys.tsunami
year_is_bcd=false
pio=testsys.iobus.port[23]

12
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
View file

@ -139,9 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
host_inst_rate 6618724 # Simulator instruction rate (inst/s)
host_seconds 41.30 # Real time elapsed on the host
host_tick_rate 4842704130 # Simulator tick rate (ticks/s)
host_inst_rate 51081325 # Simulator instruction rate (inst/s)
host_mem_usage 406704 # Number of bytes of host memory used
host_seconds 5.35 # Real time elapsed on the host
host_tick_rate 37372483621 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
@ -380,9 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
host_inst_rate 65191624612 # Simulator instruction rate (inst/s)
host_inst_rate 71036507796 # Simulator instruction rate (inst/s)
host_mem_usage 406704 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 183725573 # Simulator tick rate (ticks/s)
host_tick_rate 191282064 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

8
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
View file

@ -1,6 +1,6 @@
Listening for testsys connection on port 3456
Listening for drivesys connection on port 3457
0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001
Listening for testsys connection on port 3457
Listening for drivesys connection on port 3458
0: testsys.remote_gdb.listener: listening for remote gdb on port 7001
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
warn: Obsolete M5 instruction ivlb encountered.

10
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
View file

@ -5,11 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:47:32 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
M5 compiled Aug 3 2007 04:02:11
M5 started Fri Aug 3 04:26:58 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 4300235844056 because checkpoint