ARM: Update stats for default inclusion of CF adapter.
This commit is contained in:
Ali Saidi
parent
d6289507d8
commit
afa897403d
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@ -9,7 +9,7 @@ time_sync_spin_threshold=100000000
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type=LinuxArmSystem
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children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
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boot_cpu_frequency=500
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boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
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boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
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init_param=0
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kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
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load_addr_mask=268435455
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@ -515,7 +515,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma
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port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
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[system.iocache]
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type=BaseCache
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@ -621,7 +621,7 @@ port=system.membus.port[2]
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[system.realview]
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type=RealView
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children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
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children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
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intrctrl=system.intrctrl
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system=system
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@ -633,23 +633,63 @@ pio_addr=268451840
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[20]
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pio=system.iobus.port[21]
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[system.realview.cf0_fake]
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type=IsaFake
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pio_addr=402653184
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[system.realview.cf_ctrl]
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type=IdeController
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BAR0=402653184
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BAR0LegacyIO=true
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BAR0Size=16
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BAR1=402653440
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BAR1LegacyIO=true
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BAR1Size=1
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BAR2=1
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BAR2LegacyIO=false
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BAR2Size=8
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BAR3=1
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BAR3LegacyIO=false
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BAR3Size=4
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BAR4=1
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BAR4LegacyIO=false
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BAR4Size=16
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BAR5=1
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BAR5LegacyIO=false
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BAR5Size=0
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BIST=0
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CacheLineSize=0
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CardbusCIS=0
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ClassCode=1
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Command=1
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DeviceID=28945
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ExpansionROM=0
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HeaderType=0
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InterruptLine=31
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InterruptPin=1
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LatencyTimer=0
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MaximumLatency=0
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MinimumGrant=0
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ProgIF=133
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Revision=0
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Status=640
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SubClassCode=1
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SubsystemID=0
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SubsystemVendorID=0
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VendorID=32902
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config_latency=20000
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ctrl_offset=2
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disks=
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io_shift=1
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max_backoff_delay=10000000
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min_backoff_delay=4000
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pci_bus=0
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pci_dev=0
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pci_func=0
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pio_latency=1000
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pio_size=4095
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platform=system.realview
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[24]
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config=system.iobus.port[26]
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dma=system.iobus.port[27]
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pio=system.iobus.port[8]
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[system.realview.clcd]
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type=Pl111
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@ -664,7 +704,7 @@ pio_latency=10000
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platform=system.realview
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system=system
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vnc=system.vncserver
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dma=system.iobus.port[26]
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dma=system.iobus.port[28]
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pio=system.iobus.port[5]
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[system.realview.dmac_fake]
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@ -675,7 +715,7 @@ pio_addr=268632064
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[8]
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pio=system.iobus.port[9]
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[system.realview.flash_fake]
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type=IsaFake
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@ -691,7 +731,7 @@ ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[23]
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pio=system.iobus.port[24]
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[system.realview.gic]
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type=Gic
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@ -712,7 +752,7 @@ pio_addr=268513280
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[15]
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pio=system.iobus.port[16]
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[system.realview.gpio1_fake]
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type=AmbaFake
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@ -722,7 +762,7 @@ pio_addr=268517376
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[16]
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pio=system.iobus.port[17]
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[system.realview.gpio2_fake]
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type=AmbaFake
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@ -732,7 +772,7 @@ pio_addr=268521472
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[17]
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pio=system.iobus.port[18]
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[system.realview.kmi0]
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type=Pl050
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@ -786,7 +826,7 @@ pio_addr=268455936
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[21]
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pio=system.iobus.port[22]
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[system.realview.realview_io]
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type=RealViewCtrl
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@ -805,7 +845,7 @@ pio_addr=268529664
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[22]
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pio=system.iobus.port[23]
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[system.realview.sci_fake]
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type=AmbaFake
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@ -815,7 +855,7 @@ pio_addr=268492800
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[19]
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pio=system.iobus.port[20]
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[system.realview.smc_fake]
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type=AmbaFake
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@ -825,7 +865,7 @@ pio_addr=269357056
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[12]
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pio=system.iobus.port[13]
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[system.realview.sp810_fake]
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type=AmbaFake
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@ -835,7 +875,7 @@ pio_addr=268439552
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[13]
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pio=system.iobus.port[14]
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[system.realview.ssp_fake]
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type=AmbaFake
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@ -845,7 +885,7 @@ pio_addr=268488704
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[18]
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pio=system.iobus.port[19]
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[system.realview.timer0]
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type=Sp804
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@ -896,7 +936,7 @@ pio_addr=268476416
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[9]
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pio=system.iobus.port[10]
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[system.realview.uart2_fake]
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type=AmbaFake
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@ -906,7 +946,7 @@ pio_addr=268480512
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[10]
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pio=system.iobus.port[11]
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[system.realview.uart3_fake]
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type=AmbaFake
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@ -916,7 +956,7 @@ pio_addr=268484608
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[11]
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pio=system.iobus.port[12]
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[system.realview.watchdog_fake]
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type=AmbaFake
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@ -926,7 +966,7 @@ pio_addr=268500992
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[14]
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pio=system.iobus.port[15]
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[system.terminal]
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type=Terminal
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@ -5,11 +5,11 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Mar 31 2011 10:39:48
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M5 started Mar 31 2011 10:41:48
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M5 compiled Apr 4 2011 11:17:23
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M5 started Apr 4 2011 11:17:27
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M5 executing on u200439-lin.austin.arm.com
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command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 82667402500 because m5_exit instruction encountered
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Exiting @ tick 82662490500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
Binary file not shown.
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@ -9,7 +9,7 @@ time_sync_spin_threshold=100000000
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type=LinuxArmSystem
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children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
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boot_cpu_frequency=500
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boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
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boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
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init_param=0
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kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
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load_addr_mask=268435455
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@ -189,7 +189,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma
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port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
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[system.iocache]
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type=BaseCache
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@ -295,7 +295,7 @@ port=system.membus.port[2]
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[system.realview]
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type=RealView
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children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
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children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
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intrctrl=system.intrctrl
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system=system
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@ -307,23 +307,63 @@ pio_addr=268451840
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pio_latency=1000
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platform=system.realview
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system=system
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pio=system.iobus.port[20]
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pio=system.iobus.port[21]
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[system.realview.cf0_fake]
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type=IsaFake
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pio_addr=402653184
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[system.realview.cf_ctrl]
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type=IdeController
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BAR0=402653184
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BAR0LegacyIO=true
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BAR0Size=16
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BAR1=402653440
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BAR1LegacyIO=true
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BAR1Size=1
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BAR2=1
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BAR2LegacyIO=false
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BAR2Size=8
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BAR3=1
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BAR3LegacyIO=false
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BAR3Size=4
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BAR4=1
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BAR4LegacyIO=false
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BAR4Size=16
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BAR5=1
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BAR5LegacyIO=false
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BAR5Size=0
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BIST=0
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CacheLineSize=0
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CardbusCIS=0
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ClassCode=1
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Command=1
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DeviceID=28945
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ExpansionROM=0
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HeaderType=0
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InterruptLine=31
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InterruptPin=1
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LatencyTimer=0
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MaximumLatency=0
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MinimumGrant=0
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ProgIF=133
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Revision=0
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Status=640
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SubClassCode=1
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SubsystemID=0
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SubsystemVendorID=0
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VendorID=32902
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config_latency=20000
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ctrl_offset=2
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disks=
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io_shift=1
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max_backoff_delay=10000000
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min_backoff_delay=4000
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pci_bus=0
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pci_dev=0
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pci_func=0
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pio_latency=1000
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pio_size=4095
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platform=system.realview
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[24]
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config=system.iobus.port[26]
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dma=system.iobus.port[27]
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pio=system.iobus.port[8]
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[system.realview.clcd]
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type=Pl111
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@ -338,7 +378,7 @@ pio_latency=10000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.port[26]
|
||||
dma=system.iobus.port[28]
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
|
|
@ -349,7 +389,7 @@ pio_addr=268632064
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[8]
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -365,7 +405,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.port[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
|
|
@ -386,7 +426,7 @@ pio_addr=268513280
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.port[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -396,7 +436,7 @@ pio_addr=268517376
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.port[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -406,7 +446,7 @@ pio_addr=268521472
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.port[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
|
|
@ -460,7 +500,7 @@ pio_addr=268455936
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[21]
|
||||
pio=system.iobus.port[22]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
|
|
@ -479,7 +519,7 @@ pio_addr=268529664
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[22]
|
||||
pio=system.iobus.port[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -489,7 +529,7 @@ pio_addr=268492800
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[19]
|
||||
pio=system.iobus.port[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -499,7 +539,7 @@ pio_addr=269357056
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -509,7 +549,7 @@ pio_addr=268439552
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.port[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -519,7 +559,7 @@ pio_addr=268488704
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[18]
|
||||
pio=system.iobus.port[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
|
|
@ -570,7 +610,7 @@ pio_addr=268476416
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.port[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -580,7 +620,7 @@ pio_addr=268480512
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.port[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -590,7 +630,7 @@ pio_addr=268484608
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -600,7 +640,7 @@ pio_addr=268500992
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 31 2011 10:39:48
|
||||
M5 started Mar 31 2011 10:41:48
|
||||
M5 compiled Apr 4 2011 11:17:23
|
||||
M5 started Apr 4 2011 11:17:27
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 26404802500 because m5_exit instruction encountered
|
||||
Exiting @ tick 26405524500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,63 +1,63 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2149518 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 377184 # Number of bytes of host memory used
|
||||
host_seconds 24.24 # Real time elapsed on the host
|
||||
host_tick_rate 1089414447 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1925695 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 381972 # Number of bytes of host memory used
|
||||
host_seconds 27.06 # Real time elapsed on the host
|
||||
host_tick_rate 975977117 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 52098748 # Number of instructions simulated
|
||||
sim_seconds 0.026405 # Number of seconds simulated
|
||||
sim_ticks 26404802500 # Number of ticks simulated
|
||||
sim_insts 52100192 # Number of instructions simulated
|
||||
sim_seconds 0.026406 # Number of seconds simulated
|
||||
sim_ticks 26405524500 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 100461 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 100461 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95295 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95295 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051423 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5166 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5166 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.ReadReq_accesses::0 7831304 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7831304 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_hits::0 7594731 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7594731 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030209 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 236573 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 236573 # number of ReadReq misses
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95296 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95296 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051413 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5165 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5165 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.ReadReq_accesses::0 7831528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7831528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_hits::0 7594963 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7594963 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030207 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 236565 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 236565 # number of ReadReq misses
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 100460 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 100460 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits::0 100460 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 100460 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses::0 6676835 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6676835 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_hits::0 6504601 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6504601 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025796 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172234 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172234 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_accesses::0 6676897 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6676897 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_hits::0 6504656 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6504656 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172241 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172241 # number of WriteReq misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 34.689734 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.690601 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses::0 14508139 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::0 14508425 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 14508139 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 14508425 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits::0 14099332 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::0 14099619 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 14099332 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 14099619 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate::0 0.028178 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::0 0.028177 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses::0 408807 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::0 408806 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 408807 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 408806 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -68,25 +68,25 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.999487 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 511.737179 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14508139 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.occ_blocks::0 511.737186 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14508425 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 14508139 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 14508425 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits::0 14099332 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::0 14099619 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 14099332 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 14099619 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate::0 0.028178 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::0 0.028177 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses::0 408807 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::0 408806 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 408807 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 408806 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -95,14 +95,14 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value
|
|||
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 411625 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 412137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 411623 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 412135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 511.737179 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14296923 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 511.737186 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14297211 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 381907 # number of writebacks
|
||||
system.cpu.dtb.accesses 15532701 # DTB accesses
|
||||
system.cpu.dcache.writebacks 381909 # number of writebacks
|
||||
system.cpu.dtb.accesses 15532989 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 2238 # Number of entries that have been flushed from TLB
|
||||
|
|
@ -110,51 +110,51 @@ system.cpu.dtb.flush_tlb 2 # Nu
|
|||
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 15527171 # DTB hits
|
||||
system.cpu.dtb.hits 15527459 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 5530 # DTB misses
|
||||
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 767 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 8743653 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8739120 # DTB read hits
|
||||
system.cpu.dtb.read_accesses 8743878 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8739345 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4533 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 6789048 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6788051 # DTB write hits
|
||||
system.cpu.dtb.write_accesses 6789111 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6788114 # DTB write hits
|
||||
system.cpu.dtb.write_misses 997 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses::0 41565893 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41565893 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_hits::0 41132493 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41132493 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_accesses::0 41566870 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41566870 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_hits::0 41133444 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41133444 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.010427 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses::0 433400 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 433400 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::0 433426 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 433426 # number of ReadReq misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 94.906756 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 94.903257 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses::0 41565893 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::0 41566870 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 41565893 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 41566870 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits::0 41132493 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::0 41133444 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 41132493 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 41133444 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate::0 0.010427 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses::0 433400 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::0 433426 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 433400 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 433426 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
|
||||
|
|
@ -165,25 +165,25 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.930522 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 476.427149 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41565893 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_blocks::0 476.427204 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41566870 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 41565893 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 41566870 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits::0 41132493 # number of overall hits
|
||||
system.cpu.icache.overall_hits::0 41133444 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 41132493 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 41133444 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate::0 0.010427 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses::0 433400 # number of overall misses
|
||||
system.cpu.icache.overall_misses::0 433426 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 433400 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 433426 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
|
||||
|
|
@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value
|
|||
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 432887 # number of replacements
|
||||
system.cpu.icache.sampled_refs 433399 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 432913 # number of replacements
|
||||
system.cpu.icache.sampled_refs 433425 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 476.427149 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41132493 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 4575196500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tagsinuse 476.427204 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41133444 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 4575402000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 33681 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 41567020 # DTB accesses
|
||||
system.cpu.itb.accesses 41567997 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
|
||||
|
|
@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu
|
|||
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 41564192 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41567020 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41564192 # ITB inst hits
|
||||
system.cpu.itb.hits 41565169 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41567997 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41565169 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 2828 # ITB inst misses
|
||||
system.cpu.itb.misses 2828 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
|
|
@ -224,25 +224,25 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 52809606 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 52811050 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 52809606 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 7028794 # number of instructions that are conditional controls
|
||||
system.cpu.num_busy_cycles 52811050 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 7028967 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6058 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 1109315 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 1109362 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 52098748 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 42510432 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 42510432 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 131106250 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 34554090 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 9208607 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16295595 # number of memory refs
|
||||
system.cpu.num_store_insts 7086988 # Number of store instructions
|
||||
system.cpu.num_insts 52100192 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 42511691 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 42511691 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 131109932 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 34554918 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 9209160 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16296226 # number of memory refs
|
||||
system.cpu.num_store_insts 7087066 # Number of store instructions
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
|
|
@ -310,20 +310,20 @@ system.iocache.tagsinuse 0 # Cy
|
|||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 0 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses::0 170398 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170398 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_hits::0 60546 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 60546 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_rate::0 0.644679 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_accesses::0 170405 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170405 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_hits::0 60553 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 60553 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_rate::0 0.644652 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses::0 109852 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 109852 # number of ReadExReq misses
|
||||
system.l2c.ReadReq_accesses::0 673040 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::0 673057 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 6142 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 679182 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits::0 651887 # number of ReadReq hits
|
||||
system.l2c.ReadReq_accesses::total 679199 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_hits::0 651904 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 6117 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 658004 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate::0 0.031429 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_hits::total 658021 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_rate::0 0.031428 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.004070 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 21153 # number of ReadReq misses
|
||||
|
|
@ -336,32 +336,32 @@ system.l2c.UpgradeReq_hits::total 17 # nu
|
|||
system.l2c.UpgradeReq_miss_rate::0 0.990741 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 1819 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1819 # number of UpgradeReq misses
|
||||
system.l2c.Writeback_accesses::0 415588 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 415588 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 415588 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 415588 # number of Writeback hits
|
||||
system.l2c.Writeback_accesses::0 415590 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 415590 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 415590 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 415590 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 6.751328 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 6.746349 # Average number of references to valid blocks.
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses::0 843438 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::0 843462 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 6142 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 849580 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 849604 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.l2c.demand_hits::0 712433 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::0 712457 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 6117 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 718550 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 718574 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.155323 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::0 0.155318 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.004070 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.159393 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.159389 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 131005 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 25 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 131030 # number of demand (read+write) misses
|
||||
|
|
@ -374,25 +374,25 @@ system.l2c.demand_mshr_misses 0 # nu
|
|||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.occ_%::0 0.076956 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.477052 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5043.356614 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31264.101168 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 843438 # number of overall (read+write) accesses
|
||||
system.l2c.occ_%::0 0.076949 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.477056 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5042.918302 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31264.310783 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 843462 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 6142 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 849580 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 849604 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits::0 712433 # number of overall hits
|
||||
system.l2c.overall_hits::0 712457 # number of overall hits
|
||||
system.l2c.overall_hits::1 6117 # number of overall hits
|
||||
system.l2c.overall_hits::total 718550 # number of overall hits
|
||||
system.l2c.overall_hits::total 718574 # number of overall hits
|
||||
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.155323 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::0 0.155318 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.004070 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.159393 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.159389 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 131005 # number of overall misses
|
||||
system.l2c.overall_misses::1 25 # number of overall misses
|
||||
system.l2c.overall_misses::total 131030 # number of overall misses
|
||||
|
|
@ -407,8 +407,8 @@ system.l2c.overall_mshr_uncacheable_misses 0 #
|
|||
system.l2c.replacements 97025 # number of replacements
|
||||
system.l2c.sampled_refs 129753 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 36307.457782 # Cycle average of tags in use
|
||||
system.l2c.total_refs 876005 # Total number of references to valid blocks.
|
||||
system.l2c.tagsinuse 36307.229085 # Cycle average of tags in use
|
||||
system.l2c.total_refs 875359 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 90930 # number of writebacks
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -9,7 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
|
||||
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- root=/dev/mtdblock0
|
||||
init_param=0
|
||||
kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
load_addr_mask=268435455
|
||||
|
|
@ -186,7 +186,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma
|
||||
port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -292,7 +292,7 @@ port=system.membus.port[2]
|
|||
|
||||
[system.realview]
|
||||
type=RealView
|
||||
children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
children=aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
|
||||
intrctrl=system.intrctrl
|
||||
system=system
|
||||
|
||||
|
|
@ -304,23 +304,63 @@ pio_addr=268451840
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[20]
|
||||
pio=system.iobus.port[21]
|
||||
|
||||
[system.realview.cf0_fake]
|
||||
type=IsaFake
|
||||
pio_addr=402653184
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
BAR0=402653184
|
||||
BAR0LegacyIO=true
|
||||
BAR0Size=16
|
||||
BAR1=402653440
|
||||
BAR1LegacyIO=true
|
||||
BAR1Size=1
|
||||
BAR2=1
|
||||
BAR2LegacyIO=false
|
||||
BAR2Size=8
|
||||
BAR3=1
|
||||
BAR3LegacyIO=false
|
||||
BAR3Size=4
|
||||
BAR4=1
|
||||
BAR4LegacyIO=false
|
||||
BAR4Size=16
|
||||
BAR5=1
|
||||
BAR5LegacyIO=false
|
||||
BAR5Size=0
|
||||
BIST=0
|
||||
CacheLineSize=0
|
||||
CardbusCIS=0
|
||||
ClassCode=1
|
||||
Command=1
|
||||
DeviceID=28945
|
||||
ExpansionROM=0
|
||||
HeaderType=0
|
||||
InterruptLine=31
|
||||
InterruptPin=1
|
||||
LatencyTimer=0
|
||||
MaximumLatency=0
|
||||
MinimumGrant=0
|
||||
ProgIF=133
|
||||
Revision=0
|
||||
Status=640
|
||||
SubClassCode=1
|
||||
SubsystemID=0
|
||||
SubsystemVendorID=0
|
||||
VendorID=32902
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
disks=
|
||||
io_shift=1
|
||||
max_backoff_delay=10000000
|
||||
min_backoff_delay=4000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=1000
|
||||
pio_size=4095
|
||||
platform=system.realview
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[24]
|
||||
config=system.iobus.port[26]
|
||||
dma=system.iobus.port[27]
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
|
|
@ -335,7 +375,7 @@ pio_latency=10000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.port[26]
|
||||
dma=system.iobus.port[28]
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
|
|
@ -346,7 +386,7 @@ pio_addr=268632064
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[8]
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -362,7 +402,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.port[24]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
|
|
@ -383,7 +423,7 @@ pio_addr=268513280
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.port[16]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -393,7 +433,7 @@ pio_addr=268517376
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.port[17]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -403,7 +443,7 @@ pio_addr=268521472
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.port[18]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
|
|
@ -457,7 +497,7 @@ pio_addr=268455936
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[21]
|
||||
pio=system.iobus.port[22]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
|
|
@ -476,7 +516,7 @@ pio_addr=268529664
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[22]
|
||||
pio=system.iobus.port[23]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -486,7 +526,7 @@ pio_addr=268492800
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[19]
|
||||
pio=system.iobus.port[20]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -496,7 +536,7 @@ pio_addr=269357056
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -506,7 +546,7 @@ pio_addr=268439552
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.port[14]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -516,7 +556,7 @@ pio_addr=268488704
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[18]
|
||||
pio=system.iobus.port[19]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
|
|
@ -567,7 +607,7 @@ pio_addr=268476416
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.port[10]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -577,7 +617,7 @@ pio_addr=268480512
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.port[11]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -587,7 +627,7 @@ pio_addr=268484608
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -597,7 +637,7 @@ pio_addr=268500992
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 31 2011 10:39:48
|
||||
M5 started Mar 31 2011 10:41:48
|
||||
M5 compiled Apr 4 2011 11:17:23
|
||||
M5 started Apr 4 2011 11:17:27
|
||||
M5 executing on u200439-lin.austin.arm.com
|
||||
command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 114396880000 because m5_exit instruction encountered
|
||||
Exiting @ tick 114405702000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,252 +1,252 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 978936 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 377208 # Number of bytes of host memory used
|
||||
host_seconds 52.33 # Real time elapsed on the host
|
||||
host_tick_rate 2185988851 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 936835 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 382000 # Number of bytes of host memory used
|
||||
host_seconds 54.69 # Real time elapsed on the host
|
||||
host_tick_rate 2092010024 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 51229325 # Number of instructions simulated
|
||||
sim_seconds 0.114397 # Number of seconds simulated
|
||||
sim_ticks 114396880000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 100300 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 100300 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14571.455939 # average LoadLockedReq miss latency
|
||||
sim_insts 51232482 # Number of instructions simulated
|
||||
sim_seconds 0.114406 # Number of seconds simulated
|
||||
sim_ticks 114405702000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses::0 100305 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 100305 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14522.379495 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11571.455939 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95080 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95080 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 76063000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052044 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5220 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5220 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60403000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052044 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11522.379495 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits::0 95077 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 95077 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 75923000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052121 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses::0 5228 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 5228 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60239000 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052121 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 5220 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses::0 7828326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7828326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 15676.806243 # average ReadReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 5228 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses::0 7829265 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 7829265 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::0 15673.279330 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12676.464295 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12672.933246 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_hits::0 7589986 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7589986 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3736410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030446 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 238340 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 238340 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3021308500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030446 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_hits::0 7590884 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7590884 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3736212000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.030447 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses::0 238381 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 238381 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3020986500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030447 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 238340 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191118000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 100299 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 100299 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits::0 100299 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 100299 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses::0 6674054 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6674054 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 40732.768985 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_mshr_misses 238381 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191861000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.StoreCondReq_accesses::0 100304 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 100304 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits::0 100304 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 100304 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses::0 6674712 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6674712 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::0 40727.602969 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37732.519239 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37727.353242 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_hits::0 6501879 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6501879 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7013164500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025798 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172175 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172175 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 6496596500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025798 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_hits::0 6502524 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6502524 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7012804500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses::0 172188 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 172188 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 6496197500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 172175 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927308500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_misses 172188 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927430500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 34.522937 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 34.521241 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses::0 14502380 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::0 14503977 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 14502380 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 26185.582744 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::total 14503977 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 26180.779601 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23185.279466 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits::0 14091865 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits::0 14093408 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 14091865 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10749574500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_hits::total 14093408 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 10749016500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate::0 0.028307 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses::0 410515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::0 410569 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 410515 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 410569 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9517905000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9517184000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate::0 0.028307 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 410515 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 410569 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_%::0 0.994514 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::0 509.191175 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14502380 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.occ_blocks::0 509.191392 # Average occupied blocks per context
|
||||
system.cpu.dcache.overall_accesses::0 14503977 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 14502380 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 26185.582744 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses::total 14503977 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency::0 26180.779601 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23185.279466 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23180.473928 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits::0 14091865 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::0 14093408 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 14091865 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10749574500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_hits::total 14093408 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 10749016500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate::0 0.028307 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses::0 410515 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::0 410569 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 410515 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 410569 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9517905000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9517184000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate::0 0.028307 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 410515 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 39118426500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_misses 410569 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 39119291500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 413389 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 413901 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 413454 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 413966 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 509.191175 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14289078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 509.191392 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14290620 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 381928 # number of writebacks
|
||||
system.cpu.dtb.accesses 15530893 # DTB accesses
|
||||
system.cpu.dcache.writebacks 381963 # number of writebacks
|
||||
system.cpu.dtb.accesses 15532506 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 2229 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 2224 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 15525358 # DTB hits
|
||||
system.cpu.dtb.hits 15526972 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 5535 # DTB misses
|
||||
system.cpu.dtb.misses 5534 # DTB misses
|
||||
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 763 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 8743955 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8739401 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4554 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 6786938 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6785957 # DTB write hits
|
||||
system.cpu.dtb.write_misses 981 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses::0 41554370 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41554370 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14791.166028 # average ReadReq miss latency
|
||||
system.cpu.dtb.prefetch_faults 762 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 8744906 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 8740351 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4555 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 6787600 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 6786621 # DTB write hits
|
||||
system.cpu.dtb.write_misses 979 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses::0 41556337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 41556337 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::0 14789.924361 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.867728 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11788.627271 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.icache.ReadReq_hits::0 41120341 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41120341 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6419795000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.010445 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses::0 434029 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 434029 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 5117144500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010445 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_hits::0 41121903 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 41121903 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6425246000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.010454 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses::0 434434 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 434434 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 5121380500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010454 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 434029 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 434434 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 94.740999 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 94.656272 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses::0 41554370 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::0 41556337 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 41554370 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14791.166028 # average overall miss latency
|
||||
system.cpu.icache.demand_accesses::total 41556337 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 14789.924361 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11789.867728 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits::0 41120341 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits::0 41121903 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 41120341 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6419795000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate::0 0.010445 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_hits::total 41121903 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6425246000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate::0 0.010454 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses::0 434029 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::0 434434 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 434029 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 434434 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 5117144500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.010445 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_latency 5121380500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate::0 0.010454 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 434029 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 434434 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_%::0 0.945960 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 484.331512 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41554370 # number of overall (read+write) accesses
|
||||
system.cpu.icache.occ_%::0 0.945963 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::0 484.333151 # Average occupied blocks per context
|
||||
system.cpu.icache.overall_accesses::0 41556337 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 41554370 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14791.166028 # average overall miss latency
|
||||
system.cpu.icache.overall_accesses::total 41556337 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency::0 14789.924361 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11789.867728 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11788.627271 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits::0 41120341 # number of overall hits
|
||||
system.cpu.icache.overall_hits::0 41121903 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 41120341 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6419795000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate::0 0.010445 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_hits::total 41121903 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6425246000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate::0 0.010454 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses::0 434029 # number of overall misses
|
||||
system.cpu.icache.overall_misses::0 434434 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 434029 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 434434 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 5117144500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.010445 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_latency 5121380500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate::0 0.010454 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 434029 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 434434 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 433517 # number of replacements
|
||||
system.cpu.icache.sampled_refs 434029 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 433922 # number of replacements
|
||||
system.cpu.icache.sampled_refs 434434 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 484.331512 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41120341 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 14252346000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 33990 # number of writebacks
|
||||
system.cpu.icache.tagsinuse 484.333151 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 41121903 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 14253166000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 34027 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 41557189 # DTB accesses
|
||||
system.cpu.itb.accesses 41559156 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
|
||||
|
|
@ -254,9 +254,9 @@ system.cpu.itb.flush_tlb 2 # Nu
|
|||
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 41554370 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41557189 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41554370 # ITB inst hits
|
||||
system.cpu.itb.hits 41556337 # DTB hits
|
||||
system.cpu.itb.inst_accesses 41559156 # ITB inst accesses
|
||||
system.cpu.itb.inst_hits 41556337 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 2819 # ITB inst misses
|
||||
system.cpu.itb.misses 2819 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
|
|
@ -270,25 +270,25 @@ system.cpu.itb.write_misses 0 # DT
|
|||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 228793760 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 228811404 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 228793760 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 7027251 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6058 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
|
||||
system.cpu.num_busy_cycles 228811404 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 7027409 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6059 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 4227 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 1109649 # number of times a function call or return occured
|
||||
system.cpu.num_func_calls 1109850 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 51229325 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 42499970 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 42499970 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 139350355 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 34546681 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 9205633 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16289741 # number of memory refs
|
||||
system.cpu.num_store_insts 7084108 # Number of store instructions
|
||||
system.cpu.num_insts 51232482 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 42503602 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 42503602 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 139360817 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 34549221 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 9206942 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16291727 # number of memory refs
|
||||
system.cpu.num_store_insts 7084785 # Number of store instructions
|
||||
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
||||
|
|
@ -356,140 +356,140 @@ system.iocache.tagsinuse 0 # Cy
|
|||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.writebacks 0 # number of writebacks
|
||||
system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 170357 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 170357 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_hits::0 62528 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 62528 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_latency 5606276000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_rate::0 0.632925 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses::0 107813 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 107813 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 4312520000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.632925 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_hits::0 62554 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 62554 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_miss_latency 5605756000 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_rate::0 0.632806 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_misses::0 107803 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 107803 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_mshr_miss_latency 4312120000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_rate::0 0.632806 # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_mshr_misses 107813 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses::0 675455 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 5724 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 681179 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52080.460087 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 33716517.857143 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 33768598.317230 # average ReadReq miss latency
|
||||
system.l2c.ReadExReq_mshr_misses 107803 # number of ReadExReq MSHR misses
|
||||
system.l2c.ReadReq_accesses::0 675906 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 5729 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 681635 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_avg_miss_latency::0 52083.462261 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::1 32503672.413793 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_miss_latency::total 32555755.876054 # average ReadReq miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_hits::0 657328 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 5696 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 663024 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 944062500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate::0 0.026837 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.004892 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.031728 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 18127 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 28 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 18155 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 726200000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.026878 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 3.171733 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 3.198611 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 18155 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 29199871000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses::0 1834 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1834 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 486.784141 # average UpgradeReq miss latency
|
||||
system.l2c.ReadReq_hits::0 657808 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 5700 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 663508 # number of ReadReq hits
|
||||
system.l2c.ReadReq_miss_latency 942606500 # number of ReadReq miss cycles
|
||||
system.l2c.ReadReq_miss_rate::0 0.026776 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.005062 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.031838 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_misses::0 18098 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 29 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 18127 # number of ReadReq misses
|
||||
system.l2c.ReadReq_mshr_miss_latency 725080000 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::0 0.026819 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::1 3.164078 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::total 3.190896 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_misses 18127 # number of ReadReq MSHR misses
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency 29200537000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.UpgradeReq_accesses::0 1831 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_avg_miss_latency::0 487.589630 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.990185 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 1816 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1816 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 72640000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990185 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.990169 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_misses::0 1813 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_mshr_miss_latency 72520000 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990169 # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_mshr_misses 1816 # number of UpgradeReq MSHR misses
|
||||
system.l2c.UpgradeReq_mshr_misses 1813 # number of UpgradeReq MSHR misses
|
||||
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 740804000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses::0 415918 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 415918 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 415918 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 415918 # number of Writeback hits
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency 740916000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.Writeback_accesses::0 415990 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 415990 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_hits::0 415990 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 415990 # number of Writeback hits
|
||||
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.avg_refs 7.061430 # Average number of references to valid blocks.
|
||||
system.l2c.avg_refs 7.063302 # Average number of references to valid blocks.
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.demand_accesses::0 845796 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 5724 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 851520 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 52011.580912 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 233940660.714286 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 233992672.295197 # average overall miss latency
|
||||
system.l2c.demand_accesses::0 846263 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 5729 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 851992 # number of demand (read+write) accesses
|
||||
system.l2c.demand_avg_miss_latency::0 52011.997522 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 225805603.448276 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 225857615.445798 # average overall miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.l2c.demand_hits::0 719856 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 5696 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 725552 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 6550338500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.148901 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.004892 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.153793 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 125940 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 28 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 125968 # number of demand (read+write) misses
|
||||
system.l2c.demand_hits::0 720362 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 5700 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 726062 # number of demand (read+write) hits
|
||||
system.l2c.demand_miss_latency 6548362500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_rate::0 0.148773 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.005062 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.153835 # miss rate for demand accesses
|
||||
system.l2c.demand_misses::0 125901 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 29 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 125930 # number of demand (read+write) misses
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.demand_mshr_miss_latency 5038720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate::0 0.148934 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 22.006988 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 22.155922 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 125968 # number of demand (read+write) MSHR misses
|
||||
system.l2c.demand_mshr_miss_latency 5037200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_rate::0 0.148807 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::1 21.981149 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_miss_rate::total 22.129956 # mshr miss rate for demand accesses
|
||||
system.l2c.demand_mshr_misses 125930 # number of demand (read+write) MSHR misses
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.occ_%::0 0.081501 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.478004 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5341.251518 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31326.461137 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 845796 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 5724 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 851520 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 52011.580912 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 233940660.714286 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 233992672.295197 # average overall miss latency
|
||||
system.l2c.occ_%::0 0.081395 # Average percentage of cache occupancy
|
||||
system.l2c.occ_%::1 0.478089 # Average percentage of cache occupancy
|
||||
system.l2c.occ_blocks::0 5334.310202 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 31332.032709 # Average occupied blocks per context
|
||||
system.l2c.overall_accesses::0 846263 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 5729 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 851992 # number of overall (read+write) accesses
|
||||
system.l2c.overall_avg_miss_latency::0 52011.997522 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::1 225805603.448276 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 225857615.445798 # average overall miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
||||
system.l2c.overall_hits::0 719856 # number of overall hits
|
||||
system.l2c.overall_hits::1 5696 # number of overall hits
|
||||
system.l2c.overall_hits::total 725552 # number of overall hits
|
||||
system.l2c.overall_miss_latency 6550338500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.148901 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.004892 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.153793 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 125940 # number of overall misses
|
||||
system.l2c.overall_misses::1 28 # number of overall misses
|
||||
system.l2c.overall_misses::total 125968 # number of overall misses
|
||||
system.l2c.overall_hits::0 720362 # number of overall hits
|
||||
system.l2c.overall_hits::1 5700 # number of overall hits
|
||||
system.l2c.overall_hits::total 726062 # number of overall hits
|
||||
system.l2c.overall_miss_latency 6548362500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_rate::0 0.148773 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.005062 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.153835 # miss rate for overall accesses
|
||||
system.l2c.overall_misses::0 125901 # number of overall misses
|
||||
system.l2c.overall_misses::1 29 # number of overall misses
|
||||
system.l2c.overall_misses::total 125930 # number of overall misses
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.overall_mshr_miss_latency 5038720000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate::0 0.148934 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 22.006988 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 22.155922 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 125968 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 29940675000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_miss_latency 5037200000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_rate::0 0.148807 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::1 21.981149 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 22.129956 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_misses 125930 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_uncacheable_latency 29941453000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.l2c.replacements 93229 # number of replacements
|
||||
system.l2c.sampled_refs 124678 # Sample count of references to valid blocks.
|
||||
system.l2c.replacements 93179 # number of replacements
|
||||
system.l2c.sampled_refs 124640 # Sample count of references to valid blocks.
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.tagsinuse 36667.712655 # Cycle average of tags in use
|
||||
system.l2c.total_refs 880405 # Total number of references to valid blocks.
|
||||
system.l2c.tagsinuse 36666.342911 # Cycle average of tags in use
|
||||
system.l2c.total_refs 880370 # Total number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.writebacks 87341 # number of writebacks
|
||||
system.l2c.writebacks 87304 # number of writebacks
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Binary file not shown.
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Reference in a new issue