ruby: Regression updates for new ruby config locations
This commit is contained in:
Brad Beckmann
parent
b55e69ccac
commit
7aba8d7db0
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@ -42,6 +42,8 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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@ -43,6 +43,8 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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@ -41,6 +41,8 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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@ -41,6 +41,8 @@ config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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addToPath(config_root+'/configs/ruby/protocols')
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addToPath(config_root+'/configs/ruby/topologies')
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import Ruby
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@ -157,6 +157,7 @@ clock=1
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debug=system.ruby.debug
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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profiler=system.ruby.profiler
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random_seed=1234
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randomization=false
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@ -174,7 +175,7 @@ verbosity_string=none
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[system.ruby.network]
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type=SimpleNetwork
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children=topology
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adaptive_routing=true
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adaptive_routing=false
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buffer_size=0
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control_msg_size=8
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endpoint_bandwidth=10000
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@ -276,7 +277,7 @@ icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=1
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physMemPort=system.physmem.port[1]
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port=system.cpu1.test
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@ -328,7 +329,7 @@ icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=2
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physMemPort=system.physmem.port[2]
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port=system.cpu2.test
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@ -380,7 +381,7 @@ icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=3
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physMemPort=system.physmem.port[3]
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port=system.cpu3.test
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@ -432,7 +433,7 @@ icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=4
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physMemPort=system.physmem.port[4]
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port=system.cpu4.test
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@ -484,7 +485,7 @@ icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=5
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physMemPort=system.physmem.port[5]
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port=system.cpu5.test
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@ -536,7 +537,7 @@ icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=6
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physMemPort=system.physmem.port[6]
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port=system.cpu6.test
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@ -588,7 +589,7 @@ icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
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max_outstanding_requests=16
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physmem=system.physmem
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using_ruby_tester=false
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version=0
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version=7
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physMemPort=system.physmem.port[7]
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port=system.cpu7.test
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@ -659,7 +660,10 @@ version=0
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[system.ruby.network.topology.ext_links9.ext_node.directory]
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type=RubyDirectoryMemory
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map_levels=4
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numa_high_bit=0
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size=134217728
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use_map=false
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version=0
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[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
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File diff suppressed because it is too large
Load diff
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@ -1,74 +1,74 @@
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system.cpu1: completed 10000 read accesses @369045
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system.cpu3: completed 10000 read accesses @375134
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system.cpu0: completed 10000 read accesses @379333
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system.cpu4: completed 10000 read accesses @381010
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system.cpu2: completed 10000 read accesses @382842
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system.cpu6: completed 10000 read accesses @383698
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system.cpu7: completed 10000 read accesses @384995
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system.cpu5: completed 10000 read accesses @385374
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system.cpu1: completed 20000 read accesses @741171
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system.cpu4: completed 20000 read accesses @750155
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system.cpu0: completed 20000 read accesses @752751
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system.cpu3: completed 20000 read accesses @756635
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system.cpu2: completed 20000 read accesses @759675
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system.cpu6: completed 20000 read accesses @761608
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system.cpu7: completed 20000 read accesses @768000
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system.cpu5: completed 20000 read accesses @768371
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system.cpu1: completed 30000 read accesses @1110388
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system.cpu4: completed 30000 read accesses @1123036
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system.cpu0: completed 30000 read accesses @1128110
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system.cpu2: completed 30000 read accesses @1137867
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system.cpu3: completed 30000 read accesses @1139088
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system.cpu6: completed 30000 read accesses @1142556
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system.cpu7: completed 30000 read accesses @1150467
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system.cpu5: completed 30000 read accesses @1151106
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system.cpu1: completed 40000 read accesses @1490114
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system.cpu0: completed 40000 read accesses @1493155
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system.cpu4: completed 40000 read accesses @1497187
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system.cpu2: completed 40000 read accesses @1515309
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system.cpu3: completed 40000 read accesses @1515741
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system.cpu6: completed 40000 read accesses @1525379
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system.cpu5: completed 40000 read accesses @1530541
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system.cpu7: completed 40000 read accesses @1538741
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system.cpu1: completed 50000 read accesses @1860332
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system.cpu0: completed 50000 read accesses @1867591
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system.cpu4: completed 50000 read accesses @1873458
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system.cpu2: completed 50000 read accesses @1899397
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system.cpu3: completed 50000 read accesses @1900017
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system.cpu5: completed 50000 read accesses @1912488
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system.cpu6: completed 50000 read accesses @1915555
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system.cpu7: completed 50000 read accesses @1922782
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system.cpu1: completed 60000 read accesses @2238333
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system.cpu0: completed 60000 read accesses @2244218
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system.cpu4: completed 60000 read accesses @2255037
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system.cpu2: completed 60000 read accesses @2274576
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system.cpu3: completed 60000 read accesses @2274764
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system.cpu5: completed 60000 read accesses @2298934
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system.cpu6: completed 60000 read accesses @2309075
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system.cpu7: completed 60000 read accesses @2323339
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system.cpu1: completed 70000 read accesses @2600904
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system.cpu0: completed 70000 read accesses @2622809
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system.cpu4: completed 70000 read accesses @2633148
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system.cpu2: completed 70000 read accesses @2650372
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system.cpu3: completed 70000 read accesses @2661632
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system.cpu5: completed 70000 read accesses @2678675
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system.cpu6: completed 70000 read accesses @2697088
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system.cpu7: completed 70000 read accesses @2711986
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system.cpu1: completed 80000 read accesses @2969240
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system.cpu0: completed 80000 read accesses @2991652
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system.cpu4: completed 80000 read accesses @3015607
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system.cpu2: completed 80000 read accesses @3020165
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system.cpu3: completed 80000 read accesses @3040093
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system.cpu5: completed 80000 read accesses @3054431
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system.cpu6: completed 80000 read accesses @3090505
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system.cpu7: completed 80000 read accesses @3105496
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system.cpu1: completed 90000 read accesses @3338659
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system.cpu0: completed 90000 read accesses @3373927
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system.cpu2: completed 90000 read accesses @3397759
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system.cpu4: completed 90000 read accesses @3398901
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system.cpu3: completed 90000 read accesses @3408631
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system.cpu5: completed 90000 read accesses @3430133
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system.cpu6: completed 90000 read accesses @3467538
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system.cpu7: completed 90000 read accesses @3493036
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system.cpu1: completed 100000 read accesses @3708588
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system.cpu7: completed 10000 read accesses @373359
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system.cpu1: completed 10000 read accesses @375374
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system.cpu0: completed 10000 read accesses @376725
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system.cpu2: completed 10000 read accesses @380778
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system.cpu5: completed 10000 read accesses @382682
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system.cpu3: completed 10000 read accesses @383505
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system.cpu4: completed 10000 read accesses @386561
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system.cpu6: completed 10000 read accesses @389125
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system.cpu1: completed 20000 read accesses @745885
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system.cpu0: completed 20000 read accesses @748353
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system.cpu2: completed 20000 read accesses @753861
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system.cpu7: completed 20000 read accesses @758042
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system.cpu5: completed 20000 read accesses @759129
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system.cpu3: completed 20000 read accesses @764814
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system.cpu4: completed 20000 read accesses @768939
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system.cpu6: completed 20000 read accesses @774936
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system.cpu1: completed 30000 read accesses @1121924
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system.cpu2: completed 30000 read accesses @1124427
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system.cpu0: completed 30000 read accesses @1125253
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system.cpu7: completed 30000 read accesses @1139134
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system.cpu4: completed 30000 read accesses @1139334
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system.cpu3: completed 30000 read accesses @1144574
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system.cpu5: completed 30000 read accesses @1145748
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system.cpu6: completed 30000 read accesses @1147208
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system.cpu0: completed 40000 read accesses @1492239
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system.cpu1: completed 40000 read accesses @1495604
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system.cpu2: completed 40000 read accesses @1499940
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system.cpu4: completed 40000 read accesses @1518641
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system.cpu7: completed 40000 read accesses @1518771
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system.cpu5: completed 40000 read accesses @1528667
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system.cpu6: completed 40000 read accesses @1530209
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system.cpu3: completed 40000 read accesses @1537371
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system.cpu0: completed 50000 read accesses @1865558
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system.cpu1: completed 50000 read accesses @1868280
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system.cpu2: completed 50000 read accesses @1884528
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system.cpu7: completed 50000 read accesses @1899621
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system.cpu4: completed 50000 read accesses @1903698
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system.cpu5: completed 50000 read accesses @1909143
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system.cpu3: completed 50000 read accesses @1910503
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system.cpu6: completed 50000 read accesses @1915590
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system.cpu0: completed 60000 read accesses @2235441
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system.cpu1: completed 60000 read accesses @2240292
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system.cpu2: completed 60000 read accesses @2270206
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system.cpu4: completed 60000 read accesses @2278819
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system.cpu7: completed 60000 read accesses @2284397
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system.cpu5: completed 60000 read accesses @2288761
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system.cpu3: completed 60000 read accesses @2289377
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system.cpu6: completed 60000 read accesses @2312599
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system.cpu0: completed 70000 read accesses @2605926
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system.cpu1: completed 70000 read accesses @2606409
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system.cpu4: completed 70000 read accesses @2648937
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system.cpu2: completed 70000 read accesses @2655948
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system.cpu5: completed 70000 read accesses @2662046
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system.cpu3: completed 70000 read accesses @2664803
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system.cpu7: completed 70000 read accesses @2675843
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system.cpu6: completed 70000 read accesses @2704307
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system.cpu1: completed 80000 read accesses @2972591
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system.cpu0: completed 80000 read accesses @2986258
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system.cpu3: completed 80000 read accesses @3027695
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system.cpu4: completed 80000 read accesses @3034526
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system.cpu2: completed 80000 read accesses @3036101
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system.cpu5: completed 80000 read accesses @3049670
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system.cpu7: completed 80000 read accesses @3053840
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system.cpu6: completed 80000 read accesses @3088364
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system.cpu1: completed 90000 read accesses @3348204
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system.cpu0: completed 90000 read accesses @3355393
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system.cpu3: completed 90000 read accesses @3393344
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system.cpu2: completed 90000 read accesses @3410223
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system.cpu4: completed 90000 read accesses @3417605
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system.cpu5: completed 90000 read accesses @3432894
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system.cpu7: completed 90000 read accesses @3437480
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system.cpu6: completed 90000 read accesses @3470461
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system.cpu1: completed 100000 read accesses @3719757
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hack: be nice to actually delete the event here
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@ -5,11 +5,11 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jan 28 2010 13:54:58
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M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
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M5 started Jan 28 2010 13:57:45
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M5 executing on svvint03
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M5 compiled Mar 18 2010 14:36:48
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M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
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M5 started Mar 18 2010 15:36:46
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M5 executing on cabr0210
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command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 3708588 because maximum number of loads reached
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Exiting @ tick 3719757 because maximum number of loads reached
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@ -1,34 +1,34 @@
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---------- Begin Simulation Statistics ----------
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host_mem_usage 344972 # Number of bytes of host memory used
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host_seconds 51.38 # Real time elapsed on the host
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host_tick_rate 72178 # Simulator tick rate (ticks/s)
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host_mem_usage 340040 # Number of bytes of host memory used
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host_seconds 42.78 # Real time elapsed on the host
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host_tick_rate 86943 # Simulator tick rate (ticks/s)
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_seconds 0.003709 # Number of seconds simulated
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sim_ticks 3708588 # Number of ticks simulated
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sim_seconds 0.003720 # Number of seconds simulated
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sim_ticks 3719757 # Number of ticks simulated
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system.cpu0.num_copies 0 # number of copy accesses completed
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system.cpu0.num_reads 98991 # number of read accesses completed
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system.cpu0.num_writes 53491 # number of write accesses completed
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system.cpu0.num_reads 99860 # number of read accesses completed
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system.cpu0.num_writes 53770 # number of write accesses completed
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system.cpu1.num_copies 0 # number of copy accesses completed
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system.cpu1.num_reads 100000 # number of read accesses completed
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system.cpu1.num_writes 53368 # number of write accesses completed
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system.cpu1.num_writes 53093 # number of write accesses completed
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system.cpu2.num_copies 0 # number of copy accesses completed
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system.cpu2.num_reads 98059 # number of read accesses completed
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system.cpu2.num_writes 52566 # number of write accesses completed
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system.cpu2.num_reads 98032 # number of read accesses completed
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system.cpu2.num_writes 52757 # number of write accesses completed
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system.cpu3.num_copies 0 # number of copy accesses completed
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system.cpu3.num_reads 97980 # number of read accesses completed
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system.cpu3.num_writes 52705 # number of write accesses completed
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system.cpu3.num_reads 98573 # number of read accesses completed
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system.cpu3.num_writes 52922 # number of write accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
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system.cpu4.num_reads 98000 # number of read accesses completed
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system.cpu4.num_writes 52774 # number of write accesses completed
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system.cpu4.num_reads 97812 # number of read accesses completed
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system.cpu4.num_writes 53065 # number of write accesses completed
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system.cpu5.num_copies 0 # number of copy accesses completed
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system.cpu5.num_reads 97409 # number of read accesses completed
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system.cpu5.num_writes 52453 # number of write accesses completed
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system.cpu5.num_reads 97538 # number of read accesses completed
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system.cpu5.num_writes 52364 # number of write accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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system.cpu6.num_reads 96358 # number of read accesses completed
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system.cpu6.num_writes 51488 # number of write accesses completed
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system.cpu6.num_reads 96539 # number of read accesses completed
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system.cpu6.num_writes 52064 # number of write accesses completed
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system.cpu7.num_copies 0 # number of copy accesses completed
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system.cpu7.num_reads 95731 # number of read accesses completed
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system.cpu7.num_writes 51690 # number of write accesses completed
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system.cpu7.num_reads 97318 # number of read accesses completed
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system.cpu7.num_writes 52275 # number of write accesses completed
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---------- End Simulation Statistics ----------
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@ -157,6 +157,7 @@ clock=1
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debug=system.ruby.debug
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mem_size=134217728
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network=system.ruby.network
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no_mem_vec=false
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profiler=system.ruby.profiler
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random_seed=1234
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randomization=false
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@ -174,7 +175,7 @@ verbosity_string=none
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[system.ruby.network]
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type=SimpleNetwork
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children=topology
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adaptive_routing=true
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adaptive_routing=false
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buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -272,7 +273,7 @@ icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
|
|
@ -322,7 +323,7 @@ icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
|
|
@ -372,7 +373,7 @@ icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
|
|
@ -422,7 +423,7 @@ icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
|
|
@ -472,7 +473,7 @@ icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
|
|
@ -522,7 +523,7 @@ icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
|
|
@ -572,7 +573,7 @@ icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
|
|
@ -641,7 +642,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu0: completed 10000 read accesses @325610
|
||||
system.cpu1: completed 10000 read accesses @328426
|
||||
system.cpu2: completed 10000 read accesses @330443
|
||||
system.cpu5: completed 10000 read accesses @338385
|
||||
system.cpu7: completed 10000 read accesses @344032
|
||||
system.cpu3: completed 10000 read accesses @350837
|
||||
system.cpu4: completed 10000 read accesses @358597
|
||||
system.cpu6: completed 10000 read accesses @362921
|
||||
system.cpu0: completed 20000 read accesses @651713
|
||||
system.cpu1: completed 20000 read accesses @654395
|
||||
system.cpu5: completed 20000 read accesses @675104
|
||||
system.cpu7: completed 20000 read accesses @678502
|
||||
system.cpu2: completed 20000 read accesses @686227
|
||||
system.cpu3: completed 20000 read accesses @688125
|
||||
system.cpu4: completed 20000 read accesses @701024
|
||||
system.cpu6: completed 20000 read accesses @714978
|
||||
system.cpu1: completed 30000 read accesses @992058
|
||||
system.cpu0: completed 30000 read accesses @996204
|
||||
system.cpu2: completed 30000 read accesses @1012415
|
||||
system.cpu5: completed 30000 read accesses @1018935
|
||||
system.cpu3: completed 30000 read accesses @1028572
|
||||
system.cpu7: completed 30000 read accesses @1034750
|
||||
system.cpu4: completed 30000 read accesses @1035581
|
||||
system.cpu6: completed 30000 read accesses @1057109
|
||||
system.cpu1: completed 40000 read accesses @1328565
|
||||
system.cpu0: completed 40000 read accesses @1342349
|
||||
system.cpu5: completed 40000 read accesses @1358651
|
||||
system.cpu2: completed 40000 read accesses @1362244
|
||||
system.cpu3: completed 40000 read accesses @1365572
|
||||
system.cpu4: completed 40000 read accesses @1376682
|
||||
system.cpu7: completed 40000 read accesses @1377955
|
||||
system.cpu6: completed 40000 read accesses @1385954
|
||||
system.cpu1: completed 50000 read accesses @1651444
|
||||
system.cpu0: completed 50000 read accesses @1681780
|
||||
system.cpu2: completed 50000 read accesses @1697366
|
||||
system.cpu5: completed 50000 read accesses @1705801
|
||||
system.cpu3: completed 50000 read accesses @1712915
|
||||
system.cpu4: completed 50000 read accesses @1717462
|
||||
system.cpu7: completed 50000 read accesses @1728540
|
||||
system.cpu6: completed 50000 read accesses @1732862
|
||||
system.cpu1: completed 60000 read accesses @2001756
|
||||
system.cpu0: completed 60000 read accesses @2007806
|
||||
system.cpu4: completed 60000 read accesses @2036786
|
||||
system.cpu3: completed 60000 read accesses @2041761
|
||||
system.cpu2: completed 60000 read accesses @2049223
|
||||
system.cpu5: completed 60000 read accesses @2054495
|
||||
system.cpu6: completed 60000 read accesses @2073699
|
||||
system.cpu7: completed 60000 read accesses @2074170
|
||||
system.cpu1: completed 70000 read accesses @2344028
|
||||
system.cpu0: completed 70000 read accesses @2351090
|
||||
system.cpu4: completed 70000 read accesses @2367786
|
||||
system.cpu5: completed 70000 read accesses @2386819
|
||||
system.cpu2: completed 70000 read accesses @2390297
|
||||
system.cpu3: completed 70000 read accesses @2399080
|
||||
system.cpu6: completed 70000 read accesses @2409182
|
||||
system.cpu7: completed 70000 read accesses @2411377
|
||||
system.cpu1: completed 80000 read accesses @2685330
|
||||
system.cpu0: completed 80000 read accesses @2689745
|
||||
system.cpu4: completed 80000 read accesses @2704099
|
||||
system.cpu2: completed 80000 read accesses @2728887
|
||||
system.cpu5: completed 80000 read accesses @2735646
|
||||
system.cpu3: completed 80000 read accesses @2736625
|
||||
system.cpu7: completed 80000 read accesses @2740886
|
||||
system.cpu6: completed 80000 read accesses @2752448
|
||||
system.cpu1: completed 90000 read accesses @3013853
|
||||
system.cpu0: completed 90000 read accesses @3029349
|
||||
system.cpu4: completed 90000 read accesses @3054103
|
||||
system.cpu2: completed 90000 read accesses @3064472
|
||||
system.cpu3: completed 90000 read accesses @3075826
|
||||
system.cpu7: completed 90000 read accesses @3076830
|
||||
system.cpu5: completed 90000 read accesses @3082514
|
||||
system.cpu6: completed 90000 read accesses @3098674
|
||||
system.cpu1: completed 100000 read accesses @3340930
|
||||
system.cpu5: completed 10000 read accesses @333700
|
||||
system.cpu3: completed 10000 read accesses @335770
|
||||
system.cpu4: completed 10000 read accesses @336327
|
||||
system.cpu1: completed 10000 read accesses @339698
|
||||
system.cpu2: completed 10000 read accesses @344150
|
||||
system.cpu6: completed 10000 read accesses @345138
|
||||
system.cpu7: completed 10000 read accesses @345167
|
||||
system.cpu0: completed 10000 read accesses @349190
|
||||
system.cpu6: completed 20000 read accesses @673266
|
||||
system.cpu5: completed 20000 read accesses @676289
|
||||
system.cpu7: completed 20000 read accesses @679722
|
||||
system.cpu3: completed 20000 read accesses @681408
|
||||
system.cpu4: completed 20000 read accesses @681933
|
||||
system.cpu2: completed 20000 read accesses @683973
|
||||
system.cpu0: completed 20000 read accesses @686720
|
||||
system.cpu1: completed 20000 read accesses @692941
|
||||
system.cpu4: completed 30000 read accesses @1007235
|
||||
system.cpu6: completed 30000 read accesses @1011621
|
||||
system.cpu7: completed 30000 read accesses @1013787
|
||||
system.cpu3: completed 30000 read accesses @1022376
|
||||
system.cpu1: completed 30000 read accesses @1026321
|
||||
system.cpu0: completed 30000 read accesses @1027922
|
||||
system.cpu5: completed 30000 read accesses @1030676
|
||||
system.cpu2: completed 30000 read accesses @1030823
|
||||
system.cpu6: completed 40000 read accesses @1348685
|
||||
system.cpu3: completed 40000 read accesses @1353011
|
||||
system.cpu4: completed 40000 read accesses @1356076
|
||||
system.cpu7: completed 40000 read accesses @1357286
|
||||
system.cpu1: completed 40000 read accesses @1359706
|
||||
system.cpu5: completed 40000 read accesses @1367254
|
||||
system.cpu2: completed 40000 read accesses @1373741
|
||||
system.cpu0: completed 40000 read accesses @1379957
|
||||
system.cpu4: completed 50000 read accesses @1688392
|
||||
system.cpu7: completed 50000 read accesses @1689568
|
||||
system.cpu6: completed 50000 read accesses @1689754
|
||||
system.cpu3: completed 50000 read accesses @1696699
|
||||
system.cpu1: completed 50000 read accesses @1706109
|
||||
system.cpu5: completed 50000 read accesses @1712886
|
||||
system.cpu2: completed 50000 read accesses @1716788
|
||||
system.cpu0: completed 50000 read accesses @1719320
|
||||
system.cpu7: completed 60000 read accesses @2028845
|
||||
system.cpu6: completed 60000 read accesses @2029028
|
||||
system.cpu3: completed 60000 read accesses @2030491
|
||||
system.cpu1: completed 60000 read accesses @2034867
|
||||
system.cpu4: completed 60000 read accesses @2042771
|
||||
system.cpu5: completed 60000 read accesses @2052491
|
||||
system.cpu2: completed 60000 read accesses @2054050
|
||||
system.cpu0: completed 60000 read accesses @2059964
|
||||
system.cpu1: completed 70000 read accesses @2366182
|
||||
system.cpu3: completed 70000 read accesses @2371740
|
||||
system.cpu6: completed 70000 read accesses @2378180
|
||||
system.cpu7: completed 70000 read accesses @2384422
|
||||
system.cpu4: completed 70000 read accesses @2385664
|
||||
system.cpu5: completed 70000 read accesses @2386969
|
||||
system.cpu0: completed 70000 read accesses @2391802
|
||||
system.cpu2: completed 70000 read accesses @2394315
|
||||
system.cpu1: completed 80000 read accesses @2697050
|
||||
system.cpu3: completed 80000 read accesses @2711777
|
||||
system.cpu5: completed 80000 read accesses @2712887
|
||||
system.cpu6: completed 80000 read accesses @2716967
|
||||
system.cpu7: completed 80000 read accesses @2729293
|
||||
system.cpu4: completed 80000 read accesses @2732109
|
||||
system.cpu0: completed 80000 read accesses @2735916
|
||||
system.cpu2: completed 80000 read accesses @2746698
|
||||
system.cpu5: completed 90000 read accesses @3042585
|
||||
system.cpu1: completed 90000 read accesses @3050146
|
||||
system.cpu4: completed 90000 read accesses @3051611
|
||||
system.cpu6: completed 90000 read accesses @3054450
|
||||
system.cpu3: completed 90000 read accesses @3060838
|
||||
system.cpu7: completed 90000 read accesses @3073385
|
||||
system.cpu0: completed 90000 read accesses @3084850
|
||||
system.cpu2: completed 90000 read accesses @3085570
|
||||
system.cpu6: completed 100000 read accesses @3383480
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 14:49:51
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:08:16
|
||||
M5 executing on svvint05
|
||||
M5 compiled Mar 18 2010 14:39:50
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:38:22
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3340930 because maximum number of loads reached
|
||||
Exiting @ tick 3383480 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 345104 # Number of bytes of host memory used
|
||||
host_seconds 37.10 # Real time elapsed on the host
|
||||
host_tick_rate 90051 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 340176 # Number of bytes of host memory used
|
||||
host_seconds 30.43 # Real time elapsed on the host
|
||||
host_tick_rate 111176 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003341 # Number of seconds simulated
|
||||
sim_ticks 3340930 # Number of ticks simulated
|
||||
sim_seconds 0.003383 # Number of seconds simulated
|
||||
sim_ticks 3383480 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99074 # number of read accesses completed
|
||||
system.cpu0.num_writes 53010 # number of write accesses completed
|
||||
system.cpu0.num_reads 99022 # number of read accesses completed
|
||||
system.cpu0.num_writes 53581 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53538 # number of write accesses completed
|
||||
system.cpu1.num_reads 99831 # number of read accesses completed
|
||||
system.cpu1.num_writes 53533 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 98064 # number of read accesses completed
|
||||
system.cpu2.num_writes 52759 # number of write accesses completed
|
||||
system.cpu2.num_reads 98646 # number of read accesses completed
|
||||
system.cpu2.num_writes 53693 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97746 # number of read accesses completed
|
||||
system.cpu3.num_writes 52714 # number of write accesses completed
|
||||
system.cpu3.num_reads 99440 # number of read accesses completed
|
||||
system.cpu3.num_writes 53404 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98341 # number of read accesses completed
|
||||
system.cpu4.num_writes 53558 # number of write accesses completed
|
||||
system.cpu4.num_reads 99794 # number of read accesses completed
|
||||
system.cpu4.num_writes 53954 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97456 # number of read accesses completed
|
||||
system.cpu5.num_writes 52785 # number of write accesses completed
|
||||
system.cpu5.num_reads 99737 # number of read accesses completed
|
||||
system.cpu5.num_writes 53481 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 97173 # number of read accesses completed
|
||||
system.cpu6.num_writes 52207 # number of write accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53654 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 97832 # number of read accesses completed
|
||||
system.cpu7.num_writes 53099 # number of write accesses completed
|
||||
system.cpu7.num_reads 98991 # number of read accesses completed
|
||||
system.cpu7.num_writes 53546 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -157,6 +157,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
|
@ -174,7 +175,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -282,7 +283,7 @@ icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
|
|
@ -337,7 +338,7 @@ icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
|
|
@ -392,7 +393,7 @@ icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
|
|
@ -447,7 +448,7 @@ icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
|
|
@ -502,7 +503,7 @@ icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
|
|
@ -557,7 +558,7 @@ icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
|
|
@ -612,7 +613,7 @@ icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
|
|
@ -686,7 +687,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links9.ext_node.memBuffer]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu7: completed 10000 read accesses @318017
|
||||
system.cpu2: completed 10000 read accesses @320606
|
||||
system.cpu4: completed 10000 read accesses @323032
|
||||
system.cpu3: completed 10000 read accesses @325540
|
||||
system.cpu1: completed 10000 read accesses @326237
|
||||
system.cpu0: completed 10000 read accesses @334891
|
||||
system.cpu6: completed 10000 read accesses @335973
|
||||
system.cpu5: completed 10000 read accesses @338167
|
||||
system.cpu7: completed 20000 read accesses @641721
|
||||
system.cpu4: completed 20000 read accesses @650207
|
||||
system.cpu2: completed 20000 read accesses @650997
|
||||
system.cpu3: completed 20000 read accesses @655547
|
||||
system.cpu1: completed 20000 read accesses @658571
|
||||
system.cpu6: completed 20000 read accesses @659101
|
||||
system.cpu0: completed 20000 read accesses @665545
|
||||
system.cpu5: completed 20000 read accesses @668660
|
||||
system.cpu7: completed 30000 read accesses @967051
|
||||
system.cpu2: completed 30000 read accesses @980241
|
||||
system.cpu4: completed 30000 read accesses @981752
|
||||
system.cpu6: completed 30000 read accesses @982555
|
||||
system.cpu3: completed 30000 read accesses @983533
|
||||
system.cpu1: completed 30000 read accesses @988722
|
||||
system.cpu0: completed 30000 read accesses @995306
|
||||
system.cpu5: completed 30000 read accesses @998193
|
||||
system.cpu7: completed 40000 read accesses @1292004
|
||||
system.cpu4: completed 40000 read accesses @1308492
|
||||
system.cpu6: completed 40000 read accesses @1308579
|
||||
system.cpu2: completed 40000 read accesses @1312752
|
||||
system.cpu3: completed 40000 read accesses @1315420
|
||||
system.cpu1: completed 40000 read accesses @1322630
|
||||
system.cpu0: completed 40000 read accesses @1325206
|
||||
system.cpu5: completed 40000 read accesses @1331673
|
||||
system.cpu7: completed 50000 read accesses @1612614
|
||||
system.cpu6: completed 50000 read accesses @1633357
|
||||
system.cpu4: completed 50000 read accesses @1639815
|
||||
system.cpu2: completed 50000 read accesses @1645007
|
||||
system.cpu3: completed 50000 read accesses @1648886
|
||||
system.cpu0: completed 50000 read accesses @1653577
|
||||
system.cpu1: completed 50000 read accesses @1654071
|
||||
system.cpu5: completed 50000 read accesses @1661892
|
||||
system.cpu7: completed 60000 read accesses @1934242
|
||||
system.cpu6: completed 60000 read accesses @1953245
|
||||
system.cpu4: completed 60000 read accesses @1969088
|
||||
system.cpu2: completed 60000 read accesses @1978395
|
||||
system.cpu3: completed 60000 read accesses @1980508
|
||||
system.cpu0: completed 60000 read accesses @1980832
|
||||
system.cpu1: completed 60000 read accesses @1989869
|
||||
system.cpu5: completed 60000 read accesses @2000681
|
||||
system.cpu7: completed 70000 read accesses @2258807
|
||||
system.cpu6: completed 70000 read accesses @2276271
|
||||
system.cpu4: completed 70000 read accesses @2301792
|
||||
system.cpu2: completed 70000 read accesses @2307314
|
||||
system.cpu3: completed 70000 read accesses @2311283
|
||||
system.cpu0: completed 70000 read accesses @2312940
|
||||
system.cpu1: completed 70000 read accesses @2317714
|
||||
system.cpu5: completed 70000 read accesses @2327977
|
||||
system.cpu7: completed 80000 read accesses @2583771
|
||||
system.cpu6: completed 80000 read accesses @2602700
|
||||
system.cpu4: completed 80000 read accesses @2632241
|
||||
system.cpu2: completed 80000 read accesses @2635301
|
||||
system.cpu3: completed 80000 read accesses @2641526
|
||||
system.cpu0: completed 80000 read accesses @2641647
|
||||
system.cpu1: completed 80000 read accesses @2649443
|
||||
system.cpu5: completed 80000 read accesses @2661743
|
||||
system.cpu7: completed 90000 read accesses @2907382
|
||||
system.cpu6: completed 90000 read accesses @2926398
|
||||
system.cpu4: completed 90000 read accesses @2962227
|
||||
system.cpu2: completed 90000 read accesses @2968253
|
||||
system.cpu3: completed 90000 read accesses @2971557
|
||||
system.cpu0: completed 90000 read accesses @2972136
|
||||
system.cpu1: completed 90000 read accesses @2977260
|
||||
system.cpu5: completed 90000 read accesses @2992697
|
||||
system.cpu7: completed 100000 read accesses @3231932
|
||||
system.cpu1: completed 10000 read accesses @320533
|
||||
system.cpu0: completed 10000 read accesses @324255
|
||||
system.cpu5: completed 10000 read accesses @329816
|
||||
system.cpu4: completed 10000 read accesses @330370
|
||||
system.cpu2: completed 10000 read accesses @330850
|
||||
system.cpu3: completed 10000 read accesses @330898
|
||||
system.cpu6: completed 10000 read accesses @330981
|
||||
system.cpu7: completed 10000 read accesses @332669
|
||||
system.cpu1: completed 20000 read accesses @645951
|
||||
system.cpu6: completed 20000 read accesses @654684
|
||||
system.cpu0: completed 20000 read accesses @655122
|
||||
system.cpu5: completed 20000 read accesses @655139
|
||||
system.cpu4: completed 20000 read accesses @658112
|
||||
system.cpu7: completed 20000 read accesses @659630
|
||||
system.cpu3: completed 20000 read accesses @662399
|
||||
system.cpu2: completed 20000 read accesses @662745
|
||||
system.cpu1: completed 30000 read accesses @971498
|
||||
system.cpu0: completed 30000 read accesses @979665
|
||||
system.cpu6: completed 30000 read accesses @980753
|
||||
system.cpu4: completed 30000 read accesses @986046
|
||||
system.cpu5: completed 30000 read accesses @986992
|
||||
system.cpu7: completed 30000 read accesses @990004
|
||||
system.cpu2: completed 30000 read accesses @992746
|
||||
system.cpu3: completed 30000 read accesses @994289
|
||||
system.cpu1: completed 40000 read accesses @1295713
|
||||
system.cpu0: completed 40000 read accesses @1304844
|
||||
system.cpu6: completed 40000 read accesses @1311609
|
||||
system.cpu4: completed 40000 read accesses @1313210
|
||||
system.cpu5: completed 40000 read accesses @1315669
|
||||
system.cpu7: completed 40000 read accesses @1321203
|
||||
system.cpu3: completed 40000 read accesses @1325768
|
||||
system.cpu2: completed 40000 read accesses @1327431
|
||||
system.cpu1: completed 50000 read accesses @1620139
|
||||
system.cpu0: completed 50000 read accesses @1624207
|
||||
system.cpu6: completed 50000 read accesses @1642053
|
||||
system.cpu5: completed 50000 read accesses @1643779
|
||||
system.cpu4: completed 50000 read accesses @1647677
|
||||
system.cpu7: completed 50000 read accesses @1653016
|
||||
system.cpu3: completed 50000 read accesses @1659224
|
||||
system.cpu2: completed 50000 read accesses @1659858
|
||||
system.cpu1: completed 60000 read accesses @1944324
|
||||
system.cpu0: completed 60000 read accesses @1947039
|
||||
system.cpu5: completed 60000 read accesses @1971722
|
||||
system.cpu6: completed 60000 read accesses @1971958
|
||||
system.cpu4: completed 60000 read accesses @1978467
|
||||
system.cpu3: completed 60000 read accesses @1984371
|
||||
system.cpu7: completed 60000 read accesses @1986116
|
||||
system.cpu2: completed 60000 read accesses @1990627
|
||||
system.cpu1: completed 70000 read accesses @2268077
|
||||
system.cpu0: completed 70000 read accesses @2271308
|
||||
system.cpu6: completed 70000 read accesses @2299743
|
||||
system.cpu5: completed 70000 read accesses @2302988
|
||||
system.cpu4: completed 70000 read accesses @2306754
|
||||
system.cpu3: completed 70000 read accesses @2313390
|
||||
system.cpu7: completed 70000 read accesses @2318502
|
||||
system.cpu2: completed 70000 read accesses @2323657
|
||||
system.cpu1: completed 80000 read accesses @2590310
|
||||
system.cpu0: completed 80000 read accesses @2594700
|
||||
system.cpu5: completed 80000 read accesses @2629321
|
||||
system.cpu6: completed 80000 read accesses @2631814
|
||||
system.cpu4: completed 80000 read accesses @2636634
|
||||
system.cpu7: completed 80000 read accesses @2643921
|
||||
system.cpu2: completed 80000 read accesses @2656705
|
||||
system.cpu3: completed 80000 read accesses @2656992
|
||||
system.cpu0: completed 90000 read accesses @2911654
|
||||
system.cpu1: completed 90000 read accesses @2922192
|
||||
system.cpu5: completed 90000 read accesses @2956637
|
||||
system.cpu4: completed 90000 read accesses @2959893
|
||||
system.cpu6: completed 90000 read accesses @2961119
|
||||
system.cpu7: completed 90000 read accesses @2975550
|
||||
system.cpu2: completed 90000 read accesses @2985342
|
||||
system.cpu3: completed 90000 read accesses @2990681
|
||||
system.cpu1: completed 100000 read accesses @3238178
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 15:54:34
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:55:47
|
||||
M5 executing on svvint04
|
||||
M5 compiled Mar 18 2010 14:58:42
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:39:30
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 3231932 because maximum number of loads reached
|
||||
Exiting @ tick 3238178 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 345240 # Number of bytes of host memory used
|
||||
host_seconds 39.07 # Real time elapsed on the host
|
||||
host_tick_rate 82719 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 340284 # Number of bytes of host memory used
|
||||
host_seconds 34.80 # Real time elapsed on the host
|
||||
host_tick_rate 93055 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.003232 # Number of seconds simulated
|
||||
sim_ticks 3231932 # Number of ticks simulated
|
||||
sim_seconds 0.003238 # Number of seconds simulated
|
||||
sim_ticks 3238178 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 97882 # number of read accesses completed
|
||||
system.cpu0.num_writes 52728 # number of write accesses completed
|
||||
system.cpu0.num_reads 99983 # number of read accesses completed
|
||||
system.cpu0.num_writes 54267 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 97696 # number of read accesses completed
|
||||
system.cpu1.num_writes 52571 # number of write accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53571 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 97954 # number of read accesses completed
|
||||
system.cpu2.num_writes 52878 # number of write accesses completed
|
||||
system.cpu2.num_reads 97642 # number of read accesses completed
|
||||
system.cpu2.num_writes 52892 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 97904 # number of read accesses completed
|
||||
system.cpu3.num_writes 52886 # number of write accesses completed
|
||||
system.cpu3.num_reads 97531 # number of read accesses completed
|
||||
system.cpu3.num_writes 52364 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98144 # number of read accesses completed
|
||||
system.cpu4.num_writes 52672 # number of write accesses completed
|
||||
system.cpu4.num_reads 98570 # number of read accesses completed
|
||||
system.cpu4.num_writes 53173 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 97310 # number of read accesses completed
|
||||
system.cpu5.num_writes 52054 # number of write accesses completed
|
||||
system.cpu5.num_reads 98261 # number of read accesses completed
|
||||
system.cpu5.num_writes 52643 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99443 # number of read accesses completed
|
||||
system.cpu6.num_writes 53518 # number of write accesses completed
|
||||
system.cpu6.num_reads 98464 # number of read accesses completed
|
||||
system.cpu6.num_writes 52805 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 54238 # number of write accesses completed
|
||||
system.cpu7.num_reads 97833 # number of read accesses completed
|
||||
system.cpu7.num_writes 52922 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -157,6 +157,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
|
@ -174,7 +175,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -288,7 +289,7 @@ icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
|
|
@ -346,7 +347,7 @@ icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
|
|
@ -404,7 +405,7 @@ icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
|
|
@ -462,7 +463,7 @@ icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
|
|
@ -520,7 +521,7 @@ icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
|
|
@ -578,7 +579,7 @@ icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
|
|
@ -636,7 +637,7 @@ icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
|
|
@ -677,7 +678,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu7: completed 10000 read accesses @425814
|
||||
system.cpu1: completed 10000 read accesses @431765
|
||||
system.cpu5: completed 10000 read accesses @437116
|
||||
system.cpu3: completed 10000 read accesses @437535
|
||||
system.cpu6: completed 10000 read accesses @438270
|
||||
system.cpu4: completed 10000 read accesses @440833
|
||||
system.cpu2: completed 10000 read accesses @444354
|
||||
system.cpu0: completed 10000 read accesses @448450
|
||||
system.cpu7: completed 20000 read accesses @862753
|
||||
system.cpu1: completed 20000 read accesses @872204
|
||||
system.cpu2: completed 20000 read accesses @872666
|
||||
system.cpu6: completed 20000 read accesses @874110
|
||||
system.cpu5: completed 20000 read accesses @878379
|
||||
system.cpu0: completed 20000 read accesses @879685
|
||||
system.cpu3: completed 20000 read accesses @882760
|
||||
system.cpu4: completed 20000 read accesses @884840
|
||||
system.cpu7: completed 30000 read accesses @1288068
|
||||
system.cpu3: completed 30000 read accesses @1303299
|
||||
system.cpu5: completed 30000 read accesses @1305762
|
||||
system.cpu6: completed 30000 read accesses @1313571
|
||||
system.cpu0: completed 30000 read accesses @1317286
|
||||
system.cpu2: completed 30000 read accesses @1317386
|
||||
system.cpu1: completed 30000 read accesses @1325478
|
||||
system.cpu4: completed 30000 read accesses @1333221
|
||||
system.cpu7: completed 40000 read accesses @1730996
|
||||
system.cpu5: completed 40000 read accesses @1732724
|
||||
system.cpu1: completed 40000 read accesses @1747591
|
||||
system.cpu6: completed 40000 read accesses @1753270
|
||||
system.cpu0: completed 40000 read accesses @1754662
|
||||
system.cpu3: completed 40000 read accesses @1760631
|
||||
system.cpu4: completed 40000 read accesses @1765520
|
||||
system.cpu2: completed 40000 read accesses @1771010
|
||||
system.cpu7: completed 50000 read accesses @2170118
|
||||
system.cpu5: completed 50000 read accesses @2171036
|
||||
system.cpu1: completed 50000 read accesses @2185469
|
||||
system.cpu2: completed 50000 read accesses @2190117
|
||||
system.cpu6: completed 50000 read accesses @2190751
|
||||
system.cpu0: completed 50000 read accesses @2197570
|
||||
system.cpu3: completed 50000 read accesses @2201959
|
||||
system.cpu4: completed 50000 read accesses @2222797
|
||||
system.cpu7: completed 60000 read accesses @2610778
|
||||
system.cpu2: completed 60000 read accesses @2614670
|
||||
system.cpu1: completed 60000 read accesses @2623246
|
||||
system.cpu5: completed 60000 read accesses @2629220
|
||||
system.cpu3: completed 60000 read accesses @2631164
|
||||
system.cpu6: completed 60000 read accesses @2632436
|
||||
system.cpu0: completed 60000 read accesses @2635088
|
||||
system.cpu4: completed 60000 read accesses @2652031
|
||||
system.cpu2: completed 70000 read accesses @3051672
|
||||
system.cpu7: completed 70000 read accesses @3059272
|
||||
system.cpu1: completed 70000 read accesses @3063932
|
||||
system.cpu0: completed 70000 read accesses @3068179
|
||||
system.cpu6: completed 70000 read accesses @3068899
|
||||
system.cpu5: completed 70000 read accesses @3070562
|
||||
system.cpu3: completed 70000 read accesses @3074746
|
||||
system.cpu4: completed 70000 read accesses @3079887
|
||||
system.cpu7: completed 80000 read accesses @3496808
|
||||
system.cpu3: completed 80000 read accesses @3497818
|
||||
system.cpu1: completed 80000 read accesses @3502491
|
||||
system.cpu2: completed 80000 read accesses @3504549
|
||||
system.cpu5: completed 80000 read accesses @3505508
|
||||
system.cpu6: completed 80000 read accesses @3505668
|
||||
system.cpu4: completed 80000 read accesses @3508575
|
||||
system.cpu0: completed 80000 read accesses @3514003
|
||||
system.cpu7: completed 90000 read accesses @3930059
|
||||
system.cpu3: completed 90000 read accesses @3930742
|
||||
system.cpu1: completed 90000 read accesses @3940704
|
||||
system.cpu4: completed 90000 read accesses @3941146
|
||||
system.cpu0: completed 90000 read accesses @3943666
|
||||
system.cpu2: completed 90000 read accesses @3945855
|
||||
system.cpu6: completed 90000 read accesses @3950281
|
||||
system.cpu5: completed 90000 read accesses @3953787
|
||||
system.cpu3: completed 100000 read accesses @4369301
|
||||
system.cpu0: completed 10000 read accesses @427647
|
||||
system.cpu1: completed 10000 read accesses @431729
|
||||
system.cpu6: completed 10000 read accesses @433789
|
||||
system.cpu7: completed 10000 read accesses @439540
|
||||
system.cpu2: completed 10000 read accesses @440839
|
||||
system.cpu5: completed 10000 read accesses @442985
|
||||
system.cpu4: completed 10000 read accesses @444200
|
||||
system.cpu3: completed 10000 read accesses @449590
|
||||
system.cpu0: completed 20000 read accesses @865314
|
||||
system.cpu6: completed 20000 read accesses @868247
|
||||
system.cpu1: completed 20000 read accesses @868279
|
||||
system.cpu4: completed 20000 read accesses @868705
|
||||
system.cpu7: completed 20000 read accesses @876211
|
||||
system.cpu3: completed 20000 read accesses @884081
|
||||
system.cpu2: completed 20000 read accesses @890953
|
||||
system.cpu5: completed 20000 read accesses @896667
|
||||
system.cpu7: completed 30000 read accesses @1294509
|
||||
system.cpu0: completed 30000 read accesses @1300229
|
||||
system.cpu4: completed 30000 read accesses @1308389
|
||||
system.cpu6: completed 30000 read accesses @1309605
|
||||
system.cpu1: completed 30000 read accesses @1314626
|
||||
system.cpu2: completed 30000 read accesses @1319614
|
||||
system.cpu3: completed 30000 read accesses @1333112
|
||||
system.cpu5: completed 30000 read accesses @1342297
|
||||
system.cpu0: completed 40000 read accesses @1732725
|
||||
system.cpu7: completed 40000 read accesses @1734274
|
||||
system.cpu6: completed 40000 read accesses @1739223
|
||||
system.cpu4: completed 40000 read accesses @1750291
|
||||
system.cpu2: completed 40000 read accesses @1757823
|
||||
system.cpu1: completed 40000 read accesses @1760314
|
||||
system.cpu3: completed 40000 read accesses @1761490
|
||||
system.cpu5: completed 40000 read accesses @1777684
|
||||
system.cpu7: completed 50000 read accesses @2168908
|
||||
system.cpu0: completed 50000 read accesses @2178119
|
||||
system.cpu3: completed 50000 read accesses @2188628
|
||||
system.cpu1: completed 50000 read accesses @2189157
|
||||
system.cpu6: completed 50000 read accesses @2193920
|
||||
system.cpu2: completed 50000 read accesses @2194930
|
||||
system.cpu4: completed 50000 read accesses @2196927
|
||||
system.cpu5: completed 50000 read accesses @2215126
|
||||
system.cpu7: completed 60000 read accesses @2604948
|
||||
system.cpu0: completed 60000 read accesses @2616657
|
||||
system.cpu4: completed 60000 read accesses @2617534
|
||||
system.cpu1: completed 60000 read accesses @2632147
|
||||
system.cpu6: completed 60000 read accesses @2638426
|
||||
system.cpu3: completed 60000 read accesses @2639965
|
||||
system.cpu2: completed 60000 read accesses @2642221
|
||||
system.cpu5: completed 60000 read accesses @2647795
|
||||
system.cpu7: completed 70000 read accesses @3047214
|
||||
system.cpu0: completed 70000 read accesses @3049033
|
||||
system.cpu4: completed 70000 read accesses @3063601
|
||||
system.cpu1: completed 70000 read accesses @3069586
|
||||
system.cpu2: completed 70000 read accesses @3071644
|
||||
system.cpu3: completed 70000 read accesses @3075127
|
||||
system.cpu6: completed 70000 read accesses @3078550
|
||||
system.cpu5: completed 70000 read accesses @3088269
|
||||
system.cpu7: completed 80000 read accesses @3486517
|
||||
system.cpu0: completed 80000 read accesses @3492714
|
||||
system.cpu4: completed 80000 read accesses @3505717
|
||||
system.cpu2: completed 80000 read accesses @3505856
|
||||
system.cpu3: completed 80000 read accesses @3506369
|
||||
system.cpu1: completed 80000 read accesses @3507148
|
||||
system.cpu6: completed 80000 read accesses @3520617
|
||||
system.cpu5: completed 80000 read accesses @3524191
|
||||
system.cpu7: completed 90000 read accesses @3917341
|
||||
system.cpu0: completed 90000 read accesses @3926523
|
||||
system.cpu4: completed 90000 read accesses @3938478
|
||||
system.cpu1: completed 90000 read accesses @3940606
|
||||
system.cpu5: completed 90000 read accesses @3950826
|
||||
system.cpu3: completed 90000 read accesses @3954179
|
||||
system.cpu6: completed 90000 read accesses @3956200
|
||||
system.cpu2: completed 90000 read accesses @3961428
|
||||
system.cpu7: completed 100000 read accesses @4339943
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 11:30:01
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:55:12
|
||||
M5 executing on svvint06
|
||||
M5 compiled Mar 18 2010 14:59:19
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:40:34
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 4369301 because maximum number of loads reached
|
||||
Exiting @ tick 4339943 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 342412 # Number of bytes of host memory used
|
||||
host_seconds 54.05 # Real time elapsed on the host
|
||||
host_tick_rate 80836 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339964 # Number of bytes of host memory used
|
||||
host_seconds 41.43 # Real time elapsed on the host
|
||||
host_tick_rate 104755 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.004369 # Number of seconds simulated
|
||||
sim_ticks 4369301 # Number of ticks simulated
|
||||
sim_seconds 0.004340 # Number of seconds simulated
|
||||
sim_ticks 4339943 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99702 # number of read accesses completed
|
||||
system.cpu0.num_writes 54194 # number of write accesses completed
|
||||
system.cpu0.num_reads 99313 # number of read accesses completed
|
||||
system.cpu0.num_writes 53538 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99603 # number of read accesses completed
|
||||
system.cpu1.num_writes 53835 # number of write accesses completed
|
||||
system.cpu1.num_reads 99089 # number of read accesses completed
|
||||
system.cpu1.num_writes 53648 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99782 # number of read accesses completed
|
||||
system.cpu2.num_writes 53417 # number of write accesses completed
|
||||
system.cpu2.num_reads 98494 # number of read accesses completed
|
||||
system.cpu2.num_writes 52751 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53655 # number of write accesses completed
|
||||
system.cpu3.num_reads 98499 # number of read accesses completed
|
||||
system.cpu3.num_writes 53164 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99541 # number of read accesses completed
|
||||
system.cpu4.num_writes 53625 # number of write accesses completed
|
||||
system.cpu4.num_reads 99037 # number of read accesses completed
|
||||
system.cpu4.num_writes 53407 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99748 # number of read accesses completed
|
||||
system.cpu5.num_writes 53937 # number of write accesses completed
|
||||
system.cpu5.num_reads 99159 # number of read accesses completed
|
||||
system.cpu5.num_writes 53566 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99530 # number of read accesses completed
|
||||
system.cpu6.num_writes 53708 # number of write accesses completed
|
||||
system.cpu6.num_reads 98888 # number of read accesses completed
|
||||
system.cpu6.num_writes 53164 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99892 # number of read accesses completed
|
||||
system.cpu7.num_writes 53981 # number of write accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 54267 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -157,6 +157,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
|
@ -174,7 +175,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -263,7 +264,7 @@ icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
port=system.cpu1.test
|
||||
|
||||
|
|
@ -305,7 +306,7 @@ icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
port=system.cpu2.test
|
||||
|
||||
|
|
@ -347,7 +348,7 @@ icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
port=system.cpu3.test
|
||||
|
||||
|
|
@ -389,7 +390,7 @@ icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
port=system.cpu4.test
|
||||
|
||||
|
|
@ -431,7 +432,7 @@ icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
port=system.cpu5.test
|
||||
|
||||
|
|
@ -473,7 +474,7 @@ icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
port=system.cpu6.test
|
||||
|
||||
|
|
@ -515,7 +516,7 @@ icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
|||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
port=system.cpu7.test
|
||||
|
||||
|
|
@ -549,7 +550,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links8.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@ topology:
|
|||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
|
|
@ -34,40 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 11:10:42
|
||||
Real time: Mar/18/2010 15:36:18
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 86
|
||||
Elapsed_time_in_minutes: 1.43333
|
||||
Elapsed_time_in_hours: 0.0238889
|
||||
Elapsed_time_in_days: 0.00099537
|
||||
Elapsed_time_in_seconds: 77
|
||||
Elapsed_time_in_minutes: 1.28333
|
||||
Elapsed_time_in_hours: 0.0213889
|
||||
Elapsed_time_in_days: 0.000891204
|
||||
|
||||
Virtual_time_in_seconds: 83.22
|
||||
Virtual_time_in_minutes: 1.387
|
||||
Virtual_time_in_hours: 0.0231167
|
||||
Virtual_time_in_days: 0.000963194
|
||||
Virtual_time_in_seconds: 76.96
|
||||
Virtual_time_in_minutes: 1.28267
|
||||
Virtual_time_in_hours: 0.0213778
|
||||
Virtual_time_in_days: 0.000890741
|
||||
|
||||
Ruby_current_time: 11043028
|
||||
Ruby_current_time: 11048357
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 11043028
|
||||
Ruby_cycles: 11048357
|
||||
|
||||
mbytes_resident: 31.1562
|
||||
mbytes_total: 31.1602
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
ruby_cycles_executed: 88344232 [ 11043029 11043029 11043029 11043029 11043029 11043029 11043029 11043029 ]
|
||||
|
||||
transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
|
||||
mbytes_resident: 30.7461
|
||||
mbytes_total: 331.699
|
||||
resident_ratio: 0.0927045
|
||||
|
||||
ruby_cycles_executed: [ 11048358 11048358 11048358 11048358 11048358 11048358 11048358 11048358 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -77,13 +66,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1226994 average: 1.93527 | standard deviation: 0.246042 | 0 79418 1147576 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1227589 average: 1.875 | standard deviation: 0.330723 | 0 153452 1074137 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 4 max: 548 count: 1226980 average: 141.939 | standard deviation: 1.7969 | 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 296 4661 76324 1145657 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 4 max: 530 count: 797700 average: 141.938 | standard deviation: 1.74299 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 188 2995 49656 744835 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 4 max: 548 count: 429280 average: 141.94 | standard deviation: 1.89302 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 108 1666 26668 400822 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 4 max: 549 count: 1227573 average: 141.876 | standard deviation: 1.82074 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 294 5125 80867 1141231 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 4 max: 549 count: 798072 average: 141.875 | standard deviation: 1.78629 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 192 3318 52570 741960 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 4 max: 531 count: 429501 average: 141.879 | standard deviation: 1.88309 | 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 102 1807 28297 399271 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -97,11 +86,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 4 max: 151 count: 2453934 average: 47.4682 | standard deviation: 47.4791 | 1226968 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2453934 average: 47.4682 | standard deviation: 47.4791 | 1226968 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1226967 average: 0 | standard deviation: 0 | 1226967 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1226967 average: 94.9364 | standard deviation: 1.44009 | 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 2 0 0 0 7 141 2386 38040 613044 573338 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227559 average: 0 | standard deviation: 0 | 1227559 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 4 max: 152 count: 1227559 average: 94.8743 | standard deviation: 1.46213 | 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -113,10 +102,10 @@ Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2453934 average: 47.4682 |
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 82
|
||||
system_time: 1
|
||||
page_reclaims: 6850
|
||||
page_faults: 1924
|
||||
user_time: 76
|
||||
system_time: 0
|
||||
page_reclaims: 8851
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -126,14 +115,14 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.434014
|
||||
links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.434016
|
||||
links_utilized_percent_switch_0_link_0: 0.173607 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
|
|
@ -141,10 +130,10 @@ links_utilized_percent_switch_1: 0.434016
|
|||
links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
|
|
@ -152,10 +141,10 @@ links_utilized_percent_switch_2: 0.434016
|
|||
links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
|
|
@ -163,43 +152,43 @@ links_utilized_percent_switch_3: 0.434016
|
|||
links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 0.434016
|
||||
links_utilized_percent_switch_4: 0.434014
|
||||
links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 0.434014
|
||||
links_utilized_percent_switch_5: 0.434016
|
||||
links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 0.434016
|
||||
links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 0.434013
|
||||
links_utilized_percent_switch_6_link_0: 0.173605 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 153373 1226984 [ 153373 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
|
|
@ -207,10 +196,10 @@ links_utilized_percent_switch_7: 0.434013
|
|||
links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 153372 1226976 [ 153372 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
|
|
@ -218,71 +207,174 @@ links_utilized_percent_switch_8: 0.347219
|
|||
links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 1226981 9815848 [ 1226981 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 1226977 9815816 [ 0 0 1226977 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 1227569 9820552 [ 0 0 0 1227569 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 0.678994
|
||||
links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_0: 0.694429 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 0.694421 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 0.69442 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 0.555545 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 153373 1226984 [ 0 0 153373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 153371 11042712 [ 0 153371 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 153372 1226976 [ 0 0 153372 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 153370 11042640 [ 0 153370 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 153371 1226968 [ 0 0 153371 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 1226981 9815848 [ 1226981 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153372
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153372
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.2016%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.7984%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.0211%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.9789%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 100001
|
||||
Load 99774
|
||||
Ifetch 0
|
||||
Store 53371
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Store 53675
|
||||
Data 153446
|
||||
Fwd_GETX 153446
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 100001
|
||||
I Load 99773
|
||||
I Ifetch 0 <--
|
||||
I Store 53371
|
||||
I Store 53674
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 1
|
||||
M Ifetch 0 <--
|
||||
M Store 1
|
||||
M Fwd_GETX 153446
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99773
|
||||
|
||||
IM Data 53673
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.6816%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.3184%
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 1 ---
|
||||
- Event Counts -
|
||||
Load 99260
|
||||
Ifetch 0
|
||||
Store 54199
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99252
|
||||
I Ifetch 0 <--
|
||||
I Store 54195
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 8
|
||||
M Ifetch 0 <--
|
||||
M Store 4
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99251
|
||||
|
||||
IM Data 54194
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8804%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1196%
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 2 ---
|
||||
- Event Counts -
|
||||
Load 99557
|
||||
Ifetch 0
|
||||
Store 53890
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99557
|
||||
I Ifetch 0 <--
|
||||
I Store 53890
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
|
|
@ -291,7 +383,111 @@ II Writeback_Nack 0 <--
|
|||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99555
|
||||
|
||||
IM Data 53890
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.1254%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.8746%
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 3 ---
|
||||
- Event Counts -
|
||||
Load 99933
|
||||
Ifetch 0
|
||||
Store 53514
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99933
|
||||
I Ifetch 0 <--
|
||||
I Store 53514
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99932
|
||||
|
||||
IM Data 53513
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.1702%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.8298%
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 4 ---
|
||||
- Event Counts -
|
||||
Load 100001
|
||||
Ifetch 0
|
||||
Store 53445
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 100001
|
||||
I Ifetch 0 <--
|
||||
I Store 53445
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
|
|
@ -304,250 +500,37 @@ MII Fwd_GETX 0 <--
|
|||
|
||||
IS Data 100000
|
||||
|
||||
IM Data 53371
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153373
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153373
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.8843%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.1157%
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
|
||||
system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
|
||||
|
||||
--- L1Cache 1 ---
|
||||
- Event Counts -
|
||||
Load 99517
|
||||
Ifetch 0
|
||||
Store 53858
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99515
|
||||
I Ifetch 0 <--
|
||||
I Store 53858
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 2
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99514
|
||||
|
||||
IM Data 53857
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153373
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153373
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8569%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1431%
|
||||
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
|
||||
system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
|
||||
|
||||
--- L1Cache 2 ---
|
||||
- Event Counts -
|
||||
Load 99480
|
||||
Ifetch 0
|
||||
Store 53904
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99473
|
||||
I Ifetch 0 <--
|
||||
I Store 53900
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 7
|
||||
M Ifetch 0 <--
|
||||
M Store 4
|
||||
M Fwd_GETX 153371
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99472
|
||||
|
||||
IM Data 53899
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153373
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153373
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.0871%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.9129%
|
||||
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
|
||||
system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
|
||||
|
||||
--- L1Cache 3 ---
|
||||
- Event Counts -
|
||||
Load 99826
|
||||
Ifetch 0
|
||||
Store 53547
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99826
|
||||
I Ifetch 0 <--
|
||||
I Store 53547
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99825
|
||||
|
||||
IM Data 53546
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153373
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153373
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.0043%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.9957%
|
||||
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
|
||||
system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
|
||||
|
||||
--- L1Cache 4 ---
|
||||
- Event Counts -
|
||||
Load 99699
|
||||
Ifetch 0
|
||||
Store 53674
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99699
|
||||
I Ifetch 0 <--
|
||||
I Store 53674
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99698
|
||||
|
||||
IM Data 53673
|
||||
IM Data 53445
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153372
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153372
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153447
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153447
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.0692%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.9308%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.1137%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.8863%
|
||||
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100%
|
||||
system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ]
|
||||
|
||||
--- L1Cache 5 ---
|
||||
- Event Counts -
|
||||
Load 99798
|
||||
Load 99915
|
||||
Ifetch 0
|
||||
Store 53574
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Store 53532
|
||||
Data 153445
|
||||
Fwd_GETX 153445
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99798
|
||||
I Load 99915
|
||||
I Ifetch 0 <--
|
||||
I Store 53574
|
||||
I Store 53532
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
|
|
@ -556,7 +539,7 @@ II Writeback_Nack 0 <--
|
|||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Fwd_GETX 153445
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
|
|
@ -567,40 +550,39 @@ MI Writeback_Nack 0 <--
|
|||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99797
|
||||
IS Data 99914
|
||||
|
||||
IM Data 53574
|
||||
IM Data 53531
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153373
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153373
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0597%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9403%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0203%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9797%
|
||||
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153373 100%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153373 average: 1 | standard deviation: 0 | 0 153373 ]
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 6 ---
|
||||
- Event Counts -
|
||||
Load 99784
|
||||
Load 99771
|
||||
Ifetch 0
|
||||
Store 53589
|
||||
Data 153371
|
||||
Fwd_GETX 153371
|
||||
Store 53675
|
||||
Data 153444
|
||||
Fwd_GETX 153444
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99784
|
||||
I Load 99771
|
||||
I Ifetch 0 <--
|
||||
I Store 53589
|
||||
I Store 53675
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
|
|
@ -609,7 +591,7 @@ II Writeback_Nack 0 <--
|
|||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153371
|
||||
M Fwd_GETX 153444
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
|
|
@ -620,40 +602,39 @@ MI Writeback_Nack 0 <--
|
|||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99782
|
||||
IS Data 99770
|
||||
|
||||
IM Data 53589
|
||||
IM Data 53674
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153372
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153372
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153446
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153446
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 64.9434%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 35.0566%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 65.0841%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 34.9159%
|
||||
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153372 100%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153372 average: 1 | standard deviation: 0 | 0 153372 ]
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100%
|
||||
system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ]
|
||||
|
||||
--- L1Cache 7 ---
|
||||
- Event Counts -
|
||||
Load 99605
|
||||
Load 99869
|
||||
Ifetch 0
|
||||
Store 53767
|
||||
Data 153370
|
||||
Fwd_GETX 153370
|
||||
Store 53577
|
||||
Data 153444
|
||||
Fwd_GETX 153444
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 99605
|
||||
I Load 99869
|
||||
I Ifetch 0 <--
|
||||
I Store 53767
|
||||
I Store 53577
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
|
|
@ -662,7 +643,7 @@ II Writeback_Nack 0 <--
|
|||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 153370
|
||||
M Fwd_GETX 153444
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
|
|
@ -673,9 +654,9 @@ MI Writeback_Nack 0 <--
|
|||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 99603
|
||||
IS Data 99868
|
||||
|
||||
IM Data 53767
|
||||
IM Data 53576
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
|
||||
memory_total_requests: 2
|
||||
|
|
@ -699,7 +680,7 @@ Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer:
|
|||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 1227392
|
||||
GETX 1227984
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
|
|
@ -714,7 +695,7 @@ I PUTX_NotOwner 0 <--
|
|||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 1226979
|
||||
M GETX 1227571
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu0: completed 10000 read accesses @1103968
|
||||
system.cpu6: completed 10000 read accesses @1104382
|
||||
system.cpu5: completed 10000 read accesses @1104796
|
||||
system.cpu1: completed 10000 read accesses @1105498
|
||||
system.cpu2: completed 10000 read accesses @1106632
|
||||
system.cpu4: completed 10000 read accesses @1107712
|
||||
system.cpu7: completed 10000 read accesses @1111366
|
||||
system.cpu3: completed 10000 read accesses @1114786
|
||||
system.cpu6: completed 20000 read accesses @2206702
|
||||
system.cpu5: completed 20000 read accesses @2207332
|
||||
system.cpu4: completed 20000 read accesses @2213344
|
||||
system.cpu0: completed 20000 read accesses @2215108
|
||||
system.cpu3: completed 20000 read accesses @2216458
|
||||
system.cpu2: completed 20000 read accesses @2216584
|
||||
system.cpu1: completed 20000 read accesses @2217286
|
||||
system.cpu7: completed 20000 read accesses @2221534
|
||||
system.cpu6: completed 30000 read accesses @3313342
|
||||
system.cpu0: completed 30000 read accesses @3313972
|
||||
system.cpu2: completed 30000 read accesses @3321065
|
||||
system.cpu4: completed 30000 read accesses @3321964
|
||||
system.cpu5: completed 30000 read accesses @3324628
|
||||
system.cpu1: completed 30000 read accesses @3325258
|
||||
system.cpu3: completed 30000 read accesses @3325906
|
||||
system.cpu7: completed 30000 read accesses @3327526
|
||||
system.cpu0: completed 40000 read accesses @4414996
|
||||
system.cpu6: completed 40000 read accesses @4419838
|
||||
system.cpu4: completed 40000 read accesses @4423312
|
||||
system.cpu7: completed 40000 read accesses @4424446
|
||||
system.cpu3: completed 40000 read accesses @4428010
|
||||
system.cpu1: completed 40000 read accesses @4433050
|
||||
system.cpu2: completed 40000 read accesses @4433464
|
||||
system.cpu5: completed 40000 read accesses @4434796
|
||||
system.cpu0: completed 50000 read accesses @5511988
|
||||
system.cpu6: completed 50000 read accesses @5524786
|
||||
system.cpu3: completed 50000 read accesses @5528242
|
||||
system.cpu4: completed 50000 read accesses @5531104
|
||||
system.cpu5: completed 50000 read accesses @5534092
|
||||
system.cpu7: completed 50000 read accesses @5544478
|
||||
system.cpu2: completed 50000 read accesses @5545289
|
||||
system.cpu1: completed 50000 read accesses @5546278
|
||||
system.cpu0: completed 60000 read accesses @6613264
|
||||
system.cpu3: completed 60000 read accesses @6629122
|
||||
system.cpu5: completed 60000 read accesses @6630580
|
||||
system.cpu6: completed 60000 read accesses @6640498
|
||||
system.cpu4: completed 60000 read accesses @6648076
|
||||
system.cpu7: completed 60000 read accesses @6652270
|
||||
system.cpu2: completed 60000 read accesses @6660281
|
||||
system.cpu1: completed 60000 read accesses @6663286
|
||||
system.cpu0: completed 70000 read accesses @7721632
|
||||
system.cpu3: completed 70000 read accesses @7733602
|
||||
system.cpu6: completed 70000 read accesses @7744546
|
||||
system.cpu4: completed 70000 read accesses @7745248
|
||||
system.cpu5: completed 70000 read accesses @7745356
|
||||
system.cpu2: completed 70000 read accesses @7765913
|
||||
system.cpu1: completed 70000 read accesses @7768378
|
||||
system.cpu7: completed 70000 read accesses @7769926
|
||||
system.cpu0: completed 80000 read accesses @8821828
|
||||
system.cpu5: completed 80000 read accesses @8845300
|
||||
system.cpu3: completed 80000 read accesses @8848018
|
||||
system.cpu6: completed 80000 read accesses @8850754
|
||||
system.cpu4: completed 80000 read accesses @8854012
|
||||
system.cpu7: completed 80000 read accesses @8871886
|
||||
system.cpu1: completed 80000 read accesses @8880202
|
||||
system.cpu2: completed 80000 read accesses @8886377
|
||||
system.cpu0: completed 90000 read accesses @9929332
|
||||
system.cpu5: completed 90000 read accesses @9945316
|
||||
system.cpu3: completed 90000 read accesses @9955306
|
||||
system.cpu6: completed 90000 read accesses @9959554
|
||||
system.cpu4: completed 90000 read accesses @9962668
|
||||
system.cpu7: completed 90000 read accesses @9977536
|
||||
system.cpu1: completed 90000 read accesses @9979354
|
||||
system.cpu2: completed 90000 read accesses @10002520
|
||||
system.cpu0: completed 100000 read accesses @11043028
|
||||
system.cpu5: completed 10000 read accesses @1097795
|
||||
system.cpu1: completed 10000 read accesses @1101449
|
||||
system.cpu4: completed 10000 read accesses @1103861
|
||||
system.cpu3: completed 10000 read accesses @1104689
|
||||
system.cpu6: completed 10000 read accesses @1107767
|
||||
system.cpu2: completed 10000 read accesses @1108955
|
||||
system.cpu0: completed 10000 read accesses @1109315
|
||||
system.cpu7: completed 10000 read accesses @1115237
|
||||
system.cpu5: completed 20000 read accesses @2202527
|
||||
system.cpu4: completed 20000 read accesses @2207405
|
||||
system.cpu3: completed 20000 read accesses @2212049
|
||||
system.cpu2: completed 20000 read accesses @2212140
|
||||
system.cpu6: completed 20000 read accesses @2216495
|
||||
system.cpu1: completed 20000 read accesses @2218601
|
||||
system.cpu7: completed 20000 read accesses @2229041
|
||||
system.cpu0: completed 20000 read accesses @2229203
|
||||
system.cpu5: completed 30000 read accesses @3306575
|
||||
system.cpu4: completed 30000 read accesses @3307925
|
||||
system.cpu3: completed 30000 read accesses @3308753
|
||||
system.cpu7: completed 30000 read accesses @3318869
|
||||
system.cpu6: completed 30000 read accesses @3328247
|
||||
system.cpu2: completed 30000 read accesses @3331884
|
||||
system.cpu1: completed 30000 read accesses @3338201
|
||||
system.cpu0: completed 30000 read accesses @3340343
|
||||
system.cpu5: completed 40000 read accesses @4410227
|
||||
system.cpu4: completed 40000 read accesses @4410389
|
||||
system.cpu3: completed 40000 read accesses @4424177
|
||||
system.cpu7: completed 40000 read accesses @4429973
|
||||
system.cpu0: completed 40000 read accesses @4435175
|
||||
system.cpu6: completed 40000 read accesses @4438199
|
||||
system.cpu2: completed 40000 read accesses @4444715
|
||||
system.cpu1: completed 40000 read accesses @4450313
|
||||
system.cpu5: completed 50000 read accesses @5504627
|
||||
system.cpu4: completed 50000 read accesses @5519333
|
||||
system.cpu3: completed 50000 read accesses @5526785
|
||||
system.cpu7: completed 50000 read accesses @5529377
|
||||
system.cpu0: completed 50000 read accesses @5532419
|
||||
system.cpu6: completed 50000 read accesses @5546639
|
||||
system.cpu2: completed 50000 read accesses @5560715
|
||||
system.cpu1: completed 50000 read accesses @5569193
|
||||
system.cpu5: completed 60000 read accesses @6620303
|
||||
system.cpu4: completed 60000 read accesses @6630005
|
||||
system.cpu3: completed 60000 read accesses @6637745
|
||||
system.cpu7: completed 60000 read accesses @6639905
|
||||
system.cpu0: completed 60000 read accesses @6649463
|
||||
system.cpu6: completed 60000 read accesses @6652055
|
||||
system.cpu2: completed 60000 read accesses @6667068
|
||||
system.cpu1: completed 60000 read accesses @6690378
|
||||
system.cpu5: completed 70000 read accesses @7728671
|
||||
system.cpu3: completed 70000 read accesses @7729265
|
||||
system.cpu4: completed 70000 read accesses @7729373
|
||||
system.cpu7: completed 70000 read accesses @7748849
|
||||
system.cpu6: completed 70000 read accesses @7751423
|
||||
system.cpu0: completed 70000 read accesses @7760099
|
||||
system.cpu2: completed 70000 read accesses @7781196
|
||||
system.cpu1: completed 70000 read accesses @7788377
|
||||
system.cpu4: completed 80000 read accesses @8833637
|
||||
system.cpu3: completed 80000 read accesses @8841377
|
||||
system.cpu5: completed 80000 read accesses @8845283
|
||||
system.cpu7: completed 80000 read accesses @8850647
|
||||
system.cpu0: completed 80000 read accesses @8859269
|
||||
system.cpu6: completed 80000 read accesses @8861015
|
||||
system.cpu2: completed 80000 read accesses @8880203
|
||||
system.cpu1: completed 80000 read accesses @8893866
|
||||
system.cpu4: completed 90000 read accesses @9931349
|
||||
system.cpu7: completed 90000 read accesses @9951959
|
||||
system.cpu5: completed 90000 read accesses @9952175
|
||||
system.cpu3: completed 90000 read accesses @9957341
|
||||
system.cpu6: completed 90000 read accesses @9967079
|
||||
system.cpu0: completed 90000 read accesses @9971795
|
||||
system.cpu2: completed 90000 read accesses @9992027
|
||||
system.cpu1: completed 90000 read accesses @10012745
|
||||
system.cpu4: completed 100000 read accesses @11048357
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:23:20
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:09:16
|
||||
M5 executing on svvint07
|
||||
M5 compiled Mar 18 2010 15:34:55
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 15:35:01
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 11043028 because maximum number of loads reached
|
||||
Exiting @ tick 11048357 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 344584 # Number of bytes of host memory used
|
||||
host_seconds 85.64 # Real time elapsed on the host
|
||||
host_tick_rate 128940 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339664 # Number of bytes of host memory used
|
||||
host_seconds 76.81 # Real time elapsed on the host
|
||||
host_tick_rate 143842 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.011043 # Number of seconds simulated
|
||||
sim_ticks 11043028 # Number of ticks simulated
|
||||
sim_seconds 0.011048 # Number of seconds simulated
|
||||
sim_ticks 11048357 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53371 # number of write accesses completed
|
||||
system.cpu0.num_reads 99774 # number of read accesses completed
|
||||
system.cpu0.num_writes 53674 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99516 # number of read accesses completed
|
||||
system.cpu1.num_writes 53857 # number of write accesses completed
|
||||
system.cpu1.num_reads 99259 # number of read accesses completed
|
||||
system.cpu1.num_writes 54198 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99479 # number of read accesses completed
|
||||
system.cpu2.num_writes 53903 # number of write accesses completed
|
||||
system.cpu2.num_reads 99555 # number of read accesses completed
|
||||
system.cpu2.num_writes 53890 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99825 # number of read accesses completed
|
||||
system.cpu3.num_writes 53546 # number of write accesses completed
|
||||
system.cpu3.num_reads 99932 # number of read accesses completed
|
||||
system.cpu3.num_writes 53513 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99698 # number of read accesses completed
|
||||
system.cpu4.num_writes 53673 # number of write accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53445 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99797 # number of read accesses completed
|
||||
system.cpu5.num_writes 53574 # number of write accesses completed
|
||||
system.cpu5.num_reads 99914 # number of read accesses completed
|
||||
system.cpu5.num_writes 53531 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99782 # number of read accesses completed
|
||||
system.cpu6.num_writes 53589 # number of write accesses completed
|
||||
system.cpu6.num_reads 99770 # number of read accesses completed
|
||||
system.cpu6.num_writes 53674 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99603 # number of read accesses completed
|
||||
system.cpu7.num_writes 53767 # number of write accesses completed
|
||||
system.cpu7.num_reads 99868 # number of read accesses completed
|
||||
system.cpu7.num_writes 53576 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
|
@ -44,7 +45,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -165,7 +166,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -34,40 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/27/2010 22:07:37
|
||||
Real time: Mar/18/2010 14:37:01
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 2
|
||||
Elapsed_time_in_minutes: 0.0333333
|
||||
Elapsed_time_in_hours: 0.000555556
|
||||
Elapsed_time_in_days: 2.31481e-05
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 1.4
|
||||
Virtual_time_in_minutes: 0.0233333
|
||||
Virtual_time_in_hours: 0.000388889
|
||||
Virtual_time_in_days: 1.62037e-05
|
||||
Virtual_time_in_seconds: 1.11
|
||||
Virtual_time_in_minutes: 0.0185
|
||||
Virtual_time_in_hours: 0.000308333
|
||||
Virtual_time_in_days: 1.28472e-05
|
||||
|
||||
Ruby_current_time: 357031
|
||||
Ruby_current_time: 385311
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 357031
|
||||
Ruby_cycles: 385311
|
||||
|
||||
mbytes_resident: 31.0938
|
||||
mbytes_total: 31.1016
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 357032 [ 357032 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 30.6758
|
||||
mbytes_total: 203.664
|
||||
resident_ratio: 0.150658
|
||||
|
||||
ruby_cycles_executed: [ 385312 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -77,13 +66,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 970 average: 15.8278 | standard deviation: 1.13986 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 48 908 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1035 average: 15.8406 | standard deviation: 1.10345 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 975 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 34787 count: 954 average: 5860.09 | standard deviation: 7881.77 | 94 12 70 81 75 77 58 51 39 26 24 21 14 6 9 8 5 4 5 6 9 4 5 3 5 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 2 3 5 3 1 1 1 2 2 2 1 5 1 4 6 2 2 5 8 1 6 6 4 2 3 8 3 1 3 5 8 3 5 4 1 5 6 6 4 6 3 6 2 3 5 2 1 3 1 4 2 1 1 4 2 2 2 3 3 1 2 4 3 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 256 max: 26521 count: 100 average: 5073.78 | standard deviation: 7357.14 | 10 1 5 11 11 3 3 4 7 6 6 4 3 0 1 0 2 1 0 2 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 256 max: 34787 count: 854 average: 5952.16 | standard deviation: 7939.9 | 84 11 65 70 64 74 55 47 32 20 18 17 11 6 8 8 3 3 5 4 9 4 5 3 3 4 2 1 1 5 1 2 1 0 0 1 1 1 1 0 0 1 3 5 3 1 1 1 2 2 2 1 5 1 3 5 2 1 5 8 1 5 6 4 2 3 8 3 1 2 5 8 2 5 4 0 5 5 6 4 6 1 6 2 2 4 2 1 3 1 4 2 1 1 3 2 2 2 2 3 1 1 3 2 0 1 0 2 3 0 1 0 1 0 1 1 0 0 1 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 256 max: 34673 count: 1020 average: 5812.61 | standard deviation: 8321.57 | 94 13 65 91 82 85 75 46 28 39 28 23 31 15 11 13 6 8 12 9 6 3 9 2 3 6 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 3 1 0 0 0 0 0 0 2 2 0 3 1 3 1 3 2 1 6 1 2 2 5 2 7 2 1 3 4 4 3 2 6 5 9 2 2 10 1 6 4 3 4 4 5 3 5 2 5 5 2 3 6 3 3 1 3 3 4 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 256 max: 28025 count: 100 average: 5269.19 | standard deviation: 7878.72 | 12 1 6 6 7 10 10 8 2 4 3 0 3 2 1 2 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 2 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 256 max: 34673 count: 920 average: 5871.67 | standard deviation: 8370.25 | 82 12 59 85 75 75 65 38 26 35 25 23 28 13 10 11 6 7 11 9 6 3 8 2 2 5 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 2 1 0 0 0 0 0 0 2 2 0 2 0 3 0 3 2 1 6 1 2 1 5 2 6 2 1 3 4 3 3 1 4 4 9 2 2 10 1 5 3 3 4 4 4 3 5 2 4 5 2 3 5 3 3 1 2 3 3 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -97,12 +86,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 32 max: 1590 count: 6452 average: 19.6141 | standard deviation: 106.746 | 6116 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3918 average: 0 | standard deviation: 0 | 3918 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 32 max: 1590 count: 2534 average: 49.9408 | standard deviation: 165.845 | 2198 4 30 74 2 5 34 6 4 19 14 1 15 14 3 9 18 2 3 14 16 2 6 11 2 0 7 5 1 2 2 0 0 3 0 2 0 0 0 1 0 0 4 0 0 0 0 0 0 1 ]
|
||||
Total_delay_cycles: [binsize: 32 max: 1500 count: 6932 average: 17.1509 | standard deviation: 98.3547 | 6592 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4219 average: 0 | standard deviation: 0 | 4219 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 32 max: 1500 count: 2713 average: 43.8223 | standard deviation: 153.471 | 2373 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 531 average: 0 | standard deviation: 0 | 531 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3387 average: 0 | standard deviation: 0 | 3387 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 566 average: 0 | standard deviation: 0 | 566 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3653 average: 0 | standard deviation: 0 | 3653 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -115,8 +104,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 1
|
||||
system_time: 0
|
||||
page_reclaims: 6770
|
||||
page_faults: 1936
|
||||
page_reclaims: 8843
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -126,64 +115,64 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.106988
|
||||
links_utilized_percent_switch_0_link_0: 0.0301689 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.183808 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.105942
|
||||
links_utilized_percent_switch_0_link_0: 0.0300309 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.181853 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 866 6928 [ 0 4 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 931 7448 [ 0 6 925 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.151261
|
||||
links_utilized_percent_switch_1_link_0: 0.0751615 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.227361 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.151597
|
||||
links_utilized_percent_switch_1_link_0: 0.0748065 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.228387 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 862 6896 [ 862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1606 115632 [ 0 1606 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 415 3320 [ 0 415 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1743 125496 [ 0 1743 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 441 3528 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.071776
|
||||
links_utilized_percent_switch_2_link_0: 0.0266714 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.116881 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0722257
|
||||
links_utilized_percent_switch_2_link_0: 0.0270658 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.117386 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 831 6648 [ 0 831 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 901 7208 [ 0 901 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.176007
|
||||
links_utilized_percent_switch_3_link_0: 0.120676 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.30066 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.106685 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.175871
|
||||
links_utilized_percent_switch_3_link_0: 0.120124 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.299226 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.108263 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 531 4248 [ 531 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 862 62064 [ 0 862 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 328 2624 [ 0 328 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 863 6904 [ 863 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 835 60120 [ 0 835 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1695 13560 [ 0 835 860 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1257 90504 [ 730 527 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 83 664 [ 83 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 835 6680 [ 835 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 744 53568 [ 0 744 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 87 696 [ 0 87 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
|
|
@ -191,7 +180,6 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
|
@ -201,7 +189,6 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
|
@ -209,24 +196,24 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
|||
- Event Counts -
|
||||
Load 100
|
||||
Ifetch 0
|
||||
Store 856
|
||||
Inv 531
|
||||
L1_Replacement 507964
|
||||
Store 1000
|
||||
Inv 566
|
||||
L1_Replacement 547844
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
Fwd_GET_INSTR 0
|
||||
Data 0
|
||||
Data_Exclusive 90
|
||||
Data_Exclusive 88
|
||||
DataS_fromL1 0
|
||||
Data_all_Acks 772
|
||||
Data_all_Acks 838
|
||||
Ack 0
|
||||
Ack_all 0
|
||||
WB_Ack 328
|
||||
WB_Ack 357
|
||||
|
||||
- Transitions -
|
||||
NP Load 90
|
||||
NP Load 88
|
||||
NP Ifetch 0 <--
|
||||
NP Store 774
|
||||
NP Store 839
|
||||
NP Inv 0 <--
|
||||
NP L1_Replacement 0 <--
|
||||
|
||||
|
|
@ -234,7 +221,7 @@ I Load 0 <--
|
|||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I Inv 0 <--
|
||||
I L1_Replacement 46
|
||||
I L1_Replacement 63
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 0 <--
|
||||
|
|
@ -245,17 +232,17 @@ S L1_Replacement 0 <--
|
|||
E Load 0 <--
|
||||
E Ifetch 0 <--
|
||||
E Store 1
|
||||
E Inv 4
|
||||
E L1_Replacement 85
|
||||
E Inv 6
|
||||
E L1_Replacement 80
|
||||
E Fwd_GETX 0 <--
|
||||
E Fwd_GETS 0 <--
|
||||
E Fwd_GET_INSTR 0 <--
|
||||
|
||||
M Load 10
|
||||
M Load 12
|
||||
M Ifetch 0 <--
|
||||
M Store 81
|
||||
M Inv 42
|
||||
M L1_Replacement 730
|
||||
M Inv 57
|
||||
M L1_Replacement 781
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_GET_INSTR 0 <--
|
||||
|
|
@ -264,8 +251,8 @@ IS Load 0 <--
|
|||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS Inv 0 <--
|
||||
IS L1_Replacement 54611
|
||||
IS Data_Exclusive 90
|
||||
IS L1_Replacement 46341
|
||||
IS Data_Exclusive 88
|
||||
IS DataS_fromL1 0 <--
|
||||
IS Data_all_Acks 0 <--
|
||||
|
||||
|
|
@ -273,9 +260,9 @@ IM Load 0 <--
|
|||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM Inv 0 <--
|
||||
IM L1_Replacement 452492
|
||||
IM L1_Replacement 500579
|
||||
IM Data 0 <--
|
||||
IM Data_all_Acks 772
|
||||
IM Data_all_Acks 838
|
||||
IM Ack 0 <--
|
||||
|
||||
SM Load 0 <--
|
||||
|
|
@ -297,13 +284,13 @@ IS_I Data_all_Acks 0 <--
|
|||
|
||||
M_I Load 0 <--
|
||||
M_I Ifetch 0 <--
|
||||
M_I Store 0 <--
|
||||
M_I Inv 485
|
||||
M_I Store 79
|
||||
M_I Inv 503
|
||||
M_I L1_Replacement 0 <--
|
||||
M_I Fwd_GETX 0 <--
|
||||
M_I Fwd_GETS 0 <--
|
||||
M_I Fwd_GET_INSTR 0 <--
|
||||
M_I WB_Ack 328
|
||||
M_I WB_Ack 357
|
||||
|
||||
E_I Load 0 <--
|
||||
E_I Ifetch 0 <--
|
||||
|
|
@ -316,40 +303,39 @@ Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
|||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR 0
|
||||
L1_GETS 102
|
||||
L1_GETX 773
|
||||
L1_GETS 94
|
||||
L1_GETX 851
|
||||
L1_UPGRADE 0
|
||||
L1_PUTX 513
|
||||
L1_PUTX_old 484
|
||||
L1_PUTX 506
|
||||
L1_PUTX_old 504
|
||||
Fwd_L1_GETX 0
|
||||
Fwd_L1_GETS 0
|
||||
Fwd_L1_GET_INSTR 0
|
||||
L2_Replacement 259
|
||||
L2_Replacement_clean 13081
|
||||
Mem_Data 835
|
||||
Mem_Ack 831
|
||||
WB_Data 485
|
||||
WB_Data_clean 42
|
||||
L2_Replacement 292
|
||||
L2_Replacement_clean 12332
|
||||
Mem_Data 905
|
||||
Mem_Ack 900
|
||||
WB_Data 525
|
||||
WB_Data_clean 34
|
||||
Ack 0
|
||||
Ack_all 4
|
||||
Ack_all 6
|
||||
Unblock 0
|
||||
Unblock_Cancel 0
|
||||
Exclusive_Unblock 860
|
||||
Exclusive_Unblock 925
|
||||
MEM_Inv 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR 0 <--
|
||||
NP L1_GETS 89
|
||||
NP L1_GETX 746
|
||||
NP L1_GETS 86
|
||||
NP L1_GETX 820
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTX_old 104
|
||||
NP L1_PUTX_old 95
|
||||
|
||||
SS L1_GET_INSTR 0 <--
|
||||
SS L1_GETS 0 <--
|
||||
|
|
@ -362,30 +348,30 @@ SS L2_Replacement_clean 0 <--
|
|||
SS MEM_Inv 0 <--
|
||||
|
||||
M L1_GET_INSTR 0 <--
|
||||
M L1_GETS 1
|
||||
M L1_GETX 26
|
||||
M L1_GETS 2
|
||||
M L1_GETX 19
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTX_old 0 <--
|
||||
M L2_Replacement 259
|
||||
M L2_Replacement_clean 41
|
||||
M L2_Replacement 292
|
||||
M L2_Replacement_clean 44
|
||||
M MEM_Inv 0 <--
|
||||
|
||||
MT L1_GET_INSTR 0 <--
|
||||
MT L1_GETS 0 <--
|
||||
MT L1_GETX 0 <--
|
||||
MT L1_PUTX 328
|
||||
MT L1_PUTX 357
|
||||
MT L1_PUTX_old 0 <--
|
||||
MT L2_Replacement 0 <--
|
||||
MT L2_Replacement_clean 531
|
||||
MT L2_Replacement_clean 566
|
||||
MT MEM_Inv 0 <--
|
||||
|
||||
M_I L1_GET_INSTR 0 <--
|
||||
M_I L1_GETS 12
|
||||
M_I L1_GETX 1
|
||||
M_I L1_GETS 6
|
||||
M_I L1_GETX 12
|
||||
M_I L1_UPGRADE 0 <--
|
||||
M_I L1_PUTX 0 <--
|
||||
M_I L1_PUTX_old 107
|
||||
M_I Mem_Ack 831
|
||||
M_I L1_PUTX_old 108
|
||||
M_I Mem_Ack 900
|
||||
M_I MEM_Inv 0 <--
|
||||
|
||||
MT_I L1_GET_INSTR 0 <--
|
||||
|
|
@ -404,10 +390,10 @@ MCT_I L1_GETS 0 <--
|
|||
MCT_I L1_GETX 0 <--
|
||||
MCT_I L1_UPGRADE 0 <--
|
||||
MCT_I L1_PUTX 0 <--
|
||||
MCT_I L1_PUTX_old 135
|
||||
MCT_I WB_Data 485
|
||||
MCT_I WB_Data_clean 42
|
||||
MCT_I Ack_all 4
|
||||
MCT_I L1_PUTX_old 124
|
||||
MCT_I WB_Data 525
|
||||
MCT_I WB_Data_clean 34
|
||||
MCT_I Ack_all 6
|
||||
|
||||
I_I L1_GET_INSTR 0 <--
|
||||
I_I L1_GETS 0 <--
|
||||
|
|
@ -434,8 +420,8 @@ ISS L1_GETX 0 <--
|
|||
ISS L1_PUTX 0 <--
|
||||
ISS L1_PUTX_old 0 <--
|
||||
ISS L2_Replacement 0 <--
|
||||
ISS L2_Replacement_clean 708
|
||||
ISS Mem_Data 89
|
||||
ISS L2_Replacement_clean 481
|
||||
ISS Mem_Data 86
|
||||
ISS MEM_Inv 0 <--
|
||||
|
||||
IS L1_GET_INSTR 0 <--
|
||||
|
|
@ -454,8 +440,8 @@ IM L1_GETX 0 <--
|
|||
IM L1_PUTX 0 <--
|
||||
IM L1_PUTX_old 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L2_Replacement_clean 4762
|
||||
IM Mem_Data 746
|
||||
IM L2_Replacement_clean 4544
|
||||
IM Mem_Data 819
|
||||
IM MEM_Inv 0 <--
|
||||
|
||||
SS_MB L1_GET_INSTR 0 <--
|
||||
|
|
@ -474,12 +460,12 @@ MT_MB L1_GET_INSTR 0 <--
|
|||
MT_MB L1_GETS 0 <--
|
||||
MT_MB L1_GETX 0 <--
|
||||
MT_MB L1_UPGRADE 0 <--
|
||||
MT_MB L1_PUTX 185
|
||||
MT_MB L1_PUTX_old 138
|
||||
MT_MB L1_PUTX 149
|
||||
MT_MB L1_PUTX_old 177
|
||||
MT_MB L2_Replacement 0 <--
|
||||
MT_MB L2_Replacement_clean 7039
|
||||
MT_MB L2_Replacement_clean 6697
|
||||
MT_MB Unblock_Cancel 0 <--
|
||||
MT_MB Exclusive_Unblock 860
|
||||
MT_MB Exclusive_Unblock 925
|
||||
MT_MB MEM_Inv 0 <--
|
||||
|
||||
M_MB L1_GET_INSTR 0 <--
|
||||
|
|
@ -531,37 +517,37 @@ MT_SB Unblock 0 <--
|
|||
MT_SB MEM_Inv 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 1579
|
||||
memory_reads: 835
|
||||
memory_writes: 744
|
||||
memory_refreshes: 744
|
||||
memory_total_request_delays: 998
|
||||
memory_delays_per_request: 0.632046
|
||||
memory_delays_in_input_queue: 152
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 846
|
||||
memory_stalls_for_bank_busy: 106
|
||||
memory_total_requests: 1723
|
||||
memory_reads: 906
|
||||
memory_writes: 817
|
||||
memory_refreshes: 803
|
||||
memory_total_request_delays: 1221
|
||||
memory_delays_per_request: 0.708648
|
||||
memory_delays_in_input_queue: 188
|
||||
memory_delays_behind_head_of_bank_queue: 7
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1026
|
||||
memory_stalls_for_bank_busy: 216
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 69
|
||||
memory_stalls_for_bus: 344
|
||||
memory_stalls_for_arbitration: 86
|
||||
memory_stalls_for_bus: 387
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 255
|
||||
memory_stalls_for_read_read_turnaround: 72
|
||||
accesses_per_bank: 40 45 45 84 59 65 66 49 45 40 57 49 59 54 41 43 42 38 40 46 45 41 27 34 60 52 50 44 60 42 64 53
|
||||
memory_stalls_for_read_write_turnaround: 251
|
||||
memory_stalls_for_read_read_turnaround: 86
|
||||
accesses_per_bank: 63 53 48 94 79 59 62 65 55 57 52 50 48 47 45 40 39 56 50 45 64 47 43 53 58 51 52 54 52 47 50 45
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
Fetch 835
|
||||
Data 744
|
||||
Memory_Data 835
|
||||
Memory_Ack 744
|
||||
Fetch 906
|
||||
Data 817
|
||||
Memory_Data 906
|
||||
Memory_Ack 817
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
CleanReplacement 87
|
||||
CleanReplacement 84
|
||||
|
||||
- Transitions -
|
||||
I Fetch 835
|
||||
I Fetch 906
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -577,20 +563,20 @@ ID_W Memory_Ack 0 <--
|
|||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
|
||||
M Data 744
|
||||
M Data 817
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M CleanReplacement 87
|
||||
M CleanReplacement 84
|
||||
|
||||
IM Fetch 0 <--
|
||||
IM Data 0 <--
|
||||
IM Memory_Data 835
|
||||
IM Memory_Data 906
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
|
||||
MI Fetch 0 <--
|
||||
MI Data 0 <--
|
||||
MI Memory_Ack 744
|
||||
MI Memory_Ack 817
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:06:07
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 27 2010 22:07:35
|
||||
M5 executing on svvint03
|
||||
M5 compiled Mar 18 2010 14:36:48
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:37:00
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 357031 because Ruby Tester completed
|
||||
Exiting @ tick 385311 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213500 # Number of bytes of host memory used
|
||||
host_seconds 0.94 # Real time elapsed on the host
|
||||
host_tick_rate 379801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208556 # Number of bytes of host memory used
|
||||
host_seconds 0.90 # Real time elapsed on the host
|
||||
host_tick_rate 429636 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000357 # Number of seconds simulated
|
||||
sim_ticks 357031 # Number of ticks simulated
|
||||
sim_seconds 0.000385 # Number of seconds simulated
|
||||
sim_ticks 385311 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
|
@ -44,7 +45,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -161,7 +162,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -34,40 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/27/2010 22:10:04
|
||||
Real time: Mar/18/2010 14:40:26
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 2
|
||||
Elapsed_time_in_minutes: 0.0333333
|
||||
Elapsed_time_in_hours: 0.000555556
|
||||
Elapsed_time_in_days: 2.31481e-05
|
||||
Elapsed_time_in_seconds: 7
|
||||
Elapsed_time_in_minutes: 0.116667
|
||||
Elapsed_time_in_hours: 0.00194444
|
||||
Elapsed_time_in_days: 8.10185e-05
|
||||
|
||||
Virtual_time_in_seconds: 1.56
|
||||
Virtual_time_in_minutes: 0.026
|
||||
Virtual_time_in_hours: 0.000433333
|
||||
Virtual_time_in_days: 1.80556e-05
|
||||
Virtual_time_in_seconds: 1.19
|
||||
Virtual_time_in_minutes: 0.0198333
|
||||
Virtual_time_in_hours: 0.000330556
|
||||
Virtual_time_in_days: 1.37731e-05
|
||||
|
||||
Ruby_current_time: 392461
|
||||
Ruby_current_time: 382981
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 392461
|
||||
Ruby_cycles: 382981
|
||||
|
||||
mbytes_resident: 31.2344
|
||||
mbytes_total: 31.2422
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 392462 [ 392462 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 30.7617
|
||||
mbytes_total: 203.789
|
||||
resident_ratio: 0.150987
|
||||
|
||||
ruby_cycles_executed: [ 382982 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L2Cache-0:0
|
||||
|
|
@ -77,13 +66,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1019 average: 15.8302 | standard deviation: 1.11429 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 54 951 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 999 average: 15.8288 | standard deviation: 1.12451 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 52 933 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 40198 count: 1004 average: 6102.55 | standard deviation: 8115.6 | 95 26 84 110 62 53 51 39 30 22 26 14 13 18 16 6 8 10 9 11 7 8 9 7 5 0 4 3 6 3 2 4 3 2 6 2 2 0 1 2 1 0 0 0 1 0 1 1 1 0 2 3 3 2 7 2 6 5 2 3 5 5 6 1 6 4 4 10 5 1 2 3 5 6 7 0 4 3 3 7 5 2 3 1 4 6 7 2 2 5 1 1 3 2 4 3 1 6 2 4 4 4 2 2 0 2 1 3 0 3 2 2 2 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 256 max: 40198 count: 100 average: 5910.08 | standard deviation: 7764.39 | 9 3 10 6 6 2 6 4 3 4 5 2 0 3 3 0 0 0 1 1 2 0 1 1 2 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 2 0 2 1 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 256 max: 33879 count: 904 average: 6123.85 | standard deviation: 8157.38 | 86 23 74 104 56 51 45 35 27 18 21 12 13 15 13 6 8 10 8 10 5 8 8 6 3 0 4 3 5 3 2 2 3 2 6 2 2 0 1 2 1 0 0 0 1 0 1 1 1 0 1 1 2 2 5 2 4 4 1 3 4 4 6 1 6 3 4 9 5 1 1 3 5 6 6 0 4 3 3 6 4 2 3 1 4 6 6 2 2 5 1 1 3 2 4 3 1 6 2 4 3 4 2 1 0 2 1 3 0 2 2 2 2 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 256 max: 35174 count: 984 average: 6099.68 | standard deviation: 8576.16 | 88 23 79 106 74 53 72 37 25 27 17 28 22 12 10 11 8 12 6 5 2 6 2 1 3 5 6 2 2 2 2 0 2 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 4 3 3 1 1 5 2 0 3 1 1 2 0 3 6 1 5 8 0 4 7 3 1 2 4 2 3 2 2 5 3 3 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 1 2 4 1 1 3 0 0 2 2 0 4 1 1 1 2 0 2 3 2 0 2 0 0 3 3 3 2 0 2 1 1 0 0 0 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 256 max: 34854 count: 100 average: 7109.16 | standard deviation: 10187.8 | 11 1 8 10 5 6 6 3 4 6 0 4 5 1 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 256 max: 35174 count: 884 average: 5985.48 | standard deviation: 8373.45 | 77 22 71 96 69 47 66 34 21 21 17 24 17 11 10 10 7 12 6 4 2 6 2 1 2 4 6 2 2 2 2 0 1 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 3 3 3 1 1 5 2 0 3 1 1 1 0 3 5 1 4 7 0 3 6 3 1 2 3 2 3 2 2 3 2 2 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 0 2 2 1 1 3 0 0 1 1 0 4 1 0 1 2 0 2 3 1 0 2 0 0 2 3 3 2 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -115,8 +104,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 1
|
||||
system_time: 0
|
||||
page_reclaims: 6770
|
||||
page_faults: 1970
|
||||
page_reclaims: 8880
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -126,68 +115,68 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0840147
|
||||
links_utilized_percent_switch_0_link_0: 0.0290093 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.13902 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.084797
|
||||
links_utilized_percent_switch_0_link_0: 0.0292998 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.140294 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 885 63720 [ 0 0 885 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.15235
|
||||
links_utilized_percent_switch_1_link_0: 0.0629553 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.241744 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.152981
|
||||
links_utilized_percent_switch_1_link_0: 0.0632212 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.242741 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 1789 14312 [ 909 880 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1878 15024 [ 909 880 89 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1837 14696 [ 895 857 85 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Unblock_Control: 863 6904 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.0720995
|
||||
links_utilized_percent_switch_2_link_0: 0.031398 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.112801 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0719863
|
||||
links_utilized_percent_switch_2_link_0: 0.0313821 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.11259 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 969 7752 [ 0 880 89 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 880 7040 [ 0 880 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 857 6856 [ 0 857 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.164522
|
||||
links_utilized_percent_switch_3_link_0: 0.116152 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.251821 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.125592 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.165204
|
||||
links_utilized_percent_switch_3_link_0: 0.117199 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.252885 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.125528 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 26 1872 [ 0 0 26 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 909 7272 [ 909 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 912 7296 [ 912 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 886 63792 [ 0 0 886 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 909 65448 [ 0 0 909 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 1789 14312 [ 909 880 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Unblock_Control: 910 7280 [ 0 0 910 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 886 7088 [ 0 886 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 791 56952 [ 0 0 791 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 969 7752 [ 0 880 89 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 884 7072 [ 0 0 884 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
|
|
@ -195,7 +184,6 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
|
@ -205,16 +193,15 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 100
|
||||
Load 101
|
||||
Ifetch 0
|
||||
Store 905
|
||||
L1_Replacement 561824
|
||||
Store 887
|
||||
L1_Replacement 547308
|
||||
Own_GETX 0
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
|
|
@ -222,17 +209,17 @@ Fwd_DMA 0
|
|||
Inv 0
|
||||
Ack 0
|
||||
Data 0
|
||||
Exclusive_Data 911
|
||||
Exclusive_Data 898
|
||||
Writeback_Ack 0
|
||||
Writeback_Ack_Data 909
|
||||
Writeback_Ack_Data 895
|
||||
Writeback_Nack 0
|
||||
All_acks 820
|
||||
Use_Timeout 910
|
||||
All_acks 809
|
||||
Use_Timeout 897
|
||||
|
||||
- Transitions -
|
||||
I Load 91
|
||||
I Load 90
|
||||
I Ifetch 0 <--
|
||||
I Store 821
|
||||
I Store 809
|
||||
I L1_Replacement 0 <--
|
||||
I Inv 0 <--
|
||||
|
||||
|
|
@ -262,8 +249,8 @@ M Fwd_DMA 0 <--
|
|||
|
||||
M_W Load 0 <--
|
||||
M_W Ifetch 0 <--
|
||||
M_W Store 1
|
||||
M_W L1_Replacement 3128
|
||||
M_W Store 0 <--
|
||||
M_W L1_Replacement 3013
|
||||
M_W Own_GETX 0 <--
|
||||
M_W Fwd_GETX 0 <--
|
||||
M_W Fwd_GETS 0 <--
|
||||
|
|
@ -271,33 +258,33 @@ M_W Fwd_DMA 0 <--
|
|||
M_W Inv 0 <--
|
||||
M_W Use_Timeout 89
|
||||
|
||||
MM Load 9
|
||||
MM Load 10
|
||||
MM Ifetch 0 <--
|
||||
MM Store 73
|
||||
MM L1_Replacement 820
|
||||
MM Store 66
|
||||
MM L1_Replacement 807
|
||||
MM Fwd_GETX 0 <--
|
||||
MM Fwd_GETS 0 <--
|
||||
MM Fwd_DMA 0 <--
|
||||
|
||||
MM_W Load 0 <--
|
||||
MM_W Load 1
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 10
|
||||
MM_W L1_Replacement 30537
|
||||
MM_W Store 9
|
||||
MM_W L1_Replacement 30209
|
||||
MM_W Own_GETX 0 <--
|
||||
MM_W Fwd_GETX 0 <--
|
||||
MM_W Fwd_GETS 0 <--
|
||||
MM_W Fwd_DMA 0 <--
|
||||
MM_W Inv 0 <--
|
||||
MM_W Use_Timeout 821
|
||||
MM_W Use_Timeout 808
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L1_Replacement 456440
|
||||
IM L1_Replacement 444777
|
||||
IM Inv 0 <--
|
||||
IM Ack 0 <--
|
||||
IM Data 0 <--
|
||||
IM Exclusive_Data 820
|
||||
IM Exclusive_Data 809
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
|
|
@ -313,21 +300,21 @@ SM Exclusive_Data 0 <--
|
|||
OM Load 0 <--
|
||||
OM Ifetch 0 <--
|
||||
OM Store 0 <--
|
||||
OM L1_Replacement 16198
|
||||
OM L1_Replacement 17359
|
||||
OM Own_GETX 0 <--
|
||||
OM Fwd_GETX 0 <--
|
||||
OM Fwd_GETS 0 <--
|
||||
OM Fwd_DMA 0 <--
|
||||
OM Ack 0 <--
|
||||
OM All_acks 820
|
||||
OM All_acks 809
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L1_Replacement 54612
|
||||
IS L1_Replacement 51054
|
||||
IS Inv 0 <--
|
||||
IS Data 0 <--
|
||||
IS Exclusive_Data 91
|
||||
IS Exclusive_Data 89
|
||||
|
||||
SI Load 0 <--
|
||||
SI Ifetch 0 <--
|
||||
|
|
@ -353,13 +340,13 @@ OI Writeback_Nack 0 <--
|
|||
|
||||
MI Load 0 <--
|
||||
MI Ifetch 0 <--
|
||||
MI Store 0 <--
|
||||
MI Store 3
|
||||
MI L1_Replacement 0 <--
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Fwd_GETS 0 <--
|
||||
MI Fwd_DMA 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
MI Writeback_Ack_Data 909
|
||||
MI Writeback_Ack_Data 895
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
II Load 0 <--
|
||||
|
|
@ -377,16 +364,15 @@ Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
|||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GETS 91
|
||||
L1_GETX 821
|
||||
L1_GETS 132
|
||||
L1_GETX 846
|
||||
L1_PUTO 0
|
||||
L1_PUTX 2498
|
||||
L1_PUTX 2074
|
||||
L1_PUTS_only 0
|
||||
L1_PUTS 0
|
||||
Fwd_GETX 0
|
||||
|
|
@ -396,20 +382,20 @@ Own_GETX 0
|
|||
Inv 0
|
||||
IntAck 0
|
||||
ExtAck 0
|
||||
All_Acks 795
|
||||
Data 795
|
||||
Data_Exclusive 91
|
||||
L1_WBCLEANDATA 89
|
||||
L1_WBDIRTYDATA 820
|
||||
Writeback_Ack 880
|
||||
All_Acks 777
|
||||
Data 777
|
||||
Data_Exclusive 86
|
||||
L1_WBCLEANDATA 85
|
||||
L1_WBDIRTYDATA 810
|
||||
Writeback_Ack 857
|
||||
Writeback_Nack 0
|
||||
Unblock 0
|
||||
Exclusive_Unblock 910
|
||||
L2_Replacement 880
|
||||
Exclusive_Unblock 898
|
||||
L2_Replacement 857
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS 91
|
||||
NP L1_GETX 795
|
||||
NP L1_GETS 86
|
||||
NP L1_GETX 777
|
||||
NP L1_PUTO 0 <--
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTS 0 <--
|
||||
|
|
@ -435,7 +421,7 @@ ILS L2_Replacement 0 <--
|
|||
ILX L1_GETS 0 <--
|
||||
ILX L1_GETX 0 <--
|
||||
ILX L1_PUTO 0 <--
|
||||
ILX L1_PUTX 909
|
||||
ILX L1_PUTX 895
|
||||
ILX L1_PUTS_only 0 <--
|
||||
ILX L1_PUTS 0 <--
|
||||
ILX Fwd_GETX 0 <--
|
||||
|
|
@ -534,15 +520,15 @@ SLS L1_PUTS 0 <--
|
|||
SLS Inv 0 <--
|
||||
SLS L2_Replacement 0 <--
|
||||
|
||||
M L1_GETS 0 <--
|
||||
M L1_GETX 26
|
||||
M L1_GETS 3
|
||||
M L1_GETX 32
|
||||
M L1_PUTO 0 <--
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTS 0 <--
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_DMA 0 <--
|
||||
M L2_Replacement 880
|
||||
M L2_Replacement 857
|
||||
|
||||
IFGX L1_GETS 0 <--
|
||||
IFGX L1_GETX 0 <--
|
||||
|
|
@ -802,8 +788,8 @@ ILXW Fwd_GETS 0 <--
|
|||
ILXW Fwd_DMA 0 <--
|
||||
ILXW Inv 0 <--
|
||||
ILXW Data 0 <--
|
||||
ILXW L1_WBCLEANDATA 89
|
||||
ILXW L1_WBDIRTYDATA 820
|
||||
ILXW L1_WBCLEANDATA 85
|
||||
ILXW L1_WBDIRTYDATA 810
|
||||
ILXW Unblock 0 <--
|
||||
ILXW L2_Replacement 0 <--
|
||||
|
||||
|
|
@ -891,7 +877,7 @@ IFLXO L2_Replacement 0 <--
|
|||
IGS L1_GETS 0 <--
|
||||
IGS L1_GETX 0 <--
|
||||
IGS L1_PUTO 0 <--
|
||||
IGS L1_PUTX 136
|
||||
IGS L1_PUTX 122
|
||||
IGS L1_PUTS_only 0 <--
|
||||
IGS L1_PUTS 0 <--
|
||||
IGS Fwd_GETX 0 <--
|
||||
|
|
@ -900,9 +886,9 @@ IGS Fwd_DMA 0 <--
|
|||
IGS Own_GETX 0 <--
|
||||
IGS Inv 0 <--
|
||||
IGS Data 0 <--
|
||||
IGS Data_Exclusive 91
|
||||
IGS Data_Exclusive 86
|
||||
IGS Unblock 0 <--
|
||||
IGS Exclusive_Unblock 90
|
||||
IGS Exclusive_Unblock 86
|
||||
IGS L2_Replacement 0 <--
|
||||
|
||||
IGM L1_GETS 0 <--
|
||||
|
|
@ -917,7 +903,7 @@ IGM Fwd_DMA 0 <--
|
|||
IGM Own_GETX 0 <--
|
||||
IGM Inv 0 <--
|
||||
IGM ExtAck 0 <--
|
||||
IGM Data 795
|
||||
IGM Data 777
|
||||
IGM Data_Exclusive 0 <--
|
||||
IGM L2_Replacement 0 <--
|
||||
|
||||
|
|
@ -938,7 +924,7 @@ IGMLS L2_Replacement 0 <--
|
|||
IGMO L1_GETS 0 <--
|
||||
IGMO L1_GETX 0 <--
|
||||
IGMO L1_PUTO 0 <--
|
||||
IGMO L1_PUTX 1443
|
||||
IGMO L1_PUTX 1052
|
||||
IGMO L1_PUTS_only 0 <--
|
||||
IGMO L1_PUTS 0 <--
|
||||
IGMO Fwd_GETX 0 <--
|
||||
|
|
@ -946,8 +932,8 @@ IGMO Fwd_GETS 0 <--
|
|||
IGMO Fwd_DMA 0 <--
|
||||
IGMO Own_GETX 0 <--
|
||||
IGMO ExtAck 0 <--
|
||||
IGMO All_Acks 795
|
||||
IGMO Exclusive_Unblock 794
|
||||
IGMO All_Acks 777
|
||||
IGMO Exclusive_Unblock 777
|
||||
IGMO L2_Replacement 0 <--
|
||||
|
||||
IGMIO L1_GETS 0 <--
|
||||
|
|
@ -1020,14 +1006,14 @@ II All_Acks 0 <--
|
|||
MM L1_GETS 0 <--
|
||||
MM L1_GETX 0 <--
|
||||
MM L1_PUTO 0 <--
|
||||
MM L1_PUTX 10
|
||||
MM L1_PUTX 5
|
||||
MM L1_PUTS_only 0 <--
|
||||
MM L1_PUTS 0 <--
|
||||
MM Fwd_GETX 0 <--
|
||||
MM Fwd_GETS 0 <--
|
||||
MM Fwd_DMA 0 <--
|
||||
MM Inv 0 <--
|
||||
MM Exclusive_Unblock 26
|
||||
MM Exclusive_Unblock 32
|
||||
MM L2_Replacement 0 <--
|
||||
|
||||
SS L1_GETS 0 <--
|
||||
|
|
@ -1054,7 +1040,7 @@ OO Fwd_GETS 0 <--
|
|||
OO Fwd_DMA 0 <--
|
||||
OO Inv 0 <--
|
||||
OO Unblock 0 <--
|
||||
OO Exclusive_Unblock 0 <--
|
||||
OO Exclusive_Unblock 3
|
||||
OO L2_Replacement 0 <--
|
||||
|
||||
OLSS L1_GETS 0 <--
|
||||
|
|
@ -1109,8 +1095,8 @@ OI Writeback_Ack 0 <--
|
|||
OI Writeback_Nack 0 <--
|
||||
OI L2_Replacement 0 <--
|
||||
|
||||
MI L1_GETS 0 <--
|
||||
MI L1_GETX 0 <--
|
||||
MI L1_GETS 43
|
||||
MI L1_GETX 37
|
||||
MI L1_PUTO 0 <--
|
||||
MI L1_PUTX 0 <--
|
||||
MI L1_PUTS_only 0 <--
|
||||
|
|
@ -1118,7 +1104,7 @@ MI L1_PUTS 0 <--
|
|||
MI Fwd_GETX 0 <--
|
||||
MI Fwd_GETS 0 <--
|
||||
MI Fwd_DMA 0 <--
|
||||
MI Writeback_Ack 880
|
||||
MI Writeback_Ack 857
|
||||
MI L2_Replacement 0 <--
|
||||
|
||||
MII L1_GETS 0 <--
|
||||
|
|
@ -1155,50 +1141,50 @@ ILSI Writeback_Ack 0 <--
|
|||
ILSI L2_Replacement 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 1677
|
||||
memory_reads: 886
|
||||
memory_writes: 790
|
||||
memory_refreshes: 818
|
||||
memory_total_request_delays: 692
|
||||
memory_delays_per_request: 0.412642
|
||||
memory_delays_in_input_queue: 87
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 605
|
||||
memory_stalls_for_bank_busy: 167
|
||||
memory_total_requests: 1635
|
||||
memory_reads: 863
|
||||
memory_writes: 772
|
||||
memory_refreshes: 798
|
||||
memory_total_request_delays: 689
|
||||
memory_delays_per_request: 0.421407
|
||||
memory_delays_in_input_queue: 101
|
||||
memory_delays_behind_head_of_bank_queue: 15
|
||||
memory_delays_stalled_at_head_of_bank_queue: 573
|
||||
memory_stalls_for_bank_busy: 170
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 43
|
||||
memory_stalls_for_bus: 243
|
||||
memory_stalls_for_arbitration: 35
|
||||
memory_stalls_for_bus: 229
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 87
|
||||
memory_stalls_for_read_read_turnaround: 65
|
||||
accesses_per_bank: 42 41 55 101 73 61 50 48 47 43 39 61 48 55 46 42 57 58 54 52 60 39 57 54 37 53 55 57 48 45 60 39
|
||||
memory_stalls_for_read_write_turnaround: 73
|
||||
memory_stalls_for_read_read_turnaround: 66
|
||||
accesses_per_bank: 29 65 49 82 66 72 63 36 52 53 42 57 62 51 33 45 44 34 49 49 50 37 55 51 60 45 63 61 47 41 45 47
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 795
|
||||
GETS 91
|
||||
PUTX 880
|
||||
GETX 782
|
||||
GETS 98
|
||||
PUTX 857
|
||||
PUTO 0
|
||||
PUTO_SHARERS 0
|
||||
Unblock 0
|
||||
Last_Unblock 0
|
||||
Exclusive_Unblock 884
|
||||
Clean_Writeback 89
|
||||
Dirty_Writeback 791
|
||||
Memory_Data 886
|
||||
Memory_Ack 790
|
||||
Exclusive_Unblock 862
|
||||
Clean_Writeback 85
|
||||
Dirty_Writeback 772
|
||||
Memory_Data 863
|
||||
Memory_Ack 772
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Data 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 795
|
||||
I GETS 91
|
||||
I GETX 777
|
||||
I GETS 86
|
||||
I PUTX 0 <--
|
||||
I PUTO 0 <--
|
||||
I Memory_Data 0 <--
|
||||
I Memory_Ack 790
|
||||
I Memory_Ack 767
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -1223,7 +1209,7 @@ O DMA_WRITE 0 <--
|
|||
|
||||
M GETX 0 <--
|
||||
M GETS 0 <--
|
||||
M PUTX 880
|
||||
M PUTX 857
|
||||
M PUTO 0 <--
|
||||
M PUTO_SHARERS 0 <--
|
||||
M Memory_Data 0 <--
|
||||
|
|
@ -1237,9 +1223,9 @@ IS PUTX 0 <--
|
|||
IS PUTO 0 <--
|
||||
IS PUTO_SHARERS 0 <--
|
||||
IS Unblock 0 <--
|
||||
IS Exclusive_Unblock 90
|
||||
IS Memory_Data 91
|
||||
IS Memory_Ack 0 <--
|
||||
IS Exclusive_Unblock 86
|
||||
IS Memory_Data 86
|
||||
IS Memory_Ack 1
|
||||
IS DMA_READ 0 <--
|
||||
IS DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -1284,21 +1270,21 @@ MM GETS 0 <--
|
|||
MM PUTX 0 <--
|
||||
MM PUTO 0 <--
|
||||
MM PUTO_SHARERS 0 <--
|
||||
MM Exclusive_Unblock 794
|
||||
MM Memory_Data 795
|
||||
MM Memory_Ack 0 <--
|
||||
MM Exclusive_Unblock 776
|
||||
MM Memory_Data 777
|
||||
MM Memory_Ack 4
|
||||
MM DMA_READ 0 <--
|
||||
MM DMA_WRITE 0 <--
|
||||
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI GETX 5
|
||||
MI GETS 12
|
||||
MI PUTX 0 <--
|
||||
MI PUTO 0 <--
|
||||
MI PUTO_SHARERS 0 <--
|
||||
MI Unblock 0 <--
|
||||
MI Clean_Writeback 89
|
||||
MI Dirty_Writeback 791
|
||||
MI Clean_Writeback 85
|
||||
MI Dirty_Writeback 772
|
||||
MI Memory_Data 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:09:32
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 27 2010 22:10:02
|
||||
M5 executing on svvint05
|
||||
M5 compiled Mar 18 2010 14:39:50
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:40:19
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 392461 because Ruby Tester completed
|
||||
Exiting @ tick 382981 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213656 # Number of bytes of host memory used
|
||||
host_seconds 1.32 # Real time elapsed on the host
|
||||
host_tick_rate 297317 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208684 # Number of bytes of host memory used
|
||||
host_seconds 6.96 # Real time elapsed on the host
|
||||
host_tick_rate 55013 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000392 # Number of seconds simulated
|
||||
sim_ticks 392461 # Number of ticks simulated
|
||||
sim_seconds 0.000383 # Number of seconds simulated
|
||||
sim_ticks 382981 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
|
@ -44,7 +45,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -171,7 +172,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ topology:
|
|||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, unordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/27/2010 22:01:59
|
||||
Real time: Mar/18/2010 14:58:52
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.6
|
||||
Virtual_time_in_minutes: 0.01
|
||||
Virtual_time_in_hours: 0.000166667
|
||||
Virtual_time_in_days: 6.94444e-06
|
||||
Virtual_time_in_seconds: 0.69
|
||||
Virtual_time_in_minutes: 0.0115
|
||||
Virtual_time_in_hours: 0.000191667
|
||||
Virtual_time_in_days: 7.98611e-06
|
||||
|
||||
Ruby_current_time: 282171
|
||||
Ruby_current_time: 275491
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 282171
|
||||
Ruby_cycles: 275491
|
||||
|
||||
mbytes_resident: 31.1484
|
||||
mbytes_total: 31.1562
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 282172 [ 282172 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 30.7305
|
||||
mbytes_total: 203.652
|
||||
resident_ratio: 0.150935
|
||||
|
||||
ruby_cycles_executed: [ 275492 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -77,13 +66,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1009 average: 15.8355 | standard deviation: 1.11759 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 47 948 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 981 average: 15.8389 | standard deviation: 1.13074 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 39 928 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 256 max: 28196 count: 994 average: 4457.39 | standard deviation: 6147.87 | 100 90 146 90 76 63 38 29 21 17 11 10 8 10 15 7 4 1 2 1 1 0 0 4 1 1 5 2 1 7 5 4 0 1 3 1 0 3 1 4 3 5 4 5 5 7 6 4 6 8 11 7 5 8 5 9 7 6 5 0 4 4 5 5 5 3 3 10 7 7 2 4 4 4 3 2 1 6 1 1 0 2 0 0 1 0 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 256 max: 26957 count: 100 average: 4118.53 | standard deviation: 6450.59 | 11 9 15 11 8 7 5 4 1 3 2 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 1 1 1 0 2 0 0 0 0 1 1 0 0 0 0 1 0 0 0 3 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 256 max: 28196 count: 894 average: 4495.3 | standard deviation: 6115.67 | 89 81 131 79 68 56 33 25 20 14 9 9 8 10 13 6 4 1 2 1 1 0 0 4 1 1 5 2 1 7 5 4 0 1 3 1 0 3 1 4 2 5 3 5 5 7 6 4 5 7 10 7 4 7 4 9 5 6 5 0 4 3 4 5 5 3 3 9 7 7 2 1 4 3 3 1 1 6 1 1 0 2 0 0 1 0 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 128 max: 24779 count: 966 average: 4458.37 | standard deviation: 6768.43 | 97 8 26 62 82 65 44 31 43 37 32 21 22 21 13 17 18 13 11 4 12 15 6 1 6 11 3 4 7 3 4 1 4 5 3 4 3 2 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 2 1 1 0 1 1 1 1 3 0 0 1 2 0 1 0 0 2 1 0 0 0 1 2 1 0 1 0 2 3 1 0 1 2 0 1 1 7 1 0 4 3 0 3 3 5 2 1 2 0 3 1 2 3 1 0 5 3 1 4 2 4 1 2 3 0 2 3 1 1 1 2 6 0 0 2 0 4 3 1 2 3 1 3 2 2 2 2 3 1 5 0 2 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 128 max: 22427 count: 100 average: 4703.38 | standard deviation: 6898.45 | 12 2 2 7 12 6 4 3 6 3 1 1 1 3 1 2 2 0 1 0 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 2 2 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ]
|
||||
miss_latency_3: [binsize: 128 max: 24779 count: 866 average: 4430.08 | standard deviation: 6756.74 | 85 6 24 55 70 59 40 28 37 34 31 20 21 18 12 15 16 13 10 4 11 13 6 1 4 11 3 4 7 3 4 1 3 5 3 3 3 1 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 1 1 1 0 1 1 1 1 3 0 0 1 1 0 1 0 0 1 1 0 0 0 1 2 1 0 1 0 2 2 1 0 1 2 0 1 1 5 1 0 2 1 0 2 3 4 1 1 2 0 2 1 1 3 1 0 5 3 1 4 1 3 1 2 3 0 1 3 1 1 1 1 5 0 0 2 0 4 3 0 2 3 1 3 2 1 2 2 3 1 5 0 1 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -115,8 +104,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6756
|
||||
page_faults: 1961
|
||||
page_reclaims: 8875
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -126,69 +115,66 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.108507
|
||||
links_utilized_percent_switch_0_link_0: 0.0403656 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.176648 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.110194
|
||||
links_utilized_percent_switch_0_link_0: 0.0410177 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.179371 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 55 3960 [ 0 55 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 955 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 932 67104 [ 0 0 0 0 932 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.095051
|
||||
links_utilized_percent_switch_1_link_0: 0.0414509 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.148651 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.092866
|
||||
links_utilized_percent_switch_1_link_0: 0.0408816 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.14485 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 900 64800 [ 0 900 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 12 864 [ 0 12 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 779 56088 [ 0 779 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 729 52488 [ 0 0 0 0 729 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.0888003
|
||||
links_utilized_percent_switch_2_link_0: 0.0375792 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.140021 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0881086
|
||||
links_utilized_percent_switch_2_link_0: 0.0370475 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.13917 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 871 62712 [ 0 871 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 7 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 845 60840 [ 0 0 0 0 845 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.157151
|
||||
links_utilized_percent_switch_3_link_0: 0.155331 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.165804 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.150317 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.156502
|
||||
links_utilized_percent_switch_3_link_0: 0.157791 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.163526 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.14819 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 883 63576 [ 0 883 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 36 2592 [ 0 36 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 55 3960 [ 0 55 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 907 7256 [ 0 0 0 0 907 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 900 64800 [ 0 900 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 4 32 [ 0 4 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 0 871 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 13 936 [ 0 13 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 786 56592 [ 0 786 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 75 600 [ 0 75 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 346 2768 [ 0 0 346 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
|
|
@ -196,7 +182,6 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
|
@ -206,7 +191,6 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
|
@ -214,11 +198,11 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
|||
- Event Counts -
|
||||
Load 100
|
||||
Ifetch 0
|
||||
Store 895
|
||||
L1_Replacement 404448
|
||||
Data_Shared 4
|
||||
Store 867
|
||||
L1_Replacement 395000
|
||||
Data_Shared 1
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 970
|
||||
Data_All_Tokens 965
|
||||
Ack 0
|
||||
Ack_All_Tokens 0
|
||||
Transient_GETX 0
|
||||
|
|
@ -230,18 +214,18 @@ Transient_Local_GETS_Last_Token 0
|
|||
Persistent_GETX 0
|
||||
Persistent_GETS 0
|
||||
Own_Lock_or_Unlock 346
|
||||
Request_Timeout 644
|
||||
Request_Timeout 545
|
||||
Use_TimeoutStarverX 0
|
||||
Use_TimeoutStarverS 0
|
||||
Use_TimeoutNoStarvers 901
|
||||
Use_TimeoutNoStarvers 867
|
||||
|
||||
- Transitions -
|
||||
NP Load 90
|
||||
NP Load 88
|
||||
NP Ifetch 0 <--
|
||||
NP Store 817
|
||||
NP Store 781
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
NP Data_All_Tokens 68
|
||||
NP Data_All_Tokens 97
|
||||
NP Ack 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_Local_GETX 0 <--
|
||||
|
|
@ -249,7 +233,7 @@ NP Transient_GETS 0 <--
|
|||
NP Transient_Local_GETS 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 175
|
||||
NP Own_Lock_or_Unlock 171
|
||||
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
|
|
@ -271,8 +255,8 @@ I Own_Lock_or_Unlock 0 <--
|
|||
|
||||
S Load 0 <--
|
||||
S Ifetch 0 <--
|
||||
S Store 0 <--
|
||||
S L1_Replacement 4
|
||||
S Store 1
|
||||
S L1_Replacement 0 <--
|
||||
S Data_Shared 0 <--
|
||||
S Data_Owner 0 <--
|
||||
S Data_All_Tokens 0 <--
|
||||
|
|
@ -308,64 +292,64 @@ O Own_Lock_or_Unlock 0 <--
|
|||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M L1_Replacement 85
|
||||
M L1_Replacement 86
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_Local_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M Transient_Local_GETS 0 <--
|
||||
M Persistent_GETX 0 <--
|
||||
M Persistent_GETS 0 <--
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
M Own_Lock_or_Unlock 2
|
||||
|
||||
MM Load 8
|
||||
MM Load 12
|
||||
MM Ifetch 0 <--
|
||||
MM Store 66
|
||||
MM L1_Replacement 815
|
||||
MM Store 74
|
||||
MM L1_Replacement 780
|
||||
MM Transient_GETX 0 <--
|
||||
MM Transient_Local_GETX 0 <--
|
||||
MM Transient_GETS 0 <--
|
||||
MM Transient_Local_GETS 0 <--
|
||||
MM Persistent_GETX 0 <--
|
||||
MM Persistent_GETS 0 <--
|
||||
MM Own_Lock_or_Unlock 24
|
||||
MM Own_Lock_or_Unlock 17
|
||||
|
||||
M_W Load 1
|
||||
M_W Load 0 <--
|
||||
M_W Ifetch 0 <--
|
||||
M_W Store 0 <--
|
||||
M_W L1_Replacement 3682
|
||||
M_W L1_Replacement 2958
|
||||
M_W Transient_GETX 0 <--
|
||||
M_W Transient_Local_GETX 0 <--
|
||||
M_W Transient_GETS 0 <--
|
||||
M_W Transient_Local_GETS 0 <--
|
||||
M_W Persistent_GETX 0 <--
|
||||
M_W Persistent_GETS 0 <--
|
||||
M_W Own_Lock_or_Unlock 3
|
||||
M_W Own_Lock_or_Unlock 2
|
||||
M_W Use_TimeoutStarverX 0 <--
|
||||
M_W Use_TimeoutStarverS 0 <--
|
||||
M_W Use_TimeoutNoStarvers 85
|
||||
M_W Use_TimeoutNoStarvers 86
|
||||
|
||||
MM_W Load 1
|
||||
MM_W Load 0 <--
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 12
|
||||
MM_W L1_Replacement 29932
|
||||
MM_W Store 11
|
||||
MM_W L1_Replacement 29196
|
||||
MM_W Transient_GETX 0 <--
|
||||
MM_W Transient_Local_GETX 0 <--
|
||||
MM_W Transient_GETS 0 <--
|
||||
MM_W Transient_Local_GETS 0 <--
|
||||
MM_W Persistent_GETX 0 <--
|
||||
MM_W Persistent_GETS 0 <--
|
||||
MM_W Own_Lock_or_Unlock 21
|
||||
MM_W Own_Lock_or_Unlock 33
|
||||
MM_W Use_TimeoutStarverX 0 <--
|
||||
MM_W Use_TimeoutStarverS 0 <--
|
||||
MM_W Use_TimeoutNoStarvers 816
|
||||
MM_W Use_TimeoutNoStarvers 781
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L1_Replacement 334259
|
||||
IM L1_Replacement 329936
|
||||
IM Data_Shared 0 <--
|
||||
IM Data_Owner 0 <--
|
||||
IM Data_All_Tokens 816
|
||||
IM Data_All_Tokens 780
|
||||
IM Ack 0 <--
|
||||
IM Transient_GETX 0 <--
|
||||
IM Transient_Local_GETX 0 <--
|
||||
|
|
@ -375,8 +359,8 @@ IM Transient_GETS_Last_Token 0 <--
|
|||
IM Transient_Local_GETS_Last_Token 0 <--
|
||||
IM Persistent_GETX 0 <--
|
||||
IM Persistent_GETS 0 <--
|
||||
IM Own_Lock_or_Unlock 109
|
||||
IM Request_Timeout 597
|
||||
IM Own_Lock_or_Unlock 112
|
||||
IM Request_Timeout 465
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
|
|
@ -384,7 +368,7 @@ SM Store 0 <--
|
|||
SM L1_Replacement 0 <--
|
||||
SM Data_Shared 0 <--
|
||||
SM Data_Owner 0 <--
|
||||
SM Data_All_Tokens 0 <--
|
||||
SM Data_All_Tokens 1
|
||||
SM Ack 0 <--
|
||||
SM Transient_GETX 0 <--
|
||||
SM Transient_Local_GETX 0 <--
|
||||
|
|
@ -419,10 +403,10 @@ OM Request_Timeout 0 <--
|
|||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L1_Replacement 35671
|
||||
IS Data_Shared 4
|
||||
IS L1_Replacement 32044
|
||||
IS Data_Shared 1
|
||||
IS Data_Owner 0 <--
|
||||
IS Data_All_Tokens 86
|
||||
IS Data_All_Tokens 87
|
||||
IS Ack 0 <--
|
||||
IS Transient_GETX 0 <--
|
||||
IS Transient_Local_GETX 0 <--
|
||||
|
|
@ -432,8 +416,8 @@ IS Transient_GETS_Last_Token 0 <--
|
|||
IS Transient_Local_GETS_Last_Token 0 <--
|
||||
IS Persistent_GETX 0 <--
|
||||
IS Persistent_GETS 0 <--
|
||||
IS Own_Lock_or_Unlock 14
|
||||
IS Request_Timeout 47
|
||||
IS Own_Lock_or_Unlock 9
|
||||
IS Request_Timeout 80
|
||||
|
||||
I_L Load 0 <--
|
||||
I_L Ifetch 0 <--
|
||||
|
|
@ -534,42 +518,41 @@ Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
|||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GETS 90
|
||||
L1_GETS 88
|
||||
L1_GETS_Last_Token 0
|
||||
L1_GETX 817
|
||||
L1_GETX 782
|
||||
L1_INV 0
|
||||
Transient_GETX 0
|
||||
Transient_GETS 0
|
||||
Transient_GETS_Last_Token 0
|
||||
L2_Replacement 821
|
||||
Writeback_Tokens 1
|
||||
L2_Replacement 781
|
||||
Writeback_Tokens 0
|
||||
Writeback_Shared_Data 0
|
||||
Writeback_All_Tokens 903
|
||||
Writeback_All_Tokens 866
|
||||
Writeback_Owned 0
|
||||
Data_Shared 0
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 0
|
||||
Ack 0
|
||||
Ack_All_Tokens 0
|
||||
Persistent_GETX 155
|
||||
Persistent_GETS 18
|
||||
Persistent_GETX 161
|
||||
Persistent_GETS 12
|
||||
Own_Lock_or_Unlock 173
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS 86
|
||||
NP L1_GETX 785
|
||||
NP L1_GETS 87
|
||||
NP L1_GETX 756
|
||||
NP L1_INV 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_GETS 0 <--
|
||||
NP Writeback_Tokens 1
|
||||
NP Writeback_Tokens 0 <--
|
||||
NP Writeback_Shared_Data 0 <--
|
||||
NP Writeback_All_Tokens 823
|
||||
NP Writeback_All_Tokens 783
|
||||
NP Writeback_Owned 0 <--
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
|
|
@ -577,7 +560,7 @@ NP Data_All_Tokens 0 <--
|
|||
NP Ack 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 161
|
||||
NP Own_Lock_or_Unlock 145
|
||||
|
||||
I L1_GETS 0 <--
|
||||
I L1_GETS_Last_Token 0 <--
|
||||
|
|
@ -586,10 +569,10 @@ I L1_INV 0 <--
|
|||
I Transient_GETX 0 <--
|
||||
I Transient_GETS 0 <--
|
||||
I Transient_GETS_Last_Token 0 <--
|
||||
I L2_Replacement 16
|
||||
I L2_Replacement 30
|
||||
I Writeback_Tokens 0 <--
|
||||
I Writeback_Shared_Data 0 <--
|
||||
I Writeback_All_Tokens 29
|
||||
I Writeback_All_Tokens 24
|
||||
I Writeback_Owned 0 <--
|
||||
I Data_Shared 0 <--
|
||||
I Data_Owner 0 <--
|
||||
|
|
@ -621,15 +604,15 @@ S Own_Lock_or_Unlock 0 <--
|
|||
|
||||
O L1_GETS 0 <--
|
||||
O L1_GETS_Last_Token 0 <--
|
||||
O L1_GETX 0 <--
|
||||
O L1_GETX 1
|
||||
O L1_INV 0 <--
|
||||
O Transient_GETX 0 <--
|
||||
O Transient_GETS 0 <--
|
||||
O Transient_GETS_Last_Token 0 <--
|
||||
O L2_Replacement 1
|
||||
O L2_Replacement 0 <--
|
||||
O Writeback_Tokens 0 <--
|
||||
O Writeback_Shared_Data 0 <--
|
||||
O Writeback_All_Tokens 3
|
||||
O Writeback_All_Tokens 0 <--
|
||||
O Data_Shared 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Ack 0 <--
|
||||
|
|
@ -638,14 +621,14 @@ O Persistent_GETX 0 <--
|
|||
O Persistent_GETS 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M L1_GETS 4
|
||||
M L1_GETX 32
|
||||
M L1_GETS 1
|
||||
M L1_GETX 25
|
||||
M L1_INV 0 <--
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M L2_Replacement 804
|
||||
M Persistent_GETX 9
|
||||
M Persistent_GETS 3
|
||||
M L2_Replacement 751
|
||||
M Persistent_GETX 26
|
||||
M Persistent_GETS 2
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I_L L1_GETS 0 <--
|
||||
|
|
@ -657,15 +640,15 @@ I_L Transient_GETS_Last_Token 0 <--
|
|||
I_L L2_Replacement 0 <--
|
||||
I_L Writeback_Tokens 0 <--
|
||||
I_L Writeback_Shared_Data 0 <--
|
||||
I_L Writeback_All_Tokens 48
|
||||
I_L Writeback_All_Tokens 59
|
||||
I_L Writeback_Owned 0 <--
|
||||
I_L Data_Shared 0 <--
|
||||
I_L Data_Owner 0 <--
|
||||
I_L Data_All_Tokens 0 <--
|
||||
I_L Ack 0 <--
|
||||
I_L Persistent_GETX 146
|
||||
I_L Persistent_GETS 15
|
||||
I_L Own_Lock_or_Unlock 12
|
||||
I_L Persistent_GETX 135
|
||||
I_L Persistent_GETS 10
|
||||
I_L Own_Lock_or_Unlock 28
|
||||
|
||||
S_L L1_GETS 0 <--
|
||||
S_L L1_GETS_Last_Token 0 <--
|
||||
|
|
@ -688,86 +671,86 @@ S_L Persistent_GETS 0 <--
|
|||
S_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 1662
|
||||
memory_reads: 871
|
||||
memory_writes: 791
|
||||
memory_refreshes: 588
|
||||
memory_total_request_delays: 1142
|
||||
memory_delays_per_request: 0.687124
|
||||
memory_delays_in_input_queue: 162
|
||||
memory_delays_behind_head_of_bank_queue: 4
|
||||
memory_delays_stalled_at_head_of_bank_queue: 976
|
||||
memory_stalls_for_bank_busy: 236
|
||||
memory_total_requests: 1599
|
||||
memory_reads: 842
|
||||
memory_writes: 756
|
||||
memory_refreshes: 574
|
||||
memory_total_request_delays: 1024
|
||||
memory_delays_per_request: 0.6404
|
||||
memory_delays_in_input_queue: 172
|
||||
memory_delays_behind_head_of_bank_queue: 2
|
||||
memory_delays_stalled_at_head_of_bank_queue: 850
|
||||
memory_stalls_for_bank_busy: 171
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 70
|
||||
memory_stalls_for_bus: 373
|
||||
memory_stalls_for_arbitration: 68
|
||||
memory_stalls_for_bus: 354
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 222
|
||||
memory_stalls_for_read_read_turnaround: 75
|
||||
accesses_per_bank: 61 57 44 91 60 64 57 46 59 42 55 67 56 38 38 46 42 46 55 49 45 45 38 58 35 54 39 48 56 43 72 56
|
||||
memory_stalls_for_read_write_turnaround: 184
|
||||
memory_stalls_for_read_read_turnaround: 73
|
||||
accesses_per_bank: 49 42 55 87 81 71 69 52 62 53 36 48 32 44 42 54 55 42 39 43 42 41 41 55 58 45 50 41 45 33 49 43
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 844
|
||||
GETS 86
|
||||
GETX 771
|
||||
GETS 89
|
||||
Lockdown 173
|
||||
Unlockdown 173
|
||||
Own_Lock_or_Unlock 0
|
||||
Data_Owner 1
|
||||
Data_All_Tokens 798
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 766
|
||||
Ack_Owner 0
|
||||
Ack_Owner_All_Tokens 74
|
||||
Ack_Owner_All_Tokens 81
|
||||
Tokens 0
|
||||
Ack_All_Tokens 1
|
||||
Ack_All_Tokens 0
|
||||
Request_Timeout 0
|
||||
Memory_Data 870
|
||||
Memory_Ack 790
|
||||
Memory_Data 842
|
||||
Memory_Ack 755
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
DMA_WRITE_All_Tokens 0
|
||||
|
||||
- Transitions -
|
||||
O GETX 782
|
||||
O GETS 86
|
||||
O Lockdown 3
|
||||
O GETX 751
|
||||
O GETS 87
|
||||
O Lockdown 5
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
O Data_Owner 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Tokens 0 <--
|
||||
O Ack_All_Tokens 1
|
||||
O Ack_All_Tokens 0 <--
|
||||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
O DMA_WRITE_All_Tokens 0 <--
|
||||
|
||||
NO GETX 0 <--
|
||||
NO GETX 4
|
||||
NO GETS 0 <--
|
||||
NO Lockdown 154
|
||||
NO Lockdown 151
|
||||
NO Own_Lock_or_Unlock 0 <--
|
||||
NO Data_Owner 1
|
||||
NO Data_All_Tokens 790
|
||||
NO Data_Owner 0 <--
|
||||
NO Data_All_Tokens 756
|
||||
NO Ack_Owner 0 <--
|
||||
NO Ack_Owner_All_Tokens 74
|
||||
NO Ack_Owner_All_Tokens 81
|
||||
NO Tokens 0 <--
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
L GETX 3
|
||||
L GETX 2
|
||||
L GETS 0 <--
|
||||
L Lockdown 0 <--
|
||||
L Unlockdown 173
|
||||
L Unlockdown 172
|
||||
L Own_Lock_or_Unlock 0 <--
|
||||
L Data_Owner 0 <--
|
||||
L Data_All_Tokens 8
|
||||
L Data_All_Tokens 10
|
||||
L Ack_Owner 0 <--
|
||||
L Ack_Owner_All_Tokens 0 <--
|
||||
L Tokens 0 <--
|
||||
L DMA_READ 0 <--
|
||||
L DMA_WRITE 0 <--
|
||||
|
||||
O_W GETX 21
|
||||
O_W GETS 0 <--
|
||||
O_W Lockdown 0 <--
|
||||
O_W GETX 4
|
||||
O_W GETS 2
|
||||
O_W Lockdown 1
|
||||
O_W Unlockdown 0 <--
|
||||
O_W Own_Lock_or_Unlock 0 <--
|
||||
O_W Data_Owner 0 <--
|
||||
|
|
@ -775,20 +758,20 @@ O_W Ack_Owner 0 <--
|
|||
O_W Tokens 0 <--
|
||||
O_W Ack_All_Tokens 0 <--
|
||||
O_W Memory_Data 0 <--
|
||||
O_W Memory_Ack 790
|
||||
O_W Memory_Ack 755
|
||||
O_W DMA_READ 0 <--
|
||||
O_W DMA_WRITE 0 <--
|
||||
|
||||
L_O_W GETX 38
|
||||
L_O_W GETX 10
|
||||
L_O_W GETS 0 <--
|
||||
L_O_W Lockdown 0 <--
|
||||
L_O_W Unlockdown 0 <--
|
||||
L_O_W Unlockdown 1
|
||||
L_O_W Own_Lock_or_Unlock 0 <--
|
||||
L_O_W Data_Owner 0 <--
|
||||
L_O_W Ack_Owner 0 <--
|
||||
L_O_W Tokens 0 <--
|
||||
L_O_W Ack_All_Tokens 0 <--
|
||||
L_O_W Memory_Data 3
|
||||
L_O_W Memory_Data 5
|
||||
L_O_W Memory_Ack 0 <--
|
||||
L_O_W DMA_READ 0 <--
|
||||
L_O_W DMA_WRITE 0 <--
|
||||
|
|
@ -829,7 +812,7 @@ NO_W Data_Owner 0 <--
|
|||
NO_W Ack_Owner 0 <--
|
||||
NO_W Tokens 0 <--
|
||||
NO_W Ack_All_Tokens 0 <--
|
||||
NO_W Memory_Data 851
|
||||
NO_W Memory_Data 821
|
||||
NO_W DMA_READ 0 <--
|
||||
NO_W DMA_WRITE 0 <--
|
||||
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:01:26
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 27 2010 22:01:59
|
||||
M5 executing on svvint04
|
||||
M5 compiled Mar 18 2010 14:58:42
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:58:52
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 282171 because Ruby Tester completed
|
||||
Exiting @ tick 275491 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213472 # Number of bytes of host memory used
|
||||
host_seconds 0.43 # Real time elapsed on the host
|
||||
host_tick_rate 656167 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208544 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 518969 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000282 # Number of seconds simulated
|
||||
sim_ticks 282171 # Number of ticks simulated
|
||||
sim_seconds 0.000275 # Number of seconds simulated
|
||||
sim_ticks 275491 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
|
@ -44,7 +45,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -141,7 +142,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -15,12 +15,12 @@ Network Configuration
|
|||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_4: active, unordered
|
||||
virtual_net_5: active, unordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/27/2010 22:06:46
|
||||
Real time: Mar/18/2010 14:59:23
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.52
|
||||
Virtual_time_in_minutes: 0.00866667
|
||||
Virtual_time_in_hours: 0.000144444
|
||||
Virtual_time_in_days: 6.01852e-06
|
||||
Virtual_time_in_seconds: 0.7
|
||||
Virtual_time_in_minutes: 0.0116667
|
||||
Virtual_time_in_hours: 0.000194444
|
||||
Virtual_time_in_days: 8.10185e-06
|
||||
|
||||
Ruby_current_time: 225461
|
||||
Ruby_current_time: 222961
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 225461
|
||||
Ruby_cycles: 222961
|
||||
|
||||
mbytes_resident: 29.9023
|
||||
mbytes_total: 29.9102
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 225462 [ 225462 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 30.5156
|
||||
mbytes_total: 203.461
|
||||
resident_ratio: 0.150021
|
||||
|
||||
ruby_cycles_executed: [ 222962 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -76,13 +65,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1003 average: 15.7986 | standard deviation: 1.13201 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 81 907 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.7946 | standard deviation: 1.13528 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 84 899 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 128 max: 18718 count: 988 average: 3556.09 | standard deviation: 5195.8 | 86 11 48 73 73 53 86 67 49 36 30 35 19 12 10 8 6 12 9 7 3 4 7 1 5 3 4 2 4 1 4 1 3 3 1 1 3 4 1 2 1 0 1 0 0 0 0 2 0 1 2 2 0 0 0 2 0 0 0 0 0 0 0 2 1 2 0 0 0 1 0 1 1 0 1 5 2 1 0 0 3 2 3 0 2 2 1 2 2 2 2 1 2 4 3 0 1 4 6 6 2 2 3 7 4 3 5 3 2 2 3 6 4 1 5 3 3 6 6 2 4 4 4 3 4 4 6 4 0 1 0 1 0 4 1 1 1 0 0 0 2 2 3 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 128 max: 17088 count: 100 average: 3614.25 | standard deviation: 5411.44 | 9 2 4 7 8 6 10 6 5 4 2 4 3 2 0 0 0 3 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 0 2 0 0 0 1 0 2 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 128 max: 18718 count: 888 average: 3549.54 | standard deviation: 5174.08 | 77 9 44 66 65 47 76 61 44 32 28 31 16 10 10 8 6 9 9 6 2 4 6 1 5 3 4 2 4 1 4 1 3 2 1 0 3 4 1 2 1 0 1 0 0 0 0 2 0 1 2 2 0 0 0 2 0 0 0 0 0 0 0 2 1 2 0 0 0 1 0 1 1 0 1 5 2 1 0 0 2 2 3 0 2 1 1 2 2 2 2 1 2 4 3 0 1 3 6 5 1 1 3 6 3 3 5 2 2 2 3 4 4 1 5 2 3 4 5 2 3 3 4 3 4 4 6 4 0 1 0 0 0 2 1 1 1 0 0 0 2 2 3 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 128 max: 23668 count: 983 average: 3530.64 | standard deviation: 5276.54 | 101 19 29 85 80 66 72 59 50 28 40 22 22 14 14 10 5 3 6 7 5 5 2 3 4 1 2 1 1 1 0 2 0 1 2 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 1 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 3 3 3 2 2 0 1 2 2 5 6 1 9 3 2 3 2 3 3 2 3 8 2 2 2 3 2 3 5 4 1 4 1 1 0 4 3 3 1 3 4 1 1 3 0 1 0 1 0 0 1 2 0 0 1 0 1 0 1 0 1 0 1 2 1 0 0 1 1 2 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 128 max: 19690 count: 100 average: 3024.87 | standard deviation: 5133.9 | 15 3 2 5 6 12 9 4 5 2 7 1 5 2 1 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_3: [binsize: 128 max: 23668 count: 883 average: 3587.92 | standard deviation: 5292.25 | 86 16 27 80 74 54 63 55 45 26 33 21 17 12 13 10 3 3 5 7 5 4 2 3 4 1 2 1 1 1 0 2 0 1 1 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 0 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 2 2 3 2 2 0 1 2 2 5 6 1 9 3 2 1 2 3 3 2 3 6 1 2 2 3 1 3 5 4 1 4 1 1 0 3 2 3 1 3 3 1 1 2 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -114,8 +103,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6560
|
||||
page_faults: 1853
|
||||
page_reclaims: 8816
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -125,42 +114,42 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.133285
|
||||
links_utilized_percent_switch_0_link_0: 0.0488166 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.217754 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.13187
|
||||
links_utilized_percent_switch_0_link_0: 0.0481867 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.215553 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 788 56736 [ 788 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.124828
|
||||
links_utilized_percent_switch_1_link_0: 0.0543886 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.195267 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.123292
|
||||
links_utilized_percent_switch_1_link_0: 0.0538379 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.192747 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 787 56664 [ 787 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 772 55584 [ 0 0 0 0 0 772 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.20641
|
||||
links_utilized_percent_switch_2_link_0: 0.195267 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.217554 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.20415
|
||||
links_utilized_percent_switch_2_link_0: 0.192747 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.215553 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 881 63432 [ 0 881 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 876 7008 [ 0 0 876 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 882 7056 [ 0 0 0 882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 787 56664 [ 787 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 965 7720 [ 88 0 0 877 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 880 7040 [ 880 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
|
|
@ -168,42 +157,43 @@ Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
|||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 882
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 882
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 889
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 889
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 10.3175%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 89.6825%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 9.67379%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 90.3262%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 882 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 882 average: 1.30952 | standard deviation: 0.913389 | 0 791 0 0 91 ]
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 889 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 889 average: 1.29021 | standard deviation: 0.887856 | 0 803 0 0 86 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 860
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 860
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 9.76744%
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 90.2326%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 860 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 4 count: 860 average: 1.29302 | standard deviation: 0.89169 | 0 776 0 0 84 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 101
|
||||
Load 100
|
||||
Ifetch 0
|
||||
Store 891
|
||||
L2_Replacement 877
|
||||
L1_to_L2 322098
|
||||
L2_to_L1D 26
|
||||
Store 887
|
||||
L2_Replacement 855
|
||||
L1_to_L2 318465
|
||||
L2_to_L1D 29
|
||||
L2_to_L1I 0
|
||||
Other_GETX 0
|
||||
Other_GETS 0
|
||||
|
|
@ -211,16 +201,16 @@ Ack 0
|
|||
Shared_Ack 0
|
||||
Data 0
|
||||
Shared_Data 0
|
||||
Exclusive_Data 881
|
||||
Writeback_Ack 876
|
||||
Exclusive_Data 860
|
||||
Writeback_Ack 855
|
||||
Writeback_Nack 0
|
||||
All_acks 0
|
||||
All_acks_no_sharers 881
|
||||
All_acks_no_sharers 859
|
||||
|
||||
- Transitions -
|
||||
I Load 91
|
||||
I Load 84
|
||||
I Ifetch 0 <--
|
||||
I Store 791
|
||||
I Store 776
|
||||
I L2_Replacement 0 <--
|
||||
I L1_to_L2 0 <--
|
||||
I L2_to_L1D 0 <--
|
||||
|
|
@ -250,20 +240,20 @@ O Other_GETS 0 <--
|
|||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M L2_Replacement 88
|
||||
M L1_to_L2 88
|
||||
M Store 1
|
||||
M L2_Replacement 82
|
||||
M L1_to_L2 82
|
||||
M L2_to_L1D 0 <--
|
||||
M L2_to_L1I 0 <--
|
||||
M Other_GETX 0 <--
|
||||
M Other_GETS 0 <--
|
||||
|
||||
MM Load 10
|
||||
MM Load 16
|
||||
MM Ifetch 0 <--
|
||||
MM Store 95
|
||||
MM L2_Replacement 789
|
||||
MM L1_to_L2 817
|
||||
MM L2_to_L1D 26
|
||||
MM Store 102
|
||||
MM L2_Replacement 773
|
||||
MM L1_to_L2 804
|
||||
MM L2_to_L1D 29
|
||||
MM L2_to_L1I 0 <--
|
||||
MM Other_GETX 0 <--
|
||||
MM Other_GETS 0 <--
|
||||
|
|
@ -272,12 +262,12 @@ IM Load 0 <--
|
|||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L1_to_L2 282750
|
||||
IM L1_to_L2 276294
|
||||
IM Other_GETX 0 <--
|
||||
IM Other_GETS 0 <--
|
||||
IM Ack 0 <--
|
||||
IM Data 0 <--
|
||||
IM Exclusive_Data 791
|
||||
IM Exclusive_Data 776
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
|
|
@ -310,32 +300,32 @@ ISM All_acks_no_sharers 0 <--
|
|||
|
||||
M_W Load 0 <--
|
||||
M_W Ifetch 0 <--
|
||||
M_W Store 1
|
||||
M_W Store 0 <--
|
||||
M_W L2_Replacement 0 <--
|
||||
M_W L1_to_L2 975
|
||||
M_W L1_to_L2 1192
|
||||
M_W Ack 0 <--
|
||||
M_W All_acks_no_sharers 89
|
||||
M_W All_acks_no_sharers 83
|
||||
|
||||
MM_W Load 0 <--
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 1
|
||||
MM_W Store 4
|
||||
MM_W L2_Replacement 0 <--
|
||||
MM_W L1_to_L2 10999
|
||||
MM_W L1_to_L2 11046
|
||||
MM_W Ack 0 <--
|
||||
MM_W All_acks_no_sharers 792
|
||||
MM_W All_acks_no_sharers 776
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L1_to_L2 26469
|
||||
IS L1_to_L2 29047
|
||||
IS Other_GETX 0 <--
|
||||
IS Other_GETS 0 <--
|
||||
IS Ack 0 <--
|
||||
IS Shared_Ack 0 <--
|
||||
IS Data 0 <--
|
||||
IS Shared_Data 0 <--
|
||||
IS Exclusive_Data 90
|
||||
IS Exclusive_Data 84
|
||||
|
||||
SS Load 0 <--
|
||||
SS Ifetch 0 <--
|
||||
|
|
@ -358,12 +348,12 @@ OI Writeback_Ack 0 <--
|
|||
|
||||
MI Load 0 <--
|
||||
MI Ifetch 0 <--
|
||||
MI Store 3
|
||||
MI Store 4
|
||||
MI L2_Replacement 0 <--
|
||||
MI L1_to_L2 0 <--
|
||||
MI Other_GETX 0 <--
|
||||
MI Other_GETS 0 <--
|
||||
MI Writeback_Ack 876
|
||||
MI Writeback_Ack 855
|
||||
|
||||
II Load 0 <--
|
||||
II Ifetch 0 <--
|
||||
|
|
@ -376,39 +366,39 @@ II Writeback_Ack 0 <--
|
|||
II Writeback_Nack 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 1668
|
||||
memory_reads: 881
|
||||
memory_writes: 787
|
||||
memory_refreshes: 470
|
||||
memory_total_request_delays: 1066
|
||||
memory_delays_per_request: 0.639089
|
||||
memory_delays_in_input_queue: 148
|
||||
memory_total_requests: 1632
|
||||
memory_reads: 860
|
||||
memory_writes: 772
|
||||
memory_refreshes: 465
|
||||
memory_total_request_delays: 1106
|
||||
memory_delays_per_request: 0.677696
|
||||
memory_delays_in_input_queue: 152
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 918
|
||||
memory_stalls_for_bank_busy: 195
|
||||
memory_delays_stalled_at_head_of_bank_queue: 954
|
||||
memory_stalls_for_bank_busy: 245
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 77
|
||||
memory_stalls_for_bus: 376
|
||||
memory_stalls_for_bus: 374
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 154
|
||||
memory_stalls_for_read_read_turnaround: 116
|
||||
accesses_per_bank: 46 46 48 83 76 73 83 52 38 57 51 55 52 49 41 48 49 44 44 60 51 41 58 49 42 38 55 47 50 52 39 51
|
||||
memory_stalls_for_read_write_turnaround: 150
|
||||
memory_stalls_for_read_read_turnaround: 108
|
||||
accesses_per_bank: 35 39 45 95 73 66 68 49 65 50 44 55 48 35 48 57 45 44 54 56 48 27 42 58 48 39 39 44 54 55 48 59
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 895
|
||||
GETS 90
|
||||
PUT 1525
|
||||
Unblock 878
|
||||
GETX 809
|
||||
GETS 84
|
||||
PUT 1454
|
||||
Unblock 858
|
||||
Writeback_Clean 0
|
||||
Writeback_Dirty 0
|
||||
Writeback_Exclusive_Clean 88
|
||||
Writeback_Exclusive_Dirty 787
|
||||
Writeback_Exclusive_Clean 82
|
||||
Writeback_Exclusive_Dirty 772
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 881
|
||||
Memory_Ack 787
|
||||
Memory_Data 860
|
||||
Memory_Ack 772
|
||||
Ack 0
|
||||
Shared_Ack 0
|
||||
Shared_Data 0
|
||||
|
|
@ -419,7 +409,7 @@ All_acks_and_data_no_sharers 0
|
|||
- Transitions -
|
||||
NO GETX 0 <--
|
||||
NO GETS 0 <--
|
||||
NO PUT 876
|
||||
NO PUT 855
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -429,16 +419,16 @@ O PUT 0 <--
|
|||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
|
||||
E GETX 791
|
||||
E GETS 90
|
||||
E GETX 776
|
||||
E GETS 84
|
||||
E PUT 0 <--
|
||||
E DMA_READ 0 <--
|
||||
E DMA_WRITE 0 <--
|
||||
|
||||
NO_B GETX 0 <--
|
||||
NO_B GETS 0 <--
|
||||
NO_B PUT 649
|
||||
NO_B Unblock 878
|
||||
NO_B PUT 599
|
||||
NO_B Unblock 858
|
||||
NO_B DMA_READ 0 <--
|
||||
NO_B DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -455,7 +445,7 @@ NO_B_W PUT 0 <--
|
|||
NO_B_W Unblock 0 <--
|
||||
NO_B_W DMA_READ 0 <--
|
||||
NO_B_W DMA_WRITE 0 <--
|
||||
NO_B_W Memory_Data 881
|
||||
NO_B_W Memory_Data 860
|
||||
|
||||
O_B_W GETX 0 <--
|
||||
O_B_W GETS 0 <--
|
||||
|
|
@ -545,14 +535,14 @@ O_DR_B DMA_WRITE 0 <--
|
|||
O_DR_B Ack 0 <--
|
||||
O_DR_B All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
WB GETX 35
|
||||
WB GETX 0 <--
|
||||
WB GETS 0 <--
|
||||
WB PUT 0 <--
|
||||
WB Unblock 0 <--
|
||||
WB Writeback_Clean 0 <--
|
||||
WB Writeback_Dirty 0 <--
|
||||
WB Writeback_Exclusive_Clean 88
|
||||
WB Writeback_Exclusive_Dirty 787
|
||||
WB Writeback_Exclusive_Clean 82
|
||||
WB Writeback_Exclusive_Dirty 772
|
||||
WB DMA_READ 0 <--
|
||||
WB DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -563,10 +553,10 @@ WB_O_W DMA_READ 0 <--
|
|||
WB_O_W DMA_WRITE 0 <--
|
||||
WB_O_W Memory_Ack 0 <--
|
||||
|
||||
WB_E_W GETX 69
|
||||
WB_E_W GETX 33
|
||||
WB_E_W GETS 0 <--
|
||||
WB_E_W PUT 0 <--
|
||||
WB_E_W DMA_READ 0 <--
|
||||
WB_E_W DMA_WRITE 0 <--
|
||||
WB_E_W Memory_Ack 787
|
||||
WB_E_W Memory_Ack 772
|
||||
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 22:05:53
|
||||
M5 revision 6068d4fc30d3 6931 default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 27 2010 22:06:45
|
||||
M5 executing on svvint06
|
||||
M5 compiled Mar 18 2010 14:59:19
|
||||
M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 14:59:22
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 225461 because Ruby Tester completed
|
||||
Exiting @ tick 222961 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 210820 # Number of bytes of host memory used
|
||||
host_seconds 0.44 # Real time elapsed on the host
|
||||
host_tick_rate 512394 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208348 # Number of bytes of host memory used
|
||||
host_seconds 0.53 # Real time elapsed on the host
|
||||
host_tick_rate 420464 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000225 # Number of seconds simulated
|
||||
sim_ticks 225461 # Number of ticks simulated
|
||||
sim_seconds 0.000223 # Number of seconds simulated
|
||||
sim_ticks 222961 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ clock=1
|
|||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
|
@ -44,7 +45,7 @@ verbosity_string=none
|
|||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
|
|
@ -125,7 +126,10 @@ version=0
|
|||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=0
|
||||
size=134217728
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@ topology:
|
|||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_3: active, ordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/27/2010 21:57:17
|
||||
Real time: Mar/18/2010 13:52:47
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.23
|
||||
Virtual_time_in_minutes: 0.00383333
|
||||
Virtual_time_in_hours: 6.38889e-05
|
||||
Virtual_time_in_days: 2.66204e-06
|
||||
Virtual_time_in_seconds: 0.27
|
||||
Virtual_time_in_minutes: 0.0045
|
||||
Virtual_time_in_hours: 7.5e-05
|
||||
Virtual_time_in_days: 3.125e-06
|
||||
|
||||
Ruby_current_time: 271191
|
||||
Ruby_current_time: 281031
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 271191
|
||||
Ruby_cycles: 281031
|
||||
|
||||
mbytes_resident: 30.8242
|
||||
mbytes_total: 30.832
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 271192 [ 271192 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
mbytes_resident: 30.418
|
||||
mbytes_total: 203.402
|
||||
resident_ratio: 0.149584
|
||||
|
||||
ruby_cycles_executed: [ 281032 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
|
@ -76,13 +65,13 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 971 average: 15.7848 | standard deviation: 1.15276 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 86 869 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1014 average: 15.7801 | standard deviation: 1.13371 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5 96 900 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 5966 count: 956 average: 4491.48 | standard deviation: 635.733 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 1 0 0 0 0 2 1 0 1 4 1 0 3 1 0 1 2 2 1 2 4 3 6 6 2 5 14 5 6 8 6 7 6 10 8 13 14 13 7 15 9 17 24 19 17 14 19 25 18 19 19 20 24 15 27 24 21 30 29 21 20 22 15 23 16 24 17 22 12 11 14 15 10 13 12 7 13 7 11 11 3 7 10 3 5 7 0 2 5 3 0 3 3 1 1 3 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 32 max: 5629 count: 100 average: 4532.09 | standard deviation: 502.331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 2 1 0 1 1 0 0 0 1 2 1 1 0 1 3 1 2 0 2 2 2 1 2 2 2 1 2 2 3 1 1 5 3 1 2 4 4 2 5 1 2 2 4 2 3 3 1 3 0 0 1 1 0 2 0 2 1 0 0 2 0 0 0 0 1 1 ]
|
||||
miss_latency_3: [binsize: 32 max: 5966 count: 856 average: 4486.74 | standard deviation: 649.61 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 1 0 0 0 0 2 1 0 1 4 1 0 3 0 0 0 2 2 1 2 4 3 6 4 1 5 13 4 6 8 6 6 4 9 7 13 13 10 6 13 9 15 22 17 16 12 17 23 17 17 17 17 23 14 22 21 20 28 25 17 18 17 14 21 14 20 15 19 9 10 11 15 10 12 11 7 11 7 9 10 3 7 8 3 5 7 0 1 4 3 0 3 3 1 1 3 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 32 max: 5702 count: 100 average: 4601.67 | standard deviation: 400.66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 0 3 1 1 3 4 5 2 3 1 2 2 1 1 5 2 0 2 2 2 5 2 2 3 1 3 3 1 5 4 4 2 3 3 1 1 3 3 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_3: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -96,11 +85,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1839 average: 0 | standard deviation: 0 | 1839 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1839 average: 0 | standard deviation: 0 | 1839 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1909 average: 0 | standard deviation: 0 | 1909 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1909 average: 0 | standard deviation: 0 | 1909 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 921 average: 0 | standard deviation: 0 | 921 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 918 average: 0 | standard deviation: 0 | 918 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 956 average: 0 | standard deviation: 0 | 956 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 953 average: 0 | standard deviation: 0 | 953 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -114,8 +103,8 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6767
|
||||
page_faults: 1920
|
||||
page_reclaims: 8779
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -125,129 +114,128 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.105956
|
||||
links_utilized_percent_switch_0_link_0: 0.0424378 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.169475 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.106147
|
||||
links_utilized_percent_switch_0_link_0: 0.0425087 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.169786 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 919 66168 [ 919 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 956 68832 [ 0 0 0 0 956 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 953 7624 [ 0 0 0 953 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.106039
|
||||
links_utilized_percent_switch_1_link_0: 0.0423272 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.169751 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.106329
|
||||
links_utilized_percent_switch_1_link_0: 0.0424464 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.170213 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 918 66096 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 957 68904 [ 0 0 0 0 957 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 954 7632 [ 0 0 0 954 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.16953
|
||||
links_utilized_percent_switch_2_link_0: 0.169751 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.169309 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.169999
|
||||
links_utilized_percent_switch_2_link_0: 0.170213 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.169786 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 921 66312 [ 0 921 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 918 7344 [ 0 0 918 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 921 7368 [ 921 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 918 66096 [ 918 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 957 68904 [ 0 0 0 0 957 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 954 7632 [ 0 0 0 954 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 923
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 923
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 957
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 957
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.9426%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.0574%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.2403%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.7597%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 923 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 923 average: 1.32828 | standard deviation: 0.937297 | 0 822 0 0 101 ]
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 957 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 957 average: 1.30721 | standard deviation: 0.910193 | 0 859 0 0 98 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 101
|
||||
Load 100
|
||||
Ifetch 0
|
||||
Store 857
|
||||
Data 921
|
||||
Store 900
|
||||
Data 956
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 920
|
||||
Writeback_Ack 918
|
||||
Replacement 954
|
||||
Writeback_Ack 953
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 101
|
||||
I Load 98
|
||||
I Ifetch 0 <--
|
||||
I Store 822
|
||||
I Store 859
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Load 2
|
||||
M Ifetch 0 <--
|
||||
M Store 35
|
||||
M Store 41
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 920
|
||||
M Replacement 954
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 918
|
||||
MI Writeback_Ack 953
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 100
|
||||
IS Data 98
|
||||
|
||||
IM Data 821
|
||||
IM Data 858
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 1839
|
||||
memory_reads: 921
|
||||
memory_writes: 918
|
||||
memory_refreshes: 565
|
||||
memory_total_request_delays: 2859
|
||||
memory_delays_per_request: 1.55465
|
||||
memory_delays_in_input_queue: 719
|
||||
memory_delays_behind_head_of_bank_queue: 15
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2125
|
||||
memory_stalls_for_bank_busy: 289
|
||||
memory_total_requests: 1911
|
||||
memory_reads: 957
|
||||
memory_writes: 954
|
||||
memory_refreshes: 586
|
||||
memory_total_request_delays: 3005
|
||||
memory_delays_per_request: 1.57248
|
||||
memory_delays_in_input_queue: 744
|
||||
memory_delays_behind_head_of_bank_queue: 13
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2248
|
||||
memory_stalls_for_bank_busy: 342
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 280
|
||||
memory_stalls_for_bus: 928
|
||||
memory_stalls_for_arbitration: 295
|
||||
memory_stalls_for_bus: 949
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 519
|
||||
memory_stalls_for_read_read_turnaround: 109
|
||||
accesses_per_bank: 62 46 62 86 113 64 68 60 64 64 56 62 48 40 46 38 62 50 52 52 58 61 56 54 52 58 58 56 51 54 52 34
|
||||
memory_stalls_for_read_write_turnaround: 550
|
||||
memory_stalls_for_read_read_turnaround: 112
|
||||
accesses_per_bank: 52 59 44 109 131 76 66 52 64 66 66 44 56 54 54 52 52 48 76 50 48 60 56 48 50 62 66 48 36 64 48 54
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 921
|
||||
GETX 957
|
||||
GETS 0
|
||||
PUTX 918
|
||||
PUTX 954
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 921
|
||||
Memory_Ack 918
|
||||
Memory_Data 957
|
||||
Memory_Ack 954
|
||||
|
||||
- Transitions -
|
||||
I GETX 921
|
||||
I GETX 957
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 918
|
||||
M PUTX 954
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
|
@ -270,7 +258,7 @@ IM PUTX 0 <--
|
|||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 921
|
||||
IM Memory_Data 957
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
|
|
@ -278,7 +266,7 @@ MI PUTX 0 <--
|
|||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 918
|
||||
MI Memory_Ack 954
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 27 2010 17:26:29
|
||||
M5 revision 6068d4fc30d3 6931 default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 27 2010 21:57:16
|
||||
M5 executing on svvint07
|
||||
M5 compiled Mar 18 2010 13:52:42
|
||||
M5 revision 6a6bb24e484f 7041 default qtip tip brad/regress_updates
|
||||
M5 started Mar 18 2010 13:52:46
|
||||
M5 executing on cabr0210
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 271191 because Ruby Tester completed
|
||||
Exiting @ tick 281031 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213104 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 3873825 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208288 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 2919378 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000271 # Number of seconds simulated
|
||||
sim_ticks 271191 # Number of ticks simulated
|
||||
sim_seconds 0.000281 # Number of seconds simulated
|
||||
sim_ticks 281031 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue