stats: Update stats for final tick and memory bandwidth patches
This commit is contained in:
Ali Saidi
parent
bd55c9e2af
commit
a17dbdf883
490 changed files with 13407 additions and 11239 deletions
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@ -10,6 +10,7 @@ type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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num_work_ids=16
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.port[0]
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[system.cpu]
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type=InOrderCPU
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@ -182,7 +184,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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mem_side=system.membus.port[2]
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[system.cpu.toL2Bus]
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type=Bus
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@ -205,7 +207,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -224,7 +226,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.physmem.port[0] system.cpu.l2cache.mem_side
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port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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@ -234,5 +236,5 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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port=system.membus.port[1]
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@ -1,9 +1,9 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jul 8 2011 15:00:53
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gem5 started Jul 8 2011 16:09:24
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gem5 executing on u200439-lin.austin.arm.com
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gem5 compiled Jan 23 2012 04:48:33
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gem5 started Jan 23 2012 05:24:12
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gem5 executing on zizzer
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command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@ -2,12 +2,23 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.274500 # Number of seconds simulated
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sim_ticks 274500333500 # Number of ticks simulated
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final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 56944 # Simulator instruction rate (inst/s)
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host_tick_rate 25971361 # Simulator tick rate (ticks/s)
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host_mem_usage 245756 # Number of bytes of host memory used
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host_seconds 10569.35 # Real time elapsed on the host
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host_inst_rate 113367 # Simulator instruction rate (inst/s)
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host_tick_rate 51705325 # Simulator tick rate (ticks/s)
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host_mem_usage 207980 # Number of bytes of host memory used
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host_seconds 5308.94 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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system.physmem.bytes_read 5894016 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3798080 # Number of bytes written to this memory
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system.physmem.num_reads 92094 # Number of read requests responded to by this memory
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system.physmem.num_writes 59345 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -10,6 +10,7 @@ type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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num_work_ids=16
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.port[0]
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[system.cpu]
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type=DerivO3CPU
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@ -477,7 +479,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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mem_side=system.membus.port[2]
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[system.cpu.toL2Bus]
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type=Bus
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@ -519,7 +521,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.physmem.port[0] system.cpu.l2cache.mem_side
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port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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@ -529,5 +531,5 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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port=system.membus.port[1]
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@ -1,10 +1,8 @@
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Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
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Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Aug 20 2011 16:10:02
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gem5 started Aug 20 2011 16:10:09
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gem5 compiled Jan 23 2012 04:48:33
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gem5 started Jan 23 2012 05:24:12
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gem5 executing on zizzer
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command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
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Global frequency set at 1000000000000 ticks per second
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@ -2,12 +2,23 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.144450 # Number of seconds simulated
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sim_ticks 144450185500 # Number of ticks simulated
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final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 180758 # Simulator instruction rate (inst/s)
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host_tick_rate 46168195 # Simulator tick rate (ticks/s)
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host_mem_usage 205240 # Number of bytes of host memory used
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host_seconds 3128.78 # Real time elapsed on the host
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host_inst_rate 205040 # Simulator instruction rate (inst/s)
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host_tick_rate 52370107 # Simulator tick rate (ticks/s)
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host_mem_usage 208620 # Number of bytes of host memory used
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host_seconds 2758.26 # Real time elapsed on the host
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sim_insts 565552443 # Number of instructions simulated
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system.physmem.bytes_read 5936768 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3797120 # Number of bytes written to this memory
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system.physmem.num_reads 92762 # Number of read requests responded to by this memory
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system.physmem.num_writes 59330 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 41099068 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 418248 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 26286709 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 67385777 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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num_work_ids=16
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.port[0]
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[system.cpu]
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type=AtomicSimpleCPU
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@ -44,8 +47,8 @@ system=system
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tracer=system.cpu.tracer
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.port[2]
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icache_port=system.membus.port[1]
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dcache_port=system.membus.port[3]
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icache_port=system.membus.port[2]
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[system.cpu.dtb]
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type=AlphaTLB
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@ -61,7 +64,7 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
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egid=100
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env=
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errout=cerr
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@ -85,7 +88,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
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port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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@ -95,5 +98,5 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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port=system.membus.port[1]
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@ -1,10 +1,10 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Jun 19 2011 06:59:13
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gem5 started Jun 20 2011 12:20:39
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gem5 executing on m60-009.pool
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command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic
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gem5 compiled Jan 23 2012 04:48:33
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gem5 started Jan 23 2012 05:24:12
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gem5 executing on zizzer
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command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -2,12 +2,23 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.300931 # Number of seconds simulated
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sim_ticks 300930958000 # Number of ticks simulated
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final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 3663682 # Simulator instruction rate (inst/s)
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host_tick_rate 1831855621 # Simulator tick rate (ticks/s)
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host_mem_usage 184012 # Number of bytes of host memory used
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host_seconds 164.28 # Real time elapsed on the host
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host_inst_rate 4527143 # Simulator instruction rate (inst/s)
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host_tick_rate 2263589972 # Simulator tick rate (ticks/s)
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host_mem_usage 198960 # Number of bytes of host memory used
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host_seconds 132.94 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 152669504 # Number of bytes written to this memory
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system.physmem.num_reads 716375939 # Number of read requests responded to by this memory
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system.physmem.num_writes 39451321 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 9247938286 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 7999999747 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 507324022 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 9755262308 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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num_work_ids=16
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.port[0]
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[system.cpu]
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type=TimingSimpleCPU
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@ -146,7 +149,7 @@ trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.port[2]
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mem_side=system.membus.port[1]
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mem_side=system.membus.port[2]
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[system.cpu.toL2Bus]
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type=Bus
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@ -164,7 +167,7 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
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cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
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egid=100
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env=
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errout=cerr
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@ -188,7 +191,7 @@ clock=1000
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header_cycles=1
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use_default_range=false
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width=64
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port=system.physmem.port[0] system.cpu.l2cache.mem_side
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port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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@ -198,5 +201,5 @@ latency_var=0
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null=false
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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port=system.membus.port[1]
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@ -1,10 +1,10 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jun 19 2011 06:59:13
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gem5 started Jun 20 2011 12:47:45
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gem5 executing on m60-009.pool
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command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
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gem5 compiled Jan 23 2012 04:48:33
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gem5 started Jan 23 2012 05:24:12
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gem5 executing on zizzer
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command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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info: Increasing stack size by one page.
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@ -2,12 +2,23 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.765623 # Number of seconds simulated
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sim_ticks 765623032000 # Number of ticks simulated
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final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1640067 # Simulator instruction rate (inst/s)
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host_tick_rate 2086331180 # Simulator tick rate (ticks/s)
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host_mem_usage 192652 # Number of bytes of host memory used
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host_seconds 366.97 # Real time elapsed on the host
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host_inst_rate 2199350 # Simulator instruction rate (inst/s)
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host_tick_rate 2797795440 # Simulator tick rate (ticks/s)
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host_mem_usage 207676 # Number of bytes of host memory used
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host_seconds 273.65 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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system.physmem.bytes_read 5889984 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 3797824 # Number of bytes written to this memory
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system.physmem.num_reads 92031 # Number of read requests responded to by this memory
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system.physmem.num_writes 59341 # Number of write requests responded to by this memory
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||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 7693060 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 66456 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 4960436 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 12653496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -500,7 +502,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 21 2011 16:28:02
|
||||
gem5 started Nov 22 2011 16:59:04
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:31:06
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.177099 # Number of seconds simulated
|
||||
sim_ticks 177098873000 # Number of ticks simulated
|
||||
final_tick 177098873000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166594 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 48979898 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214636 # Number of bytes of host memory used
|
||||
host_seconds 3615.75 # Real time elapsed on the host
|
||||
host_inst_rate 154897 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 45541130 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 220436 # Number of bytes of host memory used
|
||||
host_seconds 3888.77 # Real time elapsed on the host
|
||||
sim_insts 602359805 # Number of instructions simulated
|
||||
system.physmem.bytes_read 5833856 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3720192 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 91154 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 58128 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 32941237 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 265253 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 21006300 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 53947537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -44,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -61,7 +64,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
|
||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -85,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -95,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:47:58
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:36:54
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,76 +1,87 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2791643 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 253504 # Number of bytes of host memory used
|
||||
host_seconds 215.77 # Real time elapsed on the host
|
||||
host_tick_rate 1395873441 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 602359851 # Number of instructions simulated
|
||||
sim_seconds 0.301191 # Number of seconds simulated
|
||||
sim_ticks 301191370000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2998309 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1499211130 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210136 # Number of bytes of host memory used
|
||||
host_seconds 200.90 # Real time elapsed on the host
|
||||
sim_insts 602359851 # Number of instructions simulated
|
||||
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 236359611 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 717867713 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 69418858 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 8898529055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7570927866 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 784748949 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 9683278004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 602382741 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 602359851 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2770243005 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 602382741 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -146,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -164,7 +167,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -188,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -198,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:48:29
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:40:26
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,269 +1,280 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1298278 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 260992 # Number of bytes of host memory used
|
||||
host_seconds 462.46 # Real time elapsed on the host
|
||||
host_tick_rate 1722888732 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 600398281 # Number of instructions simulated
|
||||
sim_seconds 0.796763 # Number of seconds simulated
|
||||
sim_ticks 796762926000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 216771819 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 437564 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 392392 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1450316 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1924652930 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 219100 # Number of bytes of host memory used
|
||||
host_seconds 413.98 # Real time elapsed on the host
|
||||
sim_insts 600398281 # Number of instructions simulated
|
||||
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3704704 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 89992 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 57886 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 7228609 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 49480 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 4649694 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 11878304 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 570073892 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 643 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 600398281 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 12 # number of replacements
|
||||
system.cpu.icache.tagsinuse 577.728532 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 570073892 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.282094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 570073892 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 570073892 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 570073892 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 643 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 34874000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 34874000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 570074535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 570074535 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 570074535 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 643 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 643 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 643 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 32945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 32945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 433468 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 216774473 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 495.412038 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.222434 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 147602036 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 69169783 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 1327 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 1327 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 216771819 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 216771819 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 189816 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 247748 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 437564 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 437564 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 3956274000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5923414000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 9879688000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 9879688000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 147791852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1327 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 1327 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 217209383 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 217209383 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001284 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003569 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.002014 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.002014 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22578.841038 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 392392 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 189816 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 247748 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 437564 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 437564 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3386826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5180170000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8566996000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8566996000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001284 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003569 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002014 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002014 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71804 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 348215 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 89992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 57886 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 348215 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 89992 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 71804 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 411836 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 57886 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 1593525852 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 67017827 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 600398281 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 533522639 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 3212467108 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614470985 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 148952594 # Number of load instructions
|
||||
system.cpu.num_mem_refs 219173607 # number of memory refs
|
||||
system.cpu.num_store_insts 70221013 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -495,7 +497,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 30 2011 17:14:16
|
||||
gem5 started Nov 30 2011 17:16:48
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:17:40
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.408816 # Number of seconds simulated
|
||||
sim_ticks 408816360000 # Number of ticks simulated
|
||||
final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 252046 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 73306837 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 206388 # Number of bytes of host memory used
|
||||
host_seconds 5576.78 # Real time elapsed on the host
|
||||
host_inst_rate 175830 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 51139829 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215728 # Number of bytes of host memory used
|
||||
host_seconds 7994.10 # Real time elapsed on the host
|
||||
sim_insts 1405604152 # Number of instructions simulated
|
||||
system.physmem.bytes_read 6021376 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3792448 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 94084 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 59257 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 14728804 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 200070 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 9276654 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 24005458 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 817632721 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -45,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -62,7 +64,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -86,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -96,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 30 2011 17:14:16
|
||||
gem5 started Nov 30 2011 17:16:48
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:18:03
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.744764 # Number of seconds simulated
|
||||
sim_ticks 744764119000 # Number of ticks simulated
|
||||
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4241689 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2120851440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 196528 # Number of bytes of host memory used
|
||||
host_seconds 351.16 # Real time elapsed on the host
|
||||
host_inst_rate 3773289 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1886650577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 205844 # Number of bytes of host memory used
|
||||
host_seconds 394.75 # Real time elapsed on the host
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 614672063 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 1887625855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 166846816 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 1326 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 9837033566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7976286575 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 825324485 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 10662358051 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -147,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -165,7 +167,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -189,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -199,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 30 2011 17:14:16
|
||||
gem5 started Nov 30 2011 17:16:48
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:19:05
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.064259 # Number of seconds simulated
|
||||
sim_ticks 2064258667000 # Number of ticks simulated
|
||||
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2284016 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 3165307188 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 205232 # Number of bytes of host memory used
|
||||
host_seconds 652.15 # Real time elapsed on the host
|
||||
host_inst_rate 1766930 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2448703239 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 214556 # Number of bytes of host memory used
|
||||
host_seconds 843.00 # Real time elapsed on the host
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
system.physmem.bytes_read 5909952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3778240 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 92343 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 59035 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 49 # Number of system calls
|
||||
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -500,7 +502,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:28:24
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.586294 # Number of seconds simulated
|
||||
sim_ticks 586294224000 # Number of ticks simulated
|
||||
final_tick 586294224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 115446 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 41742717 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244900 # Number of bytes of host memory used
|
||||
host_seconds 14045.43 # Real time elapsed on the host
|
||||
host_inst_rate 145094 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 52462700 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 215548 # Number of bytes of host memory used
|
||||
host_seconds 11175.48 # Real time elapsed on the host
|
||||
sim_insts 1621493982 # Number of instructions simulated
|
||||
system.physmem.bytes_read 5880640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 56960 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3744192 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 91885 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 58503 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 10030186 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 97153 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 6386200 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 16416386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1172588449 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -45,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -67,7 +69,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -86,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -96,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:33:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.963993 # Number of seconds simulated
|
||||
sim_ticks 963992704000 # Number of ticks simulated
|
||||
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1220339 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 725502264 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234168 # Number of bytes of host memory used
|
||||
host_seconds 1328.72 # Real time elapsed on the host
|
||||
host_inst_rate 2202720 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1309536712 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 204800 # Number of bytes of host memory used
|
||||
host_seconds 736.13 # Real time elapsed on the host
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 864451000 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 1605558864 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 188186057 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 11757959140 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 9846686466 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 896740189 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 12654699330 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -147,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -170,7 +172,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -189,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -199,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:37:10
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.803259 # Number of seconds simulated
|
||||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 760773 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 846053445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242892 # Number of bytes of host memory used
|
||||
host_seconds 2131.38 # Real time elapsed on the host
|
||||
host_inst_rate 1279975 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1423455894 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213784 # Number of bytes of host memory used
|
||||
host_seconds 1266.82 # Real time elapsed on the host
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
system.physmem.bytes_read 5725952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 3712448 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 89468 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 58007 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 3175336 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 25625 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 2058744 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 5234080 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,13 +10,14 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/projects/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
pal=/projects/pd/randd/dist/binaries/ts_osfpal
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[2]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
resp_size_a=16
|
||||
resp_size_b=16
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
side_a=system.iobus.port[0]
|
||||
side_b=system.membus.port[0]
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[0]
|
||||
|
||||
[system.cpu0]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -933,7 +932,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -953,7 +952,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -969,7 +968,7 @@ header_cycles=1
|
|||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -1000,8 +999,8 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.iobus.port[32]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
|
|
@ -1033,7 +1032,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[3]
|
||||
mem_side=system.membus.port[4]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -1045,7 +1044,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -1082,7 +1081,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -1195,9 +1194,9 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
pio=system.iobus.port[29]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
|
|
@ -1583,8 +1582,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
config=system.iobus.port[27]
|
||||
dma=system.iobus.port[28]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.io]
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 21 2011 16:05:33
|
||||
gem5 started Nov 21 2011 19:03:16
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Jan 23 2012 03:53:29
|
||||
gem5 started Jan 23 2012 06:11:48
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 106949500
|
||||
Exiting @ tick 1897465263500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.897465 # Number of seconds simulated
|
||||
sim_ticks 1897465263500 # Number of ticks simulated
|
||||
final_tick 1897465263500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 138767 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 4690907118 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293696 # Number of bytes of host memory used
|
||||
host_seconds 404.50 # Real time elapsed on the host
|
||||
host_inst_rate 131690 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 4451680142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298548 # Number of bytes of host memory used
|
||||
host_seconds 426.24 # Real time elapsed on the host
|
||||
sim_insts 56130966 # Number of instructions simulated
|
||||
system.physmem.bytes_read 30408320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1097728 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10468544 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 475130 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 163571 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 16025758 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 578523 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 5517120 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 21542879 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 397795 # number of replacements
|
||||
system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2482671 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -10,13 +10,14 @@ type=LinuxAlphaSystem
|
|||
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
console=/projects/pd/randd/dist/binaries/console
|
||||
console=/dist/m5/system/binaries/console
|
||||
init_param=0
|
||||
kernel=/projects/pd/randd/dist/binaries/vmlinux
|
||||
kernel=/dist/m5/system/binaries/vmlinux
|
||||
load_addr_mask=1099511627775
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
pal=/projects/pd/randd/dist/binaries/ts_osfpal
|
||||
num_work_ids=16
|
||||
pal=/dist/m5/system/binaries/ts_osfpal
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
symbolfile=
|
||||
|
|
@ -29,20 +30,18 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[2]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:8589934591
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
resp_size_a=16
|
||||
resp_size_b=16
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
side_a=system.iobus.port[0]
|
||||
side_b=system.membus.port[0]
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -497,7 +496,7 @@ table_size=65536
|
|||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -517,7 +516,7 @@ table_size=65536
|
|||
|
||||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.intrctrl]
|
||||
|
|
@ -533,7 +532,7 @@ header_cycles=1
|
|||
use_default_range=true
|
||||
width=64
|
||||
default=system.tsunami.pciconfig.pio
|
||||
port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
|
||||
port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -564,8 +563,8 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.iobus.port[32]
|
||||
mem_side=system.membus.port[3]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
|
|
@ -597,7 +596,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[3]
|
||||
mem_side=system.membus.port[4]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -609,7 +608,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
|
||||
port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -646,7 +645,7 @@ system=system
|
|||
|
||||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-latest.img
|
||||
image_file=/dist/m5/system/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -759,9 +758,9 @@ system=system
|
|||
tx_delay=1000000
|
||||
tx_fifo_size=524288
|
||||
tx_thread=false
|
||||
config=system.iobus.port[29]
|
||||
dma=system.iobus.port[30]
|
||||
pio=system.iobus.port[27]
|
||||
config=system.iobus.port[30]
|
||||
dma=system.iobus.port[31]
|
||||
pio=system.iobus.port[29]
|
||||
|
||||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
|
|
@ -1147,8 +1146,8 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.tsunami
|
||||
system=system
|
||||
config=system.iobus.port[31]
|
||||
dma=system.iobus.port[32]
|
||||
config=system.iobus.port[27]
|
||||
dma=system.iobus.port[28]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.tsunami.io]
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 21 2011 16:05:33
|
||||
gem5 started Nov 21 2011 18:56:50
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Jan 23 2012 03:53:29
|
||||
gem5 started Jan 23 2012 06:11:15
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: kernel located at: /dist/m5/system/binaries/vmlinux
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1858873594500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.858874 # Number of seconds simulated
|
||||
sim_ticks 1858873594500 # Number of ticks simulated
|
||||
final_tick 1858873594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 141632 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 4958330764 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290572 # Number of bytes of host memory used
|
||||
host_seconds 374.90 # Real time elapsed on the host
|
||||
host_inst_rate 134152 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 4696460042 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295432 # Number of bytes of host memory used
|
||||
host_seconds 395.80 # Real time elapsed on the host
|
||||
sim_insts 53097697 # Number of instructions simulated
|
||||
system.physmem.bytes_read 29819840 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1062784 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10193408 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 465935 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 159272 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 16041887 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 571735 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 5483648 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 21525535 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 391354 # number of replacements
|
||||
system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use
|
||||
system.l2c.total_refs 2410581 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[7]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:268435455
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
resp_size_a=16
|
||||
resp_size_b=16
|
||||
ranges=268435456:520093695 1073741824:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
side_a=system.iobus.port[0]
|
||||
side_b=system.membus.port[0]
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
|
|
@ -987,7 +985,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
|
||||
port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -1018,8 +1016,8 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[25]
|
||||
mem_side=system.membus.port[7]
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[8]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
|
|
@ -1051,7 +1049,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[8]
|
||||
mem_side=system.membus.port[9]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -1063,7 +1061,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
|
||||
port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -1125,7 +1123,7 @@ pio_addr=268451840
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[21]
|
||||
pio=system.iobus.port[24]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
|
|
@ -1179,9 +1177,9 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.port[26]
|
||||
dma=system.iobus.port[27]
|
||||
pio=system.iobus.port[8]
|
||||
config=system.iobus.port[10]
|
||||
dma=system.iobus.port[11]
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
|
|
@ -1196,7 +1194,7 @@ pio_latency=10000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.port[28]
|
||||
dma=system.iobus.port[6]
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
|
|
@ -1207,7 +1205,7 @@ pio_addr=268632064
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -1224,7 +1222,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[24]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
|
|
@ -1246,7 +1244,7 @@ pio_addr=268513280
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.port[19]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1256,7 +1254,7 @@ pio_addr=268517376
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.port[20]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1266,7 +1264,7 @@ pio_addr=268521472
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[18]
|
||||
pio=system.iobus.port[21]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
|
|
@ -1280,7 +1278,7 @@ pio_latency=1000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.port[6]
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
|
|
@ -1294,7 +1292,7 @@ pio_latency=1000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.port[7]
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -1333,7 +1331,7 @@ pio_addr=268455936
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[22]
|
||||
pio=system.iobus.port[25]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
|
|
@ -1354,7 +1352,7 @@ pio_addr=268529664
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1364,7 +1362,7 @@ pio_addr=268492800
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[20]
|
||||
pio=system.iobus.port[23]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1374,7 +1372,7 @@ pio_addr=269357056
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.port[16]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1384,7 +1382,7 @@ pio_addr=268439552
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.port[17]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1394,7 +1392,7 @@ pio_addr=268488704
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[19]
|
||||
pio=system.iobus.port[22]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
|
|
@ -1445,7 +1443,7 @@ pio_addr=268476416
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1455,7 +1453,7 @@ pio_addr=268480512
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.port[14]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1465,7 +1463,7 @@ pio_addr=268484608
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1475,7 +1473,7 @@ pio_addr=268500992
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.port[18]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
|
|
|
|||
|
|
@ -1,10 +1,8 @@
|
|||
Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout
|
||||
Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 8 2012 22:12:58
|
||||
gem5 started Jan 9 2012 03:33:38
|
||||
gem5 compiled Jan 23 2012 04:21:22
|
||||
gem5 started Jan 23 2012 09:54:17
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -2,12 +2,32 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.582494 # Number of seconds simulated
|
||||
sim_ticks 2582494395500 # Number of ticks simulated
|
||||
final_tick 2582494395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 65512 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2118472138 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 384260 # Number of bytes of host memory used
|
||||
host_seconds 1219.04 # Real time elapsed on the host
|
||||
host_inst_rate 77486 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2505663009 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386072 # Number of bytes of host memory used
|
||||
host_seconds 1030.66 # Real time elapsed on the host
|
||||
sim_insts 79862069 # Number of instructions simulated
|
||||
system.nvmem.bytes_read 384 # Number of bytes read from this memory
|
||||
system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory
|
||||
system.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.nvmem.num_reads 6 # Number of read requests responded to by this memory
|
||||
system.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 131490980 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1177856 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10251344 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 15129077 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 870131 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 50916269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 456092 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 3969551 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 54885821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 132200 # number of replacements
|
||||
system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1817822 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -32,20 +32,18 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[7]
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
filter_ranges_a=0:18446744073709551615
|
||||
filter_ranges_b=0:268435455
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
resp_size_a=16
|
||||
resp_size_b=16
|
||||
ranges=268435456:520093695 1073741824:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
side_a=system.iobus.port[0]
|
||||
side_b=system.membus.port[0]
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[0]
|
||||
|
||||
[system.cf0]
|
||||
type=IdeDisk
|
||||
|
|
@ -533,7 +531,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma
|
||||
port=system.bridge.master system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.clcd.dma system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -564,8 +562,8 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[25]
|
||||
mem_side=system.membus.port[7]
|
||||
cpu_side=system.iobus.port[28]
|
||||
mem_side=system.membus.port[8]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
|
|
@ -597,7 +595,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[8]
|
||||
mem_side=system.membus.port[9]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -609,7 +607,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
|
||||
port=system.bridge.slave system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.system_port system.iocache.mem_side system.l2c.mem_side
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -671,7 +669,7 @@ pio_addr=268451840
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[21]
|
||||
pio=system.iobus.port[24]
|
||||
|
||||
[system.realview.cf_ctrl]
|
||||
type=IdeController
|
||||
|
|
@ -725,9 +723,9 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
config=system.iobus.port[26]
|
||||
dma=system.iobus.port[27]
|
||||
pio=system.iobus.port[8]
|
||||
config=system.iobus.port[10]
|
||||
dma=system.iobus.port[11]
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.realview.clcd]
|
||||
type=Pl111
|
||||
|
|
@ -742,7 +740,7 @@ pio_latency=10000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.port[28]
|
||||
dma=system.iobus.port[6]
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.realview.dmac_fake]
|
||||
|
|
@ -753,7 +751,7 @@ pio_addr=268632064
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[9]
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
[system.realview.flash_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -770,7 +768,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[24]
|
||||
pio=system.iobus.port[27]
|
||||
|
||||
[system.realview.gic]
|
||||
type=Gic
|
||||
|
|
@ -792,7 +790,7 @@ pio_addr=268513280
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.port[19]
|
||||
|
||||
[system.realview.gpio1_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -802,7 +800,7 @@ pio_addr=268517376
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.port[20]
|
||||
|
||||
[system.realview.gpio2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -812,7 +810,7 @@ pio_addr=268521472
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[18]
|
||||
pio=system.iobus.port[21]
|
||||
|
||||
[system.realview.kmi0]
|
||||
type=Pl050
|
||||
|
|
@ -826,7 +824,7 @@ pio_latency=1000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.port[6]
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.realview.kmi1]
|
||||
type=Pl050
|
||||
|
|
@ -840,7 +838,7 @@ pio_latency=1000
|
|||
platform=system.realview
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.port[7]
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
|
|
@ -879,7 +877,7 @@ pio_addr=268455936
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[22]
|
||||
pio=system.iobus.port[25]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
|
|
@ -900,7 +898,7 @@ pio_addr=268529664
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[23]
|
||||
pio=system.iobus.port[26]
|
||||
|
||||
[system.realview.sci_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -910,7 +908,7 @@ pio_addr=268492800
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[20]
|
||||
pio=system.iobus.port[23]
|
||||
|
||||
[system.realview.smc_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -920,7 +918,7 @@ pio_addr=269357056
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.port[16]
|
||||
|
||||
[system.realview.sp810_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -930,7 +928,7 @@ pio_addr=268439552
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.port[17]
|
||||
|
||||
[system.realview.ssp_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -940,7 +938,7 @@ pio_addr=268488704
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[19]
|
||||
pio=system.iobus.port[22]
|
||||
|
||||
[system.realview.timer0]
|
||||
type=Sp804
|
||||
|
|
@ -991,7 +989,7 @@ pio_addr=268476416
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[10]
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.realview.uart2_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1001,7 +999,7 @@ pio_addr=268480512
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.port[14]
|
||||
|
||||
[system.realview.uart3_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1011,7 +1009,7 @@ pio_addr=268484608
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
[system.realview.watchdog_fake]
|
||||
type=AmbaFake
|
||||
|
|
@ -1021,7 +1019,7 @@ pio_addr=268500992
|
|||
pio_latency=1000
|
||||
platform=system.realview
|
||||
system=system
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.port[18]
|
||||
|
||||
[system.terminal]
|
||||
type=Terminal
|
||||
|
|
|
|||
|
|
@ -1,10 +1,8 @@
|
|||
Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
|
||||
Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 8 2012 22:12:58
|
||||
gem5 started Jan 9 2012 03:32:35
|
||||
gem5 compiled Jan 23 2012 04:21:22
|
||||
gem5 started Jan 23 2012 09:54:06
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -2,12 +2,32 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.503566 # Number of seconds simulated
|
||||
sim_ticks 2503566110500 # Number of ticks simulated
|
||||
final_tick 2503566110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72389 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2360079964 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 384076 # Number of bytes of host memory used
|
||||
host_seconds 1060.80 # Real time elapsed on the host
|
||||
host_inst_rate 76624 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2498140220 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386188 # Number of bytes of host memory used
|
||||
host_seconds 1002.17 # Real time elapsed on the host
|
||||
sim_insts 76790007 # Number of instructions simulated
|
||||
system.nvmem.bytes_read 64 # Number of bytes read from this memory
|
||||
system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
|
||||
system.nvmem.bytes_written 0 # Number of bytes written to this memory
|
||||
system.nvmem.num_reads 1 # Number of read requests responded to by this memory
|
||||
system.nvmem.num_writes 0 # Number of write requests responded to by this memory
|
||||
system.nvmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
|
||||
system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read 130731152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1101568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 9585992 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 15117140 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 856673 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 52217975 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 440000 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 3828935 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 56046910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 119509 # number of replacements
|
||||
system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1795434 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ time_sync_spin_threshold=100000000
|
|||
|
||||
[system]
|
||||
type=LinuxX86System
|
||||
children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
|
||||
acpi_description_table_pointer=system.acpi_description_table_pointer
|
||||
boot_cpu_frequency=500
|
||||
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
|
|
@ -15,7 +15,7 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
|
|
@ -31,6 +31,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[3]
|
||||
|
||||
[system.acpi_description_table_pointer]
|
||||
type=X86ACPIRSDP
|
||||
|
|
@ -52,16 +53,13 @@ oem_table_id=
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
filter_ranges_a=0:1152921504606846975
|
||||
filter_ranges_b=0:134217727
|
||||
nack_delay=4000
|
||||
req_size_a=16
|
||||
req_size_b=16
|
||||
resp_size_a=16
|
||||
resp_size_b=16
|
||||
ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
side_a=system.iobus.port[0]
|
||||
side_b=system.membus.port[1]
|
||||
master=system.iobus.port[0]
|
||||
slave=system.membus.port[1]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -535,8 +533,8 @@ pio_addr=2305843009213693952
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
int_port=system.membus.port[5]
|
||||
pio=system.membus.port[4]
|
||||
int_port=system.membus.port[7]
|
||||
pio=system.membus.port[6]
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
|
|
@ -947,6 +945,17 @@ subtractive_decode=true
|
|||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.iobridge]
|
||||
type=Bridge
|
||||
delay=50000
|
||||
nack_delay=4000
|
||||
ranges=11529215046068469760:11529215046068473855
|
||||
req_size=16
|
||||
resp_size=16
|
||||
write_ack=false
|
||||
master=system.membus.port[2]
|
||||
slave=system.iobus.port[1]
|
||||
|
||||
[system.iobus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
|
|
@ -956,7 +965,7 @@ header_cycles=1
|
|||
use_default_range=true
|
||||
width=64
|
||||
default=system.pc.pciconfig.pio
|
||||
port=system.bridge.side_a system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma
|
||||
port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
|
||||
|
||||
[system.iocache]
|
||||
type=BaseCache
|
||||
|
|
@ -987,8 +996,8 @@ tgts_per_mshr=12
|
|||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.iobus.port[18]
|
||||
mem_side=system.membus.port[2]
|
||||
cpu_side=system.iobus.port[21]
|
||||
mem_side=system.membus.port[4]
|
||||
|
||||
[system.l2c]
|
||||
type=BaseCache
|
||||
|
|
@ -1020,7 +1029,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.toL2Bus.port[0]
|
||||
mem_side=system.membus.port[3]
|
||||
mem_side=system.membus.port[5]
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
|
|
@ -1032,7 +1041,7 @@ header_cycles=1
|
|||
use_default_range=false
|
||||
width=64
|
||||
default=system.membus.badaddr_responder.pio
|
||||
port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
|
||||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
|
|
@ -1072,7 +1081,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[12]
|
||||
pio=system.iobus.port[15]
|
||||
|
||||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
|
|
@ -1082,7 +1091,7 @@ pio_latency=1000
|
|||
platform=system.pc
|
||||
system=system
|
||||
terminal=system.pc.com_1.terminal
|
||||
pio=system.iobus.port[13]
|
||||
pio=system.iobus.port[16]
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
|
|
@ -1113,7 +1122,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[14]
|
||||
pio=system.iobus.port[17]
|
||||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
|
|
@ -1130,7 +1139,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[15]
|
||||
pio=system.iobus.port[18]
|
||||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
|
|
@ -1147,7 +1156,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[16]
|
||||
pio=system.iobus.port[19]
|
||||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
|
|
@ -1164,7 +1173,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[17]
|
||||
pio=system.iobus.port[20]
|
||||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
|
|
@ -1181,7 +1190,7 @@ ret_data8=255
|
|||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[11]
|
||||
pio=system.iobus.port[14]
|
||||
|
||||
[system.pc.pciconfig]
|
||||
type=PciConfigAll
|
||||
|
|
@ -1215,7 +1224,7 @@ pio_latency=1000
|
|||
platform=system.pc
|
||||
system=system
|
||||
time=Sun Jan 1 00:00:00 2012
|
||||
pio=system.iobus.port[1]
|
||||
pio=system.iobus.port[2]
|
||||
|
||||
[system.pc.south_bridge.cmos.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
|
@ -1226,7 +1235,7 @@ pio_addr=9223372036854775808
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[2]
|
||||
pio=system.iobus.port[3]
|
||||
|
||||
[system.pc.south_bridge.ide]
|
||||
type=IdeController
|
||||
|
|
@ -1281,9 +1290,9 @@ pci_func=0
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
config=system.iobus.port[19]
|
||||
dma=system.iobus.port[20]
|
||||
pio=system.iobus.port[3]
|
||||
config=system.iobus.port[5]
|
||||
dma=system.iobus.port[6]
|
||||
pio=system.iobus.port[4]
|
||||
|
||||
[system.pc.south_bridge.ide.disks0]
|
||||
type=IdeDisk
|
||||
|
|
@ -1302,7 +1311,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1322,7 +1331,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
@ -1411,8 +1420,8 @@ pio_addr=4273995776
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
int_port=system.iobus.port[10]
|
||||
pio=system.iobus.port[9]
|
||||
int_port=system.iobus.port[13]
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
|
|
@ -1425,7 +1434,7 @@ pio_addr=0
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[4]
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.pc.south_bridge.keyboard.keyboard_int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
|
@ -1443,7 +1452,7 @@ pio_latency=1000
|
|||
platform=system.pc
|
||||
slave=system.pc.south_bridge.pic2
|
||||
system=system
|
||||
pio=system.iobus.port[5]
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.pc.south_bridge.pic1.output]
|
||||
type=X86IntSourcePin
|
||||
|
|
@ -1458,7 +1467,7 @@ pio_latency=1000
|
|||
platform=system.pc
|
||||
slave=Null
|
||||
system=system
|
||||
pio=system.iobus.port[6]
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.pc.south_bridge.pic2.output]
|
||||
type=X86IntSourcePin
|
||||
|
|
@ -1471,7 +1480,7 @@ pio_addr=9223372036854775872
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[7]
|
||||
pio=system.iobus.port[10]
|
||||
|
||||
[system.pc.south_bridge.pit.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
|
@ -1483,7 +1492,7 @@ pio_addr=9223372036854775905
|
|||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[8]
|
||||
pio=system.iobus.port[11]
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 20:47:38
|
||||
gem5 started Jan 9 2012 21:13:16
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing
|
||||
gem5 compiled Jan 23 2012 04:12:17
|
||||
gem5 started Jan 23 2012 08:29:15
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5161177988500 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.161178 # Number of seconds simulated
|
||||
sim_ticks 5161177988500 # Number of ticks simulated
|
||||
final_tick 5161177988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 384526 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2360358751 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 386468 # Number of bytes of host memory used
|
||||
host_seconds 2186.61 # Real time elapsed on the host
|
||||
host_inst_rate 290092 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1780684720 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 364016 # Number of bytes of host memory used
|
||||
host_seconds 2898.42 # Real time elapsed on the host
|
||||
sim_insts 840808469 # Number of instructions simulated
|
||||
system.physmem.bytes_read 16106624 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1233856 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 12115136 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 251666 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 189299 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 3120726 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 239065 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 2347359 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 5468085 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.l2c.replacements 169467 # number of replacements
|
||||
system.l2c.tagsinuse 38339.786444 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3812924 # Total number of references to valid blocks.
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -500,9 +502,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
|
||||
gid=100
|
||||
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 21 2011 16:28:02
|
||||
gem5 started Nov 22 2011 17:34:42
|
||||
gem5 executing on u200540-lin
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:43:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.033081 # Number of seconds simulated
|
||||
sim_ticks 33080569000 # Number of ticks simulated
|
||||
final_tick 33080569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 152633 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 55333677 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 347340 # Number of bytes of host memory used
|
||||
host_seconds 597.84 # Real time elapsed on the host
|
||||
host_inst_rate 140676 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 50998874 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 353196 # Number of bytes of host memory used
|
||||
host_seconds 648.65 # Real time elapsed on the host
|
||||
sim_insts 91249885 # Number of instructions simulated
|
||||
system.physmem.bytes_read 997440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2048 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 15585 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 32 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 30151839 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 1356204 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 61909 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 30213749 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -44,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -61,7 +64,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
|
||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -85,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -95,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:50:38
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:47:31
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,76 +1,87 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1991743 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 385676 # Number of bytes of host memory used
|
||||
host_seconds 45.82 # Real time elapsed on the host
|
||||
host_tick_rate 1183885034 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91252969 # Number of instructions simulated
|
||||
sim_seconds 0.054241 # Number of seconds simulated
|
||||
sim_ticks 54240666000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2777644 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 342980 # Number of bytes of host memory used
|
||||
host_seconds 32.85 # Real time elapsed on the host
|
||||
sim_insts 91252969 # Number of instructions simulated
|
||||
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 18908138 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 130384074 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 4738868 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 9611602391 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7952024704 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 348597084 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 9960199475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 108481333 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 108481333 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 91252969 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525682 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 396912516 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27318811 # number of memory refs
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 108481333 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -146,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -164,7 +167,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -188,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -198,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:51:14
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:48:15
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,269 +1,280 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1371366 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 393424 # Number of bytes of host memory used
|
||||
host_seconds 66.52 # Real time elapsed on the host
|
||||
host_tick_rate 2226109550 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91226321 # Number of instructions simulated
|
||||
sim_seconds 0.148086 # Number of seconds simulated
|
||||
sim_ticks 148086239000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26337591 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 946798 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 942309 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1300672 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 351948 # Number of bytes of host memory used
|
||||
host_seconds 70.14 # Real time elapsed on the host
|
||||
sim_insts 91226321 # Number of instructions simulated
|
||||
system.physmem.bytes_read 986112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2048 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 15408 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 32 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 6659039 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 249800 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 13830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 6672869 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 107830181 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 599 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 296172478 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 91226321 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525682 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27318811 # number of memory refs
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 296172478 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.335448 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 107830181 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 107830181 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26345365 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 26337591 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 942309 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9913923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 11037638000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 11037638000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 634 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 103.595504 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 325.097811 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 8910.209882 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.009921 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.271918 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 899928 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 942309 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 32061 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 931989 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 931989 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 860 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 14548 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 15408 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 15408 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 44720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 801216000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 900788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 942309 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 947397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 947397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.000955 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.312129 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.016264 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 32 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 860 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 14548 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 15408 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 34400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 616320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000955 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312129 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.016264 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 931989 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 801216000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.016264 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 15408 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 616320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.016264 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 15408 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 634 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 9235.307693 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1594542 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 32 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 296172478 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 296172478 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 15127614 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 96832 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 91226321 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 72525682 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 464563396 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840370 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 22573967 # Number of load instructions
|
||||
system.cpu.num_mem_refs 27318811 # number of memory refs
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -45,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -62,7 +64,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
|
||||
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -86,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -96,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 30 2011 17:14:16
|
||||
gem5 started Nov 30 2011 17:16:48
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:20:13
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.122216 # Number of seconds simulated
|
||||
sim_ticks 122215830000 # Number of ticks simulated
|
||||
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3705610 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1857336235 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 328592 # Number of bytes of host memory used
|
||||
host_seconds 65.80 # Real time elapsed on the host
|
||||
host_inst_rate 3409932 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 338176 # Number of bytes of host memory used
|
||||
host_seconds 71.51 # Real time elapsed on the host
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 91606089 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 326641945 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 22901951 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 3886 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 10688959466 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7999667834 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 749543566 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 11438503032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 244431661 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -147,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -165,7 +167,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
|
||||
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -189,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -199,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 30 2011 17:14:16
|
||||
gem5 started Nov 30 2011 17:16:48
|
||||
gem5 compiled Jan 23 2012 04:02:00
|
||||
gem5 started Jan 23 2012 06:21:35
|
||||
gem5 executing on zizzer
|
||||
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
|
||||
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.362431 # Number of seconds simulated
|
||||
sim_ticks 362430887000 # Number of ticks simulated
|
||||
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1940887 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2884887520 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 337564 # Number of bytes of host memory used
|
||||
host_seconds 125.63 # Real time elapsed on the host
|
||||
host_inst_rate 1587659 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346888 # Number of bytes of host memory used
|
||||
host_seconds 153.58 # Real time elapsed on the host
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 2560 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 15648 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 40 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 2763208 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 155219 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 7063 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 2770272 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 724861774 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -500,9 +502,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:45:46
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.070313 # Number of seconds simulated
|
||||
sim_ticks 70312944500 # Number of ticks simulated
|
||||
final_tick 70312944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 109444 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 27661822 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378996 # Number of bytes of host memory used
|
||||
host_seconds 2541.88 # Real time elapsed on the host
|
||||
host_inst_rate 168126 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 42493747 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 349904 # Number of bytes of host memory used
|
||||
host_seconds 1654.67 # Real time elapsed on the host
|
||||
sim_insts 278192519 # Number of instructions simulated
|
||||
system.physmem.bytes_read 4896576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 65344 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 1867840 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 76509 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 29185 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 69639752 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 929331 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 26564668 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 96204419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 140625890 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -45,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -67,9 +69,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -86,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -96,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:52:52
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.168950 # Number of seconds simulated
|
||||
sim_ticks 168950072000 # Number of ticks simulated
|
||||
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1147935 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 697156581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 368676 # Number of bytes of host memory used
|
||||
host_seconds 242.34 # Real time elapsed on the host
|
||||
host_inst_rate 2042288 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1240309006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339312 # Number of bytes of host memory used
|
||||
host_seconds 136.22 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 243173115 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 308475658 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 31439751 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 14553504772 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 10308191310 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 1439319393 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 15992824164 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 337900145 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -147,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -170,9 +172,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -189,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -199,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:268435455
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:55:19
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.370011 # Number of seconds simulated
|
||||
sim_ticks 370010840000 # Number of ticks simulated
|
||||
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 588786 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 783116445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377276 # Number of bytes of host memory used
|
||||
host_seconds 472.49 # Real time elapsed on the host
|
||||
host_inst_rate 1163147 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 348152 # Number of bytes of host memory used
|
||||
host_seconds 239.17 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
system.physmem.bytes_read 4900800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 1885440 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 76575 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 29460 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 740021680 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -478,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -520,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -530,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,8 @@
|
|||
Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 8 2012 22:11:51
|
||||
gem5 started Jan 9 2012 02:13:40
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:49:36
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.274199 # Number of seconds simulated
|
||||
sim_ticks 274198757500 # Number of ticks simulated
|
||||
final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113676 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 54365362 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225168 # Number of bytes of host memory used
|
||||
host_seconds 5043.63 # Real time elapsed on the host
|
||||
host_inst_rate 114096 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 54566255 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225172 # Number of bytes of host memory used
|
||||
host_seconds 5025.06 # Real time elapsed on the host
|
||||
sim_insts 573341162 # Number of instructions simulated
|
||||
system.physmem.bytes_read 15248640 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 10960192 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 238260 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 171253 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -44,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
|
|
@ -61,7 +64,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
|
||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -85,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -95,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:53:21
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:54:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,76 +1,87 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3887693 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 256484 # Number of bytes of host memory used
|
||||
host_seconds 146.87 # Real time elapsed on the host
|
||||
host_tick_rate 1977989899 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 570968176 # Number of instructions simulated
|
||||
sim_seconds 0.290499 # Number of seconds simulated
|
||||
sim_ticks 290498972000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3123764 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1589318228 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 213568 # Number of bytes of host memory used
|
||||
host_seconds 182.78 # Real time elapsed on the host
|
||||
sim_insts 570968176 # Number of instructions simulated
|
||||
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 216067624 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 641840242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 8569043191 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 7113434935 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 743781028 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 9312824219 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 580997945 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 580997945 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 570968176 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 580997945 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -17,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -146,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -164,7 +167,7 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
|
||||
cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
|
|
@ -188,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -198,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,10 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:47:10
|
||||
M5 started Apr 19 2011 12:55:52
|
||||
M5 executing on maize
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
|
||||
gem5 compiled Jan 23 2012 04:16:21
|
||||
gem5 started Jan 23 2012 08:54:55
|
||||
gem5 executing on zizzer
|
||||
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,269 +1,280 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1138464 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 264236 # Number of bytes of host memory used
|
||||
host_seconds 499.83 # Real time elapsed on the host
|
||||
host_tick_rate 1444968716 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 569034848 # Number of instructions simulated
|
||||
sim_seconds 0.722234 # Number of seconds simulated
|
||||
sim_ticks 722234364000 # Number of ticks simulated
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 176840705 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1025440 # number of writebacks
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1518630 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222536 # Number of bytes of host memory used
|
||||
host_seconds 374.70 # Real time elapsed on the host
|
||||
sim_insts 569034848 # Number of instructions simulated
|
||||
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 11027328 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 231204 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 172302 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 20487887 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 261145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 15268351 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 35756238 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 516599864 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 11521 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 569034848 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 516599864 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 176840705 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1025440 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 212089 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 919235 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 231204 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 172302 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 919235 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 231204 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 212089 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 172302 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 1444468728 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 569034848 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 470727703 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 126029556 # Number of load instructions
|
||||
system.cpu.num_mem_refs 182890035 # number of memory refs
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
|
|
@ -477,7 +479,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -500,9 +502,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -519,7 +521,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -529,5 +531,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:58:28
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.493912 # Number of seconds simulated
|
||||
sim_ticks 493912286000 # Number of ticks simulated
|
||||
final_tick 493912286000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 108889 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 35174673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280548 # Number of bytes of host memory used
|
||||
host_seconds 14041.70 # Real time elapsed on the host
|
||||
host_inst_rate 145271 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 46927205 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251468 # Number of bytes of host memory used
|
||||
host_seconds 10525.07 # Real time elapsed on the host
|
||||
sim_insts 1528988756 # Number of instructions simulated
|
||||
system.physmem.bytes_read 37487424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 347584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 26320960 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 585741 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 411265 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 75898950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 703736 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 53290758 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 129189708 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 987824573 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
|
|
@ -45,8 +47,8 @@ system=system
|
|||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -67,9 +69,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -86,7 +88,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -96,5 +98,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
gem5 compiled Jan 23 2012 04:08:34
|
||||
gem5 started Jan 23 2012 06:59:28
|
||||
gem5 executing on zizzer
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -2,12 +2,23 @@
|
|||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.885229 # Number of seconds simulated
|
||||
sim_ticks 885229360000 # Number of ticks simulated
|
||||
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1063398 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 615669149 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237896 # Number of bytes of host memory used
|
||||
host_seconds 1437.83 # Real time elapsed on the host
|
||||
host_inst_rate 2258239 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1307438877 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 208528 # Number of bytes of host memory used
|
||||
host_seconds 677.07 # Real time elapsed on the host
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written 991849460 # Number of bytes written to this memory
|
||||
system.physmem.num_reads 1452449298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes 149160201 # Number of write requests responded to by this memory
|
||||
system.physmem.num_other 0 # Number of other requests responded to by this memory
|
||||
system.physmem.bw_read 12236865406 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read 9654872803 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write 1120443475 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total 13357308881 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=System
|
|||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -18,6 +19,7 @@ work_cpus_ckpt_count=0
|
|||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.port[0]
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
|
|
@ -147,7 +149,7 @@ trace_addr=0
|
|||
two_queue=false
|
||||
write_buffers=8
|
||||
cpu_side=system.cpu.toL2Bus.port[2]
|
||||
mem_side=system.membus.port[1]
|
||||
mem_side=system.membus.port[2]
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
|
|
@ -170,9 +172,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
@ -189,7 +191,7 @@ clock=1000
|
|||
header_cycles=1
|
||||
use_default_range=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
|
@ -199,5 +201,5 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.membus.port[1]
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue