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regress: Regression Tester output updates

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This commit is contained in:
Brad Beckmann 2011-02-06 22:14:23 -08:00
parent f5aa75fdc5
commit 45f881919f
228 changed files with 6848 additions and 6391 deletions
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13
tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=InOrderCPU
@ -192,7 +201,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 24 2011 18:18:02
M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
M5 started Jan 24 2011 18:18:03
M5 executing on zooks
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:43:08
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 36108 # Simulator instruction rate (inst/s)
host_mem_usage 155860 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_tick_rate 125462283 # Simulator tick rate (ticks/s)
host_inst_rate 43704 # Simulator instruction rate (inst/s)
host_mem_usage 205152 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_tick_rate 151823848 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
@ -267,6 +267,8 @@ system.cpu.l2cache.total_refs 1 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 44578 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.runCycles 7154 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode

13
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=DerivO3CPU
@ -484,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 17 2011 16:24:53
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
M5 started Jan 17 2011 16:24:57
M5 executing on zizzer
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:43:02
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

31
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 10121 # Simulator instruction rate (inst/s)
host_mem_usage 203516 # Number of bytes of host memory used
host_seconds 0.63 # Real time elapsed on the host
host_tick_rate 19665204 # Simulator tick rate (ticks/s)
host_inst_rate 94328 # Simulator instruction rate (inst/s)
host_mem_usage 205636 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 182630766 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6386 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle
system.cpu.commit.COM:count 6403 # Number of instructions committed
system.cpu.commit.COM:fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 127 # Number of function calls committed.
system.cpu.commit.COM:int_insts 6321 # Number of committed integer instructions.
system.cpu.commit.COM:loads 1185 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2050 # Number of memory references committed
@ -169,6 +172,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
@ -268,6 +273,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 394 #
system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 11489 # number of integer regfile reads
system.cpu.int_regfile_writes 6462 # number of integer regfile writes
system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
@ -359,6 +366,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 9351 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 31807 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 8672 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 14983 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
@ -450,7 +465,11 @@ system.cpu.memDep0.conflictingLoads 34 # Nu
system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 24826 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
@ -463,10 +482,14 @@ system.cpu.rename.RENAME:RunCycles 2180 # Nu
system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 15016 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 22718 # The number of ROB reads
system.cpu.rob.rob_writes 22732 # The number of ROB writes
system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls

11
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:12:40
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:01:37
M5 executing on SC2B0619
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:39
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1228467 # Simulator instruction rate (inst/s)
host_mem_usage 182556 # Number of bytes of host memory used
host_inst_rate 1335558 # Simulator instruction rate (inst/s)
host_mem_usage 196940 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 587751371 # Simulator tick rate (ticks/s)
host_tick_rate 634873618 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 6431 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 6431 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

14
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -186,6 +195,7 @@ tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory

30
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
View file

@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/13/2011 22:36:30
Real time: Feb/06/2011 20:42:15
Profiler Stats
--------------
Elapsed_time_in_seconds: 2
Elapsed_time_in_minutes: 0.0333333
Elapsed_time_in_hours: 0.000555556
Elapsed_time_in_days: 2.31481e-05
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 1.2
Virtual_time_in_minutes: 0.02
Virtual_time_in_hours: 0.000333333
Virtual_time_in_days: 1.38889e-05
Virtual_time_in_seconds: 0.5
Virtual_time_in_minutes: 0.00833333
Virtual_time_in_hours: 0.000138889
Virtual_time_in_days: 5.78704e-06
Ruby_current_time: 275313
Ruby_start_time: 0
Ruby_cycles: 275313
mbytes_resident: 22.0195
mbytes_total: 156.82
resident_ratio: 0.140462
mbytes_resident: 37.0586
mbytes_total: 210.465
resident_ratio: 0.176117
ruby_cycles_executed: [ 275314 ]
@ -117,12 +117,12 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standa
Resource Usage
--------------
page_size: 4096
user_time: 1
user_time: 0
system_time: 0
page_reclaims: 6300
page_reclaims: 10709
page_faults: 0
swaps: 0
block_inputs: 0
block_inputs: 8
block_outputs: 0
Network Stats

8
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 13 2011 22:36:25
M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
M5 started Jan 13 2011 22:36:28
M5 executing on scamorza.cs.wisc.edu
M5 compiled Feb 6 2011 15:12:58
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:15
M5 executing on SC2B0617
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 4080 # Simulator instruction rate (inst/s)
host_mem_usage 160588 # Number of bytes of host memory used
host_seconds 1.57 # Real time elapsed on the host
host_tick_rate 175338 # Simulator tick rate (ticks/s)
host_inst_rate 28908 # Simulator instruction rate (inst/s)
host_mem_usage 215520 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
host_tick_rate 1241810 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000275 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 275313 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 275313 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

68
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -108,32 +117,19 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L1DcacheMemory L1IcacheMemory
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=3
@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=3
@ -177,14 +173,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -194,13 +189,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@ -216,9 +216,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
name=Crossbar
num_int_nodes=4
print_config=false

54
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 10:35:39
Real time: Feb/06/2011 20:43:55
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.44
Virtual_time_in_minutes: 0.00733333
Virtual_time_in_hours: 0.000122222
Virtual_time_in_days: 5.09259e-06
Virtual_time_in_seconds: 0.5
Virtual_time_in_minutes: 0.00833333
Virtual_time_in_hours: 0.000138889
Virtual_time_in_days: 5.78704e-06
Ruby_current_time: 223854
Ruby_start_time: 0
Ruby_cycles: 223854
mbytes_resident: 34.9609
mbytes_total: 34.9688
resident_ratio: 1
mbytes_resident: 37.1484
mbytes_total: 210.605
resident_ratio: 0.176426
ruby_cycles_executed: [ 223855 ]
@ -119,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7630
page_faults: 2184
page_reclaims: 10697
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.349752
outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 0
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 0
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 0
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
--- L1Cache ---

8
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 10:34:54
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
M5 started Aug 5 2010 10:35:39
M5 executing on svvint09
M5 compiled Feb 6 2011 20:43:45
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:43:54
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 23717 # Simulator instruction rate (inst/s)
host_mem_usage 212528 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
host_tick_rate 829037 # Simulator tick rate (ticks/s)
host_inst_rate 25740 # Simulator instruction rate (inst/s)
host_mem_usage 215664 # Number of bytes of host memory used
host_seconds 0.25 # Real time elapsed on the host
host_tick_rate 899131 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000224 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 223854 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 223854 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

68
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -111,9 +120,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L1DcacheMemory L1IcacheMemory
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@ -125,24 +134,11 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
@ -188,14 +184,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -205,13 +200,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
name=Crossbar
num_int_nodes=4
print_config=false

94
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 10:42:35
Real time: Feb/06/2011 20:27:50
Profiler Stats
--------------
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.27
Virtual_time_in_minutes: 0.0045
Virtual_time_in_hours: 7.5e-05
Virtual_time_in_days: 3.125e-06
Virtual_time_in_seconds: 0.38
Virtual_time_in_minutes: 0.00633333
Virtual_time_in_hours: 0.000105556
Virtual_time_in_days: 4.39815e-06
Ruby_current_time: 243131
Ruby_start_time: 0
Ruby_cycles: 243131
mbytes_resident: 34.8711
mbytes_total: 34.8789
resident_ratio: 1
mbytes_resident: 37.0664
mbytes_total: 210.492
resident_ratio: 0.176131
ruby_cycles_executed: [ 243132 ]
@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ]
miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -89,13 +89,13 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 ave
imcomplete_dir_Times: 1300
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -127,10 +127,10 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7568
page_faults: 2181
page_reclaims: 10675
page_faults: 0
swaps: 0
block_inputs: 0
block_inputs: 16
block_outputs: 0
Network Stats
@ -197,28 +197,28 @@ links_utilized_percent_switch_3: 0.209297
outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 646
system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 646
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 646 100%
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 734
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 734
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259%
system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741%
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.5259%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.4741%
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 734 100%
--- L1Cache ---
- Event Counts -
@ -226,7 +226,7 @@ Load [1185 ] 1185
Ifetch [6414 ] 6414
Store [865 ] 865
Atomic [0 ] 0
L1_Replacement [1384 ] 1384
L1_Replacement [1365 ] 1365
Data_Shared [48 ] 48
Data_Owner [0 ] 0
Data_All_Tokens [1332 ] 1332
@ -356,7 +356,7 @@ M_W Load [102 ] 102
M_W Ifetch [2271 ] 2271
M_W Store [25 ] 25
M_W Atomic [0 ] 0
M_W L1_Replacement [21 ] 21
M_W L1_Replacement [8 ] 8
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0
@ -373,7 +373,7 @@ MM_W Load [21 ] 21
MM_W Ifetch [0 ] 0
MM_W Store [265 ] 265
MM_W Atomic [0 ] 0
MM_W L1_Replacement [9 ] 9
MM_W L1_Replacement [3 ] 3
MM_W Transient_GETX [0 ] 0
MM_W Transient_Local_GETX [0 ] 0
MM_W Transient_GETS [0 ] 0
@ -743,18 +743,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 1301
memory_writes: 241
memory_refreshes: 507
memory_total_request_delays: 714
memory_delays_per_request: 0.463035
memory_total_request_delays: 709
memory_delays_per_request: 0.459792
memory_delays_in_input_queue: 240
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 474
memory_stalls_for_bank_busy: 148
memory_delays_stalled_at_head_of_bank_queue: 469
memory_stalls_for_bank_busy: 141
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 30
memory_stalls_for_bus: 278
memory_stalls_for_arbitration: 33
memory_stalls_for_bus: 279
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 18
memory_stalls_for_read_write_turnaround: 16
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56

8
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 10:41:36
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
M5 started Aug 5 2010 10:42:35
M5 executing on svvint09
M5 compiled Feb 6 2011 20:27:42
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:27:50
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 45740 # Simulator instruction rate (inst/s)
host_mem_usage 212336 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_tick_rate 1736538 # Simulator tick rate (ticks/s)
host_inst_rate 49047 # Simulator instruction rate (inst/s)
host_mem_usage 215548 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 1859468 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000243 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 243131 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 243131 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

97
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -70,6 +79,7 @@ type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
directory=system.dir_cntrl0.directory
full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
@ -118,17 +128,18 @@ start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
children=L2cacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L2cacheMemory
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
issue_latency=2
l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
@ -140,35 +151,6 @@ replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.physmem]
type=PhysicalMemory
file=
@ -177,14 +159,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -194,13 +175,35 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache icache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.cpu_ruby_ports.icache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@ -216,9 +219,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
name=Crossbar
num_int_nodes=3
print_config=false

164
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 11:09:30
Real time: Feb/06/2011 20:42:21
Profiler Stats
--------------
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.61
Virtual_time_in_minutes: 0.0101667
Virtual_time_in_hours: 0.000169444
Virtual_time_in_days: 7.06019e-06
Virtual_time_in_seconds: 0.4
Virtual_time_in_minutes: 0.00666667
Virtual_time_in_hours: 0.000111111
Virtual_time_in_days: 4.62963e-06
Ruby_current_time: 207970
Ruby_current_time: 208400
Ruby_start_time: 0
Ruby_cycles: 207970
Ruby_cycles: 208400
mbytes_resident: 34.3633
mbytes_total: 206.125
resident_ratio: 0.166768
mbytes_resident: 36.6992
mbytes_total: 209.844
resident_ratio: 0.174944
ruby_cycles_executed: [ 207971 ]
ruby_cycles_executed: [ 208401 ]
Busy Controller Counts:
L1Cache-0:0
@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ]
miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 1158
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -126,7 +126,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 9927
page_reclaims: 10651
page_faults: 0
swaps: 0
block_inputs: 0
@ -144,9 +144,9 @@ total_msgs: 20718 total_bytes: 430512
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.111284
links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1
links_utilized_percent_switch_0: 0.111054
links_utilized_percent_switch_0_link_0: 0.0694218 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.152687 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.111284
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.158256
links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1
links_utilized_percent_switch_1: 0.157929
links_utilized_percent_switch_1_link_0: 0.0381718 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.277687 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.158256
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.215632
links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1
links_utilized_percent_switch_2: 0.215187
links_utilized_percent_switch_2_link_0: 0.277687 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.152687 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215632
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 646
system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.ruby.cpu_ruby_ports.icache
system.ruby.cpu_ruby_ports.icache_total_misses: 646
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100%
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 646 100%
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 716
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 716
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324%
system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676%
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676%
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100%
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 716 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 1159
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159
system.l1_cntrl0.L2cacheMemory_total_misses: 1362
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294%
system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302%
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100%
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1362 100%
--- L1Cache ---
- Event Counts -
Load [1201 ] 1201
Ifetch [6436 ] 6436
Store [919 ] 919
Load [1193 ] 1193
Ifetch [6425 ] 6425
Store [892 ] 892
L2_Replacement [1143 ] 1143
L1_to_L2 [1354 ] 1354
Trigger_L2_to_L1D [138 ] 138
@ -231,6 +231,7 @@ Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
S Load [0 ] 0
@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
O Load [0 ] 0
@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
M Load [368 ] 368
@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
MM Load [397 ] 397
@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
IM Load [0 ] 0
@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
SM Exclusive_Data [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
MI Load [16 ] 16
MI Ifetch [22 ] 22
MI Store [54 ] 54
MI Load [8 ] 8
MI Ifetch [11 ] 11
MI Store [27 ] 27
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [1143 ] 1143
@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
ST Load [0 ] 0
@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
OT Load [0 ] 0
@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
MT Load [0 ] 0
@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MMT Load [0 ] 0
@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
@ -502,19 +521,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1379
memory_reads: 1159
memory_writes: 220
memory_refreshes: 434
memory_total_request_delays: 471
memory_delays_per_request: 0.341552
memory_delays_in_input_queue: 15
memory_refreshes: 435
memory_total_request_delays: 495
memory_delays_per_request: 0.358956
memory_delays_in_input_queue: 3
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 456
memory_stalls_for_bank_busy: 86
memory_delays_stalled_at_head_of_bank_queue: 492
memory_stalls_for_bank_busy: 124
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 30
memory_stalls_for_arbitration: 23
memory_stalls_for_bus: 78
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 262
memory_stalls_for_read_write_turnaround: 267
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
NO_B_X DMA_READ [0 ] 0
NO_B_X DMA_WRITE [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
@ -648,6 +669,7 @@ O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0

10
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 11:09:13
M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
M5 started Aug 5 2010 11:09:30
M5 compiled Feb 6 2011 15:12:45
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:21
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 207970 because target called exit()
Exiting @ tick 208400 because target called exit()

30
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 31390 # Simulator instruction rate (inst/s)
host_mem_usage 211076 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
host_tick_rate 1018487 # Simulator tick rate (ticks/s)
host_inst_rate 47973 # Simulator instruction rate (inst/s)
host_mem_usage 214884 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 1559052 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000208 # Number of seconds simulated
sim_ticks 207970 # Number of ticks simulated
sim_ticks 208400 # Number of ticks simulated
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 2050 # DTB hits
@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 207970 # number of cpu cycles simulated
system.cpu.numCycles 208400 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 208400 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

228
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu physmem ruby
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -65,126 +74,27 @@ simpoint=0
system=system
uid=100
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=true
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links0.ext_node
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links0.ext_node]
type=L1Cache_Controller
children=sequencer
buffer_size=0
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
type=RubySequencer
children=icache
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
deadlock_threshold=500000
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
[system.ruby.network.topology.ext_links1]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links1.ext_node
int_node=1
latency=1
weight=1
[system.ruby.network.topology.ext_links1.ext_node]
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
directory=system.ruby.network.topology.ext_links1.ext_node.directory
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links1.ext_node.directory]
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
@ -205,6 +115,100 @@ refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
buffer_size=0
cacheMemory=system.ruby.cpu_ruby_ports.dcache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.dcache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
bw_multiplier=64
ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links1]
type=ExtLink
bw_multiplier=64
ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16

282
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
View file

@ -18,9 +18,9 @@ topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/28/2010 10:15:29
Real time: Feb/06/2011 20:42:39
Profiler Stats
--------------
@ -43,31 +43,20 @@ Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.5
Virtual_time_in_minutes: 0.00833333
Virtual_time_in_hours: 0.000138889
Virtual_time_in_days: 5.78704e-06
Virtual_time_in_seconds: 0.37
Virtual_time_in_minutes: 0.00616667
Virtual_time_in_hours: 0.000102778
Virtual_time_in_days: 4.28241e-06
Ruby_current_time: 342698
Ruby_start_time: 0
Ruby_cycles: 342698
mbytes_resident: 34.2148
mbytes_total: 34.2227
resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
ruby_cycles_executed: 342699 [ 342699 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
mbytes_resident: 36.6797
mbytes_total: 209.906
resident_ratio: 0.17478
ruby_cycles_executed: [ 342699 ]
Busy Controller Counts:
L1Cache-0:0
@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average: 3 | standard deviation: 0 | 0 0 0 6734 ]
miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1729
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average: 3 | standard deviation: 0 | 0 0 0 5684 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average: 3 | standard deviation: 0 | 0 0 0 458 ]
miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average: 3 | standard deviation: 0 | 0 0 0 592 ]
miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -115,8 +122,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7357
page_faults: 2195
page_reclaims: 10613
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -124,16 +131,22 @@ block_outputs: 0
Network Stats
-------------
total_msg_count_Control: 5190 41520
total_msg_count_Data: 5178 372816
total_msg_count_Response_Data: 5190 373680
total_msg_count_Writeback_Control: 5178 41424
total_msgs: 20736 total_bytes: 829440
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.157486
links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.157661
links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252117
links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965%
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 42.0231%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 15.7803%
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 42.1965%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1730 100%
--- L1Cache 0 ---
--- L1Cache ---
- Event Counts -
Load 1185
Ifetch 6414
Store 865
Data 1730
Fwd_GETX 0
Inv 0
Replacement 1726
Writeback_Ack 1726
Writeback_Nack 0
Load [1185 ] 1185
Ifetch [6414 ] 6414
Store [865 ] 865
Data [1730 ] 1730
Fwd_GETX [0 ] 0
Inv [0 ] 0
Replacement [1726 ] 1726
Writeback_Ack [1726 ] 1726
Writeback_Nack [0 ] 0
- Transitions -
I Load 727
I Ifetch 730
I Store 273
I Inv 0 <--
I Replacement 0 <--
I Load [727 ] 727
I Ifetch [730 ] 730
I Store [273 ] 273
I Inv [0 ] 0
I Replacement [0 ] 0
II Writeback_Nack 0 <--
II Writeback_Nack [0 ] 0
M Load 458
M Ifetch 5684
M Store 592
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 1726
M Load [458 ] 458
M Ifetch [5684 ] 5684
M Store [592 ] 592
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [1726 ] 1726
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 1726
MI Writeback_Nack 0 <--
MI Fwd_GETX [0 ] 0
MI Inv [0 ] 0
MI Writeback_Ack [1726 ] 1726
MI Writeback_Nack [0 ] 0
MII Fwd_GETX 0 <--
MII Fwd_GETX [0 ] 0
IS Data 1457
IS Data [1457 ] 1457
IM Data 273
IM Data [273 ] 273
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 3456
memory_reads: 1730
memory_writes: 1726
@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
--- Directory 0 ---
--- Directory ---
- Event Counts -
GETX 1730
GETS 0
PUTX 1726
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 1730
Memory_Ack 1726
GETX [1730 ] 1730
GETS [0 ] 0
PUTX [1726 ] 1726
PUTX_NotOwner [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [1730 ] 1730
Memory_Ack [1726 ] 1726
- Transitions -
I GETX 1730
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
I GETX [1730 ] 1730
I PUTX_NotOwner [0 ] 0
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
M GETX 0 <--
M PUTX 1726
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M GETX [0 ] 0
M PUTX [1726 ] 1726
M PUTX_NotOwner [0 ] 0
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DRD GETX [0 ] 0
M_DRD PUTX [0 ] 0
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWR GETX [0 ] 0
M_DWR PUTX [0 ] 0
M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
M_DWRI GETX [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DRDI GETX 0 <--
M_DRDI Memory_Ack 0 <--
M_DRDI GETX [0 ] 0
M_DRDI Memory_Ack [0 ] 0
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 1730
IM GETX [0 ] 0
IM GETS [0 ] 0
IM PUTX [0 ] 0
IM PUTX_NotOwner [0 ] 0
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
IM Memory_Data [1730 ] 1730
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 1726
MI GETX [0 ] 0
MI GETS [0 ] 0
MI PUTX [0 ] 0
MI PUTX_NotOwner [0 ] 0
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
MI Memory_Ack [1726 ] 1726
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
ID GETX [0 ] 0
ID GETS [0 ] 0
ID PUTX [0 ] 0
ID PUTX_NotOwner [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID Memory_Data [0 ] 0
ID_W GETX [0 ] 0
ID_W GETS [0 ] 0
ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
ID_W Memory_Ack

8
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 27 2010 22:23:20
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
M5 started Jan 28 2010 10:15:28
M5 executing on svvint07
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:38
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 19405 # Simulator instruction rate (inst/s)
host_mem_usage 215700 # Number of bytes of host memory used
host_seconds 0.33 # Real time elapsed on the host
host_tick_rate 1038428 # Simulator tick rate (ticks/s)
host_inst_rate 54314 # Simulator instruction rate (inst/s)
host_mem_usage 214948 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 2902474 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000343 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 342698 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 342698 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -157,7 +166,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

12
tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:59:22
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:57
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

26
tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 332796 # Simulator instruction rate (inst/s)
host_mem_usage 204128 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1691799077 # Simulator tick rate (ticks/s)
host_inst_rate 560476 # Simulator instruction rate (inst/s)
host_mem_usage 204672 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 2823041396 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000033 # Number of seconds simulated
@ -227,8 +227,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 66014 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 66014 # Number of busy cycles
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=DerivO3CPU
@ -484,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 17 2011 16:24:53
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
M5 started Jan 17 2011 16:48:46
M5 executing on zizzer
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:36
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

30
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 61982 # Simulator instruction rate (inst/s)
host_mem_usage 202420 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_tick_rate 188319059 # Simulator tick rate (ticks/s)
host_inst_rate 78818 # Simulator instruction rate (inst/s)
host_mem_usage 204536 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
host_tick_rate 238897798 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle
system.cpu.commit.COM:count 2576 # Number of instructions committed
system.cpu.commit.COM:fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 71 # Number of function calls committed.
system.cpu.commit.COM:int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.COM:loads 415 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 709 # Number of memory references committed
@ -169,6 +172,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency
@ -268,6 +272,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 141 #
system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 4283 # number of integer regfile reads
system.cpu.int_regfile_writes 2601 # number of integer regfile writes
system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -359,6 +365,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 3659 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 14008 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 3396 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 5997 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
@ -449,7 +463,11 @@ system.cpu.memDep0.conflictingLoads 16 # Nu
system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.numCycles 14601 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full
@ -462,10 +480,14 @@ system.cpu.rename.RENAME:RunCycles 901 # Nu
system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5502 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 10620 # The number of ROB reads
system.cpu.rob.rob_writes 9524 # The number of ROB writes
system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls

13
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@ -57,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864

10
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout
Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Nov 2 2010 21:30:55
M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
M5 started Nov 2 2010 21:32:40
M5 executing on aus-bc2-b15
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:47
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 759729 # Simulator instruction rate (inst/s)
host_mem_usage 228516 # Number of bytes of host memory used
host_inst_rate 849934 # Simulator instruction rate (inst/s)
host_mem_usage 196124 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 362937063 # Simulator tick rate (ticks/s)
host_tick_rate 396667686 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 2596 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

14
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -186,6 +195,7 @@ tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory

26
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
View file

@ -34,27 +34,27 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/13/2011 22:36:30
Real time: Feb/06/2011 20:42:15
Profiler Stats
--------------
Elapsed_time_in_seconds: 2
Elapsed_time_in_minutes: 0.0333333
Elapsed_time_in_hours: 0.000555556
Elapsed_time_in_days: 2.31481e-05
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.79
Virtual_time_in_minutes: 0.0131667
Virtual_time_in_hours: 0.000219444
Virtual_time_in_days: 9.14352e-06
Virtual_time_in_seconds: 0.37
Virtual_time_in_minutes: 0.00616667
Virtual_time_in_hours: 0.000102778
Virtual_time_in_days: 4.28241e-06
Ruby_current_time: 103637
Ruby_start_time: 0
Ruby_cycles: 103637
mbytes_resident: 20.9219
mbytes_total: 156.062
resident_ratio: 0.134111
mbytes_resident: 35.7305
mbytes_total: 209.473
resident_ratio: 0.170611
ruby_cycles_executed: [ 103638 ]
@ -119,7 +119,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 6028
page_reclaims: 10361
page_faults: 0
swaps: 0
block_inputs: 0

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 13 2011 22:36:25
M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
M5 started Jan 13 2011 22:36:28
M5 executing on scamorza.cs.wisc.edu
M5 compiled Feb 6 2011 15:12:58
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:15
M5 executing on SC2B0617
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2534 # Simulator instruction rate (inst/s)
host_mem_usage 159812 # Number of bytes of host memory used
host_seconds 1.02 # Real time elapsed on the host
host_tick_rate 101843 # Simulator tick rate (ticks/s)
host_inst_rate 29262 # Simulator instruction rate (inst/s)
host_mem_usage 214504 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 1174597 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000104 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 103637 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 103637 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

68
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -108,32 +117,19 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L1DcacheMemory L1IcacheMemory
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
buffer_size=0
l2_select_num_bits=0
number_of_TBEs=256
recycle_latency=10
request_latency=2
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=3
@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=3
@ -177,14 +173,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -194,13 +189,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@ -216,9 +216,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
name=Crossbar
num_int_nodes=4
print_config=false

46
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, unordered
virtual_net_1: active, unordered
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 10:37:10
Real time: Feb/06/2011 20:43:54
Profiler Stats
--------------
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.41
Virtual_time_in_minutes: 0.00683333
Virtual_time_in_hours: 0.000113889
Virtual_time_in_days: 4.74537e-06
Virtual_time_in_seconds: 0.34
Virtual_time_in_minutes: 0.00566667
Virtual_time_in_hours: 9.44444e-05
Virtual_time_in_days: 3.93519e-06
Ruby_current_time: 85988
Ruby_start_time: 0
Ruby_cycles: 85988
mbytes_resident: 33.6484
mbytes_total: 33.6562
resident_ratio: 1
mbytes_resident: 35.8281
mbytes_total: 209.613
resident_ratio: 0.170962
ruby_cycles_executed: [ 85989 ]
@ -119,8 +119,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7386
page_faults: 2090
page_reclaims: 10369
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645
outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 0
system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 0
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 0
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 0
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
--- L1Cache ---

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 10:34:54
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
M5 started Aug 5 2010 10:37:10
M5 executing on svvint09
M5 compiled Feb 6 2011 20:43:45
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:43:54
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 19822 # Simulator instruction rate (inst/s)
host_mem_usage 211548 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 661411 # Simulator tick rate (ticks/s)
host_inst_rate 22051 # Simulator instruction rate (inst/s)
host_mem_usage 214648 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 734783 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000086 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 85988 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 85988 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

68
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -111,9 +120,9 @@ version=0
[system.l1_cntrl0]
type=L1Cache_Controller
children=sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L1DcacheMemory L1IcacheMemory
L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
N_tokens=2
buffer_size=0
dynamic_timeout_enabled=true
@ -125,24 +134,11 @@ no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
retry_threshold=1
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
[system.l1_cntrl0.L1DcacheMemory]
type=RubyCache
assoc=2
latency=2
@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
[system.l1_cntrl0.L1IcacheMemory]
type=RubyCache
assoc=2
latency=2
@ -188,14 +184,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -205,13 +200,18 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
access_phys_mem=true
dcache=system.l1_cntrl0.L1DcacheMemory
deadlock_threshold=500000
icache=system.l1_cntrl0.L1IcacheMemory
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network]
type=SimpleNetwork
@ -227,9 +227,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
name=Crossbar
num_int_nodes=4
print_config=false

62
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, ordered
virtual_net_1: active, unordered
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 10:43:25
Real time: Feb/06/2011 20:27:50
Profiler Stats
--------------
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.25
Virtual_time_in_minutes: 0.00416667
Virtual_time_in_hours: 6.94444e-05
Virtual_time_in_days: 2.89352e-06
Virtual_time_in_seconds: 0.33
Virtual_time_in_minutes: 0.0055
Virtual_time_in_hours: 9.16667e-05
Virtual_time_in_days: 3.81944e-06
Ruby_current_time: 92099
Ruby_start_time: 0
Ruby_cycles: 92099
mbytes_resident: 33.5859
mbytes_total: 33.5938
resident_ratio: 1
mbytes_resident: 35.7734
mbytes_total: 209.453
resident_ratio: 0.170832
ruby_cycles_executed: [ 92100 ]
@ -127,10 +127,10 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7341
page_faults: 2084
page_reclaims: 10358
page_faults: 0
swaps: 0
block_inputs: 0
block_inputs: 16
block_outputs: 0
Network Stats
@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 270
system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1IcacheMemory
system.l1_cntrl0.L1IcacheMemory_total_misses: 270
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 243
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.l1_cntrl0.L1DcacheMemory
system.l1_cntrl0.L1DcacheMemory_total_misses: 243
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971%
system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029%
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100%
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
--- L1Cache ---
- Event Counts -
@ -222,7 +222,7 @@ Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Atomic [0 ] 0
L1_Replacement [506 ] 506
L1_Replacement [503 ] 503
Data_Shared [18 ] 18
Data_Owner [0 ] 0
Data_All_Tokens [495 ] 495
@ -352,7 +352,7 @@ M_W Load [47 ] 47
M_W Ifetch [1038 ] 1038
M_W Store [6 ] 6
M_W Atomic [0 ] 0
M_W L1_Replacement [4 ] 4
M_W L1_Replacement [1 ] 1
M_W Transient_GETX [0 ] 0
M_W Transient_Local_GETX [0 ] 0
M_W Transient_GETS [0 ] 0

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 10:41:36
M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
M5 started Aug 5 2010 10:43:25
M5 executing on svvint09
M5 compiled Feb 6 2011 20:27:42
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:27:50
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 42948 # Simulator instruction rate (inst/s)
host_mem_usage 211392 # Number of bytes of host memory used
host_inst_rate 45706 # Simulator instruction rate (inst/s)
host_mem_usage 214484 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 1534907 # Simulator tick rate (ticks/s)
host_tick_rate 1628169 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000092 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 92099 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 92099 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

99
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.l1_cntrl0.sequencer.port[1]
icache_port=system.l1_cntrl0.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -70,6 +79,7 @@ type=Directory_Controller
children=directory memBuffer probeFilter
buffer_size=0
directory=system.dir_cntrl0.directory
full_bit_dir_enabled=false
memBuffer=system.dir_cntrl0.memBuffer
memory_controller_latency=2
number_of_TBEs=256
@ -118,17 +128,18 @@ start_index_bit=6
[system.l1_cntrl0]
type=L1Cache_Controller
children=L2cacheMemory sequencer
L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
L1IcacheMemory=system.l1_cntrl0.sequencer.icache
children=L2cacheMemory
L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
L2cacheMemory=system.l1_cntrl0.L2cacheMemory
buffer_size=0
cache_response_latency=10
issue_latency=2
l2_cache_hit_latency=10
no_mig_atomic=true
number_of_TBEs=256
recycle_latency=10
sequencer=system.l1_cntrl0.sequencer
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
@ -140,35 +151,6 @@ replacement_policy=PSEUDO_LRU
size=512
start_index_bit=6
[system.l1_cntrl0.sequencer]
type=RubySequencer
children=dcache icache
dcache=system.l1_cntrl0.sequencer.dcache
deadlock_threshold=500000
icache=system.l1_cntrl0.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.l1_cntrl0.sequencer.dcache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.l1_cntrl0.sequencer.icache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.physmem]
type=PhysicalMemory
file=
@ -177,14 +159,13 @@ latency_var=0
null=false
range=0:134217727
zero=false
port=system.l1_cntrl0.sequencer.physMemPort
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
@ -194,13 +175,35 @@ randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache icache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.cpu_ruby_ports.icache]
type=RubyCache
assoc=2
latency=2
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
@ -216,9 +219,9 @@ topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
name=Crossbar
num_int_nodes=3
print_config=false

164
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
View file

@ -13,7 +13,7 @@ RubySystem config:
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology: Crossbar
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Aug/05/2010 14:44:19
Real time: Feb/06/2011 20:42:21
Profiler Stats
--------------
@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.21
Virtual_time_in_minutes: 0.0035
Virtual_time_in_hours: 5.83333e-05
Virtual_time_in_days: 2.43056e-06
Virtual_time_in_seconds: 0.31
Virtual_time_in_minutes: 0.00516667
Virtual_time_in_hours: 8.61111e-05
Virtual_time_in_days: 3.58796e-06
Ruby_current_time: 78408
Ruby_current_time: 78448
Ruby_start_time: 0
Ruby_cycles: 78408
Ruby_cycles: 78448
mbytes_resident: 33.3242
mbytes_total: 33.332
resident_ratio: 1
mbytes_resident: 35.418
mbytes_total: 208.91
resident_ratio: 0.169593
ruby_cycles_executed: [ 78409 ]
ruby_cycles_executed: [ 78449 ]
Busy Controller Counts:
L1Cache-0:0
@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 440
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -126,8 +126,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7298
page_faults: 2071
page_reclaims: 10333
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.110878
links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1
links_utilized_percent_switch_0: 0.110822
links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110878
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.159064
links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1
links_utilized_percent_switch_1: 0.158983
links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.159064
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.215954
links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1
links_utilized_percent_switch_2: 0.215844
links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215954
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
Cache Stats: system.l1_cntrl0.sequencer.icache
system.l1_cntrl0.sequencer.icache_total_misses: 270
system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
system.l1_cntrl0.sequencer.icache_total_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
Cache Stats: system.ruby.cpu_ruby_ports.icache
system.ruby.cpu_ruby_ports.icache_total_misses: 270
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100%
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100%
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100%
Cache Stats: system.l1_cntrl0.sequencer.dcache
system.l1_cntrl0.sequencer.dcache_total_misses: 240
system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240
system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 240
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333%
system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667%
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667%
system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100%
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 441
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441
system.l1_cntrl0.L2cacheMemory_total_misses: 510
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358%
system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100%
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100%
--- L1Cache ---
- Event Counts -
Load [428 ] 428
Ifetch [2597 ] 2597
Store [302 ] 302
Load [422 ] 422
Ifetch [2591 ] 2591
Store [298 ] 298
L2_Replacement [425 ] 425
L1_to_L2 [502 ] 502
Trigger_L2_to_L1D [47 ] 47
@ -231,6 +231,7 @@ Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
S Load [0 ] 0
@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
O Load [0 ] 0
@ -278,6 +281,7 @@ O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
M Load [131 ] 131
@ -291,6 +295,7 @@ M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
MM Load [138 ] 138
@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
IM Load [0 ] 0
@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
SM Exclusive_Data [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
MI Load [13 ] 13
MI Ifetch [12 ] 12
MI Store [8 ] 8
MI Load [7 ] 7
MI Ifetch [6 ] 6
MI Store [4 ] 4
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [425 ] 425
@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
ST Load [0 ] 0
@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
OT Load [0 ] 0
@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
MT Load [0 ] 0
@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MMT Load [0 ] 0
@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
@ -503,18 +522,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
memory_reads: 441
memory_writes: 81
memory_refreshes: 164
memory_total_request_delays: 147
memory_delays_per_request: 0.281609
memory_total_request_delays: 151
memory_delays_per_request: 0.289272
memory_delays_in_input_queue: 2
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 145
memory_stalls_for_bank_busy: 27
memory_delays_stalled_at_head_of_bank_queue: 149
memory_stalls_for_bank_busy: 22
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 6
memory_stalls_for_bus: 23
memory_stalls_for_arbitration: 7
memory_stalls_for_bus: 26
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 89
memory_stalls_for_read_write_turnaround: 94
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
NO_B_X DMA_READ [0 ] 0
NO_B_X DMA_WRITE [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
@ -648,6 +669,7 @@ O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0

10
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
View file

@ -5,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 5 2010 14:43:33
M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
M5 started Aug 5 2010 14:44:19
M5 executing on svvint09
M5 compiled Feb 6 2011 15:12:45
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:21
M5 executing on SC2B0617
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 78408 because target called exit()
Exiting @ tick 78448 because target called exit()

30
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 42947 # Simulator instruction rate (inst/s)
host_mem_usage 211060 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 1306713 # Simulator tick rate (ticks/s)
host_inst_rate 52381 # Simulator instruction rate (inst/s)
host_mem_usage 213928 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 1589078 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000078 # Number of seconds simulated
sim_ticks 78408 # Number of ticks simulated
sim_ticks 78448 # Number of ticks simulated
system.cpu.dtb.data_accesses 717 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 709 # DTB hits
@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 78408 # number of cpu cycles simulated
system.cpu.numCycles 78448 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 78448 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

228
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu physmem ruby
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=AlphaTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -65,126 +74,27 @@ simpoint=0
system=system
uid=100
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=true
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links0.ext_node
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links0.ext_node]
type=L1Cache_Controller
children=sequencer
buffer_size=0
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
type=RubySequencer
children=icache
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
deadlock_threshold=500000
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
[system.ruby.network.topology.ext_links1]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links1.ext_node
int_node=1
latency=1
weight=1
[system.ruby.network.topology.ext_links1.ext_node]
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
directory=system.ruby.network.topology.ext_links1.ext_node.directory
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links1.ext_node.directory]
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
@ -205,6 +115,100 @@ refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
buffer_size=0
cacheMemory=system.ruby.cpu_ruby_ports.dcache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.dcache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
bw_multiplier=64
ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links1]
type=ExtLink
bw_multiplier=64
ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16

290
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
View file

@ -18,9 +18,9 @@ topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@ -34,40 +34,29 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/28/2010 10:26:06
Real time: Feb/06/2011 20:42:40
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Virtual_time_in_seconds: 0.25
Virtual_time_in_minutes: 0.00416667
Virtual_time_in_hours: 6.94444e-05
Virtual_time_in_days: 2.89352e-06
Virtual_time_in_seconds: 0.32
Virtual_time_in_minutes: 0.00533333
Virtual_time_in_hours: 8.88889e-05
Virtual_time_in_days: 3.7037e-06
Ruby_current_time: 123378
Ruby_start_time: 0
Ruby_cycles: 123378
mbytes_resident: 32.8828
mbytes_total: 32.8906
resident_ratio: 1
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
ruby_cycles_executed: 123379 [ 123379 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
mbytes_resident: 35.3594
mbytes_total: 208.918
resident_ratio: 0.169287
ruby_cycles_executed: [ 123379 ]
Busy Controller Counts:
L1Cache-0:0
@ -81,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average: 3 | standard deviation: 0 | 0 0 0 2668 ]
miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 625
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average: 3 | standard deviation: 0 | 0 0 0 2288 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average: 3 | standard deviation: 0 | 0 0 0 170 ]
miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average: 3 | standard deviation: 0 | 0 0 0 210 ]
miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -115,8 +122,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7118
page_faults: 2103
page_reclaims: 10291
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -124,16 +131,22 @@ block_outputs: 0
Network Stats
-------------
total_msg_count_Control: 1878 15024
total_msg_count_Data: 1866 134352
total_msg_count_Response_Data: 1878 135216
total_msg_count_Writeback_Control: 1866 14928
total_msgs: 7488 total_bytes: 299520
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.157808
links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
@ -141,10 +154,10 @@ links_utilized_percent_switch_1: 0.158294
links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
@ -152,66 +165,64 @@ links_utilized_percent_switch_2: 0.252881
links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 626
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441%
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 39.1374%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.4185%
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 47.4441%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 626 100%
--- L1Cache 0 ---
--- L1Cache ---
- Event Counts -
Load 415
Ifetch 2585
Store 294
Data 626
Fwd_GETX 0
Inv 0
Replacement 622
Writeback_Ack 622
Writeback_Nack 0
Load [415 ] 415
Ifetch [2585 ] 2585
Store [294 ] 294
Data [626 ] 626
Fwd_GETX [0 ] 0
Inv [0 ] 0
Replacement [622 ] 622
Writeback_Ack [622 ] 622
Writeback_Nack [0 ] 0
- Transitions -
I Load 245
I Ifetch 297
I Store 84
I Inv 0 <--
I Replacement 0 <--
I Load [245 ] 245
I Ifetch [297 ] 297
I Store [84 ] 84
I Inv [0 ] 0
I Replacement [0 ] 0
II Writeback_Nack 0 <--
II Writeback_Nack [0 ] 0
M Load 170
M Ifetch 2288
M Store 210
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 622
M Load [170 ] 170
M Ifetch [2288 ] 2288
M Store [210 ] 210
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [622 ] 622
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 622
MI Writeback_Nack 0 <--
MI Fwd_GETX [0 ] 0
MI Inv [0 ] 0
MI Writeback_Ack [622 ] 622
MI Writeback_Nack [0 ] 0
MII Fwd_GETX 0 <--
MII Fwd_GETX [0 ] 0
IS Data 542
IS Data [542 ] 542
IM Data 84
IM Data [84 ] 84
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 1248
memory_reads: 626
memory_writes: 622
@ -231,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
--- Directory 0 ---
--- Directory ---
- Event Counts -
GETX 626
GETS 0
PUTX 622
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 626
Memory_Ack 622
GETX [626 ] 626
GETS [0 ] 0
PUTX [622 ] 622
PUTX_NotOwner [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [626 ] 626
Memory_Ack [622 ] 622
- Transitions -
I GETX 626
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
I GETX [626 ] 626
I PUTX_NotOwner [0 ] 0
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
M GETX 0 <--
M PUTX 622
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M GETX [0 ] 0
M PUTX [622 ] 622
M PUTX_NotOwner [0 ] 0
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DRD GETX [0 ] 0
M_DRD PUTX [0 ] 0
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWR GETX [0 ] 0
M_DWR PUTX [0 ] 0
M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
M_DWRI GETX [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DRDI GETX 0 <--
M_DRDI Memory_Ack 0 <--
M_DRDI GETX [0 ] 0
M_DRDI Memory_Ack [0 ] 0
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 626
IM GETX [0 ] 0
IM GETS [0 ] 0
IM PUTX [0 ] 0
IM PUTX_NotOwner [0 ] 0
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
IM Memory_Data [626 ] 626
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 622
MI GETX [0 ] 0
MI GETS [0 ] 0
MI PUTX [0 ] 0
MI PUTX_NotOwner [0 ] 0
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
MI Memory_Ack [622 ] 622
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
ID GETX [0 ] 0
ID GETS [0 ] 0
ID PUTX [0 ] 0
ID PUTX_NotOwner [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID Memory_Data [0 ] 0
ID_W GETX [0 ] 0
ID_W GETS [0 ] 0
ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
ID_W Memory_Ack

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 27 2010 22:23:20
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
M5 started Jan 28 2010 10:26:06
M5 executing on svvint07
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:42:39
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 51538 # Simulator instruction rate (inst/s)
host_mem_usage 214632 # Number of bytes of host memory used
host_inst_rate 50430 # Simulator instruction rate (inst/s)
host_mem_usage 213936 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 2467461 # Simulator tick rate (ticks/s)
host_tick_rate 2406014 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000123 # Number of seconds simulated
@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 123378 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 123378 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -157,7 +166,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864

12
tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 11:51:59
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
M5 compiled Feb 6 2011 20:42:22
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:43:01
M5 executing on SC2B0617
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

26
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 97740 # Simulator instruction rate (inst/s)
host_mem_usage 203308 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
host_tick_rate 629585132 # Simulator tick rate (ticks/s)
host_inst_rate 391701 # Simulator instruction rate (inst/s)
host_mem_usage 203856 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 2449817385 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
@ -226,8 +226,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 33538 # Number of busy cycles
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_fp_insts 6 # number of float instructions
system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_int_insts 2375 # number of integer instructions
system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_mem_refs 717 # number of memory refs
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=DerivO3CPU
@ -484,7 +493,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 11 2011 18:16:01
M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
M5 started Jan 12 2011 04:32:17
M5 executing on u200439-lin.austin.arm.com
M5 compiled Feb 6 2011 15:30:08
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:48:42
M5 executing on SC2B0617
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

30
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 59213 # Simulator instruction rate (inst/s)
host_mem_usage 247916 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 108401013 # Simulator tick rate (ticks/s)
host_inst_rate 76010 # Simulator instruction rate (inst/s)
host_mem_usage 216532 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_tick_rate 138961844 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5620 # Number of instructions simulated
sim_seconds 0.000010 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 10656 # Number of insts commited each cycle
system.cpu.commit.COM:count 5620 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 4889 # Number of committed integer instructions.
system.cpu.commit.COM:loads 1207 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2145 # Number of memory references committed
@ -171,6 +174,7 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11818 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 1675 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 34635.549872 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209 # average ReadReq mshr miss latency
@ -270,6 +274,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 708 #
system.cpu.iew.memOrderViolationEvents 34 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 609 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 19236 # number of integer regfile reads
system.cpu.int_regfile_writes 5710 # number of integer regfile writes
system.cpu.ipc 0.272340 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.272340 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -361,6 +367,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 11818 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.440202 # Inst issue rate
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 54 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 58 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 9243 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 30172 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 7972 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 17831 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 11904 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 9084 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2 # Number of non-speculative instructions added to the IQ
@ -458,7 +472,11 @@ system.cpu.memDep0.conflictingLoads 12 # Nu
system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2545 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1646 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 15396 # number of misc regfile reads
system.cpu.misc_regfile_writes 3 # number of misc regfile writes
system.cpu.numCycles 20636 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4006 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 46 # Number of times rename has blocked due to IQ full
@ -471,10 +489,14 @@ system.cpu.rename.RENAME:RunCycles 2314 # Nu
system.cpu.rename.RENAME:SquashCycles 1162 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 187 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 6085 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 744 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 36764 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 271 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 537 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 22070 # The number of ROB reads
system.cpu.rob.rob_writes 24470 # The number of ROB writes
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls

13
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU
@ -57,7 +66,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

10
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 11 2010 18:37:23
M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
M5 started Oct 11 2010 18:37:39
M5 executing on aus-bc3-b4
command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
M5 compiled Feb 6 2011 15:30:08
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:48:42
M5 executing on SC2B0617
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!

24
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 402550 # Simulator instruction rate (inst/s)
host_mem_usage 249936 # Number of bytes of host memory used
host_inst_rate 942479 # Simulator instruction rate (inst/s)
host_mem_usage 207780 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 197047093 # Simulator tick rate (ticks/s)
host_tick_rate 453681328 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5620 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@ -53,8 +53,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5633 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 5633 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5620 # Number of instructions executed
system.cpu.num_refs 2145 # Number of memory references
system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses
system.cpu.num_int_insts 4889 # number of integer instructions
system.cpu.num_int_register_reads 14091 # number of times the integer registers were read
system.cpu.num_int_register_writes 3689 # number of times the integer registers were written
system.cpu.num_load_insts 1207 # Number of load instructions
system.cpu.num_mem_refs 2145 # number of memory refs
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -157,7 +166,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/arm/linux/simple-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Dec 7 2010 18:51:32
M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch
M5 started Dec 7 2010 18:51:46
M5 executing on u200439-lin.austin.arm.com
M5 compiled Feb 6 2011 15:30:08
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:48:42
M5 executing on SC2B0617
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 315416 # Simulator instruction rate (inst/s)
host_mem_usage 248988 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1472008046 # Simulator tick rate (ticks/s)
host_inst_rate 437377 # Simulator instruction rate (inst/s)
host_mem_usage 215508 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 2028175520 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5563 # Number of instructions simulated
sim_seconds 0.000026 # Number of seconds simulated
@ -237,8 +237,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 52692 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 52692 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5563 # Number of instructions executed
system.cpu.num_refs 2145 # Number of memory references
system.cpu.num_int_alu_accesses 4889 # Number of integer alu accesses
system.cpu.num_int_insts 4889 # number of integer instructions
system.cpu.num_int_register_reads 15212 # number of times the integer registers were read
system.cpu.num_int_register_writes 3689 # number of times the integer registers were written
system.cpu.num_load_insts 1207 # Number of load instructions
system.cpu.num_mem_refs 2145 # number of memory refs
system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=InOrderCPU
@ -246,7 +255,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/mips/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 24 2011 18:37:16
M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
M5 started Jan 24 2011 18:37:18
M5 executing on zooks
M5 compiled Feb 6 2011 15:20:27
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:02
M5 executing on SC2B0617
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 32637 # Simulator instruction rate (inst/s)
host_mem_usage 156860 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_tick_rate 120410651 # Simulator tick rate (ticks/s)
host_inst_rate 42279 # Simulator instruction rate (inst/s)
host_mem_usage 206292 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_tick_rate 155948553 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000022 # Number of seconds simulated
@ -253,6 +253,8 @@ system.cpu.l2cache.total_refs 2 # To
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.numCycles 43069 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.runCycles 6002 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode

13
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=DerivO3CPU
@ -538,7 +547,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864

8
tests/quick/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 17 2011 21:17:36
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
M5 started Jan 17 2011 21:17:39
M5 executing on zizzer
M5 compiled Feb 6 2011 15:20:27
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:02
M5 executing on SC2B0617
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

30
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 35741 # Simulator instruction rate (inst/s)
host_mem_usage 204488 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_tick_rate 88262097 # Simulator tick rate (ticks/s)
host_inst_rate 88897 # Simulator instruction rate (inst/s)
host_mem_usage 206716 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 218871445 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5169 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 12273 # Number of insts commited each cycle
system.cpu.commit.COM:count 5826 # Number of instructions committed
system.cpu.commit.COM:fp_insts 2 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 87 # Number of function calls committed.
system.cpu.commit.COM:int_insts 5124 # Number of committed integer instructions.
system.cpu.commit.COM:loads 1164 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2089 # Number of memory references committed
@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12922 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 1555 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36274.074074 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109 # average ReadReq mshr miss latency
@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 210 #
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 9780 # number of integer regfile reads
system.cpu.int_regfile_writes 4751 # number of integer regfile writes
system.cpu.ipc 0.202151 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.202151 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 12922 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.288346 # Inst issue rate
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 7513 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 27837 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 6791 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 10538 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 8058 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 7373 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
@ -436,7 +451,10 @@ system.cpu.memDep0.conflictingLoads 5 # Nu
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2139 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1135 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 136 # number of misc regfile reads
system.cpu.numCycles 25570 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 238 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
system.cpu.rename.RENAME:IdleCycles 8931 # Number of cycles rename is idle
@ -448,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 2609 # Nu
system.cpu.rename.RENAME:SquashCycles 649 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 81 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 2709 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 5 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 12083 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 414 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 196 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 21491 # The number of ROB reads
system.cpu.rob.rob_writes 19268 # The number of ROB writes
system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls

11
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU

8
tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:13:04
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:11:22
M5 executing on SC2B0619
M5 compiled Feb 6 2011 15:20:27
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:02
M5 executing on SC2B0617
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1101929 # Simulator instruction rate (inst/s)
host_mem_usage 183300 # Number of bytes of host memory used
host_inst_rate 930385 # Simulator instruction rate (inst/s)
host_mem_usage 197752 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 525428314 # Simulator tick rate (ticks/s)
host_tick_rate 445693743 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5828 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 5828 # Number of busy cycles
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_refs 2090 # Number of memory references
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_int_insts 5126 # number of integer instructions
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_mem_refs 2090 # number of memory refs
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------

231
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu physmem ruby
mem_mode=atomic
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -86,8 +95,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=MipsTLB
@ -108,7 +117,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/mips/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -119,127 +128,27 @@ simpoint=0
system=system
uid=100
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tech_nm=45
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=true
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links0.ext_node
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links0.ext_node]
type=L1Cache_Controller
children=sequencer
buffer_size=0
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
type=RubySequencer
children=icache
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
deadlock_threshold=500000
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
[system.ruby.network.topology.ext_links1]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links1.ext_node
int_node=1
latency=1
weight=1
[system.ruby.network.topology.ext_links1.ext_node]
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
directory=system.ruby.network.topology.ext_links1.ext_node.directory
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links1.ext_node.directory]
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
@ -260,6 +169,100 @@ refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
buffer_size=0
cacheMemory=system.ruby.cpu_ruby_ports.dcache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.dcache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
bw_multiplier=64
ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links1]
type=ExtLink
bw_multiplier=64
ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16

8
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 21 2010 11:12:15
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
M5 started Jan 21 2010 11:12:51
M5 executing on svvint07
M5 compiled Feb 6 2011 15:20:27
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:13
M5 executing on SC2B0617
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 24278 # Simulator instruction rate (inst/s)
host_mem_usage 347460 # Number of bytes of host memory used
host_seconds 0.24 # Real time elapsed on the host
host_tick_rate 1220626 # Simulator tick rate (ticks/s)
host_inst_rate 54057 # Simulator instruction rate (inst/s)
host_mem_usage 215848 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
host_tick_rate 2713497 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000293 # Number of seconds simulated
@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 292960 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 292960 # Number of busy cycles
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_refs 2090 # Number of memory references
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_int_insts 5126 # number of integer instructions
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_mem_refs 2090 # number of memory refs
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -211,7 +220,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864

12
tests/quick/00.hello/ref/mips/linux/simple-timing/simout
View file

@ -1,5 +1,3 @@
Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@ -7,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 12:56:28
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:56:30
M5 executing on zizzer
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
M5 compiled Feb 6 2011 15:20:27
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:12
M5 executing on SC2B0617
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

26
tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 5098 # Simulator instruction rate (inst/s)
host_mem_usage 204896 # Number of bytes of host memory used
host_seconds 1.14 # Real time elapsed on the host
host_tick_rate 28066026 # Simulator tick rate (ticks/s)
host_inst_rate 499743 # Simulator instruction rate (inst/s)
host_mem_usage 205480 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 2679135009 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000032 # Number of seconds simulated
@ -213,8 +213,24 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 64176 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 64176 # Number of busy cycles
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_refs 2090 # Number of memory references
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_int_insts 5126 # number of integer instructions
system.cpu.num_int_register_reads 7301 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_mem_refs 2090 # number of memory refs
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------

13
tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=DerivO3CPU
@ -485,7 +494,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864

2
tests/quick/00.hello/ref/power/linux/o3-timing/simerr
View file

@ -1,5 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero.
warn: allowing mmap of file @ fd 17108232. This will break if not /dev/zero.
For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here

8
tests/quick/00.hello/ref/power/linux/o3-timing/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 17 2011 17:18:01
M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
M5 started Jan 17 2011 17:18:03
M5 executing on zizzer
M5 compiled Feb 6 2011 15:21:41
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:45
M5 executing on SC2B0617
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

29
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 12762 # Simulator instruction rate (inst/s)
host_mem_usage 202140 # Number of bytes of host memory used
host_seconds 0.45 # Real time elapsed on the host
host_tick_rate 25804848 # Simulator tick rate (ticks/s)
host_inst_rate 99962 # Simulator instruction rate (inst/s)
host_mem_usage 204080 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 201303938 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5800 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
@ -37,6 +37,9 @@ system.cpu.commit.COM:committed_per_cycle::min_value 0
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle
system.cpu.commit.COM:count 5800 # Number of instructions committed
system.cpu.commit.COM:fp_insts 22 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 103 # Number of function calls committed.
system.cpu.commit.COM:int_insts 5706 # Number of committed integer instructions.
system.cpu.commit.COM:loads 962 # Number of loads committed
system.cpu.commit.COM:membars 7 # Number of memory barriers committed
system.cpu.commit.COM:refs 2008 # Number of memory references committed
@ -162,6 +165,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency
@ -261,6 +266,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 404 #
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 12419 # number of integer regfile reads
system.cpu.int_regfile_writes 6594 # number of integer regfile writes
system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
@ -352,6 +359,14 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate
system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 8211 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 27329 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 7555 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 12158 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
@ -437,6 +452,8 @@ system.cpu.memDep0.conflictingStores 29 # Nu
system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles 23467 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full
@ -449,10 +466,14 @@ system.cpu.rename.RENAME:RunCycles 1825 # Nu
system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 55 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 16177 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 19611 # The number of ROB reads
system.cpu.rob.rob_writes 18950 # The number of ROB writes
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls

11
tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU

2
tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
View file

@ -1,5 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
warn: allowing mmap of file @ fd 16904568. This will break if not /dev/zero.
For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here

8
tests/quick/00.hello/ref/power/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 24 2010 23:13:07
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 24 2010 23:13:11
M5 executing on SC2B0619
M5 compiled Feb 6 2011 15:21:41
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:46:45
M5 executing on SC2B0617
command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

26
tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 277162 # Simulator instruction rate (inst/s)
host_mem_usage 181156 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 136566988 # Simulator tick rate (ticks/s)
host_inst_rate 1262734 # Simulator instruction rate (inst/s)
host_mem_usage 195732 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 600414079 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5801 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@ -29,8 +29,24 @@ system.cpu.itb.write_hits 0 # DT
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5801 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 5801 # Number of busy cycles
system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
system.cpu.num_fp_insts 22 # number of float instructions
system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_func_calls 200 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5801 # Number of instructions executed
system.cpu.num_refs 2008 # Number of memory references
system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
system.cpu.num_int_insts 5706 # number of integer instructions
system.cpu.num_int_register_reads 9541 # number of times the integer registers were read
system.cpu.num_int_register_writes 5005 # number of times the integer registers were written
system.cpu.num_load_insts 962 # Number of load instructions
system.cpu.num_mem_refs 2008 # number of memory refs
system.cpu.num_store_insts 1046 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
---------- End Simulation Statistics ----------

11
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=AtomicSimpleCPU

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 25 2010 03:11:27
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 03:37:59
M5 executing on SC2B0619
M5 compiled Feb 6 2011 15:23:54
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:47:20
M5 executing on SC2B0617
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 897027 # Simulator instruction rate (inst/s)
host_mem_usage 182692 # Number of bytes of host memory used
host_inst_rate 945970 # Simulator instruction rate (inst/s)
host_mem_usage 197420 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 434663663 # Simulator tick rate (ticks/s)
host_tick_rate 454943574 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 2701000 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5403 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 5403 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5340 # Number of instructions executed
system.cpu.num_refs 1402 # Number of memory references
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
system.cpu.num_int_insts 4517 # number of integer instructions
system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
system.cpu.num_int_register_writes 4859 # number of times the integer registers were written
system.cpu.num_load_insts 724 # Number of load instructions
system.cpu.num_mem_refs 1402 # number of memory refs
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------

231
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
View file

@ -1,13 +1,22 @@
[root]
type=Root
children=system
dummy=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu physmem ruby
mem_mode=atomic
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
mem_mode=timing
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
[system.cpu]
type=TimingSimpleCPU
@ -32,8 +41,8 @@ progress_interval=0
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
dcache_port=system.ruby.cpu_ruby_ports.port[1]
icache_port=system.ruby.cpu_ruby_ports.port[0]
[system.cpu.dtb]
type=SparcTLB
@ -54,7 +63,7 @@ egid=100
env=
errout=cerr
euid=100
executable=tests/test-progs/hello/bin/sparc/linux/hello
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -65,127 +74,27 @@ simpoint=0
system=system
uid=100
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
[system.ruby]
type=RubySystem
children=debug network profiler tracer
block_size_bytes=64
clock=1
debug=system.ruby.debug
mem_size=134217728
network=system.ruby.network
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tech_nm=45
tracer=system.ruby.tracer
[system.ruby.debug]
type=RubyDebug
filter_string=none
output_filename=none
protocol_trace=false
start_time=1
verbosity_string=none
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=true
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links0.ext_node
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links0.ext_node]
type=L1Cache_Controller
children=sequencer
buffer_size=0
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
type=RubySequencer
children=icache
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
deadlock_threshold=500000
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
[system.ruby.network.topology.ext_links1]
type=ExtLink
children=ext_node
bw_multiplier=64
ext_node=system.ruby.network.topology.ext_links1.ext_node
int_node=1
latency=1
weight=1
[system.ruby.network.topology.ext_links1.ext_node]
[system.dir_cntrl0]
type=Directory_Controller
children=directory memBuffer
buffer_size=0
directory=system.ruby.network.topology.ext_links1.ext_node.directory
directory=system.dir_cntrl0.directory
directory_latency=12
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
memBuffer=system.dir_cntrl0.memBuffer
number_of_TBEs=256
recycle_latency=10
transitions_per_cycle=32
version=0
[system.ruby.network.topology.ext_links1.ext_node.directory]
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
numa_high_bit=6
size=134217728
use_map=false
version=0
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
[system.dir_cntrl0.memBuffer]
type=RubyMemoryControl
bank_bit_0=8
bank_busy_time=11
@ -206,6 +115,100 @@ refresh_period=1560
tFaw=0
version=0
[system.l1_cntrl0]
type=L1Cache_Controller
buffer_size=0
cacheMemory=system.ruby.cpu_ruby_ports.dcache
cache_response_latency=12
issue_latency=2
number_of_TBEs=256
recycle_latency=10
sequencer=system.ruby.cpu_ruby_ports
transitions_per_cycle=32
version=0
[system.physmem]
type=PhysicalMemory
file=
latency=30
latency_var=0
null=false
range=0:134217727
zero=false
port=system.ruby.cpu_ruby_ports.physMemPort
[system.ruby]
type=RubySystem
children=cpu_ruby_ports network profiler tracer
block_size_bytes=64
clock=1
mem_size=134217728
network=system.ruby.network
no_mem_vec=false
profiler=system.ruby.profiler
random_seed=1234
randomization=false
stats_filename=ruby.stats
tracer=system.ruby.tracer
[system.ruby.cpu_ruby_ports]
type=RubySequencer
children=dcache
access_phys_mem=true
dcache=system.ruby.cpu_ruby_ports.dcache
deadlock_threshold=500000
icache=system.ruby.cpu_ruby_ports.dcache
max_outstanding_requests=16
physmem=system.physmem
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
port=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.cpu_ruby_ports.dcache]
type=RubyCache
assoc=2
latency=3
replacement_policy=PSEUDO_LRU
size=256
start_index_bit=6
[system.ruby.network]
type=SimpleNetwork
children=topology
adaptive_routing=false
buffer_size=0
control_msg_size=8
endpoint_bandwidth=10000
link_latency=1
number_of_virtual_networks=10
topology=system.ruby.network.topology
[system.ruby.network.topology]
type=Topology
children=ext_links0 ext_links1 int_links0 int_links1
description=Crossbar
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
num_int_nodes=3
print_config=false
[system.ruby.network.topology.ext_links0]
type=ExtLink
bw_multiplier=64
ext_node=system.l1_cntrl0
int_node=0
latency=1
weight=1
[system.ruby.network.topology.ext_links1]
type=ExtLink
bw_multiplier=64
ext_node=system.dir_cntrl0
int_node=1
latency=1
weight=1
[system.ruby.network.topology.int_links0]
type=IntLink
bw_multiplier=16

294
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
View file

@ -4,16 +4,11 @@
RubySystem config:
random_seed: 1234
randomization: 0
tech_nm: 45
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
DirectoryMemory Global Config:
number of directory memories: 1
total memory size bytes: 134217728
total memory size bits: 27
Network Configuration
---------------------
@ -23,9 +18,9 @@ topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, ordered
virtual_net_3: inactive
virtual_net_3: active, ordered
virtual_net_4: active, ordered
virtual_net_5: active, ordered
virtual_net_5: inactive
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
@ -39,40 +34,29 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Jan/21/2010 11:30:49
Real time: Feb/06/2011 20:47:21
Profiler Stats
--------------
Elapsed_time_in_seconds: 1
Elapsed_time_in_minutes: 0.0166667
Elapsed_time_in_hours: 0.000277778
Elapsed_time_in_days: 1.15741e-05
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.28
Virtual_time_in_minutes: 0.00466667
Virtual_time_in_hours: 7.77778e-05
Virtual_time_in_days: 3.24074e-06
Virtual_time_in_seconds: 0.36
Virtual_time_in_minutes: 0.006
Virtual_time_in_hours: 0.0001
Virtual_time_in_days: 4.16667e-06
Ruby_current_time: 253364
Ruby_start_time: 0
Ruby_cycles: 253364
mbytes_resident: 34.3555
mbytes_total: 34.5312
resident_ratio: 0.995136
Total_misses: 0
total_misses: 0 [ 0 ]
user_misses: 0 [ 0 ]
supervisor_misses: 0 [ 0 ]
ruby_cycles_executed: 253365 [ 253365 ]
transactions_started: 0 [ 0 ]
transactions_ended: 0 [ 0 ]
cycles_per_transaction: 0 [ 0 ]
misses_per_transaction: 0 [ 0 ]
mbytes_resident: 36.8398
mbytes_total: 210.371
resident_ratio: 0.175156
ruby_cycles_executed: [ 253365 ]
Busy Controller Counts:
L1Cache-0:0
@ -86,9 +70,27 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 |
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average: 3 | standard deviation: 0 | 0 0 0 5483 ]
miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
imcomplete_dir_Times: 1288
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average: 3 | standard deviation: 0 | 0 0 0 4668 ]
miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average: 3 | standard deviation: 0 | 0 0 0 321 ]
miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average: 3 | standard deviation: 0 | 0 0 0 494 ]
miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
@ -120,8 +122,8 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 7494
page_faults: 2200
page_reclaims: 10574
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
@ -129,16 +131,22 @@ block_outputs: 0
Network Stats
-------------
total_msg_count_Control: 3867 30936
total_msg_count_Data: 3855 277560
total_msg_count_Response_Data: 3867 278424
total_msg_count_Writeback_Control: 3855 30840
total_msgs: 15444 total_bytes: 617760
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.158621
links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
@ -146,10 +154,10 @@ links_utilized_percent_switch_1: 0.158857
links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
@ -157,63 +165,64 @@ links_utilized_percent_switch_2: 0.253982
links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694%
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 30.6439%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 13.8867%
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 55.4694%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100%
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 1289 100%
--- L1Cache 0 ---
--- L1Cache ---
- Event Counts -
Load 716
Ifetch 5383
Store 673
Data 1289
Fwd_GETX 0
Inv 0
Replacement 1285
Writeback_Ack 1285
Writeback_Nack 0
Load [716 ] 716
Ifetch [5383 ] 5383
Store [673 ] 673
Data [1289 ] 1289
Fwd_GETX [0 ] 0
Inv [0 ] 0
Replacement [1285 ] 1285
Writeback_Ack [1285 ] 1285
Writeback_Nack [0 ] 0
- Transitions -
I Load 395
I Ifetch 715
I Store 179
I Inv 0 <--
I Replacement 0 <--
I Load [395 ] 395
I Ifetch [715 ] 715
I Store [179 ] 179
I Inv [0 ] 0
I Replacement [0 ] 0
II Writeback_Nack 0 <--
II Writeback_Nack [0 ] 0
M Load 321
M Ifetch 4668
M Store 494
M Fwd_GETX 0 <--
M Inv 0 <--
M Replacement 1285
M Load [321 ] 321
M Ifetch [4668 ] 4668
M Store [494 ] 494
M Fwd_GETX [0 ] 0
M Inv [0 ] 0
M Replacement [1285 ] 1285
MI Fwd_GETX 0 <--
MI Inv 0 <--
MI Writeback_Ack 1285
MI Fwd_GETX [0 ] 0
MI Inv [0 ] 0
MI Writeback_Ack [1285 ] 1285
MI Writeback_Nack [0 ] 0
IS Data 1110
MII Fwd_GETX [0 ] 0
IM Data 179
IS Data [1110 ] 1110
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
IM Data [179 ] 179
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 2574
memory_reads: 1289
memory_writes: 1285
@ -233,70 +242,69 @@ Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
--- Directory 0 ---
--- Directory ---
- Event Counts -
GETX 1289
GETS 0
PUTX 1285
PUTX_NotOwner 0
DMA_READ 0
DMA_WRITE 0
Memory_Data 1289
Memory_Ack 1285
GETX [1289 ] 1289
GETS [0 ] 0
PUTX [1285 ] 1285
PUTX_NotOwner [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [1289 ] 1289
Memory_Ack [1285 ] 1285
- Transitions -
I GETX 1289
I PUTX_NotOwner 0 <--
I DMA_READ 0 <--
I DMA_WRITE 0 <--
I GETX [1289 ] 1289
I PUTX_NotOwner [0 ] 0
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
M GETX 0 <--
M PUTX 1285
M PUTX_NotOwner 0 <--
M DMA_READ 0 <--
M DMA_WRITE 0 <--
M GETX [0 ] 0
M PUTX [1285 ] 1285
M PUTX_NotOwner [0 ] 0
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
M_DRD GETX 0 <--
M_DRD PUTX 0 <--
M_DRD GETX [0 ] 0
M_DRD PUTX [0 ] 0
M_DWR GETX 0 <--
M_DWR PUTX 0 <--
M_DWR GETX [0 ] 0
M_DWR PUTX [0 ] 0
M_DWRI GETX 0 <--
M_DWRI Memory_Ack 0 <--
M_DWRI GETX [0 ] 0
M_DWRI Memory_Ack [0 ] 0
M_DRDI GETX 0 <--
M_DRDI Memory_Ack 0 <--
M_DRDI GETX [0 ] 0
M_DRDI Memory_Ack [0 ] 0
IM GETX 0 <--
IM GETS 0 <--
IM PUTX 0 <--
IM PUTX_NotOwner 0 <--
IM DMA_READ 0 <--
IM DMA_WRITE 0 <--
IM Memory_Data 1289
IM GETX [0 ] 0
IM GETS [0 ] 0
IM PUTX [0 ] 0
IM PUTX_NotOwner [0 ] 0
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
IM Memory_Data [1289 ] 1289
MI GETX 0 <--
MI GETS 0 <--
MI PUTX 0 <--
MI PUTX_NotOwner 0 <--
MI DMA_READ 0 <--
MI DMA_WRITE 0 <--
MI Memory_Ack 1285
MI GETX [0 ] 0
MI GETS [0 ] 0
MI PUTX [0 ] 0
MI PUTX_NotOwner [0 ] 0
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
MI Memory_Ack [1285 ] 1285
ID GETX 0 <--
ID GETS 0 <--
ID PUTX 0 <--
ID PUTX_NotOwner 0 <--
ID DMA_READ 0 <--
ID DMA_WRITE 0 <--
ID Memory_Data 0 <--
ID_W GETX 0 <--
ID_W GETS 0 <--
ID_W PUTX 0 <--
ID_W PUTX_NotOwner 0 <--
ID_W DMA_READ 0 <--
ID_W DMA_WRITE 0 <--
ID_W Memory_Ack 0 <--
ID GETX [0 ] 0
ID GETS [0 ] 0
ID PUTX [0 ] 0
ID PUTX_NotOwner [0 ] 0
ID DMA_READ [0 ] 0
ID DMA_WRITE [0 ] 0
ID Memory_Data [0 ] 0
ID_W GETX [0 ] 0
ID_W GETS [0 ] 0
ID_W PUTX [0 ] 0
ID_W PUTX_NotOwner [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
ID_W Memory_Ack

8
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
View file

@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Jan 21 2010 11:29:25
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
M5 started Jan 21 2010 11:30:48
M5 executing on svvint07
M5 compiled Feb 6 2011 15:23:54
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:47:21
M5 executing on SC2B0617
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

24
tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 59331 # Simulator instruction rate (inst/s)
host_mem_usage 347024 # Number of bytes of host memory used
host_inst_rate 56468 # Simulator instruction rate (inst/s)
host_mem_usage 215424 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
host_tick_rate 2815062 # Simulator tick rate (ticks/s)
host_tick_rate 2673942 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
sim_seconds 0.000253 # Number of seconds simulated
@ -11,8 +11,24 @@ sim_ticks 253364 # Nu
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 253364 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.num_busy_cycles 253364 # Number of busy cycles
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_insts 5340 # Number of instructions executed
system.cpu.num_refs 1402 # Number of memory references
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
system.cpu.num_int_insts 4517 # number of integer instructions
system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
system.cpu.num_load_insts 724 # Number of load instructions
system.cpu.num_mem_refs 1402 # number of memory refs
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------

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