ruby: support to stallAndWait the mandatory queue
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
This commit is contained in:
Brad Beckmann
parent
194a137498
commit
f5aa75fdc5
8 changed files with 295 additions and 107 deletions
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@ -433,7 +433,7 @@ machine(L1Cache, "Token protocol")
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// ** IN_PORTS **
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// Use Timer
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in_port(useTimerTable_in, Address, useTimerTable) {
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in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
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if (useTimerTable_in.isReady()) {
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TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
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@ -459,7 +459,7 @@ machine(L1Cache, "Token protocol")
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}
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// Reissue Timer
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in_port(reissueTimerTable_in, Address, reissueTimerTable) {
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in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
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if (reissueTimerTable_in.isReady()) {
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trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
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getCacheEntry(reissueTimerTable.readyAddress()),
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@ -467,10 +467,8 @@ machine(L1Cache, "Token protocol")
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}
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}
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// Persistent Network
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in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache) {
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in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
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if (persistentNetwork_in.isReady()) {
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peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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@ -519,56 +517,8 @@ machine(L1Cache, "Token protocol")
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}
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}
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// Request Network
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in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
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if (requestNetwork_in.isReady()) {
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peek(requestNetwork_in, RequestMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L1_TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceRequestType:GETX) {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETX, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETX, in_msg.Address,
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cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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if (getTokens(cache_entry) == 1 ||
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getTokens(cache_entry) == (max_tokens() / 2) + 1) {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
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cache_entry, tbe);
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}
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}
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else {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETS, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETS, in_msg.Address,
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cache_entry, tbe);
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}
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}
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Response Network
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in_port(responseNetwork_in, ResponseMsg, responseToL1Cache) {
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in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
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if (responseNetwork_in.isReady()) {
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peek(responseNetwork_in, ResponseMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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@ -639,8 +589,55 @@ machine(L1Cache, "Token protocol")
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}
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}
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// Request Network
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in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
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if (requestNetwork_in.isReady()) {
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peek(requestNetwork_in, RequestMsg, block_on="Address") {
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assert(in_msg.Destination.isElement(machineID));
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := L1_TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceRequestType:GETX) {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETX, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETX, in_msg.Address,
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cache_entry, tbe);
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}
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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if (getTokens(cache_entry) == 1 ||
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getTokens(cache_entry) == (max_tokens() / 2) + 1) {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETS_Last_Token, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETS_Last_Token, in_msg.Address,
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cache_entry, tbe);
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}
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}
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else {
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if (in_msg.isLocal) {
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trigger(Event:Transient_Local_GETS, in_msg.Address,
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cache_entry, tbe);
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}
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else {
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trigger(Event:Transient_GETS, in_msg.Address,
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cache_entry, tbe);
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}
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}
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Mandatory Queue
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
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// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
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@ -1339,6 +1336,11 @@ machine(L1Cache, "Token protocol")
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tbe.IssueTime := get_time();
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}
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action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
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peek(mandatoryQueue_in, CacheMsg) {
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APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
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}
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}
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action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
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if (reissueTimerTable.isSet(address)) {
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@ -1527,8 +1529,19 @@ machine(L1Cache, "Token protocol")
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}
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}
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action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
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mandatoryQueue_in.recycle();
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action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
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peek(mandatoryQueue_in, CacheMsg) {
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APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
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}
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stall_and_wait(mandatoryQueue_in, address);
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}
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action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
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wake_up_dependents(address);
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}
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action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
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wake_up_all_dependents();
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}
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//*****************************************************
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@ -1537,15 +1550,16 @@ machine(L1Cache, "Token protocol")
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// Transitions for Load/Store/L2_Replacement from transient states
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transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W}, L1_Replacement) {
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zz_recycleMandatoryQueue;
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ta_traceStalledAddress;
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zz_stallAndWaitMandatoryQueue;
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}
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transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
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zz_recycleMandatoryQueue;
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zz_stallAndWaitMandatoryQueue;
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}
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transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
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zz_recycleMandatoryQueue;
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zz_stallAndWaitMandatoryQueue;
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}
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@ -1615,8 +1629,10 @@ machine(L1Cache, "Token protocol")
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}
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transition(I, L1_Replacement) {
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ta_traceStalledAddress;
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tr_tokenReplacement;
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gg_deallocateL1CacheBlock;
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ka_wakeUpAllDependents;
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}
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transition(I, {Transient_GETX, Transient_Local_GETX}) {
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@ -1674,8 +1690,10 @@ machine(L1Cache, "Token protocol")
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}
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transition(S, L1_Replacement, I) {
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ta_traceStalledAddress;
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cc_sharedReplacement; // Only needed in some cases
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gg_deallocateL1CacheBlock;
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ka_wakeUpAllDependents;
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}
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transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
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@ -1750,8 +1768,10 @@ machine(L1Cache, "Token protocol")
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}
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transition(O, L1_Replacement, I) {
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ta_traceStalledAddress;
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c_ownedReplacement;
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gg_deallocateL1CacheBlock;
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ka_wakeUpAllDependents;
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}
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transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
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@ -1835,8 +1855,10 @@ machine(L1Cache, "Token protocol")
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}
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transition(MM, L1_Replacement, I) {
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ta_traceStalledAddress;
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c_ownedReplacement;
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gg_deallocateL1CacheBlock;
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ka_wakeUpAllDependents;
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}
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transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS, Transient_Local_GETS}, I) {
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@ -1864,11 +1886,13 @@ machine(L1Cache, "Token protocol")
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transition(MM_W, Use_TimeoutNoStarvers, MM) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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kd_wakeUpDependents;
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}
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transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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kd_wakeUpDependents;
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}
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// Transitions from Dirty Exclusive
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@ -1898,8 +1922,10 @@ machine(L1Cache, "Token protocol")
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}
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transition(M, L1_Replacement, I) {
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ta_traceStalledAddress;
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c_ownedReplacement;
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gg_deallocateL1CacheBlock;
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ka_wakeUpAllDependents;
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}
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transition(M, {Transient_GETX, Transient_Local_GETX}, I) {
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@ -1948,6 +1974,7 @@ machine(L1Cache, "Token protocol")
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transition(M_W, {Use_TimeoutNoStarvers, Use_TimeoutNoStarvers_NoMig}, M) {
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s_deallocateTBE;
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jj_unsetUseTimer;
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kd_wakeUpDependents;
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}
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transition(M_W, Use_TimeoutStarverX, I_L) {
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@ -2056,6 +2083,7 @@ machine(L1Cache, "Token protocol")
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o_scheduleUseTimeout;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(SM, Data_Shared) {
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@ -2077,6 +2105,7 @@ machine(L1Cache, "Token protocol")
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o_scheduleUseTimeout;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition({IM, SM}, {Transient_GETX, Transient_Local_GETX}, IM) { // We don't have the data yet, but we might have collected some tokens. We give them up here to avoid livelock
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@ -2106,6 +2135,7 @@ machine(L1Cache, "Token protocol")
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o_scheduleUseTimeout;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(OM, Data_Shared) {
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@ -2121,6 +2151,7 @@ machine(L1Cache, "Token protocol")
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o_scheduleUseTimeout;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(OM, Request_Timeout) {
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@ -2142,6 +2173,7 @@ machine(L1Cache, "Token protocol")
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s_deallocateTBE;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(IS, Data_Owner, O) {
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@ -2151,6 +2183,7 @@ machine(L1Cache, "Token protocol")
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s_deallocateTBE;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(IS, Data_All_Tokens, M_W) {
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@ -2160,6 +2193,7 @@ machine(L1Cache, "Token protocol")
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o_scheduleUseTimeout;
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j_unsetReissueTimer;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(IS, Request_Timeout) {
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@ -2247,6 +2281,7 @@ machine(L1Cache, "Token protocol")
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j_unsetReissueTimer;
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o_scheduleUseTimeout;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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transition(SM_L, Data_All_Tokens, S_L) {
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@ -2288,6 +2323,7 @@ machine(L1Cache, "Token protocol")
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j_unsetReissueTimer;
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o_scheduleUseTimeout;
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n_popResponseQueue;
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kd_wakeUpDependents;
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}
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@ -2295,22 +2331,27 @@ machine(L1Cache, "Token protocol")
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transition(I_L, Own_Lock_or_Unlock, I) {
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l_popPersistentQueue;
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kd_wakeUpDependents;
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}
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transition(S_L, Own_Lock_or_Unlock, S) {
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l_popPersistentQueue;
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kd_wakeUpDependents;
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}
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transition(IM_L, Own_Lock_or_Unlock, IM) {
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l_popPersistentQueue;
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kd_wakeUpDependents;
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}
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transition(IS_L, Own_Lock_or_Unlock, IS) {
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l_popPersistentQueue;
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kd_wakeUpDependents;
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}
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transition(SM_L, Own_Lock_or_Unlock, SM) {
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l_popPersistentQueue;
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kd_wakeUpDependents;
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}
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}
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@ -278,7 +278,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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// ** IN_PORTS **
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// Trigger Queue
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in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
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in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
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if (triggerQueue_in.isReady()) {
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peek(triggerQueue_in, TriggerMsg) {
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@ -298,10 +298,35 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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}
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// Nothing from the request network
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// Nothing from the unblock network
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// Response Network
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in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) {
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if (responseToCache_in.isReady()) {
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peek(responseToCache_in, ResponseMsg, block_on="Address") {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
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trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
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trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
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trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Forward Network
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in_port(forwardToCache_in, RequestMsg, forwardToCache) {
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in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) {
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if (forwardToCache_in.isReady()) {
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peek(forwardToCache_in, RequestMsg, block_on="Address") {
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@ -339,35 +364,10 @@ machine(L1Cache, "AMD Hammer-like protocol")
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}
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}
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// Response Network
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in_port(responseToCache_in, ResponseMsg, responseToCache) {
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if (responseToCache_in.isReady()) {
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peek(responseToCache_in, ResponseMsg, block_on="Address") {
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Entry cache_entry := getCacheEntry(in_msg.Address);
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TBE tbe := TBEs[in_msg.Address];
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if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
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} else if (in_msg.Type == CoherenceResponseType:ACK_SHARED) {
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trigger(Event:Shared_Ack, in_msg.Address, cache_entry, tbe);
|
||||
} else if (in_msg.Type == CoherenceResponseType:DATA) {
|
||||
trigger(Event:Data, in_msg.Address, cache_entry, tbe);
|
||||
} else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
|
||||
trigger(Event:Shared_Data, in_msg.Address, cache_entry, tbe);
|
||||
} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
|
||||
trigger(Event:Exclusive_Data, in_msg.Address, cache_entry, tbe);
|
||||
} else {
|
||||
error("Unexpected message");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Nothing from the unblock network
|
||||
// Nothing from the request network
|
||||
|
||||
// Mandatory Queue
|
||||
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
|
||||
in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
|
||||
if (mandatoryQueue_in.isReady()) {
|
||||
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
|
||||
|
||||
|
|
@ -1017,8 +1017,16 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
}
|
||||
}
|
||||
|
||||
action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
|
||||
mandatoryQueue_in.recycle();
|
||||
action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
|
||||
stall_and_wait(mandatoryQueue_in, address);
|
||||
}
|
||||
|
||||
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
|
||||
wake_up_dependents(address);
|
||||
}
|
||||
|
||||
action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
|
||||
wake_up_all_dependents();
|
||||
}
|
||||
|
||||
//*****************************************************
|
||||
|
|
@ -1027,19 +1035,19 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
|
||||
// Transitions for Load/Store/L2_Replacement from transient states
|
||||
transition({IM, SM, ISM, OM, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) {
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
}
|
||||
|
||||
transition({M_W, MM_W}, {L2_Replacement}) {
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
}
|
||||
|
||||
transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT}, {Load, Ifetch}) {
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
}
|
||||
|
||||
transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT}, L1_to_L2) {
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
}
|
||||
|
||||
transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
|
||||
|
|
@ -1053,6 +1061,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
vv_allocateL2CacheBlock;
|
||||
hp_copyFromTBEToL2;
|
||||
s_deallocateTBE;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(I, Trigger_L2_to_L1D, IT) {
|
||||
|
|
@ -1062,7 +1071,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1; // Not really needed for state I
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1073,7 +1082,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1084,7 +1093,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1095,7 +1104,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1106,7 +1115,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1117,7 +1126,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1128,7 +1137,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1139,7 +1148,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1150,7 +1159,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
|
|
@ -1161,28 +1170,33 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
nb_copyFromTBEToL1;
|
||||
s_deallocateTBE;
|
||||
uu_profileMiss;
|
||||
zz_recycleMandatoryQueue;
|
||||
zz_stallAndWaitMandatoryQueue;
|
||||
ll_L2toL1Transfer;
|
||||
}
|
||||
|
||||
transition(IT, Complete_L2_to_L1, I) {
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(ST, Complete_L2_to_L1, S) {
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(OT, Complete_L2_to_L1, O) {
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(MT, Complete_L2_to_L1, M) {
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(MMT, Complete_L2_to_L1, MM) {
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from Idle
|
||||
|
|
@ -1212,6 +1226,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
|
||||
transition(I, L2_Replacement) {
|
||||
rr_deallocateL2CacheBlock;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) {
|
||||
|
|
@ -1234,6 +1249,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
|
||||
transition(S, L2_Replacement, I) {
|
||||
rr_deallocateL2CacheBlock;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(S, {Other_GETX, Invalidate}, I) {
|
||||
|
|
@ -1264,6 +1280,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
i_allocateTBE;
|
||||
d_issuePUT;
|
||||
rr_deallocateL2CacheBlock;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(O, {Other_GETX, Invalidate}, I) {
|
||||
|
|
@ -1296,6 +1313,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
i_allocateTBE;
|
||||
d_issuePUT;
|
||||
rr_deallocateL2CacheBlock;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(MM, {Other_GETX, Invalidate}, I) {
|
||||
|
|
@ -1338,6 +1356,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
i_allocateTBE;
|
||||
d_issuePUT;
|
||||
rr_deallocateL2CacheBlock;
|
||||
ka_wakeUpAllDependents;
|
||||
}
|
||||
|
||||
transition(M, {Other_GETX, Invalidate}, I) {
|
||||
|
|
@ -1386,6 +1405,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
o_checkForCompletion;
|
||||
sx_external_store_hit;
|
||||
n_popResponseQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from SM
|
||||
|
|
@ -1424,6 +1444,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
gm_sendUnblockM;
|
||||
s_deallocateTBE;
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from OM
|
||||
|
|
@ -1455,6 +1476,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
gm_sendUnblockM;
|
||||
s_deallocateTBE;
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from IS
|
||||
|
|
@ -1484,6 +1506,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
hx_external_load_hit;
|
||||
uo_updateCurrentOwner;
|
||||
n_popResponseQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(IS, Exclusive_Data, M_W) {
|
||||
|
|
@ -1492,6 +1515,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
o_checkForCompletion;
|
||||
hx_external_load_hit;
|
||||
n_popResponseQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(IS, Shared_Data, SS) {
|
||||
|
|
@ -1502,6 +1526,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
hx_external_load_hit;
|
||||
uo_updateCurrentOwner;
|
||||
n_popResponseQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from SS
|
||||
|
|
@ -1549,6 +1574,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
gm_sendUnblockM;
|
||||
s_deallocateTBE;
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from M_W
|
||||
|
|
@ -1568,6 +1594,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
gm_sendUnblockM;
|
||||
s_deallocateTBE;
|
||||
j_popTriggerQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from OI/MI
|
||||
|
|
@ -1591,12 +1618,14 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
t_sendExclusiveDataFromTBEToMemory;
|
||||
s_deallocateTBE;
|
||||
l_popForwardQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(OI, Writeback_Ack, I) {
|
||||
qq_sendDataFromTBEToMemory;
|
||||
s_deallocateTBE;
|
||||
l_popForwardQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
// Transitions from II
|
||||
|
|
@ -1609,10 +1638,12 @@ machine(L1Cache, "AMD Hammer-like protocol")
|
|||
g_sendUnblock;
|
||||
s_deallocateTBE;
|
||||
l_popForwardQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
|
||||
transition(II, Writeback_Nack, I) {
|
||||
s_deallocateTBE;
|
||||
l_popForwardQueue;
|
||||
kd_wakeUpDependents;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -56,6 +56,8 @@ MessageBuffer::MessageBuffer(const string &name)
|
|||
m_not_avail_count = 0;
|
||||
m_priority_rank = 0;
|
||||
m_name = name;
|
||||
|
||||
m_stall_msg_map.clear();
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -337,11 +339,43 @@ MessageBuffer::reanalyzeMessages(const Address& addr)
|
|||
|
||||
m_prio_heap.push_back(msgNode);
|
||||
push_heap(m_prio_heap.begin(), m_prio_heap.end(),
|
||||
greater<MessageBufferNode>());
|
||||
greater<MessageBufferNode>());
|
||||
|
||||
g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, msgNode.m_time);
|
||||
m_stall_msg_map[addr].pop_front();
|
||||
}
|
||||
m_stall_msg_map.erase(addr);
|
||||
}
|
||||
|
||||
void
|
||||
MessageBuffer::reanalyzeAllMessages()
|
||||
{
|
||||
DPRINTF(RubyQueue, "ReanalyzeAllMessages %s\n", m_name);
|
||||
|
||||
//
|
||||
// Put all stalled messages associated with this address back on the
|
||||
// prio heap
|
||||
//
|
||||
for (StallMsgMapType::iterator map_iter = m_stall_msg_map.begin();
|
||||
map_iter != m_stall_msg_map.end();
|
||||
++map_iter) {
|
||||
|
||||
while(!(map_iter->second).empty()) {
|
||||
m_msg_counter++;
|
||||
MessageBufferNode msgNode(g_eventQueue_ptr->getTime() + 1,
|
||||
m_msg_counter,
|
||||
(map_iter->second).front());
|
||||
|
||||
m_prio_heap.push_back(msgNode);
|
||||
push_heap(m_prio_heap.begin(), m_prio_heap.end(),
|
||||
greater<MessageBufferNode>());
|
||||
|
||||
g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr,
|
||||
msgNode.m_time);
|
||||
(map_iter->second).pop_front();
|
||||
}
|
||||
}
|
||||
m_stall_msg_map.clear();
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ class MessageBuffer
|
|||
}
|
||||
|
||||
void reanalyzeMessages(const Address& addr);
|
||||
void reanalyzeAllMessages();
|
||||
void stallMessage(const Address& addr);
|
||||
|
||||
// TRUE if head of queue timestamp <= SystemTime
|
||||
|
|
|
|||
43
src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
Normal file
43
src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
|
||||
# Copyright (c) 2009 The Hewlett-Packard Development Company
|
||||
# Copyright (c) 2010 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from slicc.ast.StatementAST import StatementAST
|
||||
|
||||
class WakeUpAllDependentsStatementAST(StatementAST):
|
||||
def __init__(self, slicc):
|
||||
super(StatementAST, self).__init__(slicc)
|
||||
|
||||
def __repr__(self):
|
||||
return "[WakeUpAllDependentsStatementAst: %r]" % self.variable
|
||||
|
||||
def generate(self, code, return_type):
|
||||
code('''
|
||||
if (m_waiting_buffers.size() > 0) {
|
||||
wakeUpAllBuffers();
|
||||
}
|
||||
''')
|
||||
|
|
@ -72,4 +72,5 @@ from slicc.ast.TypeFieldEnumAST import *
|
|||
from slicc.ast.TypeFieldMemberAST import *
|
||||
from slicc.ast.TypeFieldMethodAST import *
|
||||
from slicc.ast.VarExprAST import *
|
||||
from slicc.ast.WakeUpAllDependentsStatementAST import *
|
||||
from slicc.ast.WakeUpDependentsStatementAST import *
|
||||
|
|
|
|||
|
|
@ -159,6 +159,7 @@ class SLICC(Grammar):
|
|||
'peek' : 'PEEK',
|
||||
'stall_and_wait' : 'STALL_AND_WAIT',
|
||||
'wake_up_dependents' : 'WAKE_UP_DEPENDENTS',
|
||||
'wake_up_all_dependents' : 'WAKE_UP_ALL_DEPENDENTS',
|
||||
'enqueue' : 'ENQUEUE',
|
||||
'copy_head' : 'COPY_HEAD',
|
||||
'check_allocate' : 'CHECK_ALLOCATE',
|
||||
|
|
@ -561,6 +562,10 @@ class SLICC(Grammar):
|
|||
"statement : WAKE_UP_DEPENDENTS '(' var ')' SEMI"
|
||||
p[0] = ast.WakeUpDependentsStatementAST(self, p[3])
|
||||
|
||||
def p_statement__wake_up_all_dependents(self, p):
|
||||
"statement : WAKE_UP_ALL_DEPENDENTS '(' ')' SEMI"
|
||||
p[0] = ast.WakeUpAllDependentsStatementAST(self)
|
||||
|
||||
def p_statement__peek(self, p):
|
||||
"statement : PEEK '(' var ',' type pairs ')' statements"
|
||||
p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
|
||||
|
|
|
|||
|
|
@ -258,6 +258,7 @@ public:
|
|||
const MachineType getMachineType() const;
|
||||
void stallBuffer(MessageBuffer* buf, Address addr);
|
||||
void wakeUpBuffers(Address addr);
|
||||
void wakeUpAllBuffers();
|
||||
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
|
||||
void print(std::ostream& out) const;
|
||||
void printConfig(std::ostream& out) const;
|
||||
|
|
@ -733,6 +734,37 @@ $c_ident::wakeUpBuffers(Address addr)
|
|||
m_waiting_buffers.erase(addr);
|
||||
}
|
||||
|
||||
void
|
||||
$c_ident::wakeUpAllBuffers()
|
||||
{
|
||||
//
|
||||
// Wake up all possible buffers that could be waiting on any message.
|
||||
//
|
||||
|
||||
std::vector<MsgVecType*> wokeUpMsgVecs;
|
||||
|
||||
for (WaitingBufType::iterator buf_iter = m_waiting_buffers.begin();
|
||||
buf_iter != m_waiting_buffers.end();
|
||||
++buf_iter) {
|
||||
for (MsgVecType::iterator vec_iter = buf_iter->second->begin();
|
||||
vec_iter != buf_iter->second->end();
|
||||
++vec_iter) {
|
||||
if (*vec_iter != NULL) {
|
||||
(*vec_iter)->reanalyzeAllMessages();
|
||||
}
|
||||
}
|
||||
wokeUpMsgVecs.push_back(buf_iter->second);
|
||||
}
|
||||
|
||||
for (std::vector<MsgVecType*>::iterator wb_iter = wokeUpMsgVecs.begin();
|
||||
wb_iter != wokeUpMsgVecs.end();
|
||||
++wb_iter) {
|
||||
delete (*wb_iter);
|
||||
}
|
||||
|
||||
m_waiting_buffers.clear();
|
||||
}
|
||||
|
||||
void
|
||||
$c_ident::blockOnQueue(Address addr, MessageBuffer* port)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue