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Merge with the main repository again.

Browse source
This commit is contained in:
Gabe Black 2012-01-07 02:15:35 -08:00
commit ec936364b7
125 changed files with 6491 additions and 6022 deletions
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2
configs/common/Caches.py
View file

@ -33,7 +33,7 @@ class L1Cache(BaseCache):
block_size = 64
latency = '1ns'
mshrs = 10
tgts_per_mshr = 5
tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):

7
configs/example/fs.py
View file

@ -72,6 +72,10 @@ parser.add_option("--timesync", action="store_true",
# System options
parser.add_option("--kernel", action="store", type="string")
parser.add_option("--script", action="store", type="string")
parser.add_option("--frame-capture", action="store_true",
help="Stores changed frame buffers from the VNC server to compressed "\
"files in the gem5 output directory")
if buildEnv['TARGET_ISA'] == "arm":
parser.add_option("--bare-metal", action="store_true",
help="Provide the raw system without the linux specific bits")
@ -205,4 +209,7 @@ else:
if options.timesync:
root.time_sync_enable = True
if options.frame_capture:
VncServer.frame_capture = True
Simulation.run(options, root, test_sys, FutureClass)

5
configs/ruby/Ruby.py
View file

@ -58,13 +58,16 @@ def define_options(parser):
parser.add_option("--random_seed", type="int", default=1234,
help="Used for seeding the random number generator")
parser.add_option("--ruby_stats", type="string", default="ruby.stats")
protocol = buildEnv['PROTOCOL']
exec "import %s" % protocol
eval("%s.define_options(parser)" % protocol)
def create_system(options, system, piobus = None, dma_devices = []):
system.ruby = RubySystem(clock = options.clock)
system.ruby = RubySystem(clock = options.clock,
stats_filename = options.ruby_stats)
ruby = system.ruby
protocol = buildEnv['PROTOCOL']

3
src/arch/arm/isa/insts/misc.isa
View file

@ -49,7 +49,8 @@ let {{
svcIop = InstObjParams("svc", "Svc", "PredOp",
{ "code": svcCode,
"predicate_test": predicateTest }, ["IsSyscall"])
"predicate_test": predicateTest },
["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
header_output = BasicDeclare.subst(svcIop)
decoder_output = BasicConstructor.subst(svcIop)
exec_output = PredOpExecute.subst(svcIop)

2
src/arch/arm/table_walker.cc
View file

@ -99,7 +99,7 @@ TableWalker::getPort(const std::string &if_name, int idx)
System *sys = params()->sys;
Tick minb = params()->min_backoff;
Tick maxb = params()->max_backoff;
port = new DmaPort(this, sys, minb, maxb);
port = new DmaPort(this, sys, minb, maxb, true);
return port;
}
return NULL;

68
src/arch/sparc/isa/formats/basic.isa
View file

@ -33,6 +33,11 @@ def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template DoFpOpDeclare {{
Fault doFpOp(%(CPU_exec_context)s *, Trace::InstRecord *)
const M5_NO_INLINE;
}};
// Definitions of execute methods that panic.
def template BasicExecPanic {{
Fault
@ -57,6 +62,21 @@ def template BasicDeclare {{
};
}};
// Basic instruction class declaration template.
def template FpBasicDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
%(DoFpOpDeclare)s
};
}};
// Basic instruction class declaration template.
def template BasicDeclareWithMnemonic {{
/**
@ -110,6 +130,22 @@ def template BasicExecute {{
}
}};
def template DoFpOpExecute {{
Fault
%(class_name)s::doFpOp(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(fp_code)s;
if (fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
// Basic decode template.
def template BasicDecode {{
return new %(class_name)s(machInst);
@ -131,9 +167,9 @@ def format BasicOperate(code, *flags) {{
}};
def format FpBasic(code, *flags) {{
fp_code = """
Fsr |= bits(Fsr,4,0) << 5;
Fsr = insertBits(Fsr,4,0,0);
exec_code = """
Fsr |= bits(Fsr, 4, 0) << 5;
Fsr = insertBits(Fsr, 4, 0, 0);
int newrnd = M5_FE_TONEAREST;
switch (Fsr<31:30>) {
case 0: newrnd = M5_FE_TONEAREST; break;
@ -143,18 +179,18 @@ def format FpBasic(code, *flags) {{
}
int oldrnd = m5_fegetround();
m5_fesetround(newrnd);
__asm__ __volatile__("" ::: "memory");
fault = doFpOp(xc, traceData);
__asm__ __volatile__("" ::: "memory");
m5_fesetround(oldrnd);
return fault;
"""
fp_code += code
fp_code += """
m5_fesetround(oldrnd);
"""
fp_code = filterDoubles(fp_code)
iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
fp_code = filterDoubles(code)
iop = InstObjParams(name, Name, 'SparcStaticInst',
{ "code" : exec_code, "fp_code" : fp_code }, flags)
header_output = FpBasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
exec_output += DoFpOpExecute.subst(iop)
}};

11
src/arch/x86/isa/microops/regop.isa
View file

@ -1335,16 +1335,15 @@ let {{
if (selector.si || selector.ti) {
if (!desc.p) {
fault = new StackFault(selector);
}
} else {
if ((m5reg.submode != SixtyFourBitMode ||
m5reg.cpl == 3) ||
!(desc.s == 1 &&
desc.type.codeOrData == 0 && desc.type.w) ||
} else if (!(desc.s == 1 && desc.type.codeOrData == 0 &&
desc.type.w) ||
(desc.dpl != m5reg.cpl) ||
(selector.rpl != m5reg.cpl)) {
fault = new GeneralProtection(selector);
}
} else if (m5reg.submode != SixtyFourBitMode ||
m5reg.cpl == 3) {
fault = new GeneralProtection(selector);
}
break;
case SegIretCheck:

2
src/arch/x86/predecoder.cc
View file

@ -186,7 +186,7 @@ namespace X86ISA
DPRINTF(Predecoder, "Found two byte opcode.\n");
emi.opcode.prefixA = nextByte;
}
else if(emi.opcode.num == 2 && (nextByte == 0x38 || nextByte == 0x3F))
else if(emi.opcode.num == 2 && (nextByte == 0x38 || nextByte == 0x3A))
{
nextState = OpcodeState;
DPRINTF(Predecoder, "Found three byte opcode.\n");

44
src/base/bitmap.cc
View file

@ -36,6 +36,7 @@
*
* Authors: William Wang
* Ali Saidi
* Chris Emmons
*/
#include <cassert>
@ -43,29 +44,50 @@
#include "base/bitmap.hh"
#include "base/misc.hh"
const size_t Bitmap::sizeofHeaderBuffer = sizeof(Magic) + sizeof(Header) +
sizeof(Info);
// bitmap class ctor
Bitmap::Bitmap(VideoConvert::Mode _mode, uint16_t w, uint16_t h, uint8_t *d)
: mode(_mode), height(h), width(w), data(d),
vc(mode, VideoConvert::rgb8888, width, height)
vc(mode, VideoConvert::rgb8888, width, height), headerBuffer(0)
{
}
Bitmap::~Bitmap() {
if (headerBuffer)
delete [] headerBuffer;
}
void
Bitmap::write(std::ostream *bmp)
Bitmap::write(std::ostream *bmp) const
{
assert(data);
// For further information see: http://en.wikipedia.org/wiki/BMP_file_format
Magic magic = {{'B','M'}};
Header header = {sizeof(VideoConvert::Rgb8888) * width * height , 0, 0, 54};
Info info = {sizeof(Info), width, height, 1,
sizeof(VideoConvert::Rgb8888) * 8, 0,
sizeof(VideoConvert::Rgb8888) * width * height, 1, 1, 0, 0};
// header is always the same for a bitmap object; compute the info once per
// bitmap object
if (!headerBuffer) {
// For further information see:
// http://en.wikipedia.org/wiki/BMP_file_format
Magic magic = {{'B','M'}};
Header header = {sizeof(VideoConvert::Rgb8888) * width * height,
0, 0, 54};
Info info = {sizeof(Info), width, height, 1,
sizeof(VideoConvert::Rgb8888) * 8, 0,
sizeof(VideoConvert::Rgb8888) * width * height, 1, 1, 0, 0};
bmp->write(reinterpret_cast<char*>(&magic), sizeof(magic));
bmp->write(reinterpret_cast<char*>(&header), sizeof(header));
bmp->write(reinterpret_cast<char*>(&info), sizeof(info));
char *p = headerBuffer = new char[sizeofHeaderBuffer];
memcpy(p, &magic, sizeof(Magic));
p += sizeof(Magic);
memcpy(p, &header, sizeof(Header));
p += sizeof(Header);
memcpy(p, &info, sizeof(Info));
}
// 1. write the header
bmp->write(headerBuffer, sizeofHeaderBuffer);
// 2. write the bitmap data
uint8_t *tmp = vc.convert(data);
uint32_t *tmp32 = (uint32_t*)tmp;

15
src/base/bitmap.hh
View file

@ -36,6 +36,7 @@
*
* Authors: William Wang
* Ali Saidi
* Chris Emmons
*/
#ifndef __BASE_BITMAP_HH__
#define __BASE_BITMAP_HH__
@ -62,6 +63,9 @@ class Bitmap
*/
Bitmap(VideoConvert::Mode mode, uint16_t w, uint16_t h, uint8_t *d);
/** Destructor */
~Bitmap();
/** Provide the converter with the data that should be output. It will be
* converted into rgb8888 and write out when write() is called.
* @param d the data
@ -71,7 +75,13 @@ class Bitmap
/** Write the provided data into the fstream provided
* @param bmp stream to write to
*/
void write(std::ostream *bmp);
void write(std::ostream *bmp) const;
/** Gets a hash over the bitmap for quick comparisons to other bitmaps.
* @return hash of the bitmap
*/
uint64_t getHash() const { return vc.getHash(data); }
private:
VideoConvert::Mode mode;
@ -81,6 +91,9 @@ class Bitmap
VideoConvert vc;
mutable char *headerBuffer;
static const size_t sizeofHeaderBuffer;
struct Magic
{
unsigned char magic_number[2];

2
src/base/compiler.hh
View file

@ -42,6 +42,7 @@
#define M5_DUMMY_RETURN
#define M5_VAR_USED __attribute__((unused))
#define M5_ATTR_PACKED __attribute__ ((__packed__))
#define M5_NO_INLINE __attribute__ ((__noinline__))
#elif defined(__SUNPRO_CC)
// this doesn't do anything with sun cc, but why not
#define M5_ATTR_NORETURN __sun_attr__((__noreturn__))
@ -50,6 +51,7 @@
#define M5_VAR_USED
#define M5_PRAGMA_NORETURN(x) DO_PRAGMA(does_not_return(x))
#define M5_ATTR_PACKED __attribute__ ((__packed__))
#define M5_NO_INLINE __attribute__ ((__noinline__))
#else
#error "Need to define compiler options in base/compiler.hh"
#endif

140
src/base/output.cc
View file

@ -26,11 +26,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Chris Emmons
*/
#include <sys/stat.h>
#include <sys/types.h>
#include <dirent.h>
#include <cassert>
#include <cerrno>
#include <climits>
#include <cstdlib>
@ -46,7 +49,7 @@ using namespace std;
OutputDirectory simout;
/**
*
* @file This file manages creating / deleting output files for the simulator.
*/
OutputDirectory::OutputDirectory()
{}
@ -73,25 +76,53 @@ OutputDirectory::checkForStdio(const string &name) const
ostream *
OutputDirectory::openFile(const string &filename,
ios_base::openmode mode) const
ios_base::openmode mode)
{
if (filename.find(".gz", filename.length()-3) < filename.length()) {
ogzstream *file = new ogzstream(filename.c_str(), mode);
if (!file->is_open())
fatal("Cannot open file %s", filename);
assert(files.find(filename) == files.end());
files[filename] = file;
return file;
} else {
ofstream *file = new ofstream(filename.c_str(), mode);
if (!file->is_open())
fatal("Cannot open file %s", filename);
assert(files.find(filename) == files.end());
files[filename] = file;
return file;
}
}
void
OutputDirectory::close(ostream *openStream) {
map_t::iterator i;
for (i = files.begin(); i != files.end(); i++) {
if (i->second != openStream)
continue;
ofstream *fs = dynamic_cast<ofstream*>(i->second);
if (fs) {
fs->close();
delete i->second;
break;
} else {
ogzstream *gfs = dynamic_cast<ogzstream*>(i->second);
if (gfs) {
gfs->close();
delete i->second;
break;
}
}
}
if (i == files.end())
fatal("Attempted to close an unregistred file stream");
files.erase(i);
}
void
OutputDirectory::setDirectory(const string &d)
{
@ -100,9 +131,9 @@ OutputDirectory::setDirectory(const string &d)
dir = d;
// guarantee that directory ends with a '/'
if (dir[dir.size() - 1] != '/')
dir += "/";
// guarantee that directory ends with a path separator
if (dir[dir.size() - 1] != PATH_SEPARATOR)
dir += PATH_SEPARATOR;
}
const string &
@ -117,7 +148,7 @@ OutputDirectory::directory() const
inline string
OutputDirectory::resolve(const string &name) const
{
return (name[0] != '/') ? dir + name : name;
return (name[0] != PATH_SEPARATOR) ? dir + name : name;
}
ostream *
@ -136,20 +167,18 @@ OutputDirectory::create(const string &name, bool binary)
}
ostream *
OutputDirectory::find(const string &name)
OutputDirectory::find(const string &name) const
{
ostream *file = checkForStdio(name);
if (file)
return file;
string filename = resolve(name);
map_t::iterator i = files.find(filename);
const string filename = resolve(name);
map_t::const_iterator i = files.find(filename);
if (i != files.end())
return (*i).second;
file = openFile(filename);
files[filename] = file;
return file;
return NULL;
}
bool
@ -157,3 +186,82 @@ OutputDirectory::isFile(const std::ostream *os)
{
return os && os != &cerr && os != &cout;
}
bool
OutputDirectory::isFile(const string &name) const
{
// definitely a file if in our data structure
if (find(name) != NULL) return true;
struct stat st_buf;
int st = stat(name.c_str(), &st_buf);
return (st == 0) && S_ISREG(st_buf.st_mode);
}
string
OutputDirectory::createSubdirectory(const string &name) const
{
const string new_dir = resolve(name);
if (new_dir.find(directory()) == string::npos)
fatal("Attempting to create subdirectory not in m5 output dir\n");
// if it already exists, that's ok; otherwise, fail if we couldn't create
if ((mkdir(new_dir.c_str(), 0755) != 0) && (errno != EEXIST))
fatal("Failed to create new output subdirectory '%s'\n", new_dir);
return name + PATH_SEPARATOR;
}
void
OutputDirectory::remove(const string &name, bool recursive)
{
const string fname = resolve(name);
if (fname.find(directory()) == string::npos)
fatal("Attempting to remove file/dir not in output dir\n");
if (isFile(fname)) {
// close and release file if we have it open
map_t::iterator itr = files.find(fname);
if (itr != files.end()) {
delete itr->second;
files.erase(itr);
}
if (::remove(fname.c_str()) != 0)
fatal("Could not erase file '%s'\n", fname);
} else {
// assume 'name' is a directory
if (recursive) {
DIR *dir = opendir(fname.c_str());
// silently ignore removal request for non-existent directory
if ((!dir) && (errno == ENOENT))
return;
// fail on other errors
if (!dir) {
perror("opendir");
fatal("Error opening directory for recursive removal '%s'\n",
fname);
}
struct dirent *de = readdir(dir);
while (de != NULL) {
// ignore files starting with a '.'; user must delete those
// manually if they really want to
if (de->d_name[0] != '.')
remove(name + PATH_SEPARATOR + de->d_name, recursive);
de = readdir(dir);
}
}
// try to force recognition that we deleted the files in the directory
sync();
if (::remove(fname.c_str()) != 0) {
perror("Warning! 'remove' failed. Could not erase directory.");
}
}
}

121
src/base/output.hh
View file

@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Chris Emmons
*/
#ifndef __BASE_OUTPUT_HH__
@ -35,33 +36,147 @@
#include <map>
#include <string>
/** Interface for creating files in a gem5 output directory. */
class OutputDirectory
{
private:
/** File names and associated stream handles */
typedef std::map<std::string, std::ostream *> map_t;
/** Open file streams within this directory */
map_t files;
/** Name of this directory */
std::string dir;
/** System-specific path separator character */
static const char PATH_SEPARATOR = '/';
/**
* Returns relative file names prepended with name of this directory.
* Returns absolute file names unaltered.
*
* @param name file name to prepend with directory name
* @return file name prepended with base directory name or unaltered
* absolute file name
*/
std::string resolve(const std::string &name) const;
protected:
/**
* Determines whether given file name corresponds to standard output
* streams.
*
* @param name name of file to check
* @return output stream for standard output or error stream if name
* corresponds to one or the other; NULL otherwise
*/
std::ostream *checkForStdio(const std::string &name) const;
/** Opens a file (optionally compressed).
*
* Will open a file as a compressed stream if filename ends in .gz.
*
* @param filename file to open
* @param mode attributes to open file with
* @return stream pointer to opened file; will cause sim fail on error
*/
std::ostream *openFile(const std::string &filename,
std::ios_base::openmode mode = std::ios::trunc) const;
std::ios_base::openmode mode = std::ios::trunc);
public:
/** Constructor. */
OutputDirectory();
/** Destructor. */
~OutputDirectory();
/**
* Sets name of this directory.
* @param dir name of this directory
*/
void setDirectory(const std::string &dir);
/**
* Gets name of this directory.
* @return name of this directory
*/
const std::string &directory() const;
/**
* Creates a file in this directory (optionally compressed).
*
* Will open a file as a compressed stream if filename ends in .gz.
*
* @param name name of file to create (without this directory's name
* leading it)
* @param binary true to create a binary file; false otherwise
* @return stream to the opened file
*/
std::ostream *create(const std::string &name, bool binary = false);
std::ostream *find(const std::string &name);
/**
* Closes a file stream.
*
* Stream must have been opened through this interface, or sim will fail.
*
* @param openStream open stream to close
*/
void close(std::ostream *openStream);
/**
* Finds stream associated with a file.
* @param name of file
* @return stream to specified file or NULL if file does not exist
*/
std::ostream *find(const std::string &name) const;
/**
* Returns true if stream is open and not standard output or error.
* @param os output stream to evaluate
* @return true if os is non-NULL and not cout or cerr
*/
static bool isFile(const std::ostream *os);
static inline bool isFile(const std::ostream &os) { return isFile(&os); }
/**
* Determines whether a file name corresponds to a file in this directory.
* @param name name of file to evaluate
* @return true iff file has been opened in this directory or exists on the
* file system within this directory
*/
bool isFile(const std::string &name) const;
/**
* Returns true if stream is open and not standard output or error.
* @param os output stream to evaluate
* @return true if os is non-NULL and not cout or cerr
*/
static inline bool isFile(const std::ostream &os) {
return isFile(&os);
}
/**
* Creates a subdirectory within this directory.
* @param name name of subdirectory
* @return the new subdirectory's name suffixed with a path separator
*/
std::string createSubdirectory(const std::string &name) const;
/**
* Removes a specified file or subdirectory.
*
* Will cause sim to fail for most errors. However, it will only warn the
* user if a directory could not be removed. This is in place to
* accommodate slow file systems where file deletions within a subdirectory
* may not be recognized quickly enough thereby causing the subsequent call
* to remove the directory to fail (seemingly unempty directory).
*
* @param name name of file or subdirectory to remove; name should not
* be prepended with the name of this directory object
* @param recursive set to true to attempt to recursively delete a
* subdirectory and its contents
*/
void remove(const std::string &name, bool recursive=false);
};
extern OutputDirectory simout;

6
src/base/stats/text.cc
View file

@ -674,7 +674,11 @@ initText(const string &filename, bool desc)
static bool connected = false;
if (!connected) {
text.open(*simout.find(filename));
ostream *os = simout.find(filename);
if (!os)
os = simout.create(filename);
text.open(*os);
text.descriptions = desc;
connected = true;
}

2
src/base/trace.cc
View file

@ -64,6 +64,8 @@ void
setOutput(const string &filename)
{
dprintf_stream = simout.find(filename);
if (!dprintf_stream)
dprintf_stream = simout.create(filename);
}
ObjectMatch ignore;

1
src/base/vnc/VncServer.py
View file

@ -43,3 +43,4 @@ class VncServer(SimObject):
type = 'VncServer'
port = Param.TcpPort(5900, "listen port")
number = Param.Int(0, "vnc client number")
frame_capture = Param.Bool(False, "capture changed frames to files")

23
src/base/vnc/convert.cc
View file

@ -67,7 +67,7 @@ VideoConvert::~VideoConvert()
}
uint8_t*
VideoConvert::convert(uint8_t *fb)
VideoConvert::convert(const uint8_t *fb) const
{
switch (inputMode) {
case bgr565:
@ -82,7 +82,7 @@ VideoConvert::convert(uint8_t *fb)
}
uint8_t*
VideoConvert::m565rgb8888(uint8_t *fb, bool bgr)
VideoConvert::m565rgb8888(const uint8_t *fb, bool bgr) const
{
uint8_t *out = new uint8_t[area() * sizeof(uint32_t)];
uint32_t *out32 = (uint32_t*)out;
@ -113,7 +113,7 @@ VideoConvert::m565rgb8888(uint8_t *fb, bool bgr)
uint8_t*
VideoConvert::bgr8888rgb8888(uint8_t *fb)
VideoConvert::bgr8888rgb8888(const uint8_t *fb) const
{
uint8_t *out = new uint8_t[area() * sizeof(uint32_t)];
uint32_t *out32 = (uint32_t*)out;
@ -136,4 +136,21 @@ VideoConvert::bgr8888rgb8888(uint8_t *fb)
return out;
}
/*
uint64_t
VideoConvert::getHash(const uint8_t *fb) const
{
const uint8_t *fb_e = fb + area();
uint64_t hash = 1;
while (fb < fb_e - 8) {
hash += *((const uint64_t*)fb);
fb += 8;
}
while (fb < fb_e) {
hash += *(fb++);
}
return hash;
}*/

18
src/base/vnc/convert.hh
View file

@ -44,6 +44,7 @@
#ifndef __BASE_VNC_CONVERT_HH__
#define __BASE_VNC_CONVERT_HH__
#include <zlib.h>
#include "base/bitunion.hh"
class VideoConvert
@ -107,12 +108,21 @@ class VideoConvert
* @param fb the frame buffer to convert
* @return the converted data (user must free)
*/
uint8_t* convert(uint8_t *fb);
uint8_t* convert(const uint8_t *fb) const;
/** Return the number of pixels that this buffer specifies
* @return number of pixels
*/
int area() { return width * height; }
int area() const { return width * height; }
/**
* Returns a hash on the raw data.
*
* @return hash of the buffer
*/
inline uint64_t getHash(const uint8_t *fb) const {
return adler32(0UL, fb, width * height);
}
private:
@ -121,7 +131,7 @@ class VideoConvert
* @param fb the data to convert
* @return converted data
*/
uint8_t* bgr8888rgb8888(uint8_t *fb);
uint8_t* bgr8888rgb8888(const uint8_t *fb) const;
/**
* Convert a bgr565 or rgb565 input to rgb8888.
@ -129,7 +139,7 @@ class VideoConvert
* @param bgr true if the input data is bgr565
* @return converted data
*/
uint8_t* m565rgb8888(uint8_t *fb, bool bgr);
uint8_t* m565rgb8888(const uint8_t *fb, bool bgr) const;
Mode inputMode;
Mode outputMode;

54
src/base/vnc/vncserver.cc
View file

@ -43,7 +43,10 @@
*/
#include <sys/ioctl.h>
#include <sys/stat.h>
#include <sys/termios.h>
#include <sys/types.h>
#include <fcntl.h>
#include <poll.h>
#include <unistd.h>
@ -52,11 +55,14 @@
#include "base/vnc/vncserver.hh"
#include "base/atomicio.hh"
#include "base/bitmap.hh"
#include "base/misc.hh"
#include "base/output.hh"
#include "base/socket.hh"
#include "base/trace.hh"
#include "debug/VNC.hh"
#include "sim/byteswap.hh"
#include "sim/core.hh"
using namespace std;
@ -98,14 +104,14 @@ VncServer::VncServer(const Params *p)
: SimObject(p), listenEvent(NULL), dataEvent(NULL), number(p->number),
dataFd(-1), _videoWidth(1), _videoHeight(1), clientRfb(0), keyboard(NULL),
mouse(NULL), sendUpdate(false), videoMode(VideoConvert::UnknownMode),
vc(NULL)
vc(NULL), captureEnabled(p->frame_capture), captureCurrentFrame(0),
captureLastHash(0), captureBitmap(0)
{
if (p->port)
listen(p->port);
curState = WaitForProtocolVersion;
// currently we only support this one pixel format
// unpacked 32bit rgb (rgb888 + 8 bits of nothing/alpha)
// keep it around for telling the client and making
@ -121,6 +127,14 @@ VncServer::VncServer(const Params *p)
pixelFormat.greenshift = 8;
pixelFormat.blueshift = 0;
if (captureEnabled) {
// remove existing frame output directory if it exists, then create a
// clean empty directory
const string FRAME_OUTPUT_SUBDIR = "frames_" + name();
simout.remove(FRAME_OUTPUT_SUBDIR, true);
captureOutputDirectory = simout.createSubdirectory(
FRAME_OUTPUT_SUBDIR);
}
DPRINTF(VNC, "Vnc server created at port %d\n", p->port);
}
@ -686,6 +700,16 @@ VncServer::setFrameBufferParams(VideoConvert::Mode mode, int width, int height)
vc = new VideoConvert(mode, VideoConvert::rgb8888, videoWidth(),
videoHeight());
if (captureEnabled) {
// create bitmap of the frame with new attributes
if (captureBitmap)
delete captureBitmap;
assert(clientRfb);
captureBitmap = new Bitmap(videoMode, width, height, clientRfb);
assert(captureBitmap);
}
if (dataFd > 0 && clientRfb && curState == NormalPhase) {
if (supportsResizeEnc)
sendFrameBufferResized();
@ -702,3 +726,29 @@ VncServerParams::create()
{
return new VncServer(this);
}
void
VncServer::captureFrameBuffer()
{
assert(captureBitmap);
// skip identical frames
uint64_t new_hash = captureBitmap->getHash();
if (captureLastHash == new_hash)
return;
captureLastHash = new_hash;
// get the filename for the current frame
char frameFilenameBuffer[64];
snprintf(frameFilenameBuffer, 64, "fb.%06d.%lld.bmp.gz",
captureCurrentFrame, static_cast<long long int>(curTick()));
const string frameFilename(frameFilenameBuffer);
// create the compressed framebuffer file
ostream *fb_out = simout.create(captureOutputDirectory + frameFilename,
true);
captureBitmap->write(fb_out);
simout.close(fb_out);
++captureCurrentFrame;
}

22
src/base/vnc/vncserver.hh
View file

@ -48,6 +48,7 @@
#include <iostream>
#include "base/vnc/convert.hh"
#include "base/bitmap.hh"
#include "base/circlebuf.hh"
#include "base/pollevent.hh"
#include "base/socket.hh"
@ -55,6 +56,7 @@
#include "params/VncServer.hh"
#include "sim/sim_object.hh"
/**
* A device that expects to receive input from the vnc server should derrive
* (through mulitple inheritence if necessary from VncKeyboard or VncMouse
@ -316,7 +318,25 @@ class VncServer : public SimObject
/** The video converter that transforms data for us */
VideoConvert *vc;
/** Flag indicating whether to capture snapshots of frame buffer or not */
bool captureEnabled;
/** Current frame number being captured to a file */
int captureCurrentFrame;
/** Directory to store captured frames to */
std::string captureOutputDirectory;
/** Computed hash of the last captured frame */
uint64_t captureLastHash;
/** Cached bitmap object for writing out frame buffers to file */
Bitmap *captureBitmap;
protected:
/** Captures the current frame buffer to a file */
void captureFrameBuffer();
/**
* vnc client Interface
*/
@ -449,6 +469,8 @@ class VncServer : public SimObject
setDirty()
{
sendUpdate = true;
if (captureEnabled)
captureFrameBuffer();
sendFrameBufferUpdate();
}

19
src/cpu/BaseCPU.py
View file

@ -167,15 +167,16 @@ class BaseCPU(MemObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
elif buildEnv['TARGET_ISA'] == 'arm':
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)

6
src/cpu/base.cc
View file

@ -184,7 +184,11 @@ BaseCPU::BaseCPU(Params *p)
functionTracingEnabled = false;
if (p->function_trace) {
functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
const string fname = csprintf("ftrace.%s", name());
functionTraceStream = simout.find(fname);
if (!functionTraceStream)
functionTraceStream = simout.create(fname);
currentFunctionStart = currentFunctionEnd = 0;
functionEntryTick = p->function_trace_start;

4
src/cpu/o3/O3CPU.py
View file

@ -142,7 +142,3 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
self.icache.tgts_per_mshr = 20
self.dcache.tgts_per_mshr = 20

13
src/cpu/o3/cpu.cc
View file

@ -438,6 +438,12 @@ FullO3CPU<Impl>::regStats()
"to idling")
.prereq(idleCycles);
quiesceCycles
.name(name() + ".quiesceCycles")
.desc("Total number of cycles that CPU has spent quiesced or waiting "
"for an interrupt")
.prereq(quiesceCycles);
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
@ -682,6 +688,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
lastActivatedCycle = curTick();
_status = Running;
@ -716,6 +724,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
DPRINTF(Quiesce, "Suspending Context\n");
lastRunningCycle = curTick();
_status = Idle;
}
@ -1193,6 +1204,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
lastRunningCycle = curTick();
}
template <class Impl>

3
src/cpu/o3/cpu.hh
View file

@ -713,6 +713,9 @@ class FullO3CPU : public BaseO3CPU
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar idleCycles;
/** Stat for total number of cycles the CPU spends descheduled due to a
* quiesce operation or waiting for an interrupt. */
Stats::Scalar quiesceCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
/** Stat for the total number of committed instructions. */

12
src/dev/io_device.cc
View file

@ -115,11 +115,13 @@ BasicPioDevice::addressRanges(AddrRangeList &range_list)
}
DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff)
DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff,
bool recv_snoops)
: Port(dev->name() + "-dmaport", dev), device(dev), sys(s),
pendingCount(0), actionInProgress(0), drainEvent(NULL),
backoffTime(0), minBackoffDelay(min_backoff),
maxBackoffDelay(max_backoff), inRetry(false), backoffEvent(this)
maxBackoffDelay(max_backoff), inRetry(false), recvSnoops(recv_snoops),
snoopRangeSent(false), backoffEvent(this)
{ }
bool
@ -141,6 +143,12 @@ DmaPort::recvTiming(PacketPtr pkt)
pkt->reinitNacked();
queueDma(pkt, true);
} else if (pkt->senderState) {
if (recvSnoops) {
if (pkt->isRequest()) {
return true;
}
}
DmaReqState *state;
backoffTime >>= 2;

36
src/dev/io_device.hh
View file

@ -129,20 +129,45 @@ class DmaPort : public Port
* it is that it's sending. */
bool inRetry;
/** Port accesses a cache which requires snooping */
bool recvSnoops;
/** Records snoop response so we only reply once to a status change */
bool snoopRangeSent;
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); M5_DUMMY_RETURN }
{
if (recvSnoops) return 0;
panic("dma port shouldn't be used for pio access."); M5_DUMMY_RETURN
}
virtual void recvFunctional(PacketPtr pkt)
{ panic("dma port shouldn't be used for pio access."); }
{
if (recvSnoops) return;
panic("dma port shouldn't be used for pio access.");
}
virtual void recvStatusChange(Status status)
{ ; }
{
if (recvSnoops) {
if (status == RangeChange) {
if (!snoopRangeSent) {
snoopRangeSent = true;
sendStatusChange(Port::RangeChange);
}
return;
}
panic("Unexpected recvStatusChange\n");
}
}
virtual void recvRetry() ;
virtual void getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop)
{ resp.clear(); snoop = false; }
{ resp.clear(); snoop = recvSnoops; }
void queueDma(PacketPtr pkt, bool front = false);
void sendDma();
@ -151,7 +176,8 @@ class DmaPort : public Port
EventWrapper<DmaPort, &DmaPort::sendDma> backoffEvent;
public:
DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff);
DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff,
bool recv_snoops = false);
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
uint8_t *data, Tick delay, Request::Flags flag = 0);

2
src/dev/sparc/mm_disk.cc
View file

@ -83,7 +83,7 @@ MmDisk::read(PacketPtr pkt)
break;
case sizeof(uint16_t):
memcpy(&d16, diskData + (accessAddr % SectorSize), 2);
pkt->set(htobe(d32));
pkt->set(htobe(d16));
DPRINTF(IdeDisk, "reading word %#x value= %#x\n", accessAddr, d16);
break;
case sizeof(uint32_t):

3
src/dev/terminal.cc
View file

@ -102,6 +102,9 @@ Terminal::Terminal(const Params *p)
{
if (p->output) {
outfile = simout.find(p->name);
if (!outfile)
outfile = simout.create(p->name);
outfile->setf(ios::unitbuf);
}

3
src/mem/physical.cc
View file

@ -556,7 +556,8 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(_size);
if (size() > params()->range.size())
fatal("Memory size has changed!\n");
fatal("Memory size has changed! size %lld, param size %lld\n",
size(), params()->range.size());
pmemAddr = (uint8_t *)mmap(NULL, size(),
PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);

66
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -62,6 +62,13 @@ machine(L1Cache, "AMD Hammer-like protocol")
M, AccessPermission:Read_Only, desc="Modified (dirty)";
MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
// Base states, locked and ready to service the mandatory queue
IR, AccessPermission:Invalid, desc="Idle";
SR, AccessPermission:Read_Only, desc="Shared";
OR, AccessPermission:Read_Only, desc="Owned";
MR, AccessPermission:Read_Only, desc="Modified (dirty)";
MMR, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
// Transient States
IM, AccessPermission:Busy, "IM", desc="Issued GetX";
SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have a valid copy of the line";
@ -1217,6 +1224,11 @@ machine(L1Cache, "AMD Hammer-like protocol")
stall_and_wait(mandatoryQueue_in, address);
}
action(z_stall, "z", desc="stall") {
// do nothing and the special z_stall action will return a protocol stall
// so that the next port is checked
}
action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
wakeUpBuffers(address);
}
@ -1246,7 +1258,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
zz_stallAndWaitMandatoryQueue;
}
transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F}, L1_to_L2) {
transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) {
zz_stallAndWaitMandatoryQueue;
}
@ -1259,7 +1271,11 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) {
// stall
z_stall;
}
transition({IR, SR, OR, MR, MMR}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) {
z_stall;
}
// Transitions moving data between the L1 and L2 caches
@ -1382,33 +1398,33 @@ machine(L1Cache, "AMD Hammer-like protocol")
ll_L2toL1Transfer;
}
transition(IT, Complete_L2_to_L1, I) {
transition(IT, Complete_L2_to_L1, IR) {
j_popTriggerQueue;
kd_wakeUpDependents;
}
transition(ST, Complete_L2_to_L1, S) {
transition(ST, Complete_L2_to_L1, SR) {
j_popTriggerQueue;
kd_wakeUpDependents;
}
transition(OT, Complete_L2_to_L1, O) {
transition(OT, Complete_L2_to_L1, OR) {
j_popTriggerQueue;
kd_wakeUpDependents;
}
transition(MT, Complete_L2_to_L1, M) {
transition(MT, Complete_L2_to_L1, MR) {
j_popTriggerQueue;
kd_wakeUpDependents;
}
transition(MMT, Complete_L2_to_L1, MM) {
transition(MMT, Complete_L2_to_L1, MMR) {
j_popTriggerQueue;
kd_wakeUpDependents;
}
// Transitions from Idle
transition(I, Load, IS) {
transition({I, IR}, Load, IS) {
ii_allocateL1DCacheBlock;
i_allocateTBE;
a_issueGETS;
@ -1416,7 +1432,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
k_popMandatoryQueue;
}
transition(I, Ifetch, IS) {
transition({I, IR}, Ifetch, IS) {
jj_allocateL1ICacheBlock;
i_allocateTBE;
a_issueGETS;
@ -1424,7 +1440,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
k_popMandatoryQueue;
}
transition(I, Store, IM) {
transition({I, IR}, Store, IM) {
ii_allocateL1DCacheBlock;
i_allocateTBE;
b_issueGETX;
@ -1432,7 +1448,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
k_popMandatoryQueue;
}
transition(I, Flush_line, IM_F) {
transition({I, IR}, Flush_line, IM_F) {
it_allocateTBE;
bf_issueGETF;
uu_profileMiss;
@ -1455,14 +1471,19 @@ machine(L1Cache, "AMD Hammer-like protocol")
k_popMandatoryQueue;
}
transition(S, Store, SM) {
transition(SR, {Load, Ifetch}, S) {
h_load_hit;
k_popMandatoryQueue;
}
transition({S, SR}, Store, SM) {
i_allocateTBE;
b_issueGETX;
uu_profileMiss;
k_popMandatoryQueue;
}
transition(S, Flush_line, SM_F) {
transition({S, SR}, Flush_line, SM_F) {
i_allocateTBE;
bf_issueGETF;
uu_profileMiss;
@ -1491,14 +1512,19 @@ machine(L1Cache, "AMD Hammer-like protocol")
k_popMandatoryQueue;
}
transition(O, Store, OM) {
transition(OR, {Load, Ifetch}, O) {
h_load_hit;
k_popMandatoryQueue;
}
transition({O, OR}, Store, OM) {
i_allocateTBE;
b_issueGETX;
p_decrementNumberOfMessagesByOne;
uu_profileMiss;
k_popMandatoryQueue;
}
transition(O, Flush_line, OM_F) {
transition({O, OR}, Flush_line, OM_F) {
i_allocateTBE;
bf_issueGETF;
p_decrementNumberOfMessagesByOne;
@ -1530,17 +1556,17 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
// Transitions from Modified
transition(MM, {Load, Ifetch}) {
transition({MM, MMR}, {Load, Ifetch}, MM) {
h_load_hit;
k_popMandatoryQueue;
}
transition(MM, Store) {
transition({MM, MMR}, Store, MM) {
hh_store_hit;
k_popMandatoryQueue;
}
transition({MM, M}, Flush_line, MM_F) {
transition({MM, M, MMR}, Flush_line, MM_F) {
i_allocateTBE;
bf_issueGETF;
p_decrementNumberOfMessagesByOne;
@ -1587,12 +1613,12 @@ machine(L1Cache, "AMD Hammer-like protocol")
}
// Transitions from Dirty Exclusive
transition(M, {Load, Ifetch}) {
transition({M, MR}, {Load, Ifetch}, M) {
h_load_hit;
k_popMandatoryQueue;
}
transition(M, Store, MM) {
transition({M, MR}, Store, MM) {
hh_store_hit;
k_popMandatoryQueue;
}

1
src/mem/protocol/Network_test.slicc
View file

@ -3,4 +3,3 @@ include "RubySlicc_interfaces.slicc";
include "Network_test-msg.sm";
include "Network_test-cache.sm";
include "Network_test-dir.sm";
include "standard_1level_CMP-protocol.sm";

2
src/mem/ruby/network/topologies/MeshDirCorners.py
View file

@ -99,7 +99,7 @@ def makeTopology(nodes, options, IntLink, ExtLink, Router):
# Connect the dma nodes to router 0. These should only be DMA nodes.
for (i, node) in enumerate(dma_nodes):
assert(node.type == 'DMA_Controller')
ext_links.append(ExtLink(ext_node=node, int_node=mesh.routers[0]))
ext_links.append(ExtLink(link_id=link_count, ext_node=node, int_node=mesh.routers[0]))
# Create the mesh links. First row (east-west) links then column
# (north-south) links

2
src/sim/process.cc
View file

@ -350,8 +350,6 @@ Process::fixupStackFault(Addr vaddr)
};
return true;
}
warn("Not extending stack: address %#x isn't at the end of the stack.",
vaddr);
return false;
}

2
tests/configs/o3-timing-mp.py
View file

@ -38,7 +38,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

1
tests/configs/o3-timing.py
View file

@ -39,6 +39,7 @@ class MyCache(BaseCache):
class MyL1Cache(MyCache):
is_top_level = True
tgts_per_mshr = 20
cpu = DerivO3CPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),

2
tests/configs/pc-o3-timing.py
View file

@ -42,7 +42,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

2
tests/configs/realview-o3-dual.py
View file

@ -40,7 +40,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

2
tests/configs/realview-o3.py
View file

@ -40,7 +40,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

2
tests/configs/tsunami-o3-dual.py
View file

@ -40,7 +40,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

2
tests/configs/tsunami-o3.py
View file

@ -40,7 +40,7 @@ class L1(BaseCache):
latency = '1ns'
block_size = 64
mshrs = 4
tgts_per_mshr = 8
tgts_per_mshr = 20
is_top_level = True
# ----------------------

2
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864

10
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 12:27:58
gem5 started Aug 20 2011 12:28:18
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 16:59:04
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -40,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 177134936000 because target called exit()
Exiting @ tick 177098873000 because target called exit()

708
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.177135 # Number of seconds simulated
sim_ticks 177134936000 # Number of ticks simulated
sim_seconds 0.177099 # Number of seconds simulated
sim_ticks 177098873000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 142557 # Simulator instruction rate (inst/s)
host_tick_rate 41921641 # Simulator tick rate (ticks/s)
host_mem_usage 216920 # Number of bytes of host memory used
host_seconds 4225.38 # Real time elapsed on the host
sim_insts 602359810 # Number of instructions simulated
host_inst_rate 166594 # Simulator instruction rate (inst/s)
host_tick_rate 48979898 # Simulator tick rate (ticks/s)
host_mem_usage 214636 # Number of bytes of host memory used
host_seconds 3615.75 # Real time elapsed on the host
sim_insts 602359805 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 354269873 # number of cpu cycles simulated
system.cpu.numCycles 354197747 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 91159436 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 84245505 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 4004866 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 86334569 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 80046410 # Number of BTB hits
system.cpu.BPredUnit.lookups 91137531 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 84224367 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 4001637 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 86284566 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 80014553 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1704802 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1819 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 76808344 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 703901675 # Number of instructions fetch has processed
system.cpu.fetch.Branches 91159436 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 81751212 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 159188980 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 18469359 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 103024732 # Number of cycles fetch has spent blocked
system.cpu.BPredUnit.usedRAS 1704311 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 1605 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 76786839 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 703787736 # Number of instructions fetch has processed
system.cpu.fetch.Branches 91137531 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 81718864 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 159146597 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 18455506 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 103039518 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 658 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 74435954 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1343690 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 353410599 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.128136 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.980644 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.PendingTrapStallCycles 620 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 74412736 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1337820 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 353350911 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.128080 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.980798 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 353410599 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.257316 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.986908 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 98916904 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 83485006 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 137131028 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19492362 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14385299 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6301332 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 2598 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 740264204 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 7138 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14385299 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 111881934 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 9577242 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 106466 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 143552765 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 73906893 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 727334722 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 296 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59781135 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10308783 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 341 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 753003460 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3381092272 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3381092144 # Number of integer rename lookups
system.cpu.fetch.rateDist::total 353350911 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.257307 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.986991 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 98877750 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 83515155 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 137076269 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19506954 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 14374783 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6301291 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 2551 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 740114896 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 7230 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 14374783 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 111843103 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 9537973 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 119731 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 143514381 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 73960940 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 727174418 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 286 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 59845789 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 10289393 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 334 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 752889395 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3380302991 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3380302863 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417402 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 125586053 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6434 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6436 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 132024310 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 179771780 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 82868403 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 19149565 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 24496609 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 702530034 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7346 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 663102893 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 740706 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 99626728 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 237214631 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1047 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 353410599 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.876296 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.734600 # Number of insts issued each cycle
system.cpu.rename.CommittedMaps 627417394 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 125472001 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 13297 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 13294 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 132095966 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 179744866 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 82855502 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 19180586 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 24795671 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 702443112 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 9504 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 663038146 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 743101 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 99536301 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 237037166 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3158 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 353350911 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.876430 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.733239 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 353410599 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 353350911 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2990868 71.85% 76.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 968637 23.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 412611240 62.22% 62.22% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6564 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 412586864 62.23% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.23% # Type of FU issued
@ -213,137 +213,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.23% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 172508534 26.02% 88.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 77976552 11.76% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 172485012 26.01% 88.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 77959702 11.76% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 663102893 # Type of FU issued
system.cpu.iq.rate 1.871745 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4153425 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006264 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1684510480 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 802175669 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 650244511 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 663038146 # Type of FU issued
system.cpu.iq.rate 1.871943 # Inst issue rate
system.cpu.iq.fu_busy_cnt 4162487 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006278 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1684332755 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 802000478 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 650204091 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 667256298 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 667200613 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 29664426 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 29662170 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 30819183 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 223952 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11801 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12647388 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 30792271 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 224606 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11800 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 12634488 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 13674 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12619 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 13695 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12640 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 14385299 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 811787 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 58163 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 702606824 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1856146 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 179771780 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 82868403 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6016 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13064 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5095 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11801 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4163103 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 495424 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4658527 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 656117429 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 169139334 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6985464 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 14374783 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 826341 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 58736 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 702522112 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1853549 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 179744866 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 82855502 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 8175 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 13020 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 5275 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11800 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4156328 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 497844 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 4654172 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 656067860 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 169121282 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6970286 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 69444 # number of nop insts executed
system.cpu.iew.exec_refs 245837823 # number of memory reference insts executed
system.cpu.iew.exec_branches 76466943 # Number of branches executed
system.cpu.iew.exec_stores 76698489 # Number of stores executed
system.cpu.iew.exec_rate 1.852027 # Inst execution rate
system.cpu.iew.wb_sent 652257551 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 650244527 # cumulative count of insts written-back
system.cpu.iew.wb_producers 423314128 # num instructions producing a value
system.cpu.iew.wb_consumers 657393243 # num instructions consuming a value
system.cpu.iew.exec_nop 69496 # number of nop insts executed
system.cpu.iew.exec_refs 245806937 # number of memory reference insts executed
system.cpu.iew.exec_branches 76463124 # Number of branches executed
system.cpu.iew.exec_stores 76685655 # Number of stores executed
system.cpu.iew.exec_rate 1.852264 # Inst execution rate
system.cpu.iew.wb_sent 652210228 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 650204107 # cumulative count of insts written-back
system.cpu.iew.wb_producers 423315850 # num instructions producing a value
system.cpu.iew.wb_consumers 657380921 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.835450 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.643928 # average fanout of values written-back
system.cpu.iew.wb_rate 1.835709 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.643943 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 100255909 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6299 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4064207 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 339025301 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.776740 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.152545 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 602359856 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 100172226 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6346 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4060978 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 338976129 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.776998 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.152747 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 108189269 31.91% 31.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 106528342 31.42% 63.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 49314404 14.55% 77.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9858111 2.91% 80.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 23334525 6.88% 87.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14310366 4.22% 91.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7925881 2.34% 94.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1332062 0.39% 94.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 18232341 5.38% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 108154848 31.91% 31.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 106518775 31.42% 63.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 49308103 14.55% 77.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9862304 2.91% 80.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 23329668 6.88% 87.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14306268 4.22% 91.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7919036 2.34% 94.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1343281 0.40% 94.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 18233846 5.38% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 339025301 # Number of insts commited each cycle
system.cpu.commit.count 602359861 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 338976129 # Number of insts commited each cycle
system.cpu.commit.count 602359856 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219173611 # Number of memory references committed
system.cpu.commit.loads 148952596 # Number of loads committed
system.cpu.commit.refs 219173609 # Number of memory references committed
system.cpu.commit.loads 148952595 # Number of loads committed
system.cpu.commit.membars 1328 # Number of memory barriers committed
system.cpu.commit.branches 70828603 # Number of branches committed
system.cpu.commit.branches 70828602 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522647 # Number of committed integer instructions.
system.cpu.commit.int_insts 533522643 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
system.cpu.commit.bw_lim_events 18232341 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 18233846 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1023408118 # The number of ROB reads
system.cpu.rob.rob_writes 1419658807 # The number of ROB writes
system.cpu.timesIdled 37049 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 859274 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 602359810 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated
system.cpu.cpi 0.588137 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.588137 # CPI: Total CPI of All Threads
system.cpu.ipc 1.700285 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.700285 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3276148182 # number of integer regfile reads
system.cpu.int_regfile_writes 676030301 # number of integer regfile writes
system.cpu.rob.rob_reads 1023273753 # The number of ROB reads
system.cpu.rob.rob_writes 1419480895 # The number of ROB writes
system.cpu.timesIdled 37084 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 846836 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 602359805 # Number of Instructions Simulated
system.cpu.committedInsts_total 602359805 # Number of Instructions Simulated
system.cpu.cpi 0.588017 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.588017 # CPI: Total CPI of All Threads
system.cpu.ipc 1.700631 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.700631 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3275893571 # number of integer regfile reads
system.cpu.int_regfile_writes 675997918 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 943785902 # number of misc regfile reads
system.cpu.misc_regfile_writes 2660 # number of misc regfile writes
system.cpu.icache.replacements 38 # number of replacements
system.cpu.icache.tagsinuse 657.730766 # Cycle average of tags in use
system.cpu.icache.total_refs 74434959 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 761 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 97812.035480 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 943643021 # number of misc regfile reads
system.cpu.misc_regfile_writes 2658 # number of misc regfile writes
system.cpu.icache.replacements 41 # number of replacements
system.cpu.icache.tagsinuse 657.503073 # Cycle average of tags in use
system.cpu.icache.total_refs 74411745 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 766 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 97143.270235 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 657.730766 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.321158 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 74434959 # number of ReadReq hits
system.cpu.icache.demand_hits 74434959 # number of demand (read+write) hits
system.cpu.icache.overall_hits 74434959 # number of overall hits
system.cpu.icache.ReadReq_misses 995 # number of ReadReq misses
system.cpu.icache.demand_misses 995 # number of demand (read+write) misses
system.cpu.icache.overall_misses 995 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 34724500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 34724500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 34724500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 74435954 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 74435954 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 74435954 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 657.503073 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.321046 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 74411745 # number of ReadReq hits
system.cpu.icache.demand_hits 74411745 # number of demand (read+write) hits
system.cpu.icache.overall_hits 74411745 # number of overall hits
system.cpu.icache.ReadReq_misses 991 # number of ReadReq misses
system.cpu.icache.demand_misses 991 # number of demand (read+write) misses
system.cpu.icache.overall_misses 991 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 34848500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 34848500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 34848500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 74412736 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 74412736 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 74412736 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 34898.994975 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34898.994975 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34898.994975 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 35164.984864 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35164.984864 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35164.984864 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,67 +353,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 234 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 234 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 234 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 761 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 761 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 225 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 225 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 225 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 766 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 766 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 766 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 25975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25975000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 26233500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 26233500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 26233500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34132.720105 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34132.720105 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34247.389034 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34247.389034 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 441231 # number of replacements
system.cpu.dcache.tagsinuse 4094.754255 # Cycle average of tags in use
system.cpu.dcache.total_refs 205797010 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 445327 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 462.125607 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 87838000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.754255 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999696 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 137942409 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 67851936 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1336 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1329 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 205794345 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 205794345 # number of overall hits
system.cpu.dcache.ReadReq_misses 249307 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1565595 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 8 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1814902 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1814902 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3284045500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 27041000027 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 163000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 30325045527 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 30325045527 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 138191716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 441233 # number of replacements
system.cpu.dcache.tagsinuse 4094.750739 # Cycle average of tags in use
system.cpu.dcache.total_refs 205781738 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 445329 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 462.089237 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 87973000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.750739 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999695 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 137926945 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 67852137 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 1328 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 1328 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 205779082 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 205779082 # number of overall hits
system.cpu.dcache.ReadReq_misses 249074 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1565394 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 11 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1814468 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1814468 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3282849000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 27038418025 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 203000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 30321267025 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 30321267025 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 138176019 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1329 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 207609247 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 207609247 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.001804 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.022553 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.005952 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.008742 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.008742 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 13172.696715 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17272.027585 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 20375 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 16708.916254 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 16708.916254 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 1339 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 1328 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 207593550 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 207593550 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.001803 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.022550 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.008215 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.008740 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.008740 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 13180.215518 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17272.595925 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 18454.545455 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 16710.830406 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 16710.830406 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked
@ -422,70 +422,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 395260 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 51378 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1318197 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 8 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1369575 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1369575 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 197929 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 247398 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 445327 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 445327 # number of overall MSHR misses
system.cpu.dcache.writebacks 395275 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 51126 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1318013 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 11 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1369139 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1369139 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 197948 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 247381 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 445329 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 445329 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1625138000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2544850527 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4169988527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4169988527 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1625134500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2544872027 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4170006527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4170006527 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001432 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001433 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003564 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.002145 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.002145 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8210.711922 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10286.463621 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.879861 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8209.906137 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10287.257417 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9363.878227 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 72978 # number of replacements
system.cpu.l2cache.tagsinuse 17806.299437 # Cycle average of tags in use
system.cpu.l2cache.total_refs 422221 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88511 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.770266 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 72960 # number of replacements
system.cpu.l2cache.tagsinuse 17805.724339 # Cycle average of tags in use
system.cpu.l2cache.total_refs 422235 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 88493 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.771394 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1880.880475 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15925.418963 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.057400 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486005 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 165873 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 395260 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 189038 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 354911 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 354911 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32814 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91177 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1126440500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2003739500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3130180000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3130180000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 198687 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 395260 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 247401 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 446088 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 446088 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.165154 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235904 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.204392 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.204392 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34328.045956 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34332.359543 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34330.807111 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34330.807111 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 1879.670498 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15926.053841 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.057363 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486025 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 165899 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 395275 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 189031 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 354930 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 354930 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32812 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58353 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91165 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91165 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1126662000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2003366500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3130028500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3130028500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 198711 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 395275 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 247384 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 446095 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 446095 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.165124 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235880 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.204362 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.204362 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34336.888943 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34331.850976 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34333.664235 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34333.664235 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
@ -494,28 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 58123 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 8 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32806 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91169 # number of overall MSHR misses
system.cpu.l2cache.writebacks 58128 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32801 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58353 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91154 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91154 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019567500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822366000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2841933500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2841933500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1019608000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822407000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2842015000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2842015000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165114 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235904 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.204374 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.204374 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31078.689874 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31224.680020 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31172.147331 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165069 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235880 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.204338 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.204338 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31084.662053 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31230.733638 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31178.171007 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

2
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -495,7 +495,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr

8
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 13:07:22
gem5 started Aug 20 2011 13:07:33
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

10
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.408816 # Number of seconds simulated
sim_ticks 408816360000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 166907 # Simulator instruction rate (inst/s)
host_tick_rate 48544601 # Simulator tick rate (ticks/s)
host_mem_usage 212296 # Number of bytes of host memory used
host_seconds 8421.46 # Real time elapsed on the host
host_inst_rate 252046 # Simulator instruction rate (inst/s)
host_tick_rate 73306837 # Simulator tick rate (ticks/s)
host_mem_usage 206388 # Number of bytes of host memory used
host_seconds 5576.78 # Real time elapsed on the host
sim_insts 1405604152 # Number of instructions simulated
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 817632721 # number of cpu cycles simulated
@ -273,7 +273,7 @@ system.cpu.int_regfile_writes 1303867666 # nu
system.cpu.fp_regfile_reads 16986540 # number of floating regfile reads
system.cpu.fp_regfile_writes 10452290 # number of floating regfile writes
system.cpu.misc_regfile_reads 605383822 # number of misc regfile reads
system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
system.cpu.icache.replacements 166 # number of replacements
system.cpu.icache.tagsinuse 1031.400456 # Cycle average of tags in use
system.cpu.icache.total_refs 170772098 # Total number of references to valid blocks.

3
tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -61,7 +62,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr

8
tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:15:22
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

10
tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764119000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2563815 # Simulator instruction rate (inst/s)
host_tick_rate 1281911834 # Simulator tick rate (ticks/s)
host_mem_usage 220472 # Number of bytes of host memory used
host_seconds 580.98 # Real time elapsed on the host
host_inst_rate 4241689 # Simulator instruction rate (inst/s)
host_tick_rate 2120851440 # Simulator tick rate (ticks/s)
host_mem_usage 196528 # Number of bytes of host memory used
host_seconds 351.16 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 78161763 # nu
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234411208 # number of times the integer registers were written
system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs

3
tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -164,7 +165,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr

8
tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:19:37
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init

10
tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 2.064259 # Number of seconds simulated
sim_ticks 2064258667000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1125008 # Simulator instruction rate (inst/s)
host_tick_rate 1559093873 # Simulator tick rate (ticks/s)
host_mem_usage 229120 # Number of bytes of host memory used
host_seconds 1324.01 # Real time elapsed on the host
host_inst_rate 2284016 # Simulator instruction rate (inst/s)
host_tick_rate 3165307188 # Simulator tick rate (ticks/s)
host_mem_usage 205232 # Number of bytes of host memory used
host_seconds 652.15 # Real time elapsed on the host
sim_insts 1489523295 # Number of instructions simulated
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 78161763 # nu
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234411207 # number of times the integer registers were written
system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -10,13 +10,13 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/projects/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/projects/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
pal=/dist/m5/system/binaries/ts_osfpal
pal=/projects/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -933,7 +933,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -953,7 +953,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -1082,7 +1082,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 15:21:47
gem5 started Aug 20 2011 15:21:55
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:05:33
gem5 started Nov 21 2011 19:03:16
gem5 executing on u200540-lin
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 106949500

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 1.897465 # Number of seconds simulated
sim_ticks 1897465263500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131766 # Simulator instruction rate (inst/s)
host_tick_rate 4454253159 # Simulator tick rate (ticks/s)
host_mem_usage 298700 # Number of bytes of host memory used
host_seconds 425.99 # Real time elapsed on the host
host_inst_rate 138767 # Simulator instruction rate (inst/s)
host_tick_rate 4690907118 # Simulator tick rate (ticks/s)
host_mem_usage 293696 # Number of bytes of host memory used
host_seconds 404.50 # Real time elapsed on the host
sim_insts 56130966 # Number of instructions simulated
system.l2c.replacements 397795 # number of replacements
system.l2c.tagsinuse 35116.884908 # Cycle average of tags in use
@ -594,6 +594,7 @@ system.cpu0.rob.rob_reads 136748495 # Th
system.cpu0.rob.rob_writes 124811050 # The number of ROB writes
system.cpu0.timesIdled 1231942 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 33836909 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3682845519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 50542242 # Number of Instructions Simulated
system.cpu0.committedInsts_total 50542242 # Number of Instructions Simulated
system.cpu0.cpi 2.217524 # CPI: Cycles Per Instruction
@ -1159,6 +1160,7 @@ system.cpu1.rob.rob_reads 15919184 # Th
system.cpu1.rob.rob_writes 14457399 # The number of ROB writes
system.cpu1.timesIdled 81947 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 698509 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3784960163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 5588724 # Number of Instructions Simulated
system.cpu1.committedInsts_total 5588724 # Number of Instructions Simulated
system.cpu1.cpi 1.783406 # CPI: Cycles Per Instruction

12
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -10,13 +10,13 @@ type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
console=/dist/m5/system/binaries/console
console=/projects/pd/randd/dist/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
kernel=/projects/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
pal=/dist/m5/system/binaries/ts_osfpal
pal=/projects/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@ -497,7 +497,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -517,7 +517,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@ -646,7 +646,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]

10
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 15:21:47
gem5 started Aug 20 2011 15:21:55
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:05:33
gem5 started Nov 21 2011 18:56:50
gem5 executing on u200540-lin
command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1858873594500 because m5_exit instruction encountered

9
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 1.858874 # Number of seconds simulated
sim_ticks 1858873594500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 131543 # Simulator instruction rate (inst/s)
host_tick_rate 4605131786 # Simulator tick rate (ticks/s)
host_mem_usage 295252 # Number of bytes of host memory used
host_seconds 403.65 # Real time elapsed on the host
host_inst_rate 141632 # Simulator instruction rate (inst/s)
host_tick_rate 4958330764 # Simulator tick rate (ticks/s)
host_mem_usage 290572 # Number of bytes of host memory used
host_seconds 374.90 # Real time elapsed on the host
sim_insts 53097697 # Number of instructions simulated
system.l2c.replacements 391354 # number of replacements
system.l2c.tagsinuse 34898.086140 # Cycle average of tags in use
@ -542,6 +542,7 @@ system.cpu.rob.rob_reads 143945413 # Th
system.cpu.rob.rob_writes 132113260 # The number of ROB writes
system.cpu.timesIdled 1256827 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34118395 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3601447413 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 53097697 # Number of Instructions Simulated
system.cpu.committedInsts_total 53097697 # Number of Instructions Simulated
system.cpu.cpi 2.190177 # CPI: Cycles Per Instruction

6
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -63,7 +63,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-arm-ael.img
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]

12
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simout
Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 15:41:18
gem5 started Aug 20 2011 15:46:02
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:32:34
gem5 started Nov 22 2011 02:00:14
gem5 executing on u200540-lin
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2582520130500 because m5_exit instruction encountered
Exiting @ tick 2582494395500 because m5_exit instruction encountered

1882
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@ -63,7 +63,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-arm-ael.img
image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]

12
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,14 +1,12 @@
Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 15:41:18
gem5 started Aug 20 2011 15:46:02
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:32:34
gem5 started Nov 22 2011 02:00:08
gem5 executing on u200540-lin
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2503587516500 because m5_exit instruction encountered
Exiting @ tick 2503566110500 because m5_exit instruction encountered

1075
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -15,7 +15,7 @@ e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@ -1301,7 +1301,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-x86.img
image_file=/projects/pd/randd/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1321,7 +1321,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]

11
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,16 +1,13 @@
Redirecting stdout to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout
Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Nov 17 2011 18:36:33
gem5 started Nov 17 2011 18:37:39
gem5 executing on ribera.cs.wisc.edu
gem5 compiled Nov 21 2011 16:24:08
gem5 started Nov 21 2011 23:30:30
gem5 executing on u200540-lin
command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
tests
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5145286546500 because m5_exit instruction encountered

9
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 5.145287 # Number of seconds simulated
sim_ticks 5145286546500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 252508 # Simulator instruction rate (inst/s)
host_tick_rate 1546872935 # Simulator tick rate (ticks/s)
host_mem_usage 390244 # Number of bytes of host memory used
host_seconds 3326.25 # Real time elapsed on the host
host_inst_rate 333179 # Simulator instruction rate (inst/s)
host_tick_rate 2041066369 # Simulator tick rate (ticks/s)
host_mem_usage 358476 # Number of bytes of host memory used
host_seconds 2520.88 # Real time elapsed on the host
sim_insts 839904894 # Number of instructions simulated
system.l2c.replacements 171120 # number of replacements
system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use
@ -511,6 +511,7 @@ system.cpu.rob.rob_reads 1146769000 # Th
system.cpu.rob.rob_writes 1747209492 # The number of ROB writes
system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9841548887 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 839904894 # Number of Instructions Simulated
system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated
system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction

4
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
View file

@ -500,9 +500,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100

10
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 12:27:58
gem5 started Aug 20 2011 12:28:18
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 17:34:42
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -25,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 33049447500 because target called exit()
Exiting @ tick 33080569000 because target called exit()

726
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.033049 # Number of seconds simulated
sim_ticks 33049447500 # Number of ticks simulated
sim_seconds 0.033081 # Number of seconds simulated
sim_ticks 33080569000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 142392 # Simulator instruction rate (inst/s)
host_tick_rate 51572715 # Simulator tick rate (ticks/s)
host_mem_usage 349636 # Number of bytes of host memory used
host_seconds 640.83 # Real time elapsed on the host
sim_insts 91249665 # Number of instructions simulated
host_inst_rate 152633 # Simulator instruction rate (inst/s)
host_tick_rate 55333677 # Simulator tick rate (ticks/s)
host_mem_usage 347340 # Number of bytes of host memory used
host_seconds 597.84 # Real time elapsed on the host
sim_insts 91249885 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 66098896 # number of cpu cycles simulated
system.cpu.numCycles 66161139 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 27480852 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21948199 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1405962 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24356195 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 23358870 # Number of BTB hits
system.cpu.BPredUnit.lookups 27503856 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21975755 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1408867 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 24498145 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 23511296 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 118630 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 12953 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15359689 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 131196018 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27480852 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23477500 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 32529765 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5482056 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 14124387 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14730221 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 368829 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 66068188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.007516 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.747063 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 109835 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 10070 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15373276 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 131330352 # Number of instructions fetch has processed
system.cpu.fetch.Branches 27503856 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 23621131 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 32575580 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5466802 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 14146451 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 14 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14744728 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 369535 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 66131343 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.004854 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.741973 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33589573 50.84% 50.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6678757 10.11% 60.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5691945 8.62% 69.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4809462 7.28% 76.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2791705 4.23% 81.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1680164 2.54% 83.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1554358 2.35% 85.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2929699 4.43% 90.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6342525 9.60% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 33609066 50.82% 50.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6636464 10.04% 60.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 5762437 8.71% 69.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4857984 7.35% 76.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2814891 4.26% 81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1640731 2.48% 83.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1559267 2.36% 86.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 2974436 4.50% 90.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6276067 9.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 66068188 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.415754 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.984844 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17938862 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12617377 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 30503596 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 985227 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4023126 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4444811 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 31491 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 129102519 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 31918 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4023126 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 19654279 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1111044 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8373205 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 29732459 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3174075 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 125001528 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 20 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 255212 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1879877 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 11 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 145677643 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 544340805 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 544335582 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 5223 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429087 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 38248551 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 647769 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 649953 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 7510284 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29313185 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5861466 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1226589 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 648810 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 117406606 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 634842 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 106217024 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74725 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26332148 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 63315965 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 80484 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 66068188 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.607688 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.762772 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 66131343 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.415710 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.985007 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17946396 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 12652276 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 30529024 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 996648 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4006999 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4433202 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 29411 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 129091755 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32642 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4006999 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 19654600 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1107804 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 8424491 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 29777332 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3160117 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 124853414 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 254616 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 1879605 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 145685583 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 543523067 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 543516086 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6981 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107429439 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 38256144 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 662187 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 664355 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 7619533 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29336350 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5741000 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1194254 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 692979 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 117270516 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 648807 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 106162042 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 30561 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26211084 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 62748223 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 93963 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 66131343 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.605321 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.761707 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24256842 36.71% 36.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14242052 21.56% 58.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 9853567 14.91% 73.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 8048166 12.18% 85.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4234412 6.41% 91.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2296375 3.48% 95.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2457048 3.72% 98.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 476279 0.72% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 203447 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 24322507 36.78% 36.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 14238727 21.53% 58.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 9857796 14.91% 73.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 8080873 12.22% 85.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4216462 6.38% 91.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2267133 3.43% 95.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2478028 3.75% 98.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 463113 0.70% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 206704 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 66068188 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 66131343 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 53590 10.28% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.28% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 193594 37.13% 47.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 274209 52.59% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 52363 10.31% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 27 0.01% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 192834 37.95% 48.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 262907 51.74% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 74732015 70.36% 70.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 10984 0.01% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 74696384 70.36% 70.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11141 0.01% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.37% # Type of FU issued
@ -207,144 +207,144 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.37% # Ty
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 117 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 159 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 183 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 260 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26127838 24.60% 94.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5345884 5.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26155378 24.64% 95.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5298717 4.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 106217024 # Type of FU issued
system.cpu.iq.rate 1.606941 # Inst issue rate
system.cpu.iq.fu_busy_cnt 521420 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004909 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 279097712 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 144373136 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102515328 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1008 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 309 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 106738111 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 333 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 366236 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 106162042 # Type of FU issued
system.cpu.iq.rate 1.604598 # Inst issue rate
system.cpu.iq.fu_busy_cnt 508131 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.004786 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 278993219 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 144129610 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 102521129 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 900 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1354 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 412 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 106669721 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 452 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 366276 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 6737356 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 42339 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 715 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1114761 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 6760478 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 42465 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 731 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 994251 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30343 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 30282 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4023126 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 183340 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 29024 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 118080266 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 812187 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29313185 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5861466 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 629989 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9572 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1070 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 715 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1280450 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 209997 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1490447 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104523417 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25726566 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1693607 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 4006999 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 182542 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 28701 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 117958129 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 810273 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29336350 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5741000 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 643936 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9429 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1050 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 731 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1288873 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 210071 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1498944 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 104530426 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25743276 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1631616 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 38818 # number of nop insts executed
system.cpu.iew.exec_refs 30937872 # number of memory reference insts executed
system.cpu.iew.exec_branches 21209374 # Number of branches executed
system.cpu.iew.exec_stores 5211306 # Number of stores executed
system.cpu.iew.exec_rate 1.581319 # Inst execution rate
system.cpu.iew.wb_sent 102947388 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102515637 # cumulative count of insts written-back
system.cpu.iew.wb_producers 60320212 # num instructions producing a value
system.cpu.iew.wb_consumers 97098710 # num instructions consuming a value
system.cpu.iew.exec_nop 38806 # number of nop insts executed
system.cpu.iew.exec_refs 30946109 # number of memory reference insts executed
system.cpu.iew.exec_branches 21214083 # Number of branches executed
system.cpu.iew.exec_stores 5202833 # Number of stores executed
system.cpu.iew.exec_rate 1.579937 # Inst execution rate
system.cpu.iew.wb_sent 102941811 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 102521541 # cumulative count of insts written-back
system.cpu.iew.wb_producers 60312663 # num instructions producing a value
system.cpu.iew.wb_consumers 96996327 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.550943 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.621226 # average fanout of values written-back
system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91262274 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26817270 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554358 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1387669 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 62045063 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.470903 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.226778 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26696986 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 62124345 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.469029 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.224973 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 28329843 45.66% 45.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 16548650 26.67% 72.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5280214 8.51% 80.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3902195 6.29% 87.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2034976 3.28% 90.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 672623 1.08% 91.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 530029 0.85% 92.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 208846 0.34% 92.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4537687 7.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 28387912 45.70% 45.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 16565318 26.66% 72.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 5280655 8.50% 80.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3908699 6.29% 87.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2045216 3.29% 90.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 660602 1.06% 91.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 536847 0.86% 92.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 207955 0.33% 92.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4531141 7.29% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 62045063 # Number of insts commited each cycle
system.cpu.commit.count 91262274 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle
system.cpu.commit.count 91262494 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27322533 # Number of memory references committed
system.cpu.commit.loads 22575828 # Number of loads committed
system.cpu.commit.refs 27322621 # Number of memory references committed
system.cpu.commit.loads 22575872 # Number of loads committed
system.cpu.commit.membars 3888 # Number of memory barriers committed
system.cpu.commit.branches 18722422 # Number of branches committed
system.cpu.commit.branches 18722466 # Number of branches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72533126 # Number of committed integer instructions.
system.cpu.commit.int_insts 72533302 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
system.cpu.commit.bw_lim_events 4537687 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 4531141 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 175581186 # The number of ROB reads
system.cpu.rob.rob_writes 240196081 # The number of ROB writes
system.cpu.rob.rob_reads 175546950 # The number of ROB reads
system.cpu.rob.rob_writes 239939834 # The number of ROB writes
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30708 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 91249665 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249665 # Number of Instructions Simulated
system.cpu.cpi 0.724374 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.724374 # CPI: Total CPI of All Threads
system.cpu.ipc 1.380502 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.380502 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 496839540 # number of integer regfile reads
system.cpu.int_regfile_writes 120902305 # number of integer regfile writes
system.cpu.fp_regfile_reads 158 # number of floating regfile reads
system.cpu.fp_regfile_writes 392 # number of floating regfile writes
system.cpu.misc_regfile_reads 184716876 # number of misc regfile reads
system.cpu.misc_regfile_writes 11506 # number of misc regfile writes
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 91249885 # Number of Instructions Simulated
system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
system.cpu.cpi 0.725054 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.725054 # CPI: Total CPI of All Threads
system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 496902731 # number of integer regfile reads
system.cpu.int_regfile_writes 120936097 # number of integer regfile writes
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
system.cpu.fp_regfile_writes 534 # number of floating regfile writes
system.cpu.misc_regfile_reads 184886725 # number of misc regfile reads
system.cpu.misc_regfile_writes 11594 # number of misc regfile writes
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.tagsinuse 613.066905 # Cycle average of tags in use
system.cpu.icache.total_refs 14729300 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 20514.345404 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 611.587678 # Cycle average of tags in use
system.cpu.icache.total_refs 14743812 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 20420.792244 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 613.066905 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.299349 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 14729300 # number of ReadReq hits
system.cpu.icache.demand_hits 14729300 # number of demand (read+write) hits
system.cpu.icache.overall_hits 14729300 # number of overall hits
system.cpu.icache.ReadReq_misses 921 # number of ReadReq misses
system.cpu.icache.demand_misses 921 # number of demand (read+write) misses
system.cpu.icache.overall_misses 921 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32465000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32465000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32465000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 14730221 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 14730221 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 14730221 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35249.728556 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35249.728556 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35249.728556 # average overall miss latency
system.cpu.icache.occ_blocks::0 611.587678 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.298627 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 14743812 # number of ReadReq hits
system.cpu.icache.demand_hits 14743812 # number of demand (read+write) hits
system.cpu.icache.overall_hits 14743812 # number of overall hits
system.cpu.icache.ReadReq_misses 916 # number of ReadReq misses
system.cpu.icache.demand_misses 916 # number of demand (read+write) misses
system.cpu.icache.overall_misses 916 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 32376000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 32376000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 14744728 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 14744728 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 14744728 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000062 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000062 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000062 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -354,139 +354,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 203 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 203 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 203 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 718 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 718 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 194 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 194 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 24779500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 24779500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 24779500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 24887000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 24887000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 24887000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000049 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000049 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34511.838440 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34511.838440 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943500 # number of replacements
system.cpu.dcache.tagsinuse 3561.430485 # Cycle average of tags in use
system.cpu.dcache.total_refs 28801207 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947596 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.393973 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12279149000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3561.430485 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.869490 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24229442 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4559293 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6724 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5748 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 28788735 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 28788735 # number of overall hits
system.cpu.dcache.ReadReq_misses 990132 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 175688 # number of WriteReq misses
system.cpu.dcache.replacements 943456 # number of replacements
system.cpu.dcache.tagsinuse 3558.808717 # Cycle average of tags in use
system.cpu.dcache.total_refs 28819274 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.414451 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3558.808717 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.868850 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 24247443 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 4559242 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 6797 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 5792 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 28806685 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 28806685 # number of overall hits
system.cpu.dcache.ReadReq_misses 989267 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 175739 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1165820 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1165820 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5482674500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4505328405 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 1165006 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1165006 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5475542500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4498706928 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 124500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 9988002905 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 9988002905 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25219574 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 9974249428 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 9974249428 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 25236710 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 6731 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5748 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 29954555 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 29954555 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.039260 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.037104 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001040 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.038920 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.038920 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5537.316742 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25643.916517 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_accesses 6804 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 5792 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 29971691 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 29971691 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.039200 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.037115 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001029 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.038870 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.038870 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 5534.949109 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 25598.796670 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 8567.362805 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8567.362805 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23285977 # number of cycles access was blocked
system.cpu.dcache.demand_avg_miss_latency 8561.543398 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 8561.543398 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8139 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8123 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2861.036614 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2860.950757 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 942954 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 87074 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 131149 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 942907 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 86240 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 131213 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 218223 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 218223 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 903058 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 44539 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947597 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947597 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 217453 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 217453 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 903027 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 44526 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 947553 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 947553 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2256691000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1081795530 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3338486530 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3338486530 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 2253075000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1081062556 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 3334137556 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 3334137556 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035808 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009406 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031634 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031634 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2498.943589 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24288.725162 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3523.107956 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.025066 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.354894 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3518.681864 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 742 # number of replacements
system.cpu.l2cache.tagsinuse 9256.207068 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1596737 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15558 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 102.631251 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 744 # number of replacements
system.cpu.l2cache.tagsinuse 9229.669539 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1596774 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 391.956879 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8864.250189 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.011962 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.270515 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 901452 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942954 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 31278 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 932730 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 932730 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1045 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 15585 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 15585 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 35800500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 498909000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 534709500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 534709500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 902497 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 942954 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 45818 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948315 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948315 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001158 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.317343 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016434 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016434 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34258.851675 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34312.861073 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34309.239654 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34309.239654 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 392.792284 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 8836.877255 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 901413 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 932680 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 932680 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 14538 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 15595 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 15595 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 36209000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 498763000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 534972000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 534972000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 45805 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 948275 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 948275 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.001171 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.317389 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34304.071818 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -499,24 +499,24 @@ system.cpu.l2cache.writebacks 32 # nu
system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1035 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 15575 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 15575 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 15585 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 32188500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451730000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 483918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 483918500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 484338000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001147 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317343 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016424 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.016424 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31100 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31068.088033 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.208668 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -61,7 +62,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr

8
tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:20:15
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215830000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2350642 # Simulator instruction rate (inst/s)
host_tick_rate 1178195565 # Simulator tick rate (ticks/s)
host_mem_usage 352660 # Number of bytes of host memory used
host_seconds 103.73 # Real time elapsed on the host
host_inst_rate 3705610 # Simulator instruction rate (inst/s)
host_tick_rate 1857336235 # Simulator tick rate (ticks/s)
host_mem_usage 328592 # Number of bytes of host memory used
host_seconds 65.80 # Real time elapsed on the host
sim_insts 243835278 # Number of instructions simulated
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431661 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 18619960 # nu
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451609 # number of times the integer registers were written
system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs

3
tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -164,7 +165,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr

8
tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:15:16
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.362431 # Number of seconds simulated
sim_ticks 362430887000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1087927 # Simulator instruction rate (inst/s)
host_tick_rate 1617068836 # Simulator tick rate (ticks/s)
host_mem_usage 361308 # Number of bytes of host memory used
host_seconds 224.13 # Real time elapsed on the host
host_inst_rate 1940887 # Simulator instruction rate (inst/s)
host_tick_rate 2884887520 # Simulator tick rate (ticks/s)
host_mem_usage 337564 # Number of bytes of host memory used
host_seconds 125.63 # Real time elapsed on the host
sim_insts 243835278 # Number of instructions simulated
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724861774 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 18619960 # nu
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451608 # number of times the integer registers were written
system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs

4
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
View file

@ -500,9 +500,9 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100

8
tests/long/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 11 2011 21:12:14
gem5 started Sep 11 2011 22:42:17
gem5 executing on u200439-lin.austin.arm.com
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 17:44:50
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 277977002000 because target called exit()
Exiting @ tick 274198757500 because target called exit()

814
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.277977 # Number of seconds simulated
sim_ticks 277977002000 # Number of ticks simulated
sim_seconds 0.274199 # Number of seconds simulated
sim_ticks 274198757500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 50801 # Simulator instruction rate (inst/s)
host_tick_rate 24630434 # Simulator tick rate (ticks/s)
host_mem_usage 268512 # Number of bytes of host memory used
host_seconds 11285.92 # Real time elapsed on the host
sim_insts 573340817 # Number of instructions simulated
host_inst_rate 124379 # Simulator instruction rate (inst/s)
host_tick_rate 59483814 # Simulator tick rate (ticks/s)
host_mem_usage 219308 # Number of bytes of host memory used
host_seconds 4609.64 # Real time elapsed on the host
sim_insts 573341162 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,299 +51,299 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 555954005 # number of cpu cycles simulated
system.cpu.numCycles 548397516 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 228168556 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 182073516 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18360369 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 192570670 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 159873716 # Number of BTB hits
system.cpu.BPredUnit.lookups 225101784 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 179007547 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18307036 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 189868979 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 156087931 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 11766939 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2589198 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 157542477 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1002347382 # Number of instructions fetch has processed
system.cpu.fetch.Branches 228168556 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 171640655 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 259558013 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 76911240 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 78784930 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 75608 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 144858558 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4692724 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 552173964 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.153531 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.835452 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 11743928 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2589266 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 154237973 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 996342059 # Number of instructions fetch has processed
system.cpu.fetch.Branches 225101784 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 167831859 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 251951083 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 70115496 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 88916227 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 27190 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 141601056 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4591339 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 544609039 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.120756 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.818747 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 292628171 53.00% 53.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 24182032 4.38% 57.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 41208027 7.46% 64.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 40287755 7.30% 72.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 42593934 7.71% 79.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 15362741 2.78% 82.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 18471004 3.35% 85.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 15875720 2.88% 88.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 61564580 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 292670234 53.74% 53.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 22602609 4.15% 57.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 39324759 7.22% 65.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 38673680 7.10% 72.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 44132407 8.10% 80.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 15219761 2.79% 83.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 18468380 3.39% 86.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 13866800 2.55% 89.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 59650409 10.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 552173964 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.410409 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.802932 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 174643217 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 74003655 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 241825434 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 5575388 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 56126270 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33116303 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 100775 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1131397141 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 219753 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 56126270 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 191113879 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 6444669 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 52172693 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 230777280 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 15539173 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1066388511 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1227 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2971665 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 9137935 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 123 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1187101757 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4711515581 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4711512464 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3117 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672198744 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 514903008 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2758299 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2758344 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48904017 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 194788235 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 120640917 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 16446877 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 13823038 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 932596874 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 4516730 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 763493806 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3302626 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 360793671 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1004885077 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 639153 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 552173964 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.382705 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.650964 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 544609039 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.410472 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.816825 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 173360184 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 84631968 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 232819510 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4407510 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 49389867 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33096702 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 88546 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1070717063 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 220828 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 49389867 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 189439670 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 6246457 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 67211324 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 221002512 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 11319209 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 984442373 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1013 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2966416 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5236155 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 73 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1176369692 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4273292331 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4273289228 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3103 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 672199296 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 504170396 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 6164964 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6164681 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 63358237 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 196378247 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 77986326 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 17967729 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 12612066 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 870602735 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7830625 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 735457773 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1536942 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 302215535 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 751654986 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3952431 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 544609039 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.350433 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.595771 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 245578205 44.47% 44.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 95260536 17.25% 61.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 82729163 14.98% 76.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 61462148 11.13% 87.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 37755177 6.84% 94.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16395168 2.97% 97.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 7099577 1.29% 98.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 4357430 0.79% 99.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1536560 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 241479375 44.34% 44.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 95418106 17.52% 61.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 86231703 15.83% 77.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 59231990 10.88% 88.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 36938301 6.78% 95.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 14710122 2.70% 98.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 6373652 1.17% 99.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 3471755 0.64% 99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 754035 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 552173964 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 544609039 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 144550 1.16% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 6747694 54.11% 55.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5577677 44.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 133367 1.38% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 6658147 68.82% 70.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2883419 29.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 512546383 67.13% 67.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 380050 0.05% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 132 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 170906603 22.38% 89.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 79660635 10.43% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 497367446 67.63% 67.63% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 380524 0.05% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 142 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 170820646 23.23% 90.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 66889012 9.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 763493806 # Type of FU issued
system.cpu.iq.rate 1.373304 # Inst issue rate
system.cpu.iq.fu_busy_cnt 12469921 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016333 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2094933823 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1297974964 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 705382252 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 300 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes
system.cpu.iq.FU_type_0::total 735457773 # Type of FU issued
system.cpu.iq.rate 1.341103 # Inst issue rate
system.cpu.iq.fu_busy_cnt 9674933 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013155 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2026736140 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1180706061 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 693772826 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 320 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 454 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 775963575 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 8509313 # Number of loads that had data forwarded from stores
system.cpu.iq.int_alu_accesses 745132544 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 162 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 8466293 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 68015373 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 52063 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 72908 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 63037135 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 69605317 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 50613 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 61790 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 20382475 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 28343 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 323 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 28472 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 334 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 56126270 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2680601 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 121752 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 946450192 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12430419 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 194788235 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 120640917 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2741935 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 45812 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7404 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 72908 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18589508 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6131708 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 24721216 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 732040071 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 161905826 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 31453735 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 49389867 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2700739 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 121924 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 887765924 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12225511 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 196378247 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 77986326 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6083275 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 46564 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7422 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 61790 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18530018 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5460534 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 23990552 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 711163338 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 161856987 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 24294435 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 9336588 # number of nop insts executed
system.cpu.iew.exec_refs 233639604 # number of memory reference insts executed
system.cpu.iew.exec_branches 147368049 # Number of branches executed
system.cpu.iew.exec_stores 71733778 # Number of stores executed
system.cpu.iew.exec_rate 1.316728 # Inst execution rate
system.cpu.iew.wb_sent 720193208 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 705382268 # cumulative count of insts written-back
system.cpu.iew.wb_producers 398990171 # num instructions producing a value
system.cpu.iew.wb_consumers 706117751 # num instructions consuming a value
system.cpu.iew.exec_nop 9332564 # number of nop insts executed
system.cpu.iew.exec_refs 226770071 # number of memory reference insts executed
system.cpu.iew.exec_branches 147519559 # Number of branches executed
system.cpu.iew.exec_stores 64913084 # Number of stores executed
system.cpu.iew.exec_rate 1.296803 # Inst execution rate
system.cpu.iew.wb_sent 699318417 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 693772842 # cumulative count of insts written-back
system.cpu.iew.wb_producers 395045304 # num instructions producing a value
system.cpu.iew.wb_consumers 663504976 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.268778 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.565048 # average fanout of values written-back
system.cpu.iew.wb_rate 1.265091 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.595392 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 574684701 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 371780538 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3877577 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 20554122 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 496047695 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.158527 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.880172 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 574685046 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 313100037 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3878194 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 20503761 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 495219173 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.160466 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.863525 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 262785164 52.98% 52.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 115198259 23.22% 76.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 44158877 8.90% 85.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 20159823 4.06% 89.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19759049 3.98% 93.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7211981 1.45% 94.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7550461 1.52% 96.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3502296 0.71% 96.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15721785 3.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 259975062 52.50% 52.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 116222276 23.47% 75.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 44533135 8.99% 84.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 21295357 4.30% 89.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19840150 4.01% 93.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7283820 1.47% 94.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7518006 1.52% 96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3788243 0.76% 97.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 14763124 2.98% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 496047695 # Number of insts commited each cycle
system.cpu.commit.count 574684701 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 495219173 # Number of insts commited each cycle
system.cpu.commit.count 574685046 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 184376643 # Number of memory references committed
system.cpu.commit.loads 126772861 # Number of loads committed
system.cpu.commit.refs 184376781 # Number of memory references committed
system.cpu.commit.loads 126772930 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 120192046 # Number of branches committed
system.cpu.commit.branches 120192115 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 473700921 # Number of committed integer instructions.
system.cpu.commit.int_insts 473701197 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15721785 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 14763124 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1426784011 # The number of ROB reads
system.cpu.rob.rob_writes 1949388350 # The number of ROB writes
system.cpu.timesIdled 93530 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3780041 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 573340817 # Number of Instructions Simulated
system.cpu.committedInsts_total 573340817 # Number of Instructions Simulated
system.cpu.cpi 0.969675 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.969675 # CPI: Total CPI of All Threads
system.cpu.ipc 1.031274 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.031274 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3375374322 # number of integer regfile reads
system.cpu.int_regfile_writes 818576050 # number of integer regfile writes
system.cpu.rob.rob_reads 1368233994 # The number of ROB reads
system.cpu.rob.rob_writes 1825140894 # The number of ROB writes
system.cpu.timesIdled 96084 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3788477 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 573341162 # Number of Instructions Simulated
system.cpu.committedInsts_total 573341162 # Number of Instructions Simulated
system.cpu.cpi 0.956494 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.956494 # CPI: Total CPI of All Threads
system.cpu.ipc 1.045485 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.045485 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3291621496 # number of integer regfile reads
system.cpu.int_regfile_writes 815258640 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.misc_regfile_reads 1246383424 # number of misc regfile reads
system.cpu.misc_regfile_writes 4463694 # number of misc regfile writes
system.cpu.icache.replacements 12953 # number of replacements
system.cpu.icache.tagsinuse 1066.011172 # Cycle average of tags in use
system.cpu.icache.total_refs 144842026 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 14796 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9789.269127 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 1231509968 # number of misc regfile reads
system.cpu.misc_regfile_writes 4463832 # number of misc regfile writes
system.cpu.icache.replacements 12844 # number of replacements
system.cpu.icache.tagsinuse 1060.855578 # Cycle average of tags in use
system.cpu.icache.total_refs 141584558 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 14688 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9639.471541 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1066.011172 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.520513 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 144842026 # number of ReadReq hits
system.cpu.icache.demand_hits 144842026 # number of demand (read+write) hits
system.cpu.icache.overall_hits 144842026 # number of overall hits
system.cpu.icache.ReadReq_misses 16532 # number of ReadReq misses
system.cpu.icache.demand_misses 16532 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16532 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 236127500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 236127500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 236127500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 144858558 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 144858558 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 144858558 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 14283.057101 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 14283.057101 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 14283.057101 # average overall miss latency
system.cpu.icache.occ_blocks::0 1060.855578 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.517996 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 141584561 # number of ReadReq hits
system.cpu.icache.demand_hits 141584561 # number of demand (read+write) hits
system.cpu.icache.overall_hits 141584561 # number of overall hits
system.cpu.icache.ReadReq_misses 16495 # number of ReadReq misses
system.cpu.icache.demand_misses 16495 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16495 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 235861500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 235861500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 235861500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 141601056 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 141601056 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 141601056 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000116 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000116 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000116 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 14298.969385 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 14298.969385 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 14298.969385 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -352,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 3 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1595 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1595 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1595 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 14937 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 14937 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 14937 # number of overall MSHR misses
system.cpu.icache.writebacks 1 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1651 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1651 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1651 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 14844 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 14844 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 14844 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 154963500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 154963500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 154963500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 154845500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 154845500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 154845500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000103 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000103 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000103 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10374.472786 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10374.472786 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1212304 # number of replacements
system.cpu.dcache.tagsinuse 4056.655033 # Cycle average of tags in use
system.cpu.dcache.total_refs 204333275 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1216400 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.981976 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5992651000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4056.655033 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.990394 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 146799577 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 52779397 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2522240 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 2231846 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 199578974 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 199578974 # number of overall hits
system.cpu.dcache.ReadReq_misses 1241463 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1459909 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 57 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2701372 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2701372 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14210039000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 24949440994 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 510000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 39159479994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39159479994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 148041040 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.replacements 1212341 # number of replacements
system.cpu.dcache.tagsinuse 4058.230538 # Cycle average of tags in use
system.cpu.dcache.total_refs 204314278 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1216437 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.961249 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5623770000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4058.230538 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.990779 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 146820758 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 52766592 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 2494784 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 2231915 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 199587350 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 199587350 # number of overall hits
system.cpu.dcache.ReadReq_misses 1243424 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1472714 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 59 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2716138 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2716138 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14347379500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 25015184497 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 557000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 39362563997 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 39362563997 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 148064182 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 2522297 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 2231846 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 202280346 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 202280346 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.008386 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.026916 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000023 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.013355 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.013355 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 11446.204196 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 17089.723396 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 8947.368421 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 14496.144920 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 14496.144920 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 2494843 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 2231915 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 202303488 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 202303488 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.008398 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.027152 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000024 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.013426 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.013426 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9440.677966 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 14492.107543 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 14492.107543 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 416000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 502000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 55 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 64 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7563.636364 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7843.750000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1079589 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 365099 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1119740 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 57 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1484839 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1484839 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 876364 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 340169 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1216533 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1216533 # number of overall MSHR misses
system.cpu.dcache.writebacks 1079461 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 367349 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1132203 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 59 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1499552 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1499552 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 876075 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 340511 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1216586 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1216586 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 6322701500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4343796500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 10666498000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 10666498000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 6316165000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 4359865500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 10676030500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 10676030500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005920 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006272 # mshr miss rate for WriteReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005917 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006278 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7214.697888 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12769.524854 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8767.947931 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7209.616757 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 218992 # number of replacements
system.cpu.l2cache.tagsinuse 21041.730576 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1568543 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 239349 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.553372 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 207293372000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7594.160868 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13447.569709 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.231755 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.410387 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 760588 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1079592 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 93 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 232455 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 993043 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 993043 # number of overall hits
system.cpu.l2cache.ReadReq_misses 130191 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 107958 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 238149 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 238149 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 4453286000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 204500 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3697103500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 8150389500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 8150389500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 890779 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1079592 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 129 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 340413 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1231192 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1231192 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.146154 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.279070 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.317138 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.193430 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.193430 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34205.789955 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5680.555556 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34245.757609 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34223.908142 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34223.908142 # average overall miss latency
system.cpu.l2cache.replacements 219133 # number of replacements
system.cpu.l2cache.tagsinuse 21061.116186 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1567440 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 232507 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 992847 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 992847 # number of overall hits
system.cpu.l2cache.ReadReq_misses 130056 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 33 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 238282 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 340733 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1231129 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1231129 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.146065 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -500,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 171216 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 130170 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 107958 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 238128 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 238128 # number of overall MSHR misses
system.cpu.l2cache.writebacks 171253 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 19 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 130037 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 108226 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 4041635000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3347575000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 7389210000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 7389210000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146131 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.279070 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317138 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.193413 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.193413 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31048.897595 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.123530 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.412215 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

2
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864

10
tests/long/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 12:27:58
gem5 started Aug 20 2011 12:28:18
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 17:59:30
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -15,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.100000
Exiting @ tick 104473822000 because target called exit()
Exiting @ tick 104497559500 because target called exit()

718
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.104474 # Number of seconds simulated
sim_ticks 104473822000 # Number of ticks simulated
sim_seconds 0.104498 # Number of seconds simulated
sim_ticks 104497559500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 153431 # Simulator instruction rate (inst/s)
host_tick_rate 45921219 # Simulator tick rate (ticks/s)
host_mem_usage 225932 # Number of bytes of host memory used
host_seconds 2275.07 # Real time elapsed on the host
sim_insts 349066014 # Number of instructions simulated
host_inst_rate 166687 # Simulator instruction rate (inst/s)
host_tick_rate 49899949 # Simulator tick rate (ticks/s)
host_mem_usage 223124 # Number of bytes of host memory used
host_seconds 2094.14 # Real time elapsed on the host
sim_insts 349066034 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,105 +51,105 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 208947645 # number of cpu cycles simulated
system.cpu.numCycles 208995120 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 38329680 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21105904 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3259287 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 27325340 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 21186794 # Number of BTB hits
system.cpu.BPredUnit.lookups 38326507 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 21101495 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 3258977 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 27386254 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 21276883 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 7687582 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 64950 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 43658765 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 338491573 # Number of instructions fetch has processed
system.cpu.fetch.Branches 38329680 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 28874376 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 79000452 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 11006616 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 78476147 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 177 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 41256182 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 909033 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 208834894 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.121215 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.193825 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 7682399 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 61114 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 43645867 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 338408122 # Number of instructions fetch has processed
system.cpu.fetch.Branches 38326507 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 28959282 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 79027162 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 10989913 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 78526305 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 41243030 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 908340 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 208882385 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.119969 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.192320 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 130486470 62.48% 62.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9432998 4.52% 67.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6020581 2.88% 69.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6715952 3.22% 73.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5392715 2.58% 75.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4860169 2.33% 78.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3823300 1.83% 79.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4271417 2.05% 81.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 37831292 18.12% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 130507129 62.48% 62.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 9423807 4.51% 66.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 6028759 2.89% 69.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 6771553 3.24% 73.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 5439017 2.60% 75.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4859666 2.33% 78.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 3802857 1.82% 79.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4240079 2.03% 81.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 37809518 18.10% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 208834894 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.183442 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.619983 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 51226737 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 73595547 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 72551850 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3832247 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 7628513 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7466092 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 71093 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 431841645 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 197934 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 7628513 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 58855206 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1197679 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 57579508 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 68948533 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14625455 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 416807689 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 21628 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 8007310 # Number of times rename has blocked due to LSQ full
system.cpu.fetch.rateDist::total 208882385 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.183385 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.619215 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 51208963 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 73647751 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 72596931 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3816657 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 7612083 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 7463930 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 71162 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 431701457 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 197547 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 7612083 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 58859623 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1188483 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 57604104 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 68958235 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14659857 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 416634975 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 21102 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 8024802 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 88 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 455449785 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2447349864 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1352895692 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1094454172 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384568567 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 70881213 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3981353 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4038094 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48179191 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 108793088 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 93182345 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3369455 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2301817 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 394396503 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3860146 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 379227630 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1821640 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 46525332 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 143742588 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 304700 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 208834894 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.815921 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.996738 # Number of insts issued each cycle
system.cpu.rename.RenamedOperands 455431964 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2446622850 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1351809132 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1094813718 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384568599 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 70863365 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 3987641 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 4044473 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48252141 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 108792162 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 93099672 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3342545 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2273908 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 394239255 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 3865155 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 379120981 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1801347 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 46369193 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 143590674 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 309514 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 208882385 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.814997 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.995935 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 82039971 39.28% 39.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 34743122 16.64% 55.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 24446026 11.71% 67.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18532815 8.87% 76.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21777610 10.43% 86.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15334879 7.34% 94.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8388297 4.02% 98.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2697998 1.29% 99.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 874176 0.42% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 82049002 39.28% 39.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 34801326 16.66% 55.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 24478546 11.72% 67.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 18529016 8.87% 76.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 21712805 10.39% 86.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 15357191 7.35% 94.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8402907 4.02% 98.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 2691838 1.29% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 859754 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 208834894 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 208882385 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2499 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2250 0.01% 0.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5043 0.03% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
@ -169,181 +169,181 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # at
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 10462 0.06% 0.10% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 10815 0.06% 0.10% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 2799 0.02% 0.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 391 0.00% 0.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 2509 0.01% 0.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 378 0.00% 0.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 64669 0.37% 0.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 64370 0.37% 0.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 798 0.00% 0.50% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 177194 1.02% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 177500 1.02% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9656371 55.60% 57.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 7448588 42.88% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9658261 55.66% 57.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 7430721 42.82% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 129667439 34.19% 34.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147217 0.57% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 12 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6745597 1.78% 36.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8690395 2.29% 38.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3497824 0.92% 39.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1584668 0.42% 40.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21149446 5.58% 45.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7187375 1.90% 47.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7146329 1.88% 49.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 103745248 27.36% 76.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 87490792 23.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 129606192 34.19% 34.19% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2147281 0.57% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 13 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6746387 1.78% 36.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8673518 2.29% 38.82% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3499070 0.92% 39.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1584810 0.42% 40.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 21149805 5.58% 45.74% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7187648 1.90% 47.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147289 1.89% 49.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 103746274 27.36% 76.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 87457408 23.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 379227630 # Type of FU issued
system.cpu.iq.rate 1.814941 # Inst issue rate
system.cpu.iq.fu_busy_cnt 17368817 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.045801 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 735557028 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 310975021 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 251585005 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 250923583 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 133814979 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 118291748 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 267725333 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 128871114 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 7296411 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 379120981 # Type of FU issued
system.cpu.iq.rate 1.814018 # Inst issue rate
system.cpu.iq.fu_busy_cnt 17352648 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.045771 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 735350759 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 310614656 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 251531674 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 250927583 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 133866908 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 118270115 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 267600383 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 128873246 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 7282081 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 14144091 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 112652 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 8375 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10806518 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 14143162 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 112354 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 8279 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 10723841 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 269 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.rescheduledLoads 272 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 7628513 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 19213 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 427 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 398303949 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2640938 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 108793088 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 93182345 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3848920 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 8375 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3190408 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 311351 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3501759 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 373094213 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 102121029 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6133417 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 7612083 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 19341 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 437 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 398151655 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2633597 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 108792162 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 93099672 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3853935 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 205 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 8279 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3193235 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 309338 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3502573 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 373031388 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 102121270 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6089593 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 47300 # number of nop insts executed
system.cpu.iew.exec_refs 188086624 # number of memory reference insts executed
system.cpu.iew.exec_branches 32219112 # Number of branches executed
system.cpu.iew.exec_stores 85965595 # Number of stores executed
system.cpu.iew.exec_rate 1.785587 # Inst execution rate
system.cpu.iew.wb_sent 370884944 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 369876753 # cumulative count of insts written-back
system.cpu.iew.wb_producers 175641589 # num instructions producing a value
system.cpu.iew.wb_consumers 345778200 # num instructions consuming a value
system.cpu.iew.exec_nop 47245 # number of nop insts executed
system.cpu.iew.exec_refs 188074720 # number of memory reference insts executed
system.cpu.iew.exec_branches 32215232 # Number of branches executed
system.cpu.iew.exec_stores 85953450 # Number of stores executed
system.cpu.iew.exec_rate 1.784881 # Inst execution rate
system.cpu.iew.wb_sent 370805637 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 369801789 # cumulative count of insts written-back
system.cpu.iew.wb_producers 175613931 # num instructions producing a value
system.cpu.iew.wb_consumers 345608979 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.770189 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.507960 # average fanout of values written-back
system.cpu.iew.wb_rate 1.769428 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.508129 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 349066626 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 49232556 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3230297 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 201206382 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.734869 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.321510 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 49085191 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3229927 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 201270303 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.734318 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.320939 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 89873367 44.67% 44.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 39509516 19.64% 64.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 17955811 8.92% 73.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13150988 6.54% 79.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 14566158 7.24% 87.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7624448 3.79% 90.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3491536 1.74% 92.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3420028 1.70% 94.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11614530 5.77% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 89873146 44.65% 44.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 39586205 19.67% 64.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 17962686 8.92% 73.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13145817 6.53% 79.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 14573998 7.24% 87.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7584463 3.77% 90.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 3507612 1.74% 92.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 3437369 1.71% 94.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11599007 5.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 201206382 # Number of insts commited each cycle
system.cpu.commit.count 349066626 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 201270303 # Number of insts commited each cycle
system.cpu.commit.count 349066646 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 177024823 # Number of memory references committed
system.cpu.commit.loads 94648996 # Number of loads committed
system.cpu.commit.refs 177024831 # Number of memory references committed
system.cpu.commit.loads 94649000 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.branches 30521875 # Number of branches committed
system.cpu.commit.branches 30521879 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279585913 # Number of committed integer instructions.
system.cpu.commit.int_insts 279585929 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.bw_lim_events 11614530 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 11599007 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 587888511 # The number of ROB reads
system.cpu.rob.rob_writes 804230779 # The number of ROB writes
system.cpu.timesIdled 2579 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 112751 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 349066014 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066014 # Number of Instructions Simulated
system.cpu.cpi 0.598591 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.598591 # CPI: Total CPI of All Threads
system.cpu.ipc 1.670591 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.670591 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1782159085 # number of integer regfile reads
system.cpu.int_regfile_writes 235889793 # number of integer regfile writes
system.cpu.fp_regfile_reads 188830050 # number of floating regfile reads
system.cpu.fp_regfile_writes 133876834 # number of floating regfile writes
system.cpu.misc_regfile_reads 1003607247 # number of misc regfile reads
system.cpu.misc_regfile_writes 34422185 # number of misc regfile writes
system.cpu.icache.replacements 14102 # number of replacements
system.cpu.icache.tagsinuse 1840.385487 # Cycle average of tags in use
system.cpu.icache.total_refs 41239547 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15979 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2580.859065 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 587820610 # The number of ROB reads
system.cpu.rob.rob_writes 803918901 # The number of ROB writes
system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 112735 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 349066034 # Number of Instructions Simulated
system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
system.cpu.cpi 0.598727 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.598727 # CPI: Total CPI of All Threads
system.cpu.ipc 1.670211 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.670211 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1781871579 # number of integer regfile reads
system.cpu.int_regfile_writes 235815438 # number of integer regfile writes
system.cpu.fp_regfile_reads 188771754 # number of floating regfile reads
system.cpu.fp_regfile_writes 133861667 # number of floating regfile writes
system.cpu.misc_regfile_reads 1003473737 # number of misc regfile reads
system.cpu.misc_regfile_writes 34422193 # number of misc regfile writes
system.cpu.icache.replacements 14107 # number of replacements
system.cpu.icache.tagsinuse 1842.677380 # Cycle average of tags in use
system.cpu.icache.total_refs 41226387 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15987 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2578.744417 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1840.385487 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.898626 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 41239547 # number of ReadReq hits
system.cpu.icache.demand_hits 41239547 # number of demand (read+write) hits
system.cpu.icache.overall_hits 41239547 # number of overall hits
system.cpu.icache.ReadReq_misses 16635 # number of ReadReq misses
system.cpu.icache.demand_misses 16635 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16635 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 200891500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 200891500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 200891500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 41256182 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 41256182 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 41256182 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000403 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000403 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000403 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12076.435227 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12076.435227 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12076.435227 # average overall miss latency
system.cpu.icache.occ_blocks::0 1842.677380 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.899745 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 41226387 # number of ReadReq hits
system.cpu.icache.demand_hits 41226387 # number of demand (read+write) hits
system.cpu.icache.overall_hits 41226387 # number of overall hits
system.cpu.icache.ReadReq_misses 16643 # number of ReadReq misses
system.cpu.icache.demand_misses 16643 # number of demand (read+write) misses
system.cpu.icache.overall_misses 16643 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 201090500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 201090500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 201090500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 41243030 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 41243030 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 41243030 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12082.587274 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12082.587274 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12082.587274 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,142 +353,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 640 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 640 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 640 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 15995 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 15995 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 15995 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 16006 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 16006 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 16006 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 135868500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 135868500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 135868500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 136032000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 136032000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 136032000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8494.435761 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8494.435761 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8498.812945 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8498.812945 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1418 # number of replacements
system.cpu.dcache.tagsinuse 3101.734429 # Cycle average of tags in use
system.cpu.dcache.total_refs 176600871 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4608 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38324.841797 # Average number of references to valid blocks.
system.cpu.dcache.replacements 1408 # number of replacements
system.cpu.dcache.tagsinuse 3101.194672 # Cycle average of tags in use
system.cpu.dcache.total_refs 176614084 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4596 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 38427.781549 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3101.734429 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.757259 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 94544101 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82033265 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 12379 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11110 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 176577366 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 176577366 # number of overall hits
system.cpu.dcache.ReadReq_misses 3426 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 19429 # number of WriteReq misses
system.cpu.dcache.occ_blocks::0 3101.194672 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.757128 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 94558380 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82033210 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 11361 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11114 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 176591590 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 176591590 # number of overall hits
system.cpu.dcache.ReadReq_misses 3380 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 19484 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 22855 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 22855 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 112688000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 648331000 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 22864 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 22864 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 111762500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 649531500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 761019000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 761019000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 94547527 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 761294000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 761294000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 94561760 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 12381 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11110 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 176600221 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 176600221 # number of overall (read+write) accesses
system.cpu.dcache.LoadLockedReq_accesses 11363 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11114 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 176614454 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 176614454 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000162 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 32892.002335 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33369.241855 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 33065.828402 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33336.660850 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 33297.702910 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33297.702910 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency 33296.623513 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33296.623513 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 307500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1035 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1659 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16572 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 1030 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 16619 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 18231 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 18231 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2857 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4624 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4624 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 18249 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 18249 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1750 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2865 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4615 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4615 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 53837000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 101449500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 155286500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 155286500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 53437000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 101725000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 155162000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 155162000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30468.024901 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35509.100455 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33582.720588 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30535.428571 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35506.108202 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33621.235103 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 59 # number of replacements
system.cpu.l2cache.tagsinuse 3910.433469 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13338 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5362 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.487505 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 57 # number of replacements
system.cpu.l2cache.tagsinuse 3897.011564 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13334 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 5354 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.490474 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3528.791205 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 381.642264 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.107690 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011647 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13254 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1035 # number of Writeback hits
system.cpu.l2cache.occ_blocks::0 3518.810301 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 378.201262 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.107386 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.011542 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13251 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1030 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 19 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 13273 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 13273 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4491 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 2823 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7314 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7314 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 154072000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 97347500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 251419500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 251419500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 17745 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1035 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 2842 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 20587 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 20587 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.253085 # miss rate for ReadReq accesses
system.cpu.l2cache.demand_hits 13270 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 13270 # number of overall hits
system.cpu.l2cache.ReadReq_misses 4485 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 2828 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 7313 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 7313 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 153892500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 97502000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 251394500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 251394500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 17736 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1030 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 2847 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 20583 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 20583 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.252876 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.993315 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.355273 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.355273 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34306.835894 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34483.705278 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34375.102543 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34375.102543 # average overall miss latency
system.cpu.l2cache.ReadExReq_miss_rate 0.993326 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.355293 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.355293 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34312.709030 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.369165 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34376.384521 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34376.384521 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -498,31 +498,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 56 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4435 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 2823 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 4430 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 2828 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 7258 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 7258 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 138176000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 497000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88317500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 226493500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 226493500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 138008000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 589000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 88479500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 226487500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 226487500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249930 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249774 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.352553 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.352553 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.806088 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31062.500000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31284.980517 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.048498 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993326 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.352621 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.352621 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.047404 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31286.951909 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.221824 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

2
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864

8
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 11 2011 21:12:14
gem5 started Sep 11 2011 21:52:21
gem5 executing on u200439-lin.austin.arm.com
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 18:31:45
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 708531477500 because target called exit()
Exiting @ tick 708403313500 because target called exit()

714
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.708531 # Number of seconds simulated
sim_ticks 708531477500 # Number of ticks simulated
sim_seconds 0.708403 # Number of seconds simulated
sim_ticks 708403313500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 73177 # Simulator instruction rate (inst/s)
host_tick_rate 27500789 # Simulator tick rate (ticks/s)
host_mem_usage 269872 # Number of bytes of host memory used
host_seconds 25764.04 # Real time elapsed on the host
sim_insts 1885333781 # Number of instructions simulated
host_inst_rate 129621 # Simulator instruction rate (inst/s)
host_tick_rate 48704258 # Simulator tick rate (ticks/s)
host_mem_usage 220728 # Number of bytes of host memory used
host_seconds 14545.00 # Real time elapsed on the host
sim_insts 1885333786 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,107 +51,107 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1417062956 # number of cpu cycles simulated
system.cpu.numCycles 1416806628 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 503197532 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 388248962 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 32912455 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 402367124 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 282669140 # Number of BTB hits
system.cpu.BPredUnit.lookups 503033036 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 388160087 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 32894916 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 402481986 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 281923865 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 59794264 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2845178 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 410598466 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2543215501 # Number of instructions fetch has processed
system.cpu.fetch.Branches 503197532 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 342463404 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 683221197 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 205184289 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 105176674 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2131 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 34940 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 384286264 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 12168665 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1365728364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.589436 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.160278 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 59796610 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 2840141 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 410550003 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2542460473 # Number of instructions fetch has processed
system.cpu.fetch.Branches 503033036 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 341720475 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 682921340 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 205013758 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 105428035 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2115 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 34704 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 384233965 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 12151873 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1365478165 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.588855 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.160415 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 682546834 49.98% 49.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48268776 3.53% 53.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 108820649 7.97% 61.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 62416445 4.57% 66.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 89329433 6.54% 72.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 54222188 3.97% 76.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 35559819 2.60% 79.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 34994936 2.56% 81.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 249569284 18.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 682595631 49.99% 49.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 48342952 3.54% 53.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 108702790 7.96% 61.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 62379051 4.57% 66.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 89292584 6.54% 72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 54148565 3.97% 76.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 35470304 2.60% 79.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 34965610 2.56% 81.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 249580678 18.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1365728364 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.355099 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.794709 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 455451885 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 84966420 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 647527818 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 11100617 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 166681624 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 68771353 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13534 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3425616416 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 23343 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 166681624 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 496974681 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 29107016 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3577336 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 615567899 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 53819808 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3299332882 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 85 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4545741 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42264080 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3261811960 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 15630618087 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 14995522132 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 635095955 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993153591 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1268658364 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 292165 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 287873 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 155635348 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1045682058 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 527865899 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 35886161 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 45188431 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 3078949788 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 286075 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2620068122 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 18730048 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1193263945 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2902703474 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 76157 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1365728364 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.918440 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.900398 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 1365478165 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.355047 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.794501 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 455361727 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 85217138 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 647145530 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 11223736 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 166530034 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 68649997 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12124 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3424361675 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 24057 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 166530034 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 496888956 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 29110139 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3718079 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 615295356 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 53935601 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 3298153337 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4569845 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 42334817 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 3261061532 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 15624755618 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 14989571898 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 635183720 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 1267907933 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 310582 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 306325 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 155884977 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 1045137132 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 527476218 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 35886570 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 45267364 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 3077754179 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 303954 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2619291842 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 18689867 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 1192085861 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2899457281 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 92624 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1365478165 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.918223 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.900205 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 480776818 35.20% 35.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 182697295 13.38% 48.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 216773103 15.87% 64.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 179469890 13.14% 77.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 151098316 11.06% 88.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 89760948 6.57% 95.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 48715298 3.57% 98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11568409 0.85% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4868287 0.36% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 480779837 35.21% 35.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 182587607 13.37% 48.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 216609244 15.86% 64.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 179766275 13.17% 77.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 150868799 11.05% 88.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 89721779 6.57% 95.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 48758870 3.57% 98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11536421 0.84% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 4849333 0.36% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1365728364 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1365478165 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2047633 2.26% 2.26% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23928 0.03% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2044403 2.26% 2.26% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 23929 0.03% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available
@ -179,172 +179,172 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 55695213 61.39% 63.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 32952568 36.32% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 55649007 61.42% 63.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 32885475 36.30% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1201100528 45.84% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11234357 0.43% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 6823 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876481 0.26% 46.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5505298 0.21% 46.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1200920026 45.85% 45.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11234109 0.43% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876476 0.26% 46.59% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5505406 0.21% 46.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 24361440 0.93% 47.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 24362118 0.93% 47.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 896104682 34.20% 81.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 473503224 18.07% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 895924024 34.20% 81.94% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 473094394 18.06% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2620068122 # Type of FU issued
system.cpu.iq.rate 1.848943 # Inst issue rate
system.cpu.iq.fu_busy_cnt 90719342 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.034625 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6586805397 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 4173231874 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2409969161 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 128508601 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 99321062 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 57077308 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2645158963 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 65628501 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 72009285 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2619291842 # Type of FU issued
system.cpu.iq.rate 1.848729 # Inst issue rate
system.cpu.iq.fu_busy_cnt 90602814 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.034591 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6584849993 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 4170838685 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2409550549 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 128504537 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 99358414 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 57073276 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2644267181 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 65627475 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 71974387 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 414293189 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 264533 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1389891 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 250868916 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 413748263 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 264274 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1389738 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 250479234 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 87 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 88 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 166681624 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16374995 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1474320 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3079304358 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12740517 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1045682058 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 527865899 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 274568 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1470984 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 216 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1389891 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 34543873 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8891706 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 43435579 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2534937994 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 842579419 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 85130128 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 166530034 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 16377218 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1473925 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 3078126585 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 12745051 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 1045137132 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 527476218 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 292477 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1470662 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 212 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1389738 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 34580674 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 8873578 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 43454252 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2534450261 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 842463670 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 84841581 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 68495 # number of nop insts executed
system.cpu.iew.exec_refs 1294824342 # number of memory reference insts executed
system.cpu.iew.exec_branches 344662618 # Number of branches executed
system.cpu.iew.exec_stores 452244923 # Number of stores executed
system.cpu.iew.exec_rate 1.788868 # Inst execution rate
system.cpu.iew.wb_sent 2496106713 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2467046469 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1448587293 # num instructions producing a value
system.cpu.iew.wb_consumers 2708320532 # num instructions consuming a value
system.cpu.iew.exec_nop 68452 # number of nop insts executed
system.cpu.iew.exec_refs 1294415982 # number of memory reference insts executed
system.cpu.iew.exec_branches 344601931 # Number of branches executed
system.cpu.iew.exec_stores 451952312 # Number of stores executed
system.cpu.iew.exec_rate 1.788847 # Inst execution rate
system.cpu.iew.wb_sent 2495608341 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2466623825 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1448525550 # num instructions producing a value
system.cpu.iew.wb_consumers 2707902616 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.740958 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534866 # average fanout of values written-back
system.cpu.iew.wb_rate 1.740974 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534925 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1885344797 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1193920948 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 209918 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38436982 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1199046742 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.572370 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.256600 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1192782047 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38420798 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1198948133 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.572499 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.256451 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 532251438 44.39% 44.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 299124354 24.95% 69.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 106727923 8.90% 78.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 77554525 6.47% 84.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 53347084 4.45% 89.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23351353 1.95% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 17117984 1.43% 92.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9328631 0.78% 93.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 80243450 6.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 532143962 44.38% 44.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 299077946 24.95% 69.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 106761313 8.90% 78.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 77538501 6.47% 84.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 53400435 4.45% 89.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 23357302 1.95% 91.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 17130441 1.43% 92.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 9348033 0.78% 93.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 80190200 6.69% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1199046742 # Number of insts commited each cycle
system.cpu.commit.count 1885344797 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 1198948133 # Number of insts commited each cycle
system.cpu.commit.count 1885344802 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908385851 # Number of memory references committed
system.cpu.commit.loads 631388868 # Number of loads committed
system.cpu.commit.refs 908385853 # Number of memory references committed
system.cpu.commit.loads 631388869 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 291350231 # Number of branches committed
system.cpu.commit.branches 291350232 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653705619 # Number of committed integer instructions.
system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 80243450 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 80190200 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 4198050692 # The number of ROB reads
system.cpu.rob.rob_writes 6325233568 # The number of ROB writes
system.cpu.timesIdled 1340861 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51334592 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1885333781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1885333781 # Number of Instructions Simulated
system.cpu.cpi 0.751624 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.751624 # CPI: Total CPI of All Threads
system.cpu.ipc 1.330452 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.330452 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12569578143 # number of integer regfile reads
system.cpu.int_regfile_writes 2360113760 # number of integer regfile writes
system.cpu.fp_regfile_reads 68800138 # number of floating regfile reads
system.cpu.fp_regfile_writes 50190994 # number of floating regfile writes
system.cpu.misc_regfile_reads 3981621400 # number of misc regfile reads
system.cpu.misc_regfile_writes 13776274 # number of misc regfile writes
system.cpu.icache.replacements 27318 # number of replacements
system.cpu.icache.tagsinuse 1634.845440 # Cycle average of tags in use
system.cpu.icache.total_refs 384252011 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 28994 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13252.811306 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 4196866437 # The number of ROB reads
system.cpu.rob.rob_writes 6322804382 # The number of ROB writes
system.cpu.timesIdled 1340913 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51328463 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
system.cpu.cpi 0.751488 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.751488 # CPI: Total CPI of All Threads
system.cpu.ipc 1.330692 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.330692 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12567203807 # number of integer regfile reads
system.cpu.int_regfile_writes 2360160094 # number of integer regfile writes
system.cpu.fp_regfile_reads 68800597 # number of floating regfile reads
system.cpu.fp_regfile_writes 50187558 # number of floating regfile writes
system.cpu.misc_regfile_reads 3980455481 # number of misc regfile reads
system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes
system.cpu.icache.replacements 27305 # number of replacements
system.cpu.icache.tagsinuse 1638.856970 # Cycle average of tags in use
system.cpu.icache.total_refs 384199729 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 28984 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13255.579941 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1634.845440 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.798264 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 384252124 # number of ReadReq hits
system.cpu.icache.demand_hits 384252124 # number of demand (read+write) hits
system.cpu.icache.overall_hits 384252124 # number of overall hits
system.cpu.icache.ReadReq_misses 34140 # number of ReadReq misses
system.cpu.icache.demand_misses 34140 # number of demand (read+write) misses
system.cpu.icache.overall_misses 34140 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 301222000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 301222000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 301222000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 384286264 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 384286264 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 384286264 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 1638.856970 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.800223 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 384199814 # number of ReadReq hits
system.cpu.icache.demand_hits 384199814 # number of demand (read+write) hits
system.cpu.icache.overall_hits 384199814 # number of overall hits
system.cpu.icache.ReadReq_misses 34151 # number of ReadReq misses
system.cpu.icache.demand_misses 34151 # number of demand (read+write) misses
system.cpu.icache.overall_misses 34151 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 301141000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 301141000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 301141000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 384233965 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 384233965 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 384233965 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 8823.140012 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 8823.140012 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 8823.140012 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 8817.926269 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 8817.926269 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 8817.926269 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -354,143 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 774 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 774 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 774 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 33366 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 33366 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 33366 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 772 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 772 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 772 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 33379 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 33379 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 33379 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 180870500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 180870500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 180870500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 180850500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 180850500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 180850500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5420.802613 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5420.802613 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 5418.092214 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 5418.092214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1531930 # number of replacements
system.cpu.dcache.tagsinuse 4094.787279 # Cycle average of tags in use
system.cpu.dcache.total_refs 1029517706 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1536026 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 670.247578 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306646000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.787279 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999704 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 753359421 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 276118539 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 14346 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11671 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 1029477960 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 1029477960 # number of overall hits
system.cpu.dcache.ReadReq_misses 1938279 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 817139 # number of WriteReq misses
system.cpu.dcache.replacements 1531788 # number of replacements
system.cpu.dcache.tagsinuse 4094.791932 # Cycle average of tags in use
system.cpu.dcache.total_refs 1029449306 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1535884 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 670.265011 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 305577000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.791932 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 753290045 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 276118528 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 15313 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 11672 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 1029408573 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 1029408573 # number of overall hits
system.cpu.dcache.ReadReq_misses 1938158 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 817150 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 2755418 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2755418 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 69353392500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28486542000 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 2755308 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2755308 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 69348240500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 28488261000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 97839934500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 97839934500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 755297700 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 97836501500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 97836501500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 755228203 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 14349 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11671 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 1032233378 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 1032233378 # number of overall (read+write) accesses
system.cpu.dcache.LoadLockedReq_accesses 15316 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 11672 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 1032163881 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 1032163881 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.002566 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.002951 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000209 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.000196 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.002669 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.002669 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 35780.913119 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 34861.317352 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency 35780.488742 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 34862.951722 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 35508.200389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35508.200389 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency 35508.372022 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35508.372022 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked
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system.cpu.dcache.writebacks 106827 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits 474971 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 1463326 # number of ReadReq MSHR misses
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system.cpu.dcache.overall_mshr_misses 1540399 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 1215028 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1215028 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1463187 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 77093 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 1540280 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 1540280 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 50026128000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2483951500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52510079500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52510079500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 50020048000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2484862000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 52504910000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 52504910000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001937 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000278 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001492 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001492 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34186.591368 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32228.556044 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34088.622169 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34185.683716 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32232.005500 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34087.899603 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480043 # number of replacements
system.cpu.l2cache.tagsinuse 31970.970884 # Cycle average of tags in use
system.cpu.l2cache.total_refs 85321 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512763 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.056401 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 1480006 # number of replacements
system.cpu.l2cache.tagsinuse 31970.917218 # Cycle average of tags in use
system.cpu.l2cache.total_refs 84924 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 1512726 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.056140 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 29004.040754 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2966.930131 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.885133 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.090544 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 76995 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 106827 # number of Writeback hits
system.cpu.l2cache.occ_blocks::0 29008.328912 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 2962.588306 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.090411 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 76788 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 106544 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 83615 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 83615 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1415326 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4368 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1481407 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1481407 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48560731500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2252343000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50813074500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50813074500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1492321 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 106827 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 4372 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 72701 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1565022 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1565022 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.948406 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.999085 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.908942 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.946573 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.946573 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34310.633381 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34084.578018 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34300.549748 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34300.549748 # average overall miss latency
system.cpu.l2cache.ReadExReq_hits 6616 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits 83404 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1415384 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 4391 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 1481466 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 1481466 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 48555371000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2252634000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 50808005000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 50808005000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1492172 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 106544 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 4395 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 72698 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 1564870 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 1564870 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.948539 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.999090 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.908993 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.946702 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.946702 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34305.440078 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.465845 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34295.761766 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34295.761766 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 25 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 25 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1415301 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4368 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1481382 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1481382 # number of overall MSHR misses
system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 28 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1415356 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 4391 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 1481438 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 1481438 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 43971676000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 135408000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048571000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 46020247000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 46020247000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 43973863500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 136121000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 46022461000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 46022461000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948389 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999085 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908942 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.946557 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.946557 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31068.780422 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948521 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999090 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908993 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.946684 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.946684 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118653 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.907977 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.752790 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

2
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864

10
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,13 +1,11 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 12:27:58
gem5 started Aug 20 2011 12:28:18
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 18:34:35
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 31207726500 because target called exit()
Exiting @ tick 31183407000 because target called exit()

808
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.031208 # Number of seconds simulated
sim_ticks 31207726500 # Number of ticks simulated
sim_seconds 0.031183 # Number of seconds simulated
sim_ticks 31183407000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 157603 # Simulator instruction rate (inst/s)
host_tick_rate 48874778 # Simulator tick rate (ticks/s)
host_mem_usage 225884 # Number of bytes of host memory used
host_seconds 638.52 # Real time elapsed on the host
sim_insts 100633520 # Number of instructions simulated
host_inst_rate 167832 # Simulator instruction rate (inst/s)
host_tick_rate 52006067 # Simulator tick rate (ticks/s)
host_mem_usage 223216 # Number of bytes of host memory used
host_seconds 599.61 # Real time elapsed on the host
sim_insts 100634165 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@ -51,300 +51,300 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 62415454 # number of cpu cycles simulated
system.cpu.numCycles 62366815 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 17712573 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11586024 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 828480 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 15104552 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9800008 # Number of BTB hits
system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 1894610 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 179140 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 13000723 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 88894307 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17712573 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11694618 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 23068870 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2942261 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 22994151 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1125 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12237155 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 232722 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 61101347 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.028542 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.080485 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed
system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 38048418 62.27% 62.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2437383 3.99% 66.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2590379 4.24% 70.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2495519 4.08% 74.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1726071 2.82% 77.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1712649 2.80% 80.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1014415 1.66% 81.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1324144 2.17% 84.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9752369 15.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 61101347 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.283785 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.424236 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14911699 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 21729904 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21442913 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1077075 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1939756 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3477546 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 120762342 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 332405 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1939756 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16842041 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2003570 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15407287 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20561842 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4346851 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 117493872 # Number of instructions processed by rename
system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 3565 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3003461 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 318 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 119392349 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 540581981 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 540487699 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 94282 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99143301 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 20249043 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 768563 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 768716 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12082768 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29799998 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22399772 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2425661 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3419073 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 112105098 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 764637 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107812126 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 316132 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 12020521 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 30346065 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 63680 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 61101347 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.764480 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.904021 # Number of insts issued each cycle
system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 22159484 36.27% 36.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11621982 19.02% 55.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8561362 14.01% 69.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7410232 12.13% 81.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4801172 7.86% 89.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3527397 5.77% 95.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1679086 2.75% 97.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 804521 1.32% 99.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 536111 0.88% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 61101347 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88099 3.31% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1498283 56.35% 59.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1072737 40.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57136904 53.00% 53.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 87447 0.08% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 4 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.08% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 29022906 26.92% 80.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21564833 20.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 107812126 # Type of FU issued
system.cpu.iq.rate 1.727331 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2659119 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024664 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 279700662 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 124905792 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105547410 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 188 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 166 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 110471148 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1884692 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued
system.cpu.iq.rate 1.725547 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2491561 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3411 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 16339 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1842707 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 62 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1939756 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 952120 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 28627 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 112946418 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 627319 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29799998 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22399772 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 747490 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1210 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1207 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 16339 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 688631 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 200572 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 889203 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 106427513 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28649084 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1384613 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 76683 # number of nop insts executed
system.cpu.iew.exec_refs 49896710 # number of memory reference insts executed
system.cpu.iew.exec_branches 14628801 # Number of branches executed
system.cpu.iew.exec_stores 21247626 # Number of stores executed
system.cpu.iew.exec_rate 1.705147 # Inst execution rate
system.cpu.iew.wb_sent 105874797 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105547479 # cumulative count of insts written-back
system.cpu.iew.wb_producers 52578934 # num instructions producing a value
system.cpu.iew.wb_consumers 101387160 # num instructions consuming a value
system.cpu.iew.exec_nop 76455 # number of nop insts executed
system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed
system.cpu.iew.exec_branches 14601408 # Number of branches executed
system.cpu.iew.exec_stores 21231609 # Number of stores executed
system.cpu.iew.exec_rate 1.704020 # Inst execution rate
system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back
system.cpu.iew.wb_producers 52507879 # num instructions producing a value
system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.691047 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.518596 # average fanout of values written-back
system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 100639072 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 12225024 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 700957 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 794036 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 59161592 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.701088 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.430633 # Number of insts commited each cycle
system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 26262806 44.39% 44.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14615219 24.70% 69.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4224786 7.14% 76.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3635680 6.15% 82.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2285256 3.86% 86.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1889118 3.19% 89.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 706435 1.19% 90.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 496319 0.84% 91.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5045973 8.53% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 59161592 # Number of insts commited each cycle
system.cpu.commit.count 100639072 # Number of instructions committed
system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle
system.cpu.commit.count 100639717 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47865501 # Number of memory references committed
system.cpu.commit.loads 27308436 # Number of loads committed
system.cpu.commit.refs 47865759 # Number of memory references committed
system.cpu.commit.loads 27308565 # Number of loads committed
system.cpu.commit.membars 15920 # Number of memory barriers committed
system.cpu.commit.branches 13669955 # Number of branches committed
system.cpu.commit.branches 13670084 # Number of branches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91478095 # Number of committed integer instructions.
system.cpu.commit.int_insts 91478611 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5045973 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 166954416 # The number of ROB reads
system.cpu.rob.rob_writes 227673782 # The number of ROB writes
system.cpu.timesIdled 61616 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1314107 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 100633520 # Number of Instructions Simulated
system.cpu.committedInsts_total 100633520 # Number of Instructions Simulated
system.cpu.cpi 0.620225 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.620225 # CPI: Total CPI of All Threads
system.cpu.ipc 1.612317 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.612317 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 512325342 # number of integer regfile reads
system.cpu.int_regfile_writes 104042616 # number of integer regfile writes
system.cpu.fp_regfile_reads 124 # number of floating regfile reads
system.cpu.fp_regfile_writes 92 # number of floating regfile writes
system.cpu.misc_regfile_reads 146636710 # number of misc regfile reads
system.cpu.misc_regfile_writes 34494 # number of misc regfile writes
system.cpu.icache.replacements 26059 # number of replacements
system.cpu.icache.tagsinuse 1807.414724 # Cycle average of tags in use
system.cpu.icache.total_refs 12207911 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 28088 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 434.630839 # Average number of references to valid blocks.
system.cpu.rob.rob_reads 166670760 # The number of ROB reads
system.cpu.rob.rob_writes 227084538 # The number of ROB writes
system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 100634165 # Number of Instructions Simulated
system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated
system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads
system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 511657086 # number of integer regfile reads
system.cpu.int_regfile_writes 103892124 # number of integer regfile writes
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
system.cpu.fp_regfile_writes 126 # number of floating regfile writes
system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads
system.cpu.misc_regfile_writes 34752 # number of misc regfile writes
system.cpu.icache.replacements 26083 # number of replacements
system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use
system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1807.414724 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.882527 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12207928 # number of ReadReq hits
system.cpu.icache.demand_hits 12207928 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12207928 # number of overall hits
system.cpu.icache.ReadReq_misses 29227 # number of ReadReq misses
system.cpu.icache.demand_misses 29227 # number of demand (read+write) misses
system.cpu.icache.overall_misses 29227 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 359488500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 359488500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 359488500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12237155 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12237155 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12237155 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.002388 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.002388 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.002388 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12299.876826 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12299.876826 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12299.876826 # average overall miss latency
system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits
system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits
system.cpu.icache.overall_hits 12179178 # number of overall hits
system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses
system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses
system.cpu.icache.overall_misses 29230 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -354,67 +354,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 1 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1106 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1106 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1106 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 28121 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 28121 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 28121 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 247525500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 247525500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 247525500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.002298 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.002298 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.002298 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8802.158529 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8802.158529 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157957 # number of replacements
system.cpu.dcache.tagsinuse 4072.327719 # Cycle average of tags in use
system.cpu.dcache.total_refs 44754174 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 162053 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 276.169981 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306664000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4072.327719 # Average occupied blocks per context
system.cpu.dcache.replacements 157879 # number of replacements
system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use
system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 26407726 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 18310440 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 18642 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 17246 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 44718166 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 44718166 # number of overall hits
system.cpu.dcache.ReadReq_misses 109117 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1539461 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 29 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1648578 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1648578 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2423500000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 52284424500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 398000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 54707924500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 54707924500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 26516843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 44705739 # number of overall hits
system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1648460 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 18671 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 17246 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 46366744 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 46366744 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004115 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.077555 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001553 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.035555 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035555 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 22210.104750 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33962.811984 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 13724.137931 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 33184.917244 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33184.917244 # average overall miss latency
system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -423,74 +423,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 123460 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 53919 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1432572 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 29 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1486491 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1486491 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 55198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106889 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 162087 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 162087 # number of overall MSHR misses
system.cpu.dcache.writebacks 123472 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1037796500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3662032500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4699829000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4699829000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002082 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003496 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003496 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18801.342440 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34260.143700 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 28995.718349 # average overall mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 114992 # number of replacements
system.cpu.l2cache.tagsinuse 18307.930672 # Cycle average of tags in use
system.cpu.l2cache.total_refs 72391 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 133845 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.540857 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 114920 # number of replacements
system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use
system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2377.365392 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15930.565280 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.072551 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486162 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 50505 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 123461 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 12 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 4300 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 54805 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 54805 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32740 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 21 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 102589 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 135329 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 135329 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1120810000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3525271500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4646081500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4646081500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 83245 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 123461 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 33 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106889 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 190134 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 190134 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.393297 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.959771 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.711756 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.711756 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34233.659133 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.055493 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34331.750770 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34331.750770 # average overall miss latency
system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 54819 # number of overall hits
system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 135262 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -499,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 88460 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 79 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 79 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 79 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32661 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 21 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 102589 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 135250 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 135250 # number of overall MSHR misses
system.cpu.l2cache.writebacks 88456 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1015115500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 652000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3196978500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 4212094000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 4212094000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.392348 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959771 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.711340 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.711340 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.355776 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31047.619048 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31162.975563 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.024030 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

3
tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -61,7 +62,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
egid=100
env=
errout=cerr

8
tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:19:11
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:17:49
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148678500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2568565 # Simulator instruction rate (inst/s)
host_tick_rate 1285774138 # Simulator tick rate (ticks/s)
host_mem_usage 229364 # Number of bytes of host memory used
host_seconds 53.00 # Real time elapsed on the host
host_inst_rate 3860753 # Simulator instruction rate (inst/s)
host_tick_rate 1932617843 # Simulator tick rate (ticks/s)
host_mem_usage 204428 # Number of bytes of host memory used
host_seconds 35.26 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297358 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 8898970 # nu
system.cpu.num_int_insts 115187758 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
system.cpu.num_int_register_writes 113225733 # number of times the integer registers were written
system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160249 # number of memory refs

3
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
mem_mode=atomic
memories=system.physmem
physmem=system.physmem
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
@ -164,7 +165,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr

8
tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 12 2011 07:14:44
gem5 started Jun 12 2011 07:15:05
gem5 compiled Nov 30 2011 17:14:16
gem5 started Nov 30 2011 17:16:48
gem5 executing on zizzer
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
command line: build/SPARC_SE/gem5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.

10
tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -3,10 +3,10 @@
sim_seconds 0.202942 # Number of seconds simulated
sim_ticks 202941992000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 927071 # Simulator instruction rate (inst/s)
host_tick_rate 1381979289 # Simulator tick rate (ticks/s)
host_mem_usage 238016 # Number of bytes of host memory used
host_seconds 146.85 # Real time elapsed on the host
host_inst_rate 2092270 # Simulator instruction rate (inst/s)
host_tick_rate 3118935472 # Simulator tick rate (ticks/s)
host_mem_usage 213400 # Number of bytes of host memory used
host_seconds 65.07 # Real time elapsed on the host
sim_insts 136139203 # Number of instructions simulated
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 405883984 # number of cpu cycles simulated
@ -20,7 +20,7 @@ system.cpu.num_conditional_control_insts 8898970 # nu
system.cpu.num_int_insts 115187758 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
system.cpu.num_int_register_writes 113225732 # number of times the integer registers were written
system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160249 # number of memory refs

2
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864

8
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 11 2011 21:12:14
gem5 started Sep 11 2011 22:28:54
gem5 executing on u200439-lin.austin.arm.com
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 18:44:48
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 483520764000 because target called exit()
Exiting @ tick 483463019500 because target called exit()

708
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

@ -1,12 +1,12 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.483521 # Number of seconds simulated
sim_ticks 483520764000 # Number of ticks simulated
sim_seconds 0.483463 # Number of seconds simulated
sim_ticks 483463019500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 88254 # Simulator instruction rate (inst/s)
host_tick_rate 24765480 # Simulator tick rate (ticks/s)
host_mem_usage 263692 # Number of bytes of host memory used
host_seconds 19523.98 # Real time elapsed on the host
host_inst_rate 167165 # Simulator instruction rate (inst/s)
host_tick_rate 46903472 # Simulator tick rate (ticks/s)
host_mem_usage 214756 # Number of bytes of host memory used
host_seconds 10307.62 # Real time elapsed on the host
sim_insts 1723073849 # Number of instructions simulated
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
@ -51,141 +51,141 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 967041529 # number of cpu cycles simulated
system.cpu.numCycles 966926040 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 298900449 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 243980938 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18344304 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 264330532 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 238781777 # Number of BTB hits
system.cpu.BPredUnit.lookups 298898243 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 243989412 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 18339920 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 264347245 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 238745657 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 17662867 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 3505 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 295983189 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2175588902 # Number of instructions fetch has processed
system.cpu.fetch.Branches 298900449 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 256444644 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 484812336 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 87085918 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 107601139 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 294 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 285066920 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5311321 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 956724152 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.521766 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.026486 # Number of instructions fetched each cycle (Total)
system.cpu.BPredUnit.usedRAS 17668157 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 3423 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 295953389 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2175230772 # Number of instructions fetch has processed
system.cpu.fetch.Branches 298898243 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 256413814 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 484717826 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 87053301 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 107577195 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 285045078 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5311594 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 956547645 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.521914 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.026495 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 471911868 49.33% 49.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 35379148 3.70% 53.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 65139184 6.81% 59.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 66872594 6.99% 66.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 46913058 4.90% 71.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 59711536 6.24% 77.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 54259656 5.67% 83.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 17705492 1.85% 85.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 138831616 14.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 471829873 49.33% 49.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 35367236 3.70% 53.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 65085859 6.80% 59.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 66860371 6.99% 66.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 46850107 4.90% 71.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 59747954 6.25% 77.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 54343246 5.68% 83.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 17692463 1.85% 85.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 138770536 14.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 956724152 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.309088 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.249737 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 323003673 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 92138171 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 459624740 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 13631035 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 68326533 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46888019 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2352946295 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2296 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 68326533 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 343140693 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 46558738 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 19729 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 451876616 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46801843 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2296129706 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19815 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2700855 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 37763142 # Number of times rename has blocked due to LSQ full
system.cpu.fetch.rateDist::total 956547645 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.309122 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.249635 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 322987122 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 92097194 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 459538157 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 13626726 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 68298446 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46874540 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 671 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2352694278 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2235 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 68298446 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 343127088 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 46537686 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 27220 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 451783493 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46773712 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2295847883 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19963 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2697037 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 37730930 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2264720698 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10606897757 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10606896049 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1708 # Number of floating rename lookups
system.cpu.rename.RenamedOperands 2264588148 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10605407368 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10605405778 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1590 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 558400742 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 819 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 812 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 98759000 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 618794544 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222188124 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 74432694 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 62140550 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2187930244 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 806 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2018487398 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3289652 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 458712680 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1051172668 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 349 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 956724152 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.109790 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.840040 # Number of insts issued each cycle
system.cpu.rename.UndoneMaps 558268197 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 10043 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10038 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 98804137 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 618742816 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 222099567 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 74239442 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 61602093 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2187718033 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2090 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2018498325 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3274725 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 458502719 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1049949895 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1587 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 956547645 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.110191 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.840946 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 261965292 27.38% 27.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 150944559 15.78% 43.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 168632678 17.63% 60.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 136410439 14.26% 75.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 125113434 13.08% 88.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 73446986 7.68% 95.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 29046356 3.04% 98.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10235900 1.07% 99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 928508 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 262039584 27.39% 27.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 150878554 15.77% 43.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 168430661 17.61% 60.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 136432052 14.26% 75.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 124835406 13.05% 88.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 73540708 7.69% 95.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 29241453 3.06% 98.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10225405 1.07% 99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 923822 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 956724152 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 956547645 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 898312 3.71% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 170 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 18874903 77.94% 81.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4444569 18.35% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 901388 3.68% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 177 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 19016870 77.70% 81.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4557312 18.62% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1238989796 61.38% 61.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1018767 0.05% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1238993791 61.38% 61.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1017752 0.05% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
@ -207,91 +207,91 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Ty
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 11 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 1 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 14 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 13 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 2 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 583947158 28.93% 90.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194531653 9.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 583952461 28.93% 90.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194534287 9.64% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2018487398 # Type of FU issued
system.cpu.iq.rate 2.087281 # Inst issue rate
system.cpu.iq.fu_busy_cnt 24217954 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011998 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5021206278 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2646821889 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1958327848 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 276 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2042705213 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 55649565 # Number of loads that had data forwarded from stores
system.cpu.iq.FU_type_0::total 2018498325 # Type of FU issued
system.cpu.iq.rate 2.087542 # Inst issue rate
system.cpu.iq.fu_busy_cnt 24475747 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012126 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5021294480 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2646401011 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1958335598 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 287 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 124 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2042973928 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 55719619 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 132867772 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 211365 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 180609 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 47341078 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 132816045 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 210497 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 180679 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 47252521 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 452178 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.cacheBlocked 451790 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 68326533 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 22149991 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1213461 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2187949319 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 7278781 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 618794544 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222188124 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 743 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 219838 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 61091 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 180609 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18951981 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1826621 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 20778602 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1986068567 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 570288882 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 32418831 # Number of squashed instructions skipped in execute
system.cpu.iew.iewSquashCycles 68298446 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 22155006 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1213609 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2187738627 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 7300026 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 618742816 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 222099567 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2027 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 219640 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 61277 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 180679 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 18953795 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1821941 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 20775736 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1986087052 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 570299160 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 32411273 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 18269 # number of nop insts executed
system.cpu.iew.exec_refs 761473758 # number of memory reference insts executed
system.cpu.iew.exec_branches 238644907 # Number of branches executed
system.cpu.iew.exec_stores 191184876 # Number of stores executed
system.cpu.iew.exec_rate 2.053757 # Inst execution rate
system.cpu.iew.wb_sent 1967261719 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1958327963 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1288121662 # num instructions producing a value
system.cpu.iew.wb_consumers 2036910460 # num instructions consuming a value
system.cpu.iew.exec_nop 18504 # number of nop insts executed
system.cpu.iew.exec_refs 761501875 # number of memory reference insts executed
system.cpu.iew.exec_branches 238650211 # Number of branches executed
system.cpu.iew.exec_stores 191202715 # Number of stores executed
system.cpu.iew.exec_rate 2.054022 # Inst execution rate
system.cpu.iew.wb_sent 1967277607 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1958335722 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1288034280 # num instructions producing a value
system.cpu.iew.wb_consumers 2036866160 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.025071 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.632390 # average fanout of values written-back
system.cpu.iew.wb_rate 2.025321 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.632361 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 464956551 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 457 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18344332 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 888397620 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.939530 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.671610 # Number of insts commited each cycle
system.cpu.commit.commitSquashedInsts 464746992 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18339818 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 888249200 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.939854 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.672088 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 383037346 43.12% 43.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 200906061 22.61% 65.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 81946763 9.22% 74.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 38644775 4.35% 79.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19780530 2.23% 81.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30949131 3.48% 85.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 22271905 2.51% 87.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12048122 1.36% 88.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 98812987 11.12% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 383075847 43.13% 43.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 200735352 22.60% 65.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 81917807 9.22% 74.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 38649475 4.35% 79.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19675094 2.22% 81.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 31029952 3.49% 85.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 22284246 2.51% 87.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12052552 1.36% 88.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 98828875 11.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 888397620 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 888249200 # Number of insts commited each cycle
system.cpu.commit.count 1723073867 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773817 # Number of memory references committed
@ -301,50 +301,50 @@ system.cpu.commit.branches 213462365 # Nu
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 98812987 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 98828875 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2977614452 # The number of ROB reads
system.cpu.rob.rob_writes 4444617859 # The number of ROB writes
system.cpu.timesIdled 920049 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10317377 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 2977240585 # The number of ROB reads
system.cpu.rob.rob_writes 4444170390 # The number of ROB writes
system.cpu.timesIdled 920776 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10378395 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
system.cpu.cpi 0.561230 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.561230 # CPI: Total CPI of All Threads
system.cpu.ipc 1.781799 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.781799 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9941893014 # number of integer regfile reads
system.cpu.int_regfile_writes 1939859629 # number of integer regfile writes
system.cpu.fp_regfile_reads 106 # number of floating regfile reads
system.cpu.fp_regfile_writes 43 # number of floating regfile writes
system.cpu.misc_regfile_reads 2914173755 # number of misc regfile reads
system.cpu.cpi 0.561163 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.561163 # CPI: Total CPI of All Threads
system.cpu.ipc 1.782012 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.782012 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9942029327 # number of integer regfile reads
system.cpu.int_regfile_writes 1939848996 # number of integer regfile writes
system.cpu.fp_regfile_reads 117 # number of floating regfile reads
system.cpu.fp_regfile_writes 59 # number of floating regfile writes
system.cpu.misc_regfile_reads 2913839911 # number of misc regfile reads
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.tagsinuse 611.960208 # Cycle average of tags in use
system.cpu.icache.total_refs 285065889 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 382125.856568 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 609.858480 # Cycle average of tags in use
system.cpu.icache.total_refs 285044064 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 744 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 383123.741935 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 611.960208 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.298809 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 285065889 # number of ReadReq hits
system.cpu.icache.demand_hits 285065889 # number of demand (read+write) hits
system.cpu.icache.overall_hits 285065889 # number of overall hits
system.cpu.icache.ReadReq_misses 1031 # number of ReadReq misses
system.cpu.icache.demand_misses 1031 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1031 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 35526500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 35526500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 35526500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 285066920 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 285066920 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 285066920 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::0 609.858480 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.297782 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 285044064 # number of ReadReq hits
system.cpu.icache.demand_hits 285044064 # number of demand (read+write) hits
system.cpu.icache.overall_hits 285044064 # number of overall hits
system.cpu.icache.ReadReq_misses 1014 # number of ReadReq misses
system.cpu.icache.demand_misses 1014 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1014 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 35191500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 35191500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 35191500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 285045078 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 285045078 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 285045078 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 34458.292919 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34458.292919 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34458.292919 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency 34705.621302 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34705.621302 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34705.621302 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -354,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 285 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 285 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 285 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 744 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 744 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 744 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 25635000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25635000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25635000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency 25627000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 25627000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 25627000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34363.270777 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34363.270777 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34444.892473 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34444.892473 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9570715 # number of replacements
system.cpu.dcache.tagsinuse 4087.762174 # Cycle average of tags in use
system.cpu.dcache.total_refs 666971462 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9574811 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 69.658969 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3484394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4087.762174 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 499575855 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 167395484 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits
system.cpu.dcache.replacements 9570827 # number of replacements
system.cpu.dcache.tagsinuse 4087.732038 # Cycle average of tags in use
system.cpu.dcache.total_refs 666909210 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9574923 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 69.651653 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3484303000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4087.732038 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997981 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 499513800 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 167395288 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 60 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 62 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 666971339 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 666971339 # number of overall hits
system.cpu.dcache.ReadReq_misses 10446749 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 5190563 # number of WriteReq misses
system.cpu.dcache.demand_hits 666909088 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 666909088 # number of overall hits
system.cpu.dcache.ReadReq_misses 10448466 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 5190759 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses 15637312 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 15637312 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 184495426500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 128540257604 # number of WriteReq miss cycles
system.cpu.dcache.demand_misses 15639225 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 15639225 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 184465722500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 128555474171 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 313035684104 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 313035684104 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 510022604 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency 313021196671 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 313021196671 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 509962266 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 64 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 63 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 62 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 682608651 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 682608651 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.020483 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.030075 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.046875 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.022908 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.022908 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 17660.558945 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24764.222610 # average WriteReq miss latency
system.cpu.dcache.demand_accesses 682548313 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 682548313 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.020489 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.030076 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate 0.047619 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate 0.022913 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.022913 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 17654.813874 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 24766.219000 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency 20018.509837 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 20018.509837 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 267225153 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 90802 # number of cycles access was blocked
system.cpu.dcache.demand_avg_miss_latency 20015.134808 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 20015.134808 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 266703683 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 90656 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2942.943470 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16583.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2941.930848 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16333.333333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3128462 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2764582 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 3297919 # number of WriteReq MSHR hits
system.cpu.dcache.writebacks 3128328 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 2766203 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 3298099 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits 6062501 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6062501 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7682167 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1892644 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9574811 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9574811 # number of overall MSHR misses
system.cpu.dcache.demand_mshr_hits 6064302 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6064302 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7682263 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1892660 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9574923 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9574923 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 92043723000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 45263737820 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 137307460820 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 137307460820 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency 92044930000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 45262385908 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 137307315908 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 137307315908 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015062 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate 0.015064 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.014027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.014027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.479054 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.611082 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 14340.487851 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate 0.014028 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11981.486445 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23914.694614 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 14340.304972 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2927649 # number of replacements
system.cpu.l2cache.tagsinuse 26780.067409 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7851232 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2954973 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.656956 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 102089125500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15983.054222 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10797.013187 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.487764 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.329499 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5655215 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3128462 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 980262 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6635477 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6635477 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2027697 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 912383 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2940080 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2940080 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 69611953000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 31645995500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 101257948500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 101257948500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7682912 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3128462 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1892645 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9575557 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9575557 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.263923 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.482068 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.307040 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.307040 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34330.549880 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.990295 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34440.541924 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34440.541924 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 56517000 # number of cycles access was blocked
system.cpu.l2cache.replacements 2927819 # number of replacements
system.cpu.l2cache.tagsinuse 26780.774124 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7851022 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2955142 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.656733 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 102041743500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15984.490640 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10796.283484 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.487808 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.329476 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5655252 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3128328 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 980176 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6635428 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6635428 # number of overall hits
system.cpu.l2cache.ReadReq_misses 2027753 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 912486 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2940239 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2940239 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 69614113000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 31648901500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 101263014500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 101263014500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7683005 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3128328 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1892662 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9575667 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9575667 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.263927 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.482118 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.307053 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.307053 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34330.666999 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34684.259813 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34440.402464 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34440.402464 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 56231500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6610 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6603 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8550.226929 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8516.053309 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 1217515 # number of writebacks
system.cpu.l2cache.writebacks 1217598 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 2027686 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 912383 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2940069 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2940069 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses 2027742 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 912486 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2940228 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2940228 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 63233834500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28812323000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 92046157500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 92046157500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency 63235914500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 28815026500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 92050941000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 92050941000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263922 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482068 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.307039 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.307039 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.220246 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.197552 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.482069 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263926 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482118 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.307052 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.307052 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.384778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31578.595726 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31307.415955 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

2
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
View file

@ -500,7 +500,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864

10
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,9 @@
Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simout
Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 12:27:58
gem5 started Aug 20 2011 12:28:18
gem5 executing on zizzer
gem5 compiled Nov 21 2011 16:28:02
gem5 started Nov 22 2011 18:53:02
gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
@ -25,4 +23,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 105782426500 because target called exit()
122 123 124 Exiting @ tick 105874925000 because target called exit()

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