61c14da751
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
100 lines
3.1 KiB
Python
100 lines
3.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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# --------------------
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# Base L1 Cache
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# ====================
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class L1(BaseCache):
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latency = '1ns'
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block_size = 64
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mshrs = 4
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tgts_per_mshr = 20
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is_top_level = True
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# ----------------------
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# Base L2 Cache
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# ----------------------
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class L2(BaseCache):
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block_size = 64
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latency = '10ns'
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mshrs = 92
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tgts_per_mshr = 16
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write_buffers = 8
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# ---------------------
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# I/O Cache
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# ---------------------
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class IOCache(BaseCache):
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assoc = 8
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block_size = 64
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latency = '50ns'
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mshrs = 20
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size = '1kB'
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tgts_per_mshr = 12
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addr_range=AddrRange(0, size='8GB')
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forward_snoops = False
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is_top_level = True
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#cpu
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cpu = DerivO3CPU(cpu_id=0)
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#the system
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system = FSConfig.makeLinuxAlphaSystem('timing')
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system.cpu = cpu
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#create the l1/l2 bus
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system.toL2Bus = Bus()
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system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
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system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
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system.iocache = IOCache()
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system.iocache.cpu_side = system.iobus.port
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system.iocache.mem_side = system.membus.port
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#connect up the l2 cache
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system.l2c = L2(size='4MB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.port
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system.l2c.mem_side = system.membus.port
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#connect up the cpu and l1s
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cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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L1(size = '32kB', assoc = 4))
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# connect cpu level-1 caches to shared level-2 cache
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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root = Root(system=system)
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m5.ticks.setGlobalFrequency('1THz')
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