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sparc: update o3 regressions

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This commit is contained in:
Korey Sewell 2011-06-10 22:15:34 -04:00
parent c8b43641fd
commit fb8c958241
6 changed files with 2160 additions and 2169 deletions
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1
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
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@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

18
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
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@ -1,14 +1,10 @@
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 13:27:10
M5 started Apr 21 2011 13:28:40
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
gem5 compiled Jun 10 2011 22:06:52
gem5 started Jun 10 2011 22:07:32
gem5 executing on zooks
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
@ -22,4 +18,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 18633000 because target called exit()
Exiting @ tick 19016500 because target called exit()

879
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
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@ -1,459 +1,460 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 79158 # Simulator instruction rate (inst/s)
host_mem_usage 209796 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_tick_rate 101982426 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
sim_seconds 0.000019 # Number of seconds simulated
sim_ticks 18633000 # Number of ticks simulated
sim_ticks 19016500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 51742 # Simulator instruction rate (inst/s)
host_tick_rate 68090181 # Simulator tick rate (ticks/s)
host_mem_usage 162768 # Number of bytes of host memory used
host_seconds 0.28 # Real time elapsed on the host
sim_insts 14449 # Number of instructions simulated
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 38034 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 5148 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 3432 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 838 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 4682 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2465 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 2697 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 5067 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 714 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 5154 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 5154 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.branchMispredicts 714 # The number of times a branch was mispredicted
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.bw_lim_events 86 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 5051 # The number of squashed insts skipped by commit
system.cpu.commit.committed_per_cycle::samples 27481 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.552200 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.190718 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 19704 71.70% 71.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4516 16.43% 88.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1458 5.31% 93.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 763 2.78% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 370 1.35% 97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 256 0.93% 98.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 290 1.06% 99.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 38 0.14% 99.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 86 0.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 27481 # Number of insts commited each cycle
system.cpu.commit.count 15175 # Number of instructions committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.refs 3674 # Number of memory references committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.579210 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.579210 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 2764 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33620.967742 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35563.492063 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 2640 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 4169000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.044863 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 124 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 61 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2240500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022793 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 35890.931373 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35837.349398 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 14643500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2974500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 25.205479 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 4206 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 35361.842105 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency
system.cpu.dcache.demand_hits 3674 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 18812500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.126486 # miss rate for demand accesses
system.cpu.dcache.demand_misses 532 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 386 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5215000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.034712 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_blocks::0 102.139862 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.024936 # Average percentage of cache occupancy
system.cpu.dcache.overall_accesses 4206 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 35361.842105 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35719.178082 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 3674 # number of overall hits
system.cpu.dcache.overall_miss_latency 18812500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.126486 # miss rate for overall accesses
system.cpu.dcache.overall_misses 532 # number of overall misses
system.cpu.dcache.overall_mshr_hits 386 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5215000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.034712 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 102.139862 # Cycle average of tags in use
system.cpu.dcache.total_refs 3680 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.BlockedCycles 7079 # Number of cycles decode is blocked
system.cpu.decode.DecodedInsts 23444 # Number of instructions handled by decode
system.cpu.decode.IdleCycles 13037 # Number of cycles decode is idle
system.cpu.decode.RunCycles 7241 # Number of cycles decode is running
system.cpu.decode.SquashCycles 1159 # Number of cycles decode is squashing
system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 5154 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 4051 # Number of cache lines fetched
system.cpu.fetch.Cycles 7481 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 377 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 23840 # Number of instructions fetch has processed
system.cpu.BPredUnit.usedRAS 337 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 167 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 4256 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 23684 # Number of instructions fetch has processed
system.cpu.fetch.Branches 5148 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2802 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 7695 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 937 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 813 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.138299 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 4051 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 2697 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.639708 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 28623 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.832897 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.946042 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 4256 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 353 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 29221 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.810513 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.905949 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21142 73.86% 73.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3578 12.50% 86.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 587 2.05% 88.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 505 1.76% 90.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 662 2.31% 92.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 528 1.84% 94.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 244 0.85% 95.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 195 0.68% 95.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1182 4.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21526 73.67% 73.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3882 13.28% 86.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 537 1.84% 88.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 503 1.72% 90.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 680 2.33% 92.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 525 1.80% 94.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 239 0.82% 95.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 192 0.66% 96.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1137 3.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 28623 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 4051 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35069.791667 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34975.988701 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 3571 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 16833500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.118489 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 480 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 126 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 12381500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.087386 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 10.087571 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4051 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35069.791667 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
system.cpu.icache.demand_hits 3571 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 16833500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.118489 # miss rate for demand accesses
system.cpu.icache.demand_misses 480 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 126 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 12381500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.087386 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 354 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_blocks::0 204.373592 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.099792 # Average percentage of cache occupancy
system.cpu.icache.overall_accesses 4051 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35069.791667 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34975.988701 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 3571 # number of overall hits
system.cpu.icache.overall_miss_latency 16833500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.118489 # miss rate for overall accesses
system.cpu.icache.overall_misses 480 # number of overall misses
system.cpu.icache.overall_mshr_hits 126 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 12381500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.087386 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 354 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 354 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 204.373592 # Cycle average of tags in use
system.cpu.icache.total_refs 3571 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 8644 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.branchMispredicts 800 # Number of branch mispredicts detected at execute
system.cpu.iew.exec_branches 3851 # Number of branches executed
system.cpu.iew.exec_nop 1086 # number of nop insts executed
system.cpu.iew.exec_rate 0.469692 # Inst execution rate
system.cpu.iew.exec_refs 4584 # number of memory reference insts executed
system.cpu.iew.exec_stores 1742 # Number of stores executed
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.iewBlockCycles 147 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 3044 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 564 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 420 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1894 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 20242 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 2842 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 465 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 17504 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1159 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.squashedLoads 818 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedStores 446 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 560 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly
system.cpu.iew.wb_consumers 9307 # num instructions consuming a value
system.cpu.iew.wb_count 17063 # cumulative count of insts written-back
system.cpu.iew.wb_fanout 0.856022 # average fanout of values written-back
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_producers 7967 # num instructions producing a value
system.cpu.iew.wb_rate 0.457858 # insts written-back per cycle
system.cpu.iew.wb_sent 17239 # cumulative count of insts sent to commit
system.cpu.int_regfile_reads 28062 # number of integer regfile reads
system.cpu.int_regfile_writes 15640 # number of integer regfile writes
system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13268 73.84% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2908 16.18% 90.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1793 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 17969 # Type of FU issued
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fu_busy_cnt 125 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006956 # FU busy rate (busy events/executed inst)
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 28 22.40% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 29 23.20% 45.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 68 54.40% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.int_alu_accesses 18094 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 64767 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 17063 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 23189 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 18592 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 17969 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 564 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 4009 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 3563 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::samples 28623 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.627782 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.193207 # Number of insts issued each cycle
system.cpu.fetch.rateDist::total 29221 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.135353 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.622706 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 13502 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 6935 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 7417 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1260 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 23270 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1260 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13958 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 243 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6236 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7103 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 21729 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 19486 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 40358 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 40358 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 5654 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 629 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 601 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2349 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3050 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1902 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 18598 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 18016 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3968 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3549 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 95 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 29221 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.616543 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.185129 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 19805 69.19% 69.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 4241 14.82% 84.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1891 6.61% 90.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1717 6.00% 96.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 425 1.48% 98.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 278 0.97% 99.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 172 0.60% 99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 79 0.28% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 20388 69.77% 69.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 4239 14.51% 84.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1899 6.50% 90.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1712 5.86% 96.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 440 1.51% 98.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 282 0.97% 99.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 168 0.57% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 79 0.27% 99.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 28623 # Number of insts issued each cycle
system.cpu.iq.rate 0.482169 # Inst issue rate
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34590.361446 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31451.807229 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2871000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.iq.issued_per_cycle::total 29221 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13295 73.80% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2920 16.21% 90.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1801 10.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 18016 # Type of FU issued
system.cpu.iq.rate 0.473681 # Inst issue rate
system.cpu.iq.fu_busy_cnt 123 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006827 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 65447 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 23160 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 17101 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 18139 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 824 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 454 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 132 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20254 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3050 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1902 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 372 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 17560 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2852 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 456 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1086 # number of nop insts executed
system.cpu.iew.exec_refs 4598 # number of memory reference insts executed
system.cpu.iew.exec_branches 3866 # Number of branches executed
system.cpu.iew.exec_stores 1746 # Number of stores executed
system.cpu.iew.exec_rate 0.461692 # Inst execution rate
system.cpu.iew.wb_sent 17276 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 17101 # cumulative count of insts written-back
system.cpu.iew.wb_producers 7938 # num instructions producing a value
system.cpu.iew.wb_consumers 9273 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.449624 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.856034 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 838 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 27978 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.542390 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.183434 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 20215 72.25% 72.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4492 16.06% 88.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1466 5.24% 93.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 768 2.75% 96.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 366 1.31% 97.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 259 0.93% 98.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 283 1.01% 99.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 42 0.15% 99.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 87 0.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 27978 # Number of insts commited each cycle
system.cpu.commit.count 15175 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 87 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 47306 # The number of ROB reads
system.cpu.rob.rob_writes 41741 # The number of ROB writes
system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8813 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.632293 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.632293 # CPI: Total CPI of All Threads
system.cpu.ipc 0.379897 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.379897 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 28130 # number of integer regfile reads
system.cpu.int_regfile_writes 15668 # number of integer regfile writes
system.cpu.misc_regfile_reads 6217 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 195.108308 # Cycle average of tags in use
system.cpu.icache.total_refs 3800 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 11.445783 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 195.108308 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.095268 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 3800 # number of ReadReq hits
system.cpu.icache.demand_hits 3800 # number of demand (read+write) hits
system.cpu.icache.overall_hits 3800 # number of overall hits
system.cpu.icache.ReadReq_misses 456 # number of ReadReq misses
system.cpu.icache.demand_misses 456 # number of demand (read+write) misses
system.cpu.icache.overall_misses 456 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 15987000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 15987000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 15987000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 4256 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 4256 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 4256 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.107143 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.107143 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.107143 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35059.210526 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35059.210526 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35059.210526 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 11676000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 11676000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 11676000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.078008 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.078008 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.078008 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35168.674699 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.568719 # Cycle average of tags in use
system.cpu.dcache.total_refs 3697 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25.321918 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 102.568719 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.025041 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 2657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.demand_hits 3691 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 3691 # number of overall hits
system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
system.cpu.dcache.demand_misses 523 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 523 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 4005000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 14642500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18647500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18647500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 2772 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 4214 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 4214 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.041486 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.124110 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.124110 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 34826.086957 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35888.480392 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 35654.875717 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35654.875717 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 377 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 377 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 2242500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2973500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5216000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5216000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022727 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.034646 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.034646 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35595.238095 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35825.301205 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 230.191737 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 230.191737 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.007025 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34314.769976 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.324455 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14172000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990408 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 413 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12837000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990408 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 413 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 476 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 13493000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2870000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 16363000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 16363000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.313253 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34376.050420 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34376.050420 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 500 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34360.887097 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 17043000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 496 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 15447500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 496 # number of demand (read+write) MSHR misses
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_blocks::0 238.651434 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.007283 # Average percentage of cache occupancy
system.cpu.l2cache.overall_accesses 500 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34360.887097 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31144.153226 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
system.cpu.l2cache.overall_miss_latency 17043000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 496 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 15447500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 496 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 238.651434 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 3044 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1894 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 6202 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.numCycles 37267 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.BlockCycles 254 # Number of cycles rename is blocking
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.IdleCycles 13492 # Number of cycles rename is idle
system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenameLookups 40241 # Number of register rename lookups that rename has made
system.cpu.rename.RenamedInsts 21695 # Number of instructions processed by rename
system.cpu.rename.RenamedOperands 19448 # Number of destination operands rename has renamed
system.cpu.rename.RunCycles 7019 # Number of cycles rename is running
system.cpu.rename.SquashCycles 1159 # Number of cycles rename is squashing
system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking
system.cpu.rename.UndoneMaps 5616 # Number of HB maps that are undone due to squashing
system.cpu.rename.int_rename_lookups 40241 # Number of integer rename lookups
system.cpu.rename.serializeStallCycles 6278 # count of cycles rename stalled for serializing inst
system.cpu.rename.serializingInsts 613 # count of serializing insts renamed
system.cpu.rename.skidInsts 2673 # count of insts added to the skid buffer
system.cpu.rename.tempSerializingInsts 579 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 46798 # The number of ROB reads
system.cpu.rob.rob_writes 41616 # The number of ROB writes
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12217500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14827500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 14827500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31087.786260 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31445.783133 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

1
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
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@ -1,3 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
hack: be nice to actually delete the event here

48
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
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@ -1,30 +1,26 @@
M5 Simulator System
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Apr 21 2011 13:27:10
M5 started Apr 21 2011 13:27:31
M5 executing on maize
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
gem5 compiled Jun 10 2011 22:06:52
gem5 started Jun 10 2011 22:06:57
gem5 executing on zooks
command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
[Iteration 1, Thread 2] Got lock
[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 1, Thread 1] Got lock
[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 1, Thread 3] Got lock
[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 1, Thread 1] Got lock
[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
Iteration 1 completed
[Iteration 2, Thread 3] Got lock
[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 2, Thread 1] Got lock
[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 2, Thread 3] Got lock
[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 2, Thread 2] Got lock
[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
Iteration 2 completed
[Iteration 3, Thread 2] Got lock
[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
@ -61,19 +57,19 @@ Iteration 6 completed
[Iteration 7, Thread 2] Got lock
[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
Iteration 7 completed
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 8, Thread 2] Got lock
[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 8, Thread 1] Got lock
[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
Iteration 8 completed
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 9, Thread 1] Got lock
[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
Iteration 9 completed
[Iteration 10, Thread 1] Got lock
[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
@ -83,4 +79,4 @@ Iteration 9 completed
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
Iteration 10 completed
PASSED :-)
Exiting @ tick 117445500 because target called exit()
Exiting @ tick 117354500 because target called exit()

3382
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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