tests: update reference outputs for ruby cache index change
MOESI_CMP_token is the only protocol that showed noticeable stats differences.
This commit is contained in:
parent
e0fdd86fd9
commit
bb67c706d6
17 changed files with 1301 additions and 1289 deletions
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@ -63,7 +63,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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@ -174,7 +174,7 @@ assoc=2
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latency=10
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replacement_policy=PSEUDO_LRU
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size=512
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start_index_bit=0
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start_index_bit=6
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[system.physmem]
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type=PhysicalMemory
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@ -208,6 +208,7 @@ deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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using_network_tester=false
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using_ruby_tester=false
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version=0
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physMemPort=system.physmem.port[0]
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@ -34,7 +34,7 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Feb/08/2011 17:51:05
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Real time: Mar/26/2011 22:00:44
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Profiler Stats
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--------------
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@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.4
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Virtual_time_in_minutes: 0.00666667
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Virtual_time_in_hours: 0.000111111
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Virtual_time_in_days: 4.62963e-06
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Virtual_time_in_seconds: 0.23
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Virtual_time_in_minutes: 0.00383333
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Virtual_time_in_hours: 6.38889e-05
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Virtual_time_in_days: 2.66204e-06
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Ruby_current_time: 243131
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Ruby_current_time: 217591
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Ruby_start_time: 0
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Ruby_cycles: 243131
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Ruby_cycles: 217591
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mbytes_resident: 37.0508
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mbytes_total: 210.492
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resident_ratio: 0.176057
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mbytes_resident: 38.1094
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mbytes_total: 199.473
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resident_ratio: 0.19107
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ruby_cycles_executed: [ 243132 ]
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ruby_cycles_executed: [ 217592 ]
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Busy Controller Counts:
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L1Cache-0:0
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@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 |
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ]
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miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
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miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency: [binsize: 2 max: 276 count: 8464 average: 24.7078 | standard deviation: 56.4373 | 0 7081 0 0 0 0 0 0 0 0 251 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 191 158 138 129 298 6 3 5 6 6 28 26 44 26 38 0 2 1 0 1 3 3 2 4 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 2 max: 276 count: 1185 average: 60.9418 | standard deviation: 78.0106 | 0 660 0 0 0 0 0 0 0 0 117 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 64 48 37 108 1 2 2 5 0 10 8 6 14 20 0 1 0 0 1 0 2 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 2 max: 202 count: 865 average: 31.3526 | standard deviation: 61.6294 | 0 653 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 38 22 7 29 0 0 1 0 2 2 8 21 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.1174 | standard deviation: 47.5593 | 0 5768 0 0 0 0 0 0 0 0 68 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 56 68 85 161 5 1 2 1 4 16 10 17 12 18 0 1 1 0 0 1 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_L1Cache: [binsize: 1 max: 2 count: 7081 average: 2 | standard deviation: 0 | 0 0 7081 ]
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miss_latency_L2Cache: [binsize: 1 max: 21 count: 251 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 ]
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miss_latency_Directory: [binsize: 2 max: 276 count: 1132 average: 167.574 | standard deviation: 13.1739 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 191 158 138 129 298 6 3 5 6 6 28 26 44 26 38 0 2 1 0 1 3 3 2 4 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@ -86,16 +86,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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imcomplete_dir_Times: 1300
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
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miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
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miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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imcomplete_dir_Times: 1131
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miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ]
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miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
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miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ]
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miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
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miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 117 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 117 ]
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miss_latency_LD_Directory: [binsize: 2 max: 276 count: 408 average: 167.743 | standard deviation: 13.3005 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 71 64 48 37 108 1 2 2 5 0 10 8 6 14 20 0 1 0 0 1 0 2 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 653 average: 2 | standard deviation: 0 | 0 0 653 ]
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miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 66 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 66 ]
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miss_latency_ST_Directory: [binsize: 2 max: 202 count: 146 average: 167.315 | standard deviation: 9.47738 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 38 22 7 29 0 0 1 0 2 2 8 21 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ]
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miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 68 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 ]
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miss_latency_IFETCH_Directory: [binsize: 2 max: 276 count: 578 average: 167.521 | standard deviation: 13.885 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107 56 68 85 161 5 1 2 1 4 16 10 17 12 18 0 1 1 0 0 1 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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@ -127,75 +127,75 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 10655
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page_reclaims: 10053
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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block_outputs: 64
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Network Stats
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-------------
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total_msg_count_Request_Control: 8046 64368
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total_msg_count_Response_Data: 3903 281016
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total_msg_count_ResponseL2hit_Data: 237 17064
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total_msg_count_Response_Control: 3 24
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total_msg_count_Writeback_Data: 4785 344520
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total_msg_count_Writeback_Control: 3222 25776
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total_msgs: 20196 total_bytes: 732768
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total_msg_count_Request_Control: 7599 60792
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total_msg_count_Response_Data: 3396 244512
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total_msg_count_ResponseL2hit_Data: 753 54216
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total_msg_count_Response_Control: 21 168
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total_msg_count_Writeback_Data: 4683 337176
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total_msg_count_Writeback_Control: 2883 23064
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total_msgs: 19335 total_bytes: 719928
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.171423
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links_utilized_percent_switch_0_link_0: 0.0638596 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.278985 bw: 160000 base_latency: 1
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links_utilized_percent_switch_0: 0.191673
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links_utilized_percent_switch_0_link_0: 0.0715448 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.311801 bw: 160000 base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 1132 81504 [ 0 0 0 0 1132 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 251 18072 [ 0 0 0 0 251 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Request_Control: 1383 11064 [ 0 1383 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.0889284
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links_utilized_percent_switch_1_link_0: 0.0697464 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.10811 bw: 160000 base_latency: 1
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links_utilized_percent_switch_1: 0.110669
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links_utilized_percent_switch_1_link_0: 0.0779501 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.143388 bw: 160000 base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Request_Control: 1383 11064 [ 0 1383 0 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 1150 9200 [ 0 0 1150 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 251 18072 [ 0 0 0 0 251 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 961 7688 [ 0 0 0 0 961 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.132082
|
||||
links_utilized_percent_switch_2_link_0: 0.023367 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.240796 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.128469
|
||||
links_utilized_percent_switch_2_link_0: 0.0228295 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.234109 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 1150 9200 [ 0 0 1150 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 961 7688 [ 0 0 0 0 961 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1132 81504 [ 0 0 0 0 1132 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.209297
|
||||
links_utilized_percent_switch_3_link_0: 0.255438 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.278985 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0934681 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.229766
|
||||
links_utilized_percent_switch_3_link_0: 0.286179 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.311801 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0913181 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1132 81504 [ 0 0 0 0 1132 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 251 18072 [ 0 0 0 0 251 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 1383 11064 [ 0 1383 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 1150 9200 [ 0 0 1150 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 0 0 0 207 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 961 7688 [ 0 0 0 0 961 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 646
|
||||
|
@ -206,19 +206,19 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 646 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 646 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 734
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 737
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 737
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.5259%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.4741%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.2347%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.7653%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 734 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 737 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
@ -226,11 +226,11 @@ Load [1185 ] 1185
|
|||
Ifetch [6414 ] 6414
|
||||
Store [865 ] 865
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [1365 ] 1365
|
||||
Data_Shared [48 ] 48
|
||||
L1_Replacement [1366 ] 1366
|
||||
Data_Shared [185 ] 185
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [1332 ] 1332
|
||||
Ack [1 ] 1
|
||||
Data_All_Tokens [1198 ] 1198
|
||||
Ack [7 ] 7
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
|
@ -245,7 +245,7 @@ Own_Lock_or_Unlock [0 ] 0
|
|||
Request_Timeout [0 ] 0
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [1331 ] 1331
|
||||
Use_TimeoutNoStarvers [1197 ] 1197
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
|
@ -286,11 +286,11 @@ I Persistent_GETS [0 ] 0
|
|||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [95 ] 95
|
||||
S Ifetch [64 ] 64
|
||||
S Store [18 ] 18
|
||||
S Load [172 ] 172
|
||||
S Ifetch [356 ] 356
|
||||
S Store [21 ] 21
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [30 ] 30
|
||||
S L1_Replacement [164 ] 164
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
|
@ -326,11 +326,11 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [222 ] 222
|
||||
M Ifetch [3433 ] 3433
|
||||
M Store [35 ] 35
|
||||
M Load [176 ] 176
|
||||
M Ifetch [3228 ] 3228
|
||||
M Store [32 ] 32
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [1056 ] 1056
|
||||
M L1_Replacement [922 ] 922
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
|
@ -341,7 +341,7 @@ M Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
MM Load [220 ] 220
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [331 ] 331
|
||||
MM Store [329 ] 329
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [268 ] 268
|
||||
MM Transient_GETX [0 ] 0
|
||||
|
@ -352,8 +352,8 @@ MM Persistent_GETX [0 ] 0
|
|||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M_W Load [102 ] 102
|
||||
M_W Ifetch [2271 ] 2271
|
||||
M_W Load [71 ] 71
|
||||
M_W Ifetch [2184 ] 2184
|
||||
M_W Store [25 ] 25
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [8 ] 8
|
||||
|
@ -366,14 +366,14 @@ M_W Persistent_GETS [0 ] 0
|
|||
M_W Own_Lock_or_Unlock [0 ] 0
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [1097 ] 1097
|
||||
M_W Use_TimeoutNoStarvers [960 ] 960
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [21 ] 21
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [265 ] 265
|
||||
MM_W Store [267 ] 267
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [3 ] 3
|
||||
MM_W L1_Replacement [4 ] 4
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
|
@ -383,7 +383,7 @@ MM_W Persistent_GETS [0 ] 0
|
|||
MM_W Own_Lock_or_Unlock [0 ] 0
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [234 ] 234
|
||||
MM_W Use_TimeoutNoStarvers [237 ] 237
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
|
@ -394,7 +394,7 @@ IM L1_Replacement [0 ] 0
|
|||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [191 ] 191
|
||||
IM Ack [1 ] 1
|
||||
IM Ack [7 ] 7
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
|
@ -414,7 +414,7 @@ SM Atomic [0 ] 0
|
|||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [18 ] 18
|
||||
SM Data_All_Tokens [21 ] 21
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
|
@ -454,9 +454,9 @@ IS Ifetch [0 ] 0
|
|||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Shared [48 ] 48
|
||||
IS Data_Shared [185 ] 185
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [1123 ] 1123
|
||||
IS Data_All_Tokens [986 ] 986
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
|
@ -572,30 +572,30 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
|||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 1302
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1302
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 1150
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1150
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 86.2519%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.7481%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 85.7391%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 14.2609%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1302 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 1150 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [1168 ] 1168
|
||||
L1_GETS_Last_Token [3 ] 3
|
||||
L1_GETX [209 ] 209
|
||||
L1_GETS [1117 ] 1117
|
||||
L1_GETS_Last_Token [54 ] 54
|
||||
L1_GETX [212 ] 212
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [1349 ] 1349
|
||||
L2_Replacement [1272 ] 1272
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [28 ] 28
|
||||
Writeback_All_Tokens [1326 ] 1326
|
||||
Writeback_Shared_Data [113 ] 113
|
||||
Writeback_All_Tokens [1241 ] 1241
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
|
@ -608,14 +608,14 @@ Persistent_GETS_Last_Token [0 ] 0
|
|||
Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [1123 ] 1123
|
||||
NP L1_GETX [177 ] 177
|
||||
NP L1_GETS [986 ] 986
|
||||
NP L1_GETX [138 ] 138
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [28 ] 28
|
||||
NP Writeback_All_Tokens [1323 ] 1323
|
||||
NP Writeback_Shared_Data [109 ] 109
|
||||
NP Writeback_All_Tokens [1171 ] 1171
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
|
@ -628,15 +628,15 @@ NP Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_GETX [1 ] 1
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [34 ] 34
|
||||
I L2_Replacement [104 ] 104
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [1 ] 1
|
||||
I Writeback_Shared_Data [4 ] 4
|
||||
I Writeback_All_Tokens [19 ] 19
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
|
@ -648,13 +648,13 @@ I Persistent_GETS_Last_Token [0 ] 0
|
|||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [3 ] 3
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_GETS_Last_Token [54 ] 54
|
||||
S L1_GETX [7 ] 7
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [24 ] 24
|
||||
S L2_Replacement [52 ] 52
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
|
@ -670,15 +670,15 @@ S Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_GETX [18 ] 18
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [42 ] 42
|
||||
O L2_Replacement [62 ] 62
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [2 ] 2
|
||||
O Writeback_All_Tokens [51 ] 51
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
|
@ -688,12 +688,12 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [45 ] 45
|
||||
M L1_GETX [30 ] 30
|
||||
M L1_GETS [131 ] 131
|
||||
M L1_GETX [48 ] 48
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [1249 ] 1249
|
||||
M L2_Replacement [1054 ] 1054
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
@ -739,49 +739,49 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
|||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1542
|
||||
memory_reads: 1301
|
||||
memory_writes: 241
|
||||
memory_refreshes: 507
|
||||
memory_total_request_delays: 709
|
||||
memory_delays_per_request: 0.459792
|
||||
memory_delays_in_input_queue: 240
|
||||
memory_total_requests: 1339
|
||||
memory_reads: 1132
|
||||
memory_writes: 207
|
||||
memory_refreshes: 454
|
||||
memory_total_request_delays: 574
|
||||
memory_delays_per_request: 0.428678
|
||||
memory_delays_in_input_queue: 179
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 469
|
||||
memory_stalls_for_bank_busy: 141
|
||||
memory_delays_stalled_at_head_of_bank_queue: 395
|
||||
memory_stalls_for_bank_busy: 125
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 33
|
||||
memory_stalls_for_bus: 279
|
||||
memory_stalls_for_bus: 219
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 16
|
||||
memory_stalls_for_read_write_turnaround: 18
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56
|
||||
accesses_per_bank: 75 17 45 40 54 100 30 16 19 22 32 34 52 48 39 30 39 21 21 21 28 38 61 22 30 22 32 72 90 123 13 53
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [179 ] 179
|
||||
GETS [1123 ] 1123
|
||||
GETX [164 ] 164
|
||||
GETS [986 ] 986
|
||||
Lockdown [0 ] 0
|
||||
Unlockdown [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [21 ] 21
|
||||
Data_All_Tokens [220 ] 220
|
||||
Ack_Owner [21 ] 21
|
||||
Ack_Owner_All_Tokens [1029 ] 1029
|
||||
Data_Owner [19 ] 19
|
||||
Data_All_Tokens [188 ] 188
|
||||
Ack_Owner [43 ] 43
|
||||
Ack_Owner_All_Tokens [866 ] 866
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [24 ] 24
|
||||
Ack_All_Tokens [52 ] 52
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [1301 ] 1301
|
||||
Memory_Ack [241 ] 241
|
||||
Memory_Data [1132 ] 1132
|
||||
Memory_Ack [207 ] 207
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [178 ] 178
|
||||
O GETS [1123 ] 1123
|
||||
O GETX [146 ] 146
|
||||
O GETS [986 ] 986
|
||||
O Lockdown [0 ] 0
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
@ -789,21 +789,21 @@ O Own_Lock_or_Unlock_Tokens [0 ] 0
|
|||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [24 ] 24
|
||||
O Ack_All_Tokens [52 ] 52
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [1 ] 1
|
||||
NO GETX [18 ] 18
|
||||
NO GETS [0 ] 0
|
||||
NO Lockdown [0 ] 0
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [21 ] 21
|
||||
NO Data_All_Tokens [220 ] 220
|
||||
NO Ack_Owner [21 ] 21
|
||||
NO Ack_Owner_All_Tokens [1029 ] 1029
|
||||
NO Data_Owner [19 ] 19
|
||||
NO Data_All_Tokens [188 ] 188
|
||||
NO Ack_Owner [43 ] 43
|
||||
NO Ack_Owner_All_Tokens [866 ] 866
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
@ -835,7 +835,7 @@ O_W Ack_Owner [0 ] 0
|
|||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [241 ] 241
|
||||
O_W Memory_Ack [207 ] 207
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
@ -918,7 +918,7 @@ NO_W Data_All_Tokens [0 ] 0
|
|||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [1301 ] 1301
|
||||
NO_W Memory_Data [1132 ] 1132
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Mar 26 2011 14:06:20
|
||||
M5 started Mar 26 2011 22:00:43
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 243131 because target called exit()
|
||||
Exiting @ tick 217591 because target called exit()
|
||||
|
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 46789 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215548 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1774187 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 21360 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204264 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_tick_rate 725351 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000243 # Number of seconds simulated
|
||||
sim_ticks 243131 # Number of ticks simulated
|
||||
sim_seconds 0.000218 # Number of seconds simulated
|
||||
sim_ticks 217591 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
@ -42,10 +42,10 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 243131 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 217591 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 243131 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 217591 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 10 # number of float instructions
|
||||
|
|
|
@ -63,7 +63,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
@ -174,7 +174,7 @@ assoc=2
|
|||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
@ -208,6 +208,7 @@ deadlock_threshold=500000
|
|||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
|
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
Real time: Mar/26/2011 22:00:44
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.33
|
||||
Virtual_time_in_minutes: 0.0055
|
||||
Virtual_time_in_hours: 9.16667e-05
|
||||
Virtual_time_in_days: 3.81944e-06
|
||||
Virtual_time_in_seconds: 0.19
|
||||
Virtual_time_in_minutes: 0.00316667
|
||||
Virtual_time_in_hours: 5.27778e-05
|
||||
Virtual_time_in_days: 2.19907e-06
|
||||
|
||||
Ruby_current_time: 92099
|
||||
Ruby_current_time: 84059
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 92099
|
||||
Ruby_cycles: 84059
|
||||
|
||||
mbytes_resident: 35.7695
|
||||
mbytes_total: 209.457
|
||||
resident_ratio: 0.17081
|
||||
mbytes_resident: 36.8242
|
||||
mbytes_total: 198.527
|
||||
resident_ratio: 0.185507
|
||||
|
||||
ruby_cycles_executed: [ 92100 ]
|
||||
ruby_cycles_executed: [ 84060 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 |
|
|||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 293 count: 3294 average: 26.9596 | standard deviation: 59.7209 | 0 2781 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 293 count: 2585 average: 18.7741 | standard deviation: 50.0281 | 0 2315 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 72.1108 | standard deviation: 82.9193 | 0 233 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 277 count: 294 average: 35.1973 | standard deviation: 68.9222 | 0 233 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2781 average: 2 | standard deviation: 0 | 0 0 2781 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 21 count: 23 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 293 count: 490 average: 168.898 | standard deviation: 16.9003 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 2 max: 296 count: 3294 average: 24.5188 | standard deviation: 56.5949 | 0 2775 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69 73 60 58 94 4 3 2 0 4 10 7 7 7 24 0 0 0 0 1 0 3 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 61.5639 | standard deviation: 79.411 | 0 233 0 0 0 0 0 0 0 0 39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 15 18 15 36 0 0 1 0 2 8 1 2 3 6 0 0 0 0 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 2 max: 263 count: 294 average: 31.415 | standard deviation: 62.6615 | 0 227 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 6 8 5 13 0 0 0 0 2 0 1 1 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 2 max: 296 count: 2585 average: 17.7872 | standard deviation: 48.5294 | 0 2315 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 52 34 38 45 4 3 1 0 0 2 5 4 4 13 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2775 average: 2 | standard deviation: 0 | 0 0 2775 ]
|
||||
miss_latency_L2Cache: [binsize: 1 max: 21 count: 82 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 ]
|
||||
miss_latency_Directory: [binsize: 2 max: 296 count: 437 average: 168.176 | standard deviation: 16.6337 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 69 73 60 58 94 4 3 2 0 4 10 7 7 7 24 0 0 0 0 1 0 3 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
@ -86,16 +86,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 489
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 293 count: 261 average: 167.479 | standard deviation: 13.0564 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 436
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 277 count: 173 average: 169.197 | standard deviation: 16.5371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 5 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 277 count: 56 average: 174.589 | standard deviation: 28.9061 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 39 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39 ]
|
||||
miss_latency_LD_Directory: [binsize: 2 max: 281 count: 143 average: 169.678 | standard deviation: 18.465 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 15 18 15 36 0 0 1 0 2 8 1 2 3 6 0 0 0 0 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 227 average: 2 | standard deviation: 0 | 0 0 227 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 17 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 ]
|
||||
miss_latency_ST_Directory: [binsize: 2 max: 263 count: 50 average: 168.5 | standard deviation: 16.0261 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 6 8 5 13 0 0 0 0 2 0 1 1 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 26 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 2 max: 296 count: 244 average: 167.23 | standard deviation: 15.5933 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 52 34 38 45 4 3 1 0 0 2 5 4 4 13 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
@ -127,71 +127,75 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10334
|
||||
page_reclaims: 9723
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 64
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 3012 24096
|
||||
total_msg_count_Response_Data: 1470 105840
|
||||
total_msg_count_ResponseL2hit_Data: 69 4968
|
||||
total_msg_count_Writeback_Data: 1782 128304
|
||||
total_msg_count_Writeback_Control: 1206 9648
|
||||
total_msgs: 7539 total_bytes: 272856
|
||||
total_msg_count_Request_Control: 2883 23064
|
||||
total_msg_count_Response_Data: 1311 94392
|
||||
total_msg_count_ResponseL2hit_Data: 246 17712
|
||||
total_msg_count_Response_Control: 3 24
|
||||
total_msg_count_Writeback_Data: 1749 125928
|
||||
total_msg_count_Writeback_Control: 1101 8808
|
||||
total_msgs: 7293 total_bytes: 269928
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.167897
|
||||
links_utilized_percent_switch_0_link_0: 0.0626635 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.27313 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.184543
|
||||
links_utilized_percent_switch_0_link_0: 0.069475 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.299611 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 437 31464 [ 0 0 0 0 437 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 519 4152 [ 0 519 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0864762
|
||||
links_utilized_percent_switch_1_link_0: 0.0682825 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.10467 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.105172
|
||||
links_utilized_percent_switch_1_link_0: 0.0749027 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.135441 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 519 4152 [ 0 519 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 442 3536 [ 0 0 442 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 367 2936 [ 0 0 0 0 367 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.131387
|
||||
links_utilized_percent_switch_2_link_0: 0.023358 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.239416 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.128407
|
||||
links_utilized_percent_switch_2_link_0: 0.0228708 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.233943 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 442 3536 [ 0 0 442 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 367 2936 [ 0 0 0 0 367 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 437 31464 [ 0 0 0 0 437 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.205739
|
||||
links_utilized_percent_switch_3_link_0: 0.250654 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.27313 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0934321 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.222998
|
||||
links_utilized_percent_switch_3_link_0: 0.2779 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.299611 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0914834 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 437 31464 [ 0 0 0 0 437 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 519 4152 [ 0 519 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 442 3536 [ 0 0 442 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 367 2936 [ 0 0 0 0 367 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 270
|
||||
|
@ -202,19 +206,19 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
|||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 270 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 243
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 249
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 249
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 73.0924%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 26.9076%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 249 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
@ -223,10 +227,10 @@ Ifetch [2585 ] 2585
|
|||
Store [294 ] 294
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [503 ] 503
|
||||
Data_Shared [18 ] 18
|
||||
Data_Shared [65 ] 65
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [495 ] 495
|
||||
Ack [0 ] 0
|
||||
Data_All_Tokens [454 ] 454
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
|
@ -241,7 +245,7 @@ Own_Lock_or_Unlock [0 ] 0
|
|||
Request_Timeout [0 ] 0
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [494 ] 494
|
||||
Use_TimeoutNoStarvers [453 ] 453
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
|
@ -282,11 +286,11 @@ I Persistent_GETS [0 ] 0
|
|||
I Persistent_GETS_Last_Token [0 ] 0
|
||||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [6 ] 6
|
||||
S Ifetch [44 ] 44
|
||||
S Store [3 ] 3
|
||||
S Load [30 ] 30
|
||||
S Ifetch [249 ] 249
|
||||
S Store [9 ] 9
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [15 ] 15
|
||||
S L1_Replacement [55 ] 55
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
|
@ -322,11 +326,11 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [78 ] 78
|
||||
M Ifetch [1233 ] 1233
|
||||
M Store [31 ] 31
|
||||
M Load [65 ] 65
|
||||
M Ifetch [1061 ] 1061
|
||||
M Store [28 ] 28
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [391 ] 391
|
||||
M L1_Replacement [351 ] 351
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
|
@ -335,9 +339,9 @@ M Persistent_GETX [0 ] 0
|
|||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
MM Load [98 ] 98
|
||||
MM Load [95 ] 95
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [107 ] 107
|
||||
MM Store [102 ] 102
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [96 ] 96
|
||||
MM Transient_GETX [0 ] 0
|
||||
|
@ -348,11 +352,11 @@ MM Persistent_GETX [0 ] 0
|
|||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M_W Load [47 ] 47
|
||||
M_W Ifetch [1038 ] 1038
|
||||
M_W Store [6 ] 6
|
||||
M_W Load [36 ] 36
|
||||
M_W Ifetch [1005 ] 1005
|
||||
M_W Store [3 ] 3
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [1 ] 1
|
||||
M_W L1_Replacement [0 ] 0
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
|
@ -362,14 +366,14 @@ M_W Persistent_GETS [0 ] 0
|
|||
M_W Own_Lock_or_Unlock [0 ] 0
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [427 ] 427
|
||||
M_W Use_TimeoutNoStarvers [383 ] 383
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [4 ] 4
|
||||
MM_W Load [7 ] 7
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [89 ] 89
|
||||
MM_W Store [94 ] 94
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [0 ] 0
|
||||
MM_W L1_Replacement [1 ] 1
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
|
@ -379,7 +383,7 @@ MM_W Persistent_GETS [0 ] 0
|
|||
MM_W Own_Lock_or_Unlock [0 ] 0
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [67 ] 67
|
||||
MM_W Use_TimeoutNoStarvers [70 ] 70
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
|
@ -390,7 +394,7 @@ IM L1_Replacement [0 ] 0
|
|||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [58 ] 58
|
||||
IM Ack [0 ] 0
|
||||
IM Ack [1 ] 1
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
|
@ -410,7 +414,7 @@ SM Atomic [0 ] 0
|
|||
SM L1_Replacement [0 ] 0
|
||||
SM Data_Shared [0 ] 0
|
||||
SM Data_Owner [0 ] 0
|
||||
SM Data_All_Tokens [3 ] 3
|
||||
SM Data_All_Tokens [9 ] 9
|
||||
SM Ack [0 ] 0
|
||||
SM Transient_GETX [0 ] 0
|
||||
SM Transient_Local_GETX [0 ] 0
|
||||
|
@ -450,9 +454,9 @@ IS Ifetch [0 ] 0
|
|||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [0 ] 0
|
||||
IS Data_Shared [18 ] 18
|
||||
IS Data_Shared [65 ] 65
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [434 ] 434
|
||||
IS Data_All_Tokens [387 ] 387
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
|
@ -568,30 +572,30 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
|||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 491
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 491
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 442
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 442
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 88.391%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.609%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 87.5566%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 12.4434%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 491 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 442 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [451 ] 451
|
||||
L1_GETS_Last_Token [1 ] 1
|
||||
L1_GETX [61 ] 61
|
||||
L1_GETS [444 ] 444
|
||||
L1_GETS_Last_Token [8 ] 8
|
||||
L1_GETX [67 ] 67
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [500 ] 500
|
||||
L2_Replacement [464 ] 464
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [15 ] 15
|
||||
Writeback_All_Tokens [487 ] 487
|
||||
Writeback_Shared_Data [34 ] 34
|
||||
Writeback_All_Tokens [468 ] 468
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
|
@ -604,14 +608,14 @@ Persistent_GETS_Last_Token [0 ] 0
|
|||
Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [434 ] 434
|
||||
NP L1_GETX [56 ] 56
|
||||
NP L1_GETS [387 ] 387
|
||||
NP L1_GETX [48 ] 48
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [15 ] 15
|
||||
NP Writeback_All_Tokens [487 ] 487
|
||||
NP Writeback_Shared_Data [31 ] 31
|
||||
NP Writeback_All_Tokens [441 ] 441
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
|
@ -624,15 +628,15 @@ NP Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_GETX [1 ] 1
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [6 ] 6
|
||||
I L2_Replacement [16 ] 16
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [3 ] 3
|
||||
I Writeback_All_Tokens [6 ] 6
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
|
@ -644,13 +648,13 @@ I Persistent_GETS_Last_Token [0 ] 0
|
|||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [1 ] 1
|
||||
S L1_GETX [0 ] 0
|
||||
S L1_GETS_Last_Token [8 ] 8
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [14 ] 14
|
||||
S L2_Replacement [24 ] 24
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
|
@ -666,15 +670,15 @@ S Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_GETX [5 ] 5
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [16 ] 16
|
||||
O L2_Replacement [31 ] 31
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [0 ] 0
|
||||
O Writeback_All_Tokens [21 ] 21
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
|
@ -684,12 +688,12 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [17 ] 17
|
||||
M L1_GETX [4 ] 4
|
||||
M L1_GETS [57 ] 57
|
||||
M L1_GETX [12 ] 12
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [464 ] 464
|
||||
M L2_Replacement [393 ] 393
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
@ -735,49 +739,49 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
|||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 582
|
||||
memory_reads: 490
|
||||
memory_writes: 92
|
||||
memory_refreshes: 192
|
||||
memory_total_request_delays: 314
|
||||
memory_delays_per_request: 0.539519
|
||||
memory_delays_in_input_queue: 90
|
||||
memory_total_requests: 518
|
||||
memory_reads: 437
|
||||
memory_writes: 81
|
||||
memory_refreshes: 176
|
||||
memory_total_request_delays: 223
|
||||
memory_delays_per_request: 0.430502
|
||||
memory_delays_in_input_queue: 67
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 224
|
||||
memory_stalls_for_bank_busy: 106
|
||||
memory_delays_stalled_at_head_of_bank_queue: 156
|
||||
memory_stalls_for_bank_busy: 61
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 8
|
||||
memory_stalls_for_bus: 104
|
||||
memory_stalls_for_arbitration: 7
|
||||
memory_stalls_for_bus: 80
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 6
|
||||
memory_stalls_for_read_write_turnaround: 8
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 20 13 0 46 20 20 38 23 5 5 7 4 24 42 25 3 4 6 7 14 10 21 14 46 16 5 5 12 14 18 16 79
|
||||
accesses_per_bank: 18 10 0 40 20 20 29 22 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 16 5 5 12 12 18 14 65
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [57 ] 57
|
||||
GETS [434 ] 434
|
||||
GETX [65 ] 65
|
||||
GETS [407 ] 407
|
||||
Lockdown [0 ] 0
|
||||
Unlockdown [0 ] 0
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [2 ] 2
|
||||
Data_All_Tokens [90 ] 90
|
||||
Ack_Owner [14 ] 14
|
||||
Ack_Owner_All_Tokens [374 ] 374
|
||||
Data_Owner [6 ] 6
|
||||
Data_All_Tokens [75 ] 75
|
||||
Ack_Owner [25 ] 25
|
||||
Ack_Owner_All_Tokens [318 ] 318
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [14 ] 14
|
||||
Ack_All_Tokens [24 ] 24
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [490 ] 490
|
||||
Memory_Ack [92 ] 92
|
||||
Memory_Data [437 ] 437
|
||||
Memory_Ack [81 ] 81
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [56 ] 56
|
||||
O GETS [434 ] 434
|
||||
O GETX [50 ] 50
|
||||
O GETS [387 ] 387
|
||||
O Lockdown [0 ] 0
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
@ -785,21 +789,21 @@ O Own_Lock_or_Unlock_Tokens [0 ] 0
|
|||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [14 ] 14
|
||||
O Ack_All_Tokens [24 ] 24
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [1 ] 1
|
||||
NO GETX [5 ] 5
|
||||
NO GETS [0 ] 0
|
||||
NO Lockdown [0 ] 0
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [2 ] 2
|
||||
NO Data_All_Tokens [90 ] 90
|
||||
NO Ack_Owner [14 ] 14
|
||||
NO Ack_Owner_All_Tokens [374 ] 374
|
||||
NO Data_Owner [6 ] 6
|
||||
NO Data_All_Tokens [75 ] 75
|
||||
NO Ack_Owner [25 ] 25
|
||||
NO Ack_Owner_All_Tokens [318 ] 318
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
@ -819,8 +823,8 @@ L DMA_READ [0 ] 0
|
|||
L DMA_WRITE [0 ] 0
|
||||
L DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W GETX [10 ] 10
|
||||
O_W GETS [20 ] 20
|
||||
O_W Lockdown [0 ] 0
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
|
@ -831,7 +835,7 @@ O_W Ack_Owner [0 ] 0
|
|||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [92 ] 92
|
||||
O_W Memory_Ack [81 ] 81
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
@ -914,7 +918,7 @@ NO_W Data_All_Tokens [0 ] 0
|
|||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [490 ] 490
|
||||
NO_W Memory_Data [437 ] 437
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
|
@ -5,13 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Mar 26 2011 14:06:20
|
||||
M5 started Mar 26 2011 22:00:43
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 92099 because target called exit()
|
||||
Exiting @ tick 84059 because target called exit()
|
||||
|
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 44139 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214488 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 1572917 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 8652 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203296 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_tick_rate 282076 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000092 # Number of seconds simulated
|
||||
sim_ticks 92099 # Number of ticks simulated
|
||||
sim_seconds 0.000084 # Number of seconds simulated
|
||||
sim_ticks 84059 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
@ -42,10 +42,10 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 92099 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 84059 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 92099 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 84059 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 6 # number of float instructions
|
||||
|
|
|
@ -508,7 +508,7 @@ assoc=2
|
|||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
@ -542,6 +542,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
|
@ -555,6 +556,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl1.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=1
|
||||
physMemPort=system.physmem.port[1]
|
||||
|
@ -568,6 +570,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl2.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=2
|
||||
physMemPort=system.physmem.port[2]
|
||||
|
@ -581,6 +584,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl3.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=3
|
||||
physMemPort=system.physmem.port[3]
|
||||
|
@ -594,6 +598,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl4.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=4
|
||||
physMemPort=system.physmem.port[4]
|
||||
|
@ -607,6 +612,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl5.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=5
|
||||
physMemPort=system.physmem.port[5]
|
||||
|
@ -620,6 +626,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl6.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=6
|
||||
physMemPort=system.physmem.port[6]
|
||||
|
@ -633,6 +640,7 @@ deadlock_threshold=1000000
|
|||
icache=system.l1_cntrl7.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=7
|
||||
physMemPort=system.physmem.port[7]
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -1,74 +1,74 @@
|
|||
system.cpu5: completed 10000 read accesses @3921160
|
||||
system.cpu1: completed 10000 read accesses @3925580
|
||||
system.cpu0: completed 10000 read accesses @3934400
|
||||
system.cpu2: completed 10000 read accesses @3939680
|
||||
system.cpu3: completed 10000 read accesses @3944050
|
||||
system.cpu6: completed 10000 read accesses @3950830
|
||||
system.cpu7: completed 10000 read accesses @3958280
|
||||
system.cpu4: completed 10000 read accesses @3974010
|
||||
system.cpu0: completed 20000 read accesses @7820430
|
||||
system.cpu5: completed 20000 read accesses @7822630
|
||||
system.cpu1: completed 20000 read accesses @7842540
|
||||
system.cpu2: completed 20000 read accesses @7858630
|
||||
system.cpu3: completed 20000 read accesses @7865210
|
||||
system.cpu4: completed 20000 read accesses @7866290
|
||||
system.cpu6: completed 20000 read accesses @7899300
|
||||
system.cpu7: completed 20000 read accesses @7926330
|
||||
system.cpu0: completed 30000 read accesses @11730870
|
||||
system.cpu1: completed 30000 read accesses @11752380
|
||||
system.cpu5: completed 30000 read accesses @11754100
|
||||
system.cpu4: completed 30000 read accesses @11817260
|
||||
system.cpu3: completed 30000 read accesses @11833290
|
||||
system.cpu2: completed 30000 read accesses @11849820
|
||||
system.cpu6: completed 30000 read accesses @11858520
|
||||
system.cpu7: completed 30000 read accesses @11878780
|
||||
system.cpu1: completed 40000 read accesses @15666470
|
||||
system.cpu0: completed 40000 read accesses @15689570
|
||||
system.cpu5: completed 40000 read accesses @15693470
|
||||
system.cpu3: completed 40000 read accesses @15770740
|
||||
system.cpu2: completed 40000 read accesses @15801030
|
||||
system.cpu4: completed 40000 read accesses @15802680
|
||||
system.cpu6: completed 40000 read accesses @15812300
|
||||
system.cpu7: completed 40000 read accesses @15814020
|
||||
system.cpu0: completed 50000 read accesses @19587160
|
||||
system.cpu1: completed 50000 read accesses @19609890
|
||||
system.cpu5: completed 50000 read accesses @19679290
|
||||
system.cpu3: completed 50000 read accesses @19706240
|
||||
system.cpu6: completed 50000 read accesses @19738150
|
||||
system.cpu2: completed 50000 read accesses @19790350
|
||||
system.cpu4: completed 50000 read accesses @19793110
|
||||
system.cpu7: completed 50000 read accesses @19826670
|
||||
system.cpu0: completed 60000 read accesses @23442420
|
||||
system.cpu1: completed 60000 read accesses @23506570
|
||||
system.cpu5: completed 60000 read accesses @23555050
|
||||
system.cpu3: completed 60000 read accesses @23640540
|
||||
system.cpu6: completed 60000 read accesses @23651620
|
||||
system.cpu4: completed 60000 read accesses @23764590
|
||||
system.cpu2: completed 60000 read accesses @23767160
|
||||
system.cpu7: completed 60000 read accesses @23798150
|
||||
system.cpu0: completed 70000 read accesses @27346650
|
||||
system.cpu1: completed 70000 read accesses @27417040
|
||||
system.cpu5: completed 70000 read accesses @27459850
|
||||
system.cpu3: completed 70000 read accesses @27568910
|
||||
system.cpu7: completed 70000 read accesses @27679260
|
||||
system.cpu4: completed 70000 read accesses @27695210
|
||||
system.cpu2: completed 70000 read accesses @27695820
|
||||
system.cpu6: completed 70000 read accesses @27700350
|
||||
system.cpu0: completed 80000 read accesses @31228160
|
||||
system.cpu5: completed 80000 read accesses @31278826
|
||||
system.cpu1: completed 80000 read accesses @31322150
|
||||
system.cpu3: completed 80000 read accesses @31508190
|
||||
system.cpu2: completed 80000 read accesses @31596330
|
||||
system.cpu6: completed 80000 read accesses @31639000
|
||||
system.cpu4: completed 80000 read accesses @31655530
|
||||
system.cpu7: completed 80000 read accesses @31659000
|
||||
system.cpu0: completed 90000 read accesses @35134550
|
||||
system.cpu5: completed 90000 read accesses @35282690
|
||||
system.cpu1: completed 90000 read accesses @35298090
|
||||
system.cpu2: completed 90000 read accesses @35490890
|
||||
system.cpu3: completed 90000 read accesses @35500970
|
||||
system.cpu6: completed 90000 read accesses @35564170
|
||||
system.cpu7: completed 90000 read accesses @35589110
|
||||
system.cpu4: completed 90000 read accesses @35604290
|
||||
system.cpu0: completed 100000 read accesses @39098820
|
||||
system.cpu2: completed 10000 read accesses @3880600
|
||||
system.cpu0: completed 10000 read accesses @3900250
|
||||
system.cpu7: completed 10000 read accesses @3928880
|
||||
system.cpu3: completed 10000 read accesses @3934460
|
||||
system.cpu6: completed 10000 read accesses @3935850
|
||||
system.cpu4: completed 10000 read accesses @3946000
|
||||
system.cpu1: completed 10000 read accesses @3949880
|
||||
system.cpu5: completed 10000 read accesses @3967300
|
||||
system.cpu1: completed 20000 read accesses @7757400
|
||||
system.cpu0: completed 20000 read accesses @7813850
|
||||
system.cpu7: completed 20000 read accesses @7822110
|
||||
system.cpu5: completed 20000 read accesses @7829210
|
||||
system.cpu2: completed 20000 read accesses @7843670
|
||||
system.cpu3: completed 20000 read accesses @7845820
|
||||
system.cpu6: completed 20000 read accesses @7858990
|
||||
system.cpu4: completed 20000 read accesses @7910990
|
||||
system.cpu1: completed 30000 read accesses @11704120
|
||||
system.cpu0: completed 30000 read accesses @11727890
|
||||
system.cpu6: completed 30000 read accesses @11743280
|
||||
system.cpu5: completed 30000 read accesses @11745370
|
||||
system.cpu2: completed 30000 read accesses @11756280
|
||||
system.cpu7: completed 30000 read accesses @11778210
|
||||
system.cpu3: completed 30000 read accesses @11784640
|
||||
system.cpu4: completed 30000 read accesses @11880500
|
||||
system.cpu1: completed 40000 read accesses @15614450
|
||||
system.cpu0: completed 40000 read accesses @15634590
|
||||
system.cpu6: completed 40000 read accesses @15652430
|
||||
system.cpu7: completed 40000 read accesses @15693740
|
||||
system.cpu2: completed 40000 read accesses @15704970
|
||||
system.cpu5: completed 40000 read accesses @15719380
|
||||
system.cpu4: completed 40000 read accesses @15743020
|
||||
system.cpu3: completed 40000 read accesses @15752060
|
||||
system.cpu1: completed 50000 read accesses @19503290
|
||||
system.cpu6: completed 50000 read accesses @19564210
|
||||
system.cpu0: completed 50000 read accesses @19589810
|
||||
system.cpu7: completed 50000 read accesses @19637850
|
||||
system.cpu5: completed 50000 read accesses @19649100
|
||||
system.cpu2: completed 50000 read accesses @19656580
|
||||
system.cpu4: completed 50000 read accesses @19675040
|
||||
system.cpu3: completed 50000 read accesses @19751940
|
||||
system.cpu1: completed 60000 read accesses @23347410
|
||||
system.cpu2: completed 60000 read accesses @23488920
|
||||
system.cpu6: completed 60000 read accesses @23531160
|
||||
system.cpu5: completed 60000 read accesses @23535230
|
||||
system.cpu0: completed 60000 read accesses @23535670
|
||||
system.cpu7: completed 60000 read accesses @23550840
|
||||
system.cpu4: completed 60000 read accesses @23573690
|
||||
system.cpu3: completed 60000 read accesses @23767280
|
||||
system.cpu1: completed 70000 read accesses @27185170
|
||||
system.cpu2: completed 70000 read accesses @27435280
|
||||
system.cpu5: completed 70000 read accesses @27435560
|
||||
system.cpu0: completed 70000 read accesses @27469520
|
||||
system.cpu6: completed 70000 read accesses @27474180
|
||||
system.cpu7: completed 70000 read accesses @27485750
|
||||
system.cpu4: completed 70000 read accesses @27535930
|
||||
system.cpu3: completed 70000 read accesses @27613200
|
||||
system.cpu1: completed 80000 read accesses @31085850
|
||||
system.cpu2: completed 80000 read accesses @31338160
|
||||
system.cpu6: completed 80000 read accesses @31350620
|
||||
system.cpu0: completed 80000 read accesses @31358600
|
||||
system.cpu5: completed 80000 read accesses @31368420
|
||||
system.cpu7: completed 80000 read accesses @31416500
|
||||
system.cpu4: completed 80000 read accesses @31419350
|
||||
system.cpu3: completed 80000 read accesses @31455520
|
||||
system.cpu1: completed 90000 read accesses @35053840
|
||||
system.cpu2: completed 90000 read accesses @35240590
|
||||
system.cpu0: completed 90000 read accesses @35240750
|
||||
system.cpu6: completed 90000 read accesses @35256170
|
||||
system.cpu5: completed 90000 read accesses @35346540
|
||||
system.cpu7: completed 90000 read accesses @35372670
|
||||
system.cpu3: completed 90000 read accesses @35393860
|
||||
system.cpu4: completed 90000 read accesses @35404470
|
||||
system.cpu1: completed 100000 read accesses @38958200
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -5,11 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Mar 26 2011 14:06:20
|
||||
M5 started Mar 26 2011 22:00:43
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 39098820 because maximum number of loads reached
|
||||
Exiting @ tick 38958200 because maximum number of loads reached
|
||||
|
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 346136 # Number of bytes of host memory used
|
||||
host_seconds 306.11 # Real time elapsed on the host
|
||||
host_tick_rate 127726 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 334776 # Number of bytes of host memory used
|
||||
host_seconds 165.00 # Real time elapsed on the host
|
||||
host_tick_rate 236117 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.039099 # Number of seconds simulated
|
||||
sim_ticks 39098820 # Number of ticks simulated
|
||||
sim_seconds 0.038958 # Number of seconds simulated
|
||||
sim_ticks 38958200 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 53574 # number of write accesses completed
|
||||
system.cpu0.num_reads 99480 # number of read accesses completed
|
||||
system.cpu0.num_writes 53708 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99631 # number of read accesses completed
|
||||
system.cpu1.num_writes 53502 # number of write accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 53515 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99061 # number of read accesses completed
|
||||
system.cpu2.num_writes 53455 # number of write accesses completed
|
||||
system.cpu2.num_reads 99617 # number of read accesses completed
|
||||
system.cpu2.num_writes 53776 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98999 # number of read accesses completed
|
||||
system.cpu3.num_writes 53370 # number of write accesses completed
|
||||
system.cpu3.num_reads 98906 # number of read accesses completed
|
||||
system.cpu3.num_writes 53879 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99076 # number of read accesses completed
|
||||
system.cpu4.num_writes 53347 # number of write accesses completed
|
||||
system.cpu4.num_reads 99109 # number of read accesses completed
|
||||
system.cpu4.num_writes 53268 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99631 # number of read accesses completed
|
||||
system.cpu5.num_writes 53316 # number of write accesses completed
|
||||
system.cpu5.num_reads 99212 # number of read accesses completed
|
||||
system.cpu5.num_writes 53268 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99060 # number of read accesses completed
|
||||
system.cpu6.num_writes 53733 # number of write accesses completed
|
||||
system.cpu6.num_reads 99524 # number of read accesses completed
|
||||
system.cpu6.num_writes 53108 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99033 # number of read accesses completed
|
||||
system.cpu7.num_writes 53376 # number of write accesses completed
|
||||
system.cpu7.num_reads 99071 # number of read accesses completed
|
||||
system.cpu7.num_writes 53234 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -118,7 +118,7 @@ assoc=2
|
|||
latency=10
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
start_index_bit=0
|
||||
start_index_bit=6
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
|
@ -152,6 +152,7 @@ deadlock_threshold=500000
|
|||
icache=system.l1_cntrl0.L1IcacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
|
|
|
@ -34,29 +34,29 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/08/2011 17:51:05
|
||||
Real time: Mar/26/2011 22:00:44
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
Virtual_time_in_seconds: 0.23
|
||||
Virtual_time_in_minutes: 0.00383333
|
||||
Virtual_time_in_hours: 6.38889e-05
|
||||
Virtual_time_in_days: 2.66204e-06
|
||||
|
||||
Ruby_current_time: 267511
|
||||
Ruby_current_time: 268001
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 267511
|
||||
Ruby_cycles: 268001
|
||||
|
||||
mbytes_resident: 33.7617
|
||||
mbytes_total: 208.121
|
||||
resident_ratio: 0.162259
|
||||
mbytes_resident: 34.8828
|
||||
mbytes_total: 197.086
|
||||
resident_ratio: 0.177013
|
||||
|
||||
ruby_cycles_executed: [ 267512 ]
|
||||
ruby_cycles_executed: [ 268002 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
|
@ -66,17 +66,17 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.8225 | standard deviation: 1.14181 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 902 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 991 average: 15.8113 | standard deviation: 1.1344 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 66 910 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 6580 count: 954 average: 4444.74 | standard deviation: 1862.02 | 67 9 3 1 6 4 9 12 10 7 1 8 5 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1214 count: 48 average: 548.458 | standard deviation: 260.39 | 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 6135 count: 52 average: 4940.85 | standard deviation: 1334.03 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 6580 count: 854 average: 4633.53 | standard deviation: 1690.7 | 62 8 1 0 3 2 5 7 3 2 0 1 1 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 73 average: 12.8356 | standard deviation: 32.0687 | 0 17 17 15 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_L2Cache: [binsize: 8 max: 812 count: 13 average: 309.154 | standard deviation: 223.678 | 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 6580 count: 868 average: 4879.41 | standard deviation: 1307.99 | 0 0 1 1 4 2 7 12 10 6 1 8 4 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 64 max: 7191 count: 977 average: 4347.37 | standard deviation: 1873.72 | 65 10 4 2 10 4 11 8 8 10 4 4 5 3 3 2 3 1 0 2 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 3 1 4 11 9 14 15 17 20 30 32 30 37 40 32 35 26 42 36 36 35 33 31 25 28 28 22 21 22 13 11 14 6 7 10 5 5 5 5 2 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 64 max: 6460 count: 50 average: 4586.28 | standard deviation: 1763.78 | 3 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 0 1 3 0 1 0 0 2 1 2 1 3 1 1 3 0 3 1 1 1 1 1 1 1 2 0 3 2 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 64 max: 7191 count: 877 average: 4552.04 | standard deviation: 1688.95 | 60 8 2 1 4 2 3 5 3 1 2 1 2 1 2 1 2 1 0 2 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 2 1 3 9 9 13 12 17 19 30 32 28 36 38 31 32 25 41 33 36 32 32 30 24 27 27 21 20 20 13 8 12 6 5 10 4 5 5 4 2 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1070 count: 50 average: 518.7 | standard deviation: 237.384 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 5 1 0 0 2 0 0 0 0 0 0 0 1 2 1 2 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 2 2 1 3 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 118 count: 74 average: 15.527 | standard deviation: 35.3032 | 0 19 12 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 2 0 1 ]
|
||||
miss_latency_L2Cache: [binsize: 32 max: 6258 count: 47 average: 3122.72 | standard deviation: 2249.67 | 0 0 1 0 2 0 1 0 1 2 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 3 0 0 1 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 2 0 0 0 2 0 1 0 1 1 0 0 2 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 64 max: 7191 count: 856 average: 4789.1 | standard deviation: 1354.03 | 0 0 2 1 7 3 10 6 8 10 4 4 4 0 3 0 2 1 0 0 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 3 1 3 10 8 13 14 16 19 28 32 28 36 39 31 33 26 41 36 35 32 33 31 24 27 28 21 21 22 13 11 14 5 6 10 4 5 5 5 2 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
@ -86,15 +86,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
|
|||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 868
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 108 count: 2 average: 55.5 | standard deviation: 74.2496 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 2 max: 359 count: 3 average: 181.333 | standard deviation: 165.7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1214 count: 43 average: 597 | standard deviation: 225.443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 3 average: 1.66667 | standard deviation: 0.707107 | 0 1 2 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 6135 count: 49 average: 5243.24 | standard deviation: 522.306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 68 average: 12.0735 | standard deviation: 31.0217 | 0 16 15 14 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 2 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 8 max: 812 count: 10 average: 347.5 | standard deviation: 231.361 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 6580 count: 776 average: 5093.73 | standard deviation: 906.859 | 0 0 0 0 1 1 3 7 3 1 0 1 0 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 856
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 118 count: 5 average: 46.6 | standard deviation: 58.5747 | 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L2Cache: [binsize: 32 max: 6110 count: 3 average: 5432.67 | standard deviation: 624.405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 64 max: 6460 count: 42 average: 5066.26 | standard deviation: 947.048 | 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 0 1 3 0 1 0 0 2 1 2 0 3 1 1 3 0 2 1 1 1 1 1 1 1 2 0 3 2 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 116 count: 67 average: 13.6119 | standard deviation: 32.9867 | 0 18 12 15 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 2 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 32 max: 6258 count: 39 average: 3264.08 | standard deviation: 2198.62 | 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 2 0 0 0 2 0 1 0 1 0 0 0 2 0 0 1 0 0 0 0 1 0 2 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 64 max: 7191 count: 771 average: 5011.58 | standard deviation: 958.595 | 0 0 1 0 2 1 2 3 3 1 2 1 1 0 2 0 1 1 0 0 0 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 1 0 2 2 1 2 8 8 12 11 16 18 28 32 26 35 37 31 30 25 40 33 35 30 32 30 23 26 27 20 20 20 13 8 12 5 5 10 3 5 5 4 2 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2 | standard deviation: 1.41421 | 0 1 0 1 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 8 max: 960 count: 5 average: 634.2 | standard deviation: 383.132 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1070 count: 43 average: 529.302 | standard deviation: 193.252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 4 1 0 0 2 0 0 0 0 0 0 0 1 2 1 2 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 2 2 1 3 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
@ -126,125 +127,125 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9836
|
||||
page_reclaims: 9226
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 56
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Request_Control: 5259 42072
|
||||
total_msg_count_Response_Data: 2727 196344
|
||||
total_msg_count_ResponseL2hit_Data: 33 2376
|
||||
total_msg_count_Request_Control: 5307 42456
|
||||
total_msg_count_Response_Data: 2667 192024
|
||||
total_msg_count_ResponseL2hit_Data: 120 8640
|
||||
total_msg_count_Response_Control: 3 24
|
||||
total_msg_count_Writeback_Data: 5187 373464
|
||||
total_msg_count_Writeback_Control: 234 1872
|
||||
total_msg_count_Persistent_Control: 2388 19104
|
||||
total_msgs: 15831 total_bytes: 635256
|
||||
total_msg_count_Writeback_Data: 5190 373680
|
||||
total_msg_count_Writeback_Control: 207 1656
|
||||
total_msg_count_Persistent_Control: 2148 17184
|
||||
total_msgs: 15642 total_bytes: 635664
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.115486
|
||||
links_utilized_percent_switch_0_link_0: 0.0430356 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.187936 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.114279
|
||||
links_utilized_percent_switch_0_link_0: 0.0424765 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.186081 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 876 63072 [ 0 0 0 0 876 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Data: 56 4032 [ 0 0 0 0 56 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 904 7232 [ 0 904 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 13 936 [ 0 0 0 0 13 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 0 0 0 955 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0975123
|
||||
links_utilized_percent_switch_1_link_0: 0.0428627 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.152162 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.100049
|
||||
links_utilized_percent_switch_1_link_0: 0.0436239 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.156473 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 904 7232 [ 0 904 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 899 64728 [ 0 0 0 0 899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 865 6920 [ 0 0 865 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 768 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 69 552 [ 0 0 0 0 69 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.0934167
|
||||
links_utilized_percent_switch_2_link_0: 0.0396432 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.14719 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.0920053
|
||||
links_utilized_percent_switch_2_link_0: 0.0391043 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.144906 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 865 6920 [ 0 0 865 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 13 936 [ 0 0 0 0 13 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 775 55800 [ 0 0 0 0 775 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 69 552 [ 0 0 0 0 69 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 856 61632 [ 0 0 0 0 856 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.164909
|
||||
links_utilized_percent_switch_3_link_0: 0.164704 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.171451 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.158573 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 0.164713
|
||||
links_utilized_percent_switch_3_link_0: 0.163227 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.174496 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.156417 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 876 63072 [ 0 0 0 0 876 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 40 2880 [ 0 0 0 0 40 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Data: 56 4032 [ 0 0 0 0 56 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 904 7232 [ 0 904 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 899 64728 [ 0 0 0 0 899 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 865 6920 [ 0 0 865 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 13 936 [ 0 0 0 0 13 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 775 55800 [ 0 0 0 0 775 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 69 552 [ 0 0 0 0 69 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Persistent_Control: 358 2864 [ 0 0 0 358 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1IcacheMemory
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 46
|
||||
system.l1_cntrl0.L1IcacheMemory_total_misses: 48
|
||||
system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 48
|
||||
system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
|
||||
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 46 100%
|
||||
system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 48 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L1DcacheMemory
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 836
|
||||
system.l1_cntrl0.L1DcacheMemory_total_misses: 856
|
||||
system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 856
|
||||
system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.86124%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.1388%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.25701%
|
||||
system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.743%
|
||||
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 836 100%
|
||||
system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 856 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [52 ] 52
|
||||
Ifetch [48 ] 48
|
||||
Store [855 ] 855
|
||||
Load [50 ] 50
|
||||
Ifetch [50 ] 50
|
||||
Store [878 ] 878
|
||||
Atomic [0 ] 0
|
||||
L1_Replacement [19142 ] 19142
|
||||
Data_Shared [3 ] 3
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [976 ] 976
|
||||
Ack [1 ] 1
|
||||
Ack_All_Tokens [0 ] 0
|
||||
L1_Replacement [19825 ] 19825
|
||||
Data_Shared [5 ] 5
|
||||
Data_Owner [1 ] 1
|
||||
Data_All_Tokens [966 ] 966
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [1 ] 1
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_Local_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
|
@ -254,21 +255,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
|
|||
Persistent_GETX [0 ] 0
|
||||
Persistent_GETS [0 ] 0
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [398 ] 398
|
||||
Request_Timeout [783 ] 783
|
||||
Own_Lock_or_Unlock [358 ] 358
|
||||
Request_Timeout [599 ] 599
|
||||
Use_TimeoutStarverX [0 ] 0
|
||||
Use_TimeoutStarverS [0 ] 0
|
||||
Use_TimeoutNoStarvers [877 ] 877
|
||||
Use_TimeoutNoStarvers [896 ] 896
|
||||
Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NP Load [49 ] 49
|
||||
NP Ifetch [46 ] 46
|
||||
NP Store [787 ] 787
|
||||
NP Load [45 ] 45
|
||||
NP Ifetch [48 ] 48
|
||||
NP Store [811 ] 811
|
||||
NP Atomic [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
NP Data_All_Tokens [98 ] 98
|
||||
NP Data_All_Tokens [69 ] 69
|
||||
NP Ack [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_Local_GETX [0 ] 0
|
||||
|
@ -277,7 +278,7 @@ NP Transient_Local_GETS [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [190 ] 190
|
||||
NP Own_Lock_or_Unlock [176 ] 176
|
||||
|
||||
I Load [0 ] 0
|
||||
I Ifetch [0 ] 0
|
||||
|
@ -300,10 +301,10 @@ I Persistent_GETS_Last_Token [0 ] 0
|
|||
I Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [2 ] 2
|
||||
S Ifetch [0 ] 0
|
||||
S Store [0 ] 0
|
||||
S Atomic [0 ] 0
|
||||
S L1_Replacement [3 ] 3
|
||||
S L1_Replacement [5 ] 5
|
||||
S Data_Shared [0 ] 0
|
||||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
|
@ -340,74 +341,74 @@ O Persistent_GETS_Last_Token [0 ] 0
|
|||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
M Ifetch [2 ] 2
|
||||
M Store [0 ] 0
|
||||
M Atomic [0 ] 0
|
||||
M L1_Replacement [88 ] 88
|
||||
M L1_Replacement [85 ] 85
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_Local_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M Transient_Local_GETS [0 ] 0
|
||||
M Persistent_GETX [0 ] 0
|
||||
M Persistent_GETS [0 ] 0
|
||||
M Own_Lock_or_Unlock [15 ] 15
|
||||
M Own_Lock_or_Unlock [11 ] 11
|
||||
|
||||
MM Load [2 ] 2
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [0 ] 0
|
||||
MM Store [57 ] 57
|
||||
MM Store [59 ] 59
|
||||
MM Atomic [0 ] 0
|
||||
MM L1_Replacement [786 ] 786
|
||||
MM L1_Replacement [809 ] 809
|
||||
MM Transient_GETX [0 ] 0
|
||||
MM Transient_Local_GETX [0 ] 0
|
||||
MM Transient_GETS [0 ] 0
|
||||
MM Transient_Local_GETS [0 ] 0
|
||||
MM Persistent_GETX [0 ] 0
|
||||
MM Persistent_GETS [0 ] 0
|
||||
MM Own_Lock_or_Unlock [15 ] 15
|
||||
MM Own_Lock_or_Unlock [13 ] 13
|
||||
|
||||
M_W Load [1 ] 1
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
M_W Store [1 ] 1
|
||||
M_W Atomic [0 ] 0
|
||||
M_W L1_Replacement [396 ] 396
|
||||
M_W L1_Replacement [376 ] 376
|
||||
M_W Transient_GETX [0 ] 0
|
||||
M_W Transient_Local_GETX [0 ] 0
|
||||
M_W Transient_GETS [0 ] 0
|
||||
M_W Transient_Local_GETS [0 ] 0
|
||||
M_W Persistent_GETX [0 ] 0
|
||||
M_W Persistent_GETS [0 ] 0
|
||||
M_W Own_Lock_or_Unlock [1 ] 1
|
||||
M_W Own_Lock_or_Unlock [3 ] 3
|
||||
M_W Use_TimeoutStarverX [0 ] 0
|
||||
M_W Use_TimeoutStarverS [0 ] 0
|
||||
M_W Use_TimeoutNoStarvers [90 ] 90
|
||||
M_W Use_TimeoutNoStarvers [86 ] 86
|
||||
M_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Load [1 ] 1
|
||||
MM_W Ifetch [0 ] 0
|
||||
MM_W Store [10 ] 10
|
||||
MM_W Store [7 ] 7
|
||||
MM_W Atomic [0 ] 0
|
||||
MM_W L1_Replacement [7395 ] 7395
|
||||
MM_W L1_Replacement [7825 ] 7825
|
||||
MM_W Transient_GETX [0 ] 0
|
||||
MM_W Transient_Local_GETX [0 ] 0
|
||||
MM_W Transient_GETS [0 ] 0
|
||||
MM_W Transient_Local_GETS [0 ] 0
|
||||
MM_W Persistent_GETX [0 ] 0
|
||||
MM_W Persistent_GETS [0 ] 0
|
||||
MM_W Own_Lock_or_Unlock [25 ] 25
|
||||
MM_W Own_Lock_or_Unlock [18 ] 18
|
||||
MM_W Use_TimeoutStarverX [0 ] 0
|
||||
MM_W Use_TimeoutStarverS [0 ] 0
|
||||
MM_W Use_TimeoutNoStarvers [787 ] 787
|
||||
MM_W Use_TimeoutNoStarvers [810 ] 810
|
||||
MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
IM Store [0 ] 0
|
||||
IM Atomic [0 ] 0
|
||||
IM L1_Replacement [9791 ] 9791
|
||||
IM L1_Replacement [10209 ] 10209
|
||||
IM Data_Shared [0 ] 0
|
||||
IM Data_Owner [0 ] 0
|
||||
IM Data_All_Tokens [786 ] 786
|
||||
IM Ack [1 ] 1
|
||||
IM Data_Owner [1 ] 1
|
||||
IM Data_All_Tokens [809 ] 809
|
||||
IM Ack [0 ] 0
|
||||
IM Transient_GETX [0 ] 0
|
||||
IM Transient_Local_GETX [0 ] 0
|
||||
IM Transient_GETS [0 ] 0
|
||||
|
@ -417,8 +418,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IM Persistent_GETX [0 ] 0
|
||||
IM Persistent_GETS [0 ] 0
|
||||
IM Persistent_GETS_Last_Token [0 ] 0
|
||||
IM Own_Lock_or_Unlock [135 ] 135
|
||||
IM Request_Timeout [709 ] 709
|
||||
IM Own_Lock_or_Unlock [122 ] 122
|
||||
IM Request_Timeout [523 ] 523
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
|
@ -449,7 +450,7 @@ OM L1_Replacement [0 ] 0
|
|||
OM Data_Shared [0 ] 0
|
||||
OM Data_All_Tokens [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM Ack_All_Tokens [0 ] 0
|
||||
OM Ack_All_Tokens [1 ] 1
|
||||
OM Transient_GETX [0 ] 0
|
||||
OM Transient_Local_GETX [0 ] 0
|
||||
OM Transient_GETS [0 ] 0
|
||||
|
@ -459,17 +460,17 @@ OM Transient_Local_GETS_Last_Token [0 ] 0
|
|||
OM Persistent_GETX [0 ] 0
|
||||
OM Persistent_GETS [0 ] 0
|
||||
OM Persistent_GETS_Last_Token [0 ] 0
|
||||
OM Own_Lock_or_Unlock [0 ] 0
|
||||
OM Request_Timeout [0 ] 0
|
||||
OM Own_Lock_or_Unlock [1 ] 1
|
||||
OM Request_Timeout [1 ] 1
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
IS Store [0 ] 0
|
||||
IS Atomic [0 ] 0
|
||||
IS L1_Replacement [683 ] 683
|
||||
IS Data_Shared [3 ] 3
|
||||
IS L1_Replacement [516 ] 516
|
||||
IS Data_Shared [5 ] 5
|
||||
IS Data_Owner [0 ] 0
|
||||
IS Data_All_Tokens [92 ] 92
|
||||
IS Data_All_Tokens [88 ] 88
|
||||
IS Ack [0 ] 0
|
||||
IS Transient_GETX [0 ] 0
|
||||
IS Transient_Local_GETX [0 ] 0
|
||||
|
@ -480,8 +481,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0
|
|||
IS Persistent_GETX [0 ] 0
|
||||
IS Persistent_GETS [0 ] 0
|
||||
IS Persistent_GETS_Last_Token [0 ] 0
|
||||
IS Own_Lock_or_Unlock [17 ] 17
|
||||
IS Request_Timeout [74 ] 74
|
||||
IS Own_Lock_or_Unlock [14 ] 14
|
||||
IS Request_Timeout [75 ] 75
|
||||
|
||||
I_L Load [0 ] 0
|
||||
I_L Ifetch [0 ] 0
|
||||
|
@ -585,50 +586,50 @@ IS_L Own_Lock_or_Unlock [0 ] 0
|
|||
IS_L Request_Timeout [0 ] 0
|
||||
|
||||
Cache Stats: system.l2_cntrl0.L2cacheMemory
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 871
|
||||
system.l2_cntrl0.L2cacheMemory_total_misses: 865
|
||||
system.l2_cntrl0.L2cacheMemory_total_demand_misses: 865
|
||||
system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.5626%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4374%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.1734%
|
||||
system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.8266%
|
||||
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 871 100%
|
||||
system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 865 100%
|
||||
|
||||
--- L2Cache ---
|
||||
- Event Counts -
|
||||
L1_GETS [95 ] 95
|
||||
L1_GETS [93 ] 93
|
||||
L1_GETS_Last_Token [0 ] 0
|
||||
L1_GETX [787 ] 787
|
||||
L1_GETX [811 ] 811
|
||||
L1_INV [0 ] 0
|
||||
Transient_GETX [0 ] 0
|
||||
Transient_GETS [0 ] 0
|
||||
Transient_GETS_Last_Token [0 ] 0
|
||||
L2_Replacement [799 ] 799
|
||||
L2_Replacement [807 ] 807
|
||||
Writeback_Tokens [0 ] 0
|
||||
Writeback_Shared_Data [3 ] 3
|
||||
Writeback_All_Tokens [874 ] 874
|
||||
Writeback_Shared_Data [2 ] 2
|
||||
Writeback_All_Tokens [897 ] 897
|
||||
Writeback_Owned [0 ] 0
|
||||
Data_Shared [0 ] 0
|
||||
Data_Owner [0 ] 0
|
||||
Data_All_Tokens [0 ] 0
|
||||
Ack [0 ] 0
|
||||
Ack_All_Tokens [0 ] 0
|
||||
Persistent_GETX [179 ] 179
|
||||
Persistent_GETS [20 ] 20
|
||||
Persistent_GETX [160 ] 160
|
||||
Persistent_GETS [19 ] 19
|
||||
Persistent_GETS_Last_Token [0 ] 0
|
||||
Own_Lock_or_Unlock [199 ] 199
|
||||
Own_Lock_or_Unlock [179 ] 179
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS [92 ] 92
|
||||
NP L1_GETX [777 ] 777
|
||||
NP L1_GETS [85 ] 85
|
||||
NP L1_GETX [774 ] 774
|
||||
NP L1_INV [0 ] 0
|
||||
NP Transient_GETX [0 ] 0
|
||||
NP Transient_GETS [0 ] 0
|
||||
NP Writeback_Tokens [0 ] 0
|
||||
NP Writeback_Shared_Data [3 ] 3
|
||||
NP Writeback_All_Tokens [798 ] 798
|
||||
NP Writeback_Shared_Data [1 ] 1
|
||||
NP Writeback_All_Tokens [810 ] 810
|
||||
NP Writeback_Owned [0 ] 0
|
||||
NP Data_Shared [0 ] 0
|
||||
NP Data_Owner [0 ] 0
|
||||
|
@ -637,19 +638,19 @@ NP Ack [0 ] 0
|
|||
NP Persistent_GETX [0 ] 0
|
||||
NP Persistent_GETS [0 ] 0
|
||||
NP Persistent_GETS_Last_Token [0 ] 0
|
||||
NP Own_Lock_or_Unlock [181 ] 181
|
||||
NP Own_Lock_or_Unlock [159 ] 159
|
||||
|
||||
I L1_GETS [0 ] 0
|
||||
I L1_GETS [3 ] 3
|
||||
I L1_GETS_Last_Token [0 ] 0
|
||||
I L1_GETX [0 ] 0
|
||||
I L1_GETX [2 ] 2
|
||||
I L1_INV [0 ] 0
|
||||
I Transient_GETX [0 ] 0
|
||||
I Transient_GETS [0 ] 0
|
||||
I Transient_GETS_Last_Token [0 ] 0
|
||||
I L2_Replacement [24 ] 24
|
||||
I L2_Replacement [18 ] 18
|
||||
I Writeback_Tokens [0 ] 0
|
||||
I Writeback_Shared_Data [0 ] 0
|
||||
I Writeback_All_Tokens [3 ] 3
|
||||
I Writeback_Shared_Data [1 ] 1
|
||||
I Writeback_All_Tokens [35 ] 35
|
||||
I Writeback_Owned [0 ] 0
|
||||
I Data_Shared [0 ] 0
|
||||
I Data_Owner [0 ] 0
|
||||
|
@ -662,12 +663,12 @@ I Own_Lock_or_Unlock [0 ] 0
|
|||
|
||||
S L1_GETS [0 ] 0
|
||||
S L1_GETS_Last_Token [0 ] 0
|
||||
S L1_GETX [1 ] 1
|
||||
S L1_GETX [0 ] 0
|
||||
S L1_INV [0 ] 0
|
||||
S Transient_GETX [0 ] 0
|
||||
S Transient_GETS [0 ] 0
|
||||
S Transient_GETS_Last_Token [0 ] 0
|
||||
S L2_Replacement [2 ] 2
|
||||
S L2_Replacement [1 ] 1
|
||||
S Writeback_Tokens [0 ] 0
|
||||
S Writeback_Shared_Data [0 ] 0
|
||||
S Writeback_All_Tokens [0 ] 0
|
||||
|
@ -676,22 +677,22 @@ S Data_Shared [0 ] 0
|
|||
S Data_Owner [0 ] 0
|
||||
S Data_All_Tokens [0 ] 0
|
||||
S Ack [0 ] 0
|
||||
S Persistent_GETX [0 ] 0
|
||||
S Persistent_GETX [1 ] 1
|
||||
S Persistent_GETS [0 ] 0
|
||||
S Persistent_GETS_Last_Token [0 ] 0
|
||||
S Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
O L1_GETS [0 ] 0
|
||||
O L1_GETS_Last_Token [0 ] 0
|
||||
O L1_GETX [0 ] 0
|
||||
O L1_GETX [1 ] 1
|
||||
O L1_INV [0 ] 0
|
||||
O Transient_GETX [0 ] 0
|
||||
O Transient_GETS [0 ] 0
|
||||
O Transient_GETS_Last_Token [0 ] 0
|
||||
O L2_Replacement [3 ] 3
|
||||
O L2_Replacement [1 ] 1
|
||||
O Writeback_Tokens [0 ] 0
|
||||
O Writeback_Shared_Data [0 ] 0
|
||||
O Writeback_All_Tokens [0 ] 0
|
||||
O Writeback_All_Tokens [3 ] 3
|
||||
O Data_Shared [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Ack [0 ] 0
|
||||
|
@ -701,34 +702,34 @@ O Persistent_GETS [0 ] 0
|
|||
O Persistent_GETS_Last_Token [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
M L1_GETS [3 ] 3
|
||||
M L1_GETX [8 ] 8
|
||||
M L1_GETS [5 ] 5
|
||||
M L1_GETX [34 ] 34
|
||||
M L1_INV [0 ] 0
|
||||
M Transient_GETX [0 ] 0
|
||||
M Transient_GETS [0 ] 0
|
||||
M L2_Replacement [768 ] 768
|
||||
M Persistent_GETX [20 ] 20
|
||||
M Persistent_GETS [0 ] 0
|
||||
M L2_Replacement [786 ] 786
|
||||
M Persistent_GETX [17 ] 17
|
||||
M Persistent_GETS [3 ] 3
|
||||
M Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
I_L L1_GETS [0 ] 0
|
||||
I_L L1_GETX [1 ] 1
|
||||
I_L L1_GETX [0 ] 0
|
||||
I_L L1_INV [0 ] 0
|
||||
I_L Transient_GETX [0 ] 0
|
||||
I_L Transient_GETS [0 ] 0
|
||||
I_L Transient_GETS_Last_Token [0 ] 0
|
||||
I_L L2_Replacement [2 ] 2
|
||||
I_L L2_Replacement [1 ] 1
|
||||
I_L Writeback_Tokens [0 ] 0
|
||||
I_L Writeback_Shared_Data [0 ] 0
|
||||
I_L Writeback_All_Tokens [73 ] 73
|
||||
I_L Writeback_All_Tokens [49 ] 49
|
||||
I_L Writeback_Owned [0 ] 0
|
||||
I_L Data_Shared [0 ] 0
|
||||
I_L Data_Owner [0 ] 0
|
||||
I_L Data_All_Tokens [0 ] 0
|
||||
I_L Ack [0 ] 0
|
||||
I_L Persistent_GETX [159 ] 159
|
||||
I_L Persistent_GETS [20 ] 20
|
||||
I_L Own_Lock_or_Unlock [18 ] 18
|
||||
I_L Persistent_GETX [142 ] 142
|
||||
I_L Persistent_GETS [16 ] 16
|
||||
I_L Own_Lock_or_Unlock [20 ] 20
|
||||
|
||||
S_L L1_GETS [0 ] 0
|
||||
S_L L1_GETS_Last_Token [0 ] 0
|
||||
|
@ -752,79 +753,79 @@ S_L Persistent_GETS_Last_Token [0 ] 0
|
|||
S_L Own_Lock_or_Unlock [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1655
|
||||
memory_reads: 869
|
||||
memory_writes: 786
|
||||
memory_refreshes: 558
|
||||
memory_total_request_delays: 1116
|
||||
memory_delays_per_request: 0.67432
|
||||
memory_delays_in_input_queue: 156
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 957
|
||||
memory_stalls_for_bank_busy: 245
|
||||
memory_total_requests: 1638
|
||||
memory_reads: 857
|
||||
memory_writes: 781
|
||||
memory_refreshes: 559
|
||||
memory_total_request_delays: 1137
|
||||
memory_delays_per_request: 0.694139
|
||||
memory_delays_in_input_queue: 178
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 959
|
||||
memory_stalls_for_bank_busy: 158
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 76
|
||||
memory_stalls_for_bus: 363
|
||||
memory_stalls_for_arbitration: 113
|
||||
memory_stalls_for_bus: 401
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 197
|
||||
memory_stalls_for_read_read_turnaround: 76
|
||||
accesses_per_bank: 42 44 54 72 110 62 62 43 42 53 38 40 51 47 54 42 48 54 39 56 64 58 51 54 48 46 43 52 46 43 49 48
|
||||
memory_stalls_for_read_write_turnaround: 205
|
||||
memory_stalls_for_read_read_turnaround: 82
|
||||
accesses_per_bank: 43 36 45 82 56 68 39 49 63 53 46 57 46 44 30 48 52 45 51 51 50 54 52 58 33 59 64 54 43 63 43 61
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [807 ] 807
|
||||
GETS [92 ] 92
|
||||
Lockdown [199 ] 199
|
||||
Unlockdown [199 ] 199
|
||||
GETX [796 ] 796
|
||||
GETS [88 ] 88
|
||||
Lockdown [179 ] 179
|
||||
Unlockdown [179 ] 179
|
||||
Own_Lock_or_Unlock [0 ] 0
|
||||
Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
Data_Owner [3 ] 3
|
||||
Data_All_Tokens [790 ] 790
|
||||
Data_Owner [1 ] 1
|
||||
Data_All_Tokens [787 ] 787
|
||||
Ack_Owner [0 ] 0
|
||||
Ack_Owner_All_Tokens [76 ] 76
|
||||
Ack_Owner_All_Tokens [68 ] 68
|
||||
Tokens [0 ] 0
|
||||
Ack_All_Tokens [2 ] 2
|
||||
Ack_All_Tokens [1 ] 1
|
||||
Request_Timeout [0 ] 0
|
||||
Memory_Data [868 ] 868
|
||||
Memory_Ack [786 ] 786
|
||||
Memory_Data [856 ] 856
|
||||
Memory_Ack [781 ] 781
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
O GETX [773 ] 773
|
||||
O GETS [90 ] 90
|
||||
O Lockdown [5 ] 5
|
||||
O GETX [766 ] 766
|
||||
O GETS [85 ] 85
|
||||
O Lockdown [6 ] 6
|
||||
O Unlockdown [0 ] 0
|
||||
O Own_Lock_or_Unlock [0 ] 0
|
||||
O Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
O Data_Owner [0 ] 0
|
||||
O Data_All_Tokens [0 ] 0
|
||||
O Tokens [0 ] 0
|
||||
O Ack_All_Tokens [2 ] 2
|
||||
O Ack_All_Tokens [1 ] 1
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
NO GETX [2 ] 2
|
||||
NO GETS [2 ] 2
|
||||
NO Lockdown [180 ] 180
|
||||
NO GETX [9 ] 9
|
||||
NO GETS [3 ] 3
|
||||
NO Lockdown [162 ] 162
|
||||
NO Unlockdown [0 ] 0
|
||||
NO Own_Lock_or_Unlock [0 ] 0
|
||||
NO Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
NO Data_Owner [3 ] 3
|
||||
NO Data_All_Tokens [783 ] 783
|
||||
NO Data_Owner [1 ] 1
|
||||
NO Data_All_Tokens [780 ] 780
|
||||
NO Ack_Owner [0 ] 0
|
||||
NO Ack_Owner_All_Tokens [76 ] 76
|
||||
NO Ack_Owner_All_Tokens [68 ] 68
|
||||
NO Tokens [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
|
||||
L GETX [4 ] 4
|
||||
L GETX [2 ] 2
|
||||
L GETS [0 ] 0
|
||||
L Lockdown [0 ] 0
|
||||
L Unlockdown [199 ] 199
|
||||
L Unlockdown [179 ] 179
|
||||
L Own_Lock_or_Unlock [0 ] 0
|
||||
L Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
L Data_Owner [0 ] 0
|
||||
|
@ -838,7 +839,7 @@ L DMA_WRITE_All_Tokens [0 ] 0
|
|||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
O_W Lockdown [1 ] 1
|
||||
O_W Lockdown [0 ] 0
|
||||
O_W Unlockdown [0 ] 0
|
||||
O_W Own_Lock_or_Unlock [0 ] 0
|
||||
O_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
@ -848,12 +849,12 @@ O_W Ack_Owner [0 ] 0
|
|||
O_W Tokens [0 ] 0
|
||||
O_W Ack_All_Tokens [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W Memory_Ack [785 ] 785
|
||||
O_W Memory_Ack [781 ] 781
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
||||
L_O_W GETX [28 ] 28
|
||||
L_O_W GETX [19 ] 19
|
||||
L_O_W GETS [0 ] 0
|
||||
L_O_W Lockdown [0 ] 0
|
||||
L_O_W Unlockdown [0 ] 0
|
||||
|
@ -865,7 +866,7 @@ L_O_W Ack_Owner [0 ] 0
|
|||
L_O_W Tokens [0 ] 0
|
||||
L_O_W Ack_All_Tokens [0 ] 0
|
||||
L_O_W Memory_Data [6 ] 6
|
||||
L_O_W Memory_Ack [1 ] 1
|
||||
L_O_W Memory_Ack [0 ] 0
|
||||
L_O_W DMA_READ [0 ] 0
|
||||
L_O_W DMA_WRITE [0 ] 0
|
||||
L_O_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
@ -881,7 +882,7 @@ L_NO_W Data_All_Tokens [0 ] 0
|
|||
L_NO_W Ack_Owner [0 ] 0
|
||||
L_NO_W Tokens [0 ] 0
|
||||
L_NO_W Ack_All_Tokens [0 ] 0
|
||||
L_NO_W Memory_Data [13 ] 13
|
||||
L_NO_W Memory_Data [11 ] 11
|
||||
L_NO_W DMA_READ [0 ] 0
|
||||
L_NO_W DMA_WRITE [0 ] 0
|
||||
L_NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
@ -922,7 +923,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0
|
|||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
NO_W Lockdown [13 ] 13
|
||||
NO_W Lockdown [11 ] 11
|
||||
NO_W Unlockdown [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock [0 ] 0
|
||||
NO_W Own_Lock_or_Unlock_Tokens [0 ] 0
|
||||
|
@ -931,7 +932,7 @@ NO_W Data_All_Tokens [0 ] 0
|
|||
NO_W Ack_Owner [0 ] 0
|
||||
NO_W Tokens [0 ] 0
|
||||
NO_W Ack_All_Tokens [0 ] 0
|
||||
NO_W Memory_Data [849 ] 849
|
||||
NO_W Memory_Data [839 ] 839
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W DMA_WRITE_All_Tokens [0 ] 0
|
||||
|
|
|
@ -5,11 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:50:56
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:51:05
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Mar 26 2011 14:06:20
|
||||
M5 started Mar 26 2011 22:00:43
|
||||
M5 executing on phenom
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 267511 because Ruby Tester completed
|
||||
Exiting @ tick 268001 because Ruby Tester completed
|
||||
|
|
|
@ -1,10 +1,10 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213120 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_tick_rate 1663377 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 201820 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_tick_rate 910825 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000268 # Number of seconds simulated
|
||||
sim_ticks 267511 # Number of ticks simulated
|
||||
sim_ticks 268001 # Number of ticks simulated
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
Loading…
Reference in a new issue