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mips: cleanup ISA-specific code

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***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
 anyway.
This commit is contained in:
Korey Sewell 2011-03-26 09:23:52 -04:00
parent 48b58b3332
commit e0fdd86fd9
13 changed files with 57 additions and 158 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/arch/alpha/isa.hh
View file

@ -90,14 +90,6 @@ namespace AlphaISA
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu)
{ }
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
{ }
int
flattenIntIndex(int reg)
{

5
src/arch/alpha/types.hh
View file

@ -51,11 +51,6 @@ enum annotes
ITOUCH_ANNOTE = 0xffffffff,
};
struct CoreSpecific
{
int core_type;
};
} // namespace AlphaISA
#endif // __ARCH_ALPHA_TYPES_HH__

4
src/arch/arm/types.hh
View file

@ -497,10 +497,6 @@ namespace ArmISA
}
}
struct CoreSpecific {
// Empty for now on the ARM
};
} // namespace ArmISA
namespace __hash_namespace {

67
src/arch/mips/isa.cc
View file

@ -86,14 +86,11 @@ ISA::miscRegNames[NumMiscRegs] =
"LLFlag"
};
ISA::ISA()
ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
{
init();
}
numThreads = num_threads;
numVpes = num_vpes;
void
ISA::init()
{
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
@ -107,21 +104,7 @@ ISA::init()
for (int i = 0; i < NumMiscRegs; i++) {
miscRegFile_WriteMask[i].push_back(0);
}
clear(0);
}
void
ISA::clear(unsigned tid_or_vpn)
{
for(int i = 0; i < NumMiscRegs; i++) {
miscRegFile[i][tid_or_vpn] = 0;
miscRegFile_WriteMask[i][tid_or_vpn] = (long unsigned int)(-1);
}
}
void
ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
{
// Initialize all Per-VPE regs
uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
@ -134,8 +117,8 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
};
uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
for (int i = 0; i < num_vpe_regs; i++) {
if (num_vpes > 1) {
miscRegFile[per_vpe_regs[i]].resize(num_vpes);
if (numVpes > 1) {
miscRegFile[per_vpe_regs[i]].resize(numVpes);
}
bankType[per_vpe_regs[i]] = perVirtProcessor;
}
@ -151,28 +134,34 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
for (int i = 0; i < num_tc_regs; i++) {
miscRegFile[per_tc_regs[i]].resize(num_threads);
miscRegFile[per_tc_regs[i]].resize(numThreads);
bankType[per_tc_regs[i]] = perThreadContext;
}
if (num_vpes > 1) {
for (int i=1; i < num_vpes; i++) {
clear(i);
}
}
clear();
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
ISA::reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *cpu)
ISA::clear()
{
for(int i = 0; i < NumMiscRegs; i++) {
for (int j = 0; j < miscRegFile[i].size(); j++)
miscRegFile[i][j] = 0;
for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
}
}
void
ISA::configCP()
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
num_threads, num_vpes);
numThreads, numVpes);
MipsISA::CoreSpecific &cp = cpu->coreParams;
CoreSpecific cp;
panic("CP state must be set before the following code is used");
// Do Default CP0 initialization HERE
@ -350,8 +339,8 @@ ISA::reset(std::string core_name, ThreadID num_threads,
// MVPConf0
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
mvpConf0.tca = 1;
mvpConf0.pvpe = num_vpes - 1;
mvpConf0.ptc = num_threads - 1;
mvpConf0.pvpe = numVpes - 1;
mvpConf0.ptc = numThreads - 1;
setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
// VPEConf0
@ -360,7 +349,7 @@ ISA::reset(std::string core_name, ThreadID num_threads,
setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
// TCBind
for (ThreadID tid = 0; tid < num_threads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
tcBind.curTC = tid;
setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
@ -377,7 +366,7 @@ ISA::reset(std::string core_name, ThreadID num_threads,
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
// Set Dynamically Allocatable bit to 1 for all other threads
for (ThreadID tid = 1; tid < num_threads; tid++) {
for (ThreadID tid = 1; tid < numThreads; tid++) {
tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
tcStatus.da = 1;
setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);

15
src/arch/mips/isa.hh
View file

@ -54,6 +54,10 @@ namespace MipsISA
typedef ISA CP0;
protected:
// Number of threads and vpes an individual ISA state can handle
uint8_t numThreads;
uint8_t numVpes;
enum BankType {
perProcessor,
perThreadContext,
@ -65,16 +69,11 @@ namespace MipsISA
std::vector<BankType> bankType;
public:
ISA();
ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
void init();
void clear();
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *cpu);
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
void configCP();
unsigned getVPENum(ThreadID tid);

30
src/arch/mips/types.hh
View file

@ -77,13 +77,28 @@ enum RoundMode{
};
struct CoreSpecific {
/* Note: It looks like it will be better to allow simulator users
to specify the values of individual variables instead of requiring
users to define the values of entire registers
Especially since a lot of these variables can be created from other
user parameters (cache descriptions)
-jpp
*/
CoreSpecific()
: CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
CP0_Config2(0), CP0_Config3(0)
{ }
// MIPS CP0 State - First individual variables
// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
// Volume III (PRA)
@ -149,5 +164,4 @@ struct CoreSpecific {
};
} // namespace MipsISA
#endif

4
src/arch/power/types.hh
View file

@ -87,10 +87,6 @@ typedef GenericISA::SimplePCState<MachInst> PCState;
// typedef int RegContextParam;
// typedef int RegContextVal;
struct CoreSpecific {
};
} // PowerISA namspace
namespace __hash_namespace {

5
src/arch/sparc/types.hh
View file

@ -45,11 +45,6 @@ typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
typedef Twin64_t LargestRead;
struct CoreSpecific
{
int core_type;
};
}
#endif

3
src/arch/x86/types.hh
View file

@ -278,9 +278,6 @@ namespace X86ISA
}
};
struct CoreSpecific {
int core_type;
};
};
namespace __hash_namespace {

56
src/cpu/BaseCPU.py
View file

@ -199,59 +199,3 @@ class BaseCPU(MemObject):
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
self._cached_ports = ['l2cache.mem_side']
if buildEnv['TARGET_ISA'] == 'mips':
CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
CP0_Config_AT = Param.Unsigned(0,"No Description")
CP0_Config_AR = Param.Unsigned(0,"No Description")
CP0_Config_MT = Param.Unsigned(0,"No Description")
CP0_Config_VI = Param.Unsigned(0,"No Description")
CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
CP0_Config1_IS = Param.Unsigned(0,"No Description")
CP0_Config1_IL = Param.Unsigned(0,"No Description")
CP0_Config1_IA = Param.Unsigned(0,"No Description")
CP0_Config1_DS = Param.Unsigned(0,"No Description")
CP0_Config1_DL = Param.Unsigned(0,"No Description")
CP0_Config1_DA = Param.Unsigned(0,"No Description")
CP0_Config1_C2 = Param.Bool(False,"No Description")
CP0_Config1_MD = Param.Bool(False,"No Description")
CP0_Config1_PC = Param.Bool(False,"No Description")
CP0_Config1_WR = Param.Bool(False,"No Description")
CP0_Config1_CA = Param.Bool(False,"No Description")
CP0_Config1_EP = Param.Bool(False,"No Description")
CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
CP0_Config2_TU = Param.Unsigned(0,"No Description")
CP0_Config2_TS = Param.Unsigned(0,"No Description")
CP0_Config2_TL = Param.Unsigned(0,"No Description")
CP0_Config2_TA = Param.Unsigned(0,"No Description")
CP0_Config2_SU = Param.Unsigned(0,"No Description")
CP0_Config2_SS = Param.Unsigned(0,"No Description")
CP0_Config2_SL = Param.Unsigned(0,"No Description")
CP0_Config2_SA = Param.Unsigned(0,"No Description")
CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
CP0_Config3_LPA = Param.Bool(False,"No Description")
CP0_Config3_VEIC = Param.Bool(False,"No Description")
CP0_Config3_VInt = Param.Bool(False,"No Description")
CP0_Config3_SP = Param.Bool(False,"No Description")
CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
CP0_Config3_SM = Param.Bool(False,"No Description")
CP0_Config3_TL = Param.Bool(False,"No Description")
CP0_WatchHi_M = Param.Bool(False,"No Description")
CP0_PerfCtr_M = Param.Bool(False,"No Description")
CP0_PerfCtr_W = Param.Bool(False,"No Description")
CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
CP0_Config = Param.Unsigned(0,"CP0 Config Register")
CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")

2
src/cpu/base.hh
View file

@ -239,8 +239,6 @@ class BaseCPU : public MemObject
*/
ThreadID numThreads;
TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
/**
* Vector of per-thread instruction-based event queues. Used for
* scheduling events based on number of instructions committed by

13
src/cpu/inorder/cpu.cc
View file

@ -315,8 +315,6 @@ InOrderCPU::InOrderCPU(Params *params)
memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
isa[tid].clear();
isa[tid].expandForMultithreading(numThreads, 1/*numVirtProcs*/);
// Define dummy instructions and resource requests to be used.
dummyInst[tid] = new InOrderDynInst(this,
thread[tid],
@ -344,8 +342,6 @@ InOrderCPU::InOrderCPU(Params *params)
#if FULL_SYSTEM
Fault resetFault = new ResetFault();
resetFault->invoke(tcBase());
#else
reset();
#endif
@ -696,15 +692,6 @@ InOrderCPU::init()
resPool->init();
}
void
InOrderCPU::reset()
{
for (int i = 0; i < numThreads; i++) {
isa[i].reset(coreType, numThreads,
1/*numVirtProcs*/, dynamic_cast<BaseCPU*>(this));
}
}
Port*
InOrderCPU::getPort(const std::string &if_name, int idx)
{

3
src/cpu/inorder/cpu.hh
View file

@ -395,9 +395,6 @@ class InOrderCPU : public BaseCPU
/** Initialize the CPU */
void init();
/** Reset State in the CPU */
void reset();
/** Get a Memory Port */
Port* getPort(const std::string &if_name, int idx = 0);