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ARM: Update the stats now that VFP load/store multiple is implemented.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:04 -05:00
parent 9ebaf8ecd5
commit d8294575e1
4 changed files with 15 additions and 17 deletions
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2
tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
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@ -58,7 +58,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864

2
tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr
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@ -1,5 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
warn: instruction 'fstmx' unimplemented
For more information see: http://www.m5sim.org/warn/21b09adb
hack: be nice to actually delete the event here

10
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
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@ -5,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 25 2010 04:11:39
M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
M5 started Feb 25 2010 04:11:44
M5 executing on SC2B0619
M5 compiled Feb 27 2010 16:56:18
M5 revision 6429cd018766 7083 default qtip vfpmacromemstats.patch tip
M5 started Feb 27 2010 16:56:19
M5 executing on tater
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 2748500 because target called exit()
Exiting @ tick 2756500 because target called exit()

18
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
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@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1074248 # Simulator instruction rate (inst/s)
host_mem_usage 180696 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 511253720 # Simulator tick rate (ticks/s)
host_inst_rate 15740 # Simulator instruction rate (inst/s)
host_mem_usage 201240 # Number of bytes of host memory used
host_seconds 0.35 # Real time elapsed on the host
host_tick_rate 7864008 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5498 # Number of instructions simulated
sim_insts 5514 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2748500 # Number of ticks simulated
sim_ticks 2756500 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
@ -28,9 +28,9 @@ system.cpu.itb.write_accesses 0 # DT
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5498 # number of cpu cycles simulated
system.cpu.num_insts 5498 # Number of instructions executed
system.cpu.num_refs 2127 # Number of memory references
system.cpu.numCycles 5514 # number of cpu cycles simulated
system.cpu.num_insts 5514 # Number of instructions executed
system.cpu.num_refs 2143 # Number of memory references
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------