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bp: fix up stats for changes to branch predictor

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This commit is contained in:
Ali Saidi 2012-02-13 12:30:30 -06:00
parent 9b05e96b9e
commit 0d46708dc2
88 changed files with 22752 additions and 22162 deletions
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8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
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@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:47:49
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 18:11:03
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 106949500
Exiting @ tick 1897464893500 because m5_exit instruction encountered
info: Launching CPU 1 @ 107002000
Exiting @ tick 1899401490000 because m5_exit instruction encountered

2752
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
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@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:47:47
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 18:10:30
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1859850554500 because m5_exit instruction encountered
Exiting @ tick 1858684403000 because m5_exit instruction encountered

1351
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
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@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:40:16
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 21:03:21
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2582494330500 because m5_exit instruction encountered
Exiting @ tick 2572328372500 because m5_exit instruction encountered

2708
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
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@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:39:00
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 21:01:11
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2503580880500 because m5_exit instruction encountered
Exiting @ tick 2503289265500 because m5_exit instruction encountered

1417
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
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@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 15:31:16
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 19:53:18
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5163317092500 because m5_exit instruction encountered
Exiting @ tick 5155288336500 because m5_exit instruction encountered

1558
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
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@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:10:21
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:26
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 274500333500 because target called exit()
Exiting @ tick 274300226500 because target called exit()

534
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
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@ -1,46 +1,46 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.274500 # Number of seconds simulated
sim_ticks 274500333500 # Number of ticks simulated
final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.274300 # Number of seconds simulated
sim_ticks 274300226500 # Number of ticks simulated
final_tick 274300226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 160535 # Simulator instruction rate (inst/s)
host_op_rate 160535 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 73218214 # Simulator tick rate (ticks/s)
host_inst_rate 157937 # Simulator instruction rate (inst/s)
host_op_rate 157937 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 71980747 # Simulator tick rate (ticks/s)
host_mem_usage 209892 # Number of bytes of host memory used
host_seconds 3749.07 # Real time elapsed on the host
host_seconds 3810.74 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5894016 # Number of bytes read from this memory
system.physmem.bytes_read 5894080 # Number of bytes read from this memory
system.physmem.bytes_inst_read 54720 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3798080 # Number of bytes written to this memory
system.physmem.num_reads 92094 # Number of read requests responded to by this memory
system.physmem.num_writes 59345 # Number of write requests responded to by this memory
system.physmem.bytes_written 3798144 # Number of bytes written to this memory
system.physmem.num_reads 92095 # Number of read requests responded to by this memory
system.physmem.num_writes 59346 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 21471799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 199344 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13836340 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 35308139 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 21487696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 199489 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13846667 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 35334364 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 114517568 # DTB read hits
system.cpu.dtb.read_hits 114517577 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 114520199 # DTB read accesses
system.cpu.dtb.write_hits 39666597 # DTB write hits
system.cpu.dtb.read_accesses 114520208 # DTB read accesses
system.cpu.dtb.write_hits 39666608 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 39668899 # DTB write accesses
system.cpu.dtb.data_hits 154184165 # DTB hits
system.cpu.dtb.write_accesses 39668910 # DTB write accesses
system.cpu.dtb.data_hits 154184185 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 154189098 # DTB accesses
system.cpu.itb.fetch_hits 27986226 # ITB hits
system.cpu.dtb.data_accesses 154189118 # DTB accesses
system.cpu.itb.fetch_hits 25020502 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 27986248 # ITB accesses
system.cpu.itb.fetch_accesses 25020524 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 549000668 # number of cpu cycles simulated
system.cpu.numCycles 548600454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 538371184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed.
system.cpu.activity 89.164571 # Percentage of cycles cpu is active
system.cpu.timesIdled 412150 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59439534 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 489160920 # Number of cycles cpu stages are processed.
system.cpu.activity 89.165242 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
@ -75,158 +75,158 @@ system.cpu.committedInsts 601856964 # Nu
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.911513 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads
system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.911513 # CPI: Total CPI of All Threads
system.cpu.ipc 1.097077 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits
system.cpu.ipc_total 1.097077 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 86318297 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 81372201 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 36359139 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 52872243 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 34320184 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 64.911534 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 36897167 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49421130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541659172 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 1005514018 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 161 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154582342 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 203 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 254972528 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 155051949 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 33760596 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2593556 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36354152 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26193756 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.122091 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 412334574 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage0.idleCycles 209725198 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 338875256 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 61.770867 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 237724577 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 310875877 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 56.667083 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 206774969 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 341825485 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.308641 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 437071966 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 111528488 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.329638 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 201598142 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 347002312 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 63.252283 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use
system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 728.232127 # Cycle average of tags in use
system.cpu.icache.total_refs 25019479 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 29262.548538 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 728.259897 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355596 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355596 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 27985205 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27985205 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27985205 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27985205 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27985205 # number of overall hits
system.cpu.icache.overall_hits::total 27985205 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1019 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1019 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1019 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1019 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1019 # number of overall misses
system.cpu.icache.overall_misses::total 1019 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56646500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 56646500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 56646500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 56646500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56646500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56646500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27986224 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27986224 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27986224 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27986224 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27986224 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27986224 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 728.232127 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.355582 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.355582 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 25019479 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 25019479 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 25019479 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 25019479 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 25019479 # number of overall hits
system.cpu.icache.overall_hits::total 25019479 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1021 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1021 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 1021 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 56709500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 56709500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 56709500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 56709500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 25020500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 25020500 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 25020500 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 25020500 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 25020500 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 25020500 # number of overall (read+write) accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55543.095005 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55543.095005 # average overall miss latency
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system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45774000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45774000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45774000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45774000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45774000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45774000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000031 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45765000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45765000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45765000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45765000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53526.315789 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53526.315789 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use
system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks.
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system.cpu.dcache.total_refs 152394215 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::cpu.data 0.999543 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999543 # Average percentage of cache occupancy
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system.cpu.dcache.warmup_cycle 267632000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.124914 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::total 0.999542 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 114120509 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114120509 # number of ReadReq hits
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system.cpu.dcache.demand_hits::total 152394244 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::total 152394244 # number of overall hits
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system.cpu.dcache.WriteReq_hits::total 38273706 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 152394215 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 393533 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 1177586 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 1571119 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 1571119 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 8150453500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 25245531000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 33395984500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 33395984500 # number of overall miss cycles
system.cpu.dcache.WriteReq_misses::cpu.data 1177615 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1177615 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 1571148 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1571148 # number of overall misses
system.cpu.dcache.overall_misses::total 1571148 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::total 8150462000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 25247540000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 33398002000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::total 33398002000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 153965363 # nu
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603 # average overall miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21439.553674 # average WriteReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 21257.069353 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 3424818500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2777 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 216268 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 15835.992842 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 408188 # number of writebacks
system.cpu.dcache.writebacks::total 408188 # number of writebacks
system.cpu.dcache.writebacks::writebacks 408190 # number of writebacks
system.cpu.dcache.writebacks::total 408190 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192301 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 192301 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 923423 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 923423 # number of WriteReq MSHR hits
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system.cpu.dcache.overall_mshr_hits::cpu.data 1115724 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1115724 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 1115753 # number of overall MSHR hits
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@ -269,75 +269,75 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_miss_latency::total 9028878000 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 3562095500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 9028960000 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.436650 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21509.285380 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.655980 # average overall mshr miss latency
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system.cpu.l2cache.replacements 73798 # number of replacements
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system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor
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system.cpu.l2cache.Writeback_hits::total 408188 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 194105 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 194105 # number of ReadExReq hits
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system.cpu.l2cache.ReadReq_hits::total 170049 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 194106 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 194106 # number of ReadExReq hits
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system.cpu.l2cache.overall_hits::cpu.data 364155 # number of overall hits
system.cpu.l2cache.overall_hits::total 364155 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 60075 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 60075 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 60076 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 60076 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 91239 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 92094 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 91240 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 92095 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 91239 # number of overall misses
system.cpu.l2cache.overall_misses::total 92094 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44769000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630148000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1674917000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134446000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3134446000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44769000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles
system.cpu.l2cache.overall_misses::cpu.data 91240 # number of overall misses
system.cpu.l2cache.overall_misses::total 92095 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44767500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630159000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1674926500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134429000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3134429000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44767500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 4764588000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 4809355500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44767500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 4764588000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 4809355500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 201213 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 202068 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254182 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 254182 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
@ -345,65 +345,65 @@ system.cpu.l2cache.overall_accesses::cpu.inst 855
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236350 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.200354 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked
system.cpu.l2cache.overall_miss_rate::cpu.data 0.200354 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52359.649123 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.042485 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52174.395765 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52359.649123 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52220.385796 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1278500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10066.929134 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks
system.cpu.l2cache.writebacks::total 59345 # number of writebacks
system.cpu.l2cache.writebacks::writebacks 59346 # number of writebacks
system.cpu.l2cache.writebacks::total 59346 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60076 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 60076 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 91240 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 92095 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 91240 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 92095 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246682000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281027000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406884500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406884500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653566500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 3687911500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653566500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 3687911500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236350 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200354 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.914773 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40063.993941 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40043.473257 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:10:26
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:40
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 144450185500 because target called exit()
Exiting @ tick 134621123500 because target called exit()

1024
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:39:44
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:00:24
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 177116942500 because target called exit()
Exiting @ tick 164280509500 because target called exit()

1067
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:33
gem5 started Feb 11 2012 13:56:12
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:18:25
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 408816360000 because target called exit()
Exiting @ tick 388554296500 because target called exit()

1004
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 14:08:06
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:30:36
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -19,9 +19,9 @@ info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
info: Increasing stack size by one page.
Compressed data 97831 bytes in length
Uncompressing Data
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
@ -40,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 586834596000 because target called exit()
Exiting @ tick 637054100000 because target called exit()

974
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:46:15
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:09:43
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 33080570000 because target called exit()
Exiting @ tick 30872383000 because target called exit()

1066
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 14:13:01
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:37:07
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,6 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 70046988500 because target called exit()
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Exiting @ tick 67367177000 because target called exit()

978
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:53:02
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:11:33
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 274128411000 because target called exit()
Exiting @ tick 237773144000 because target called exit()

1112
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

23
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,15 +1,28 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 14:22:59
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:44:57
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: ***********************info: Increasing stack size by one page.
**************************
***************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
***********
58924 words stored in 3784810 bytes
@ -21,10 +34,8 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@ -69,4 +80,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 488026375000 because target called exit()
Exiting @ tick 460107924500 because target called exit()

1017
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:10:43
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:34:00
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
@ -11,4 +11,4 @@ info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 139995113500 because target called exit()
Exiting @ tick 141175129500 because target called exit()

454
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,25 +1,25 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.139995 # Number of seconds simulated
sim_ticks 139995113500 # Number of ticks simulated
final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.141175 # Number of seconds simulated
sim_ticks 141175129500 # Number of ticks simulated
final_tick 141175129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 154307 # Simulator instruction rate (inst/s)
host_op_rate 154307 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 54186341 # Simulator tick rate (ticks/s)
host_mem_usage 215920 # Number of bytes of host memory used
host_seconds 2583.59 # Real time elapsed on the host
host_inst_rate 157275 # Simulator instruction rate (inst/s)
host_op_rate 157275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55694402 # Simulator tick rate (ticks/s)
host_mem_usage 215928 # Number of bytes of host memory used
host_seconds 2534.82 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 469184 # Number of bytes read from this memory
system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
system.physmem.bytes_read 468992 # Number of bytes read from this memory
system.physmem.bytes_inst_read 214592 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 7331 # Number of read requests responded to by this memory
system.physmem.num_reads 7328 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 3351431 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1534225 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 3351431 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 3322058 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1520041 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 3322058 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 168277058 # DT
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168277114 # DTB accesses
system.cpu.itb.fetch_hits 48859849 # ITB hits
system.cpu.itb.fetch_misses 44521 # ITB misses
system.cpu.itb.fetch_hits 49111850 # ITB hits
system.cpu.itb.fetch_misses 88782 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 48904370 # ITB accesses
system.cpu.itb.fetch_accesses 49200632 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 279990228 # number of cpu cycles simulated
system.cpu.numCycles 282350260 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 281921224 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed.
system.cpu.activity 95.173539 # Percentage of cycles cpu is active
system.cpu.timesIdled 6799 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13475974 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268874286 # Number of cycles cpu stages are processed.
system.cpu.activity 95.227214 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
@ -74,92 +74,92 @@ system.cpu.committedInsts 398664595 # Nu
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.708240 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads
system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.708240 # CPI: Total CPI of All Threads
system.cpu.ipc 1.411951 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits
system.cpu.ipc_total 1.411951 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 53870351 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30921654 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16037209 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33426940 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15653987 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File
system.cpu.branch_predictor.RASInCorrect 18 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.830452 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29683846 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24186505 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280818442 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 440154301 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119907697 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168369236 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed
system.cpu.regfile_manager.floatRegFileAccesses 220104178 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100457644 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168700458 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14475221 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1561329 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16036550 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28551001 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.966429 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205750873 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124330 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1970 # number of replacements
system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use
system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 78536322 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203813938 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.184788 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108863639 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173486621 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.443762 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104640873 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177709387 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.939339 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183568799 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98781461 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 34.985433 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92657665 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189692595 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.183432 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1974 # number of replacements
system.cpu.icache.tagsinuse 1829.918694 # Cycle average of tags in use
system.cpu.icache.total_refs 49107469 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3901 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12588.430915 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits
system.cpu.icache.overall_hits::total 48855472 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4376 # number of overall misses
system.cpu.icache.overall_misses::total 4376 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 214318500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 214318500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 214318500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 214318500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 214318500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 214318500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 48859848 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 48859848 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 48859848 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 48859848 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 48859848 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 48859848 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000090 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000090 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000090 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 1829.918694 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.893515 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.893515 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49107469 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49107469 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49107469 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49107469 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49107469 # number of overall hits
system.cpu.icache.overall_hits::total 49107469 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4380 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4380 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4380 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4380 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4380 # number of overall misses
system.cpu.icache.overall_misses::total 4380 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 214309000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 214309000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 214309000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 214309000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 214309000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 214309000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49111849 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49111849 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49111849 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49111849 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49111849 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49111849 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000089 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000089 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000089 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -174,34 +174,34 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 479
system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3897 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3897 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3897 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3897 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3897 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3897 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185285000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 185285000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185285000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 185285000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185285000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 185285000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3901 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3901 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3901 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3901 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3901 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 185222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 185222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185222000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 185222000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988 # average overall mshr miss latency
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system.cpu.dcache.tagsinuse 3284.843893 # Cycle average of tags in use
system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::total 94753265 # number of ReadReq hits
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@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 13259 # n
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system.cpu.dcache.overall_miss_latency::total 690562000 # number of overall miss cycles
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@ -238,16 +238,16 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 52068.406365 # average overall miss latency
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@ -268,98 +268,98 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
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@ -368,42 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
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system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134591000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168108500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134591000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160275000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 294866000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134591000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160275000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 294866000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859523 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40382.530120 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40320.754717 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

8
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:10:45
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:34:05
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -10,5 +10,5 @@ info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.083333
Exiting @ tick 89480174500 because target called exit()
OO-style eon Time= 0.066667
Exiting @ tick 80257421500 because target called exit()

1048
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:57:28
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:20:40
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.100000
Exiting @ tick 104492506500 because target called exit()
Exiting @ tick 106128099500 because target called exit()

1014
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:12:28
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:35:37
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 643030478500 because target called exit()
Exiting @ tick 645508416000 because target called exit()

1030
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:06:03
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:29:25
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
Exiting @ tick 708285420500 because target called exit()
Exiting @ tick 733277720500 because target called exit()

1075
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

6
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:15:15
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:38:51
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 46914279500 because target called exit()
Exiting @ tick 47232621500 because target called exit()

594
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,46 +1,46 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.046914 # Number of seconds simulated
sim_ticks 46914279500 # Number of ticks simulated
final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.047233 # Number of seconds simulated
sim_ticks 47232621500 # Number of ticks simulated
final_tick 47232621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 145791 # Simulator instruction rate (inst/s)
host_op_rate 145791 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 77424105 # Simulator tick rate (ticks/s)
host_mem_usage 218104 # Number of bytes of host memory used
host_seconds 605.94 # Real time elapsed on the host
host_inst_rate 142426 # Simulator instruction rate (inst/s)
host_op_rate 142426 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 76149893 # Simulator tick rate (ticks/s)
host_mem_usage 218108 # Number of bytes of host memory used
host_seconds 620.26 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11164096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7712960 # Number of bytes written to this memory
system.physmem.num_reads 174439 # Number of read requests responded to by this memory
system.physmem.num_writes 120515 # Number of write requests responded to by this memory
system.physmem.bytes_read 11167232 # Number of bytes read from this memory
system.physmem.bytes_inst_read 602240 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7713024 # Number of bytes written to this memory
system.physmem.num_reads 174488 # Number of read requests responded to by this memory
system.physmem.num_writes 120516 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 237967973 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 12774277 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 164405381 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 402373354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 236430493 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 12750510 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 163298664 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 399729158 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277222 # DTB read hits
system.cpu.dtb.read_hits 20277221 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367370 # DTB read accesses
system.cpu.dtb.read_accesses 20367369 # DTB read accesses
system.cpu.dtb.write_hits 14736811 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14744063 # DTB write accesses
system.cpu.dtb.data_hits 35014033 # DTB hits
system.cpu.dtb.data_hits 35014032 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35111433 # DTB accesses
system.cpu.itb.fetch_hits 12380499 # ITB hits
system.cpu.itb.fetch_misses 10576 # ITB misses
system.cpu.dtb.data_accesses 35111432 # DTB accesses
system.cpu.itb.fetch_hits 12477897 # ITB hits
system.cpu.itb.fetch_misses 13095 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12391075 # ITB accesses
system.cpu.itb.fetch_accesses 12490992 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 93828560 # number of cpu cycles simulated
system.cpu.numCycles 94465244 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 78066794 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed.
system.cpu.activity 74.177435 # Percentage of cycles cpu is active
system.cpu.timesIdled 305627 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 24182755 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 70282489 # Number of cycles cpu stages are processed.
system.cpu.activity 74.400368 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
@ -75,158 +75,158 @@ system.cpu.committedInsts 88340673 # Nu
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.069329 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads
system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.069329 # CPI: Total CPI of All Threads
system.cpu.ipc 0.935166 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target.
system.cpu.ipc_total 0.935166 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 18828991 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 12440560 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 5024685 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 16222590 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 5048183 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1660950 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 31.118231 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8476014 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10352977 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74323677 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 126642927 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 65289 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35053135 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 292919 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14127497 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35064147 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4680877 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 233308 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4914185 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 8858001 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.681953 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44775654 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 83610 # number of replacements
system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use
system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 41039233 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 53426011 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 56.556262 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 51809989 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42655255 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 45.154443 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 51339314 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43125930 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 45.652695 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 72336276 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22128968 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 23.425513 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 48368266 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46096978 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 48.797818 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 85310 # number of replacements
system.cpu.icache.tagsinuse 1887.040544 # Cycle average of tags in use
system.cpu.icache.total_refs 12359577 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 87356 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 141.485153 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1886.858130 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.921317 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.921317 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 12263478 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12263478 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12263478 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12263478 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12263478 # number of overall hits
system.cpu.icache.overall_hits::total 12263478 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 116984 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 116984 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 116984 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 116984 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 116984 # number of overall misses
system.cpu.icache.overall_misses::total 116984 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 2068004000 # number of ReadReq miss cycles
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system.cpu.icache.overall_miss_latency::total 2068004000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 12380462 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322 # average overall miss latency
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system.cpu.icache.overall_hits::total 12359577 # number of overall hits
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system.cpu.icache.ReadReq_misses::total 118263 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 118263 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 118263 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::total 2089534000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::total 2089534000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 2089534000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 2089534000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 12477840 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 12477840 # number of demand (read+write) accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.009478 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17668.535383 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17668.535383 # average overall miss latency
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system.cpu.icache.overall_mshr_hits::total 31328 # number of overall MSHR hits
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system.cpu.icache.demand_mshr_misses::total 85656 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 85656 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1345401500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1345401500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30907 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 30907 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 30907 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 30907 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 30907 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 30907 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87356 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 87356 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 87356 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 87356 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 87356 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 87356 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1366128500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1366128500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1366128500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1366128500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1366128500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1366128500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007001 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15638.633866 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15638.633866 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200251 # number of replacements
system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use
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system.cpu.dcache.total_refs 34125996 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.ReadReq_hits::total 20180445 # number of ReadReq hits
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system.cpu.dcache.overall_hits::total 34126014 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 96193 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 667808 # number of WriteReq misses
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system.cpu.dcache.demand_misses::total 764001 # number of demand (read+write) misses
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system.cpu.dcache.WriteReq_miss_latency::total 35332073000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 39490722000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39490722000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39490722000 # number of overall miss cycles
system.cpu.dcache.avg_refs 167.000230 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4073.126583 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::total 0.994416 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::total 20180455 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 13945541 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 34125996 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 96183 # number of ReadReq misses
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system.cpu.dcache.demand_misses::total 764019 # number of demand (read+write) misses
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@ -236,31 +236,31 @@ system.cpu.dcache.demand_accesses::total 34890015 # nu
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 51683.893332 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 6329431500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 161216 # number of writebacks
system.cpu.dcache.writebacks::total 161216 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35426 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35426 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524228 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 524228 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 559654 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 559654 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 559654 # number of overall MSHR hits
system.cpu.dcache.writebacks::writebacks 161215 # number of writebacks
system.cpu.dcache.writebacks::total 161215 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35416 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35416 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524256 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 524256 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 559672 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 559672 # number of overall MSHR hits
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@ -269,98 +269,98 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254482000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 9343358000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 9343358000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34375.170734 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.713888 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45723.000582 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 148060 # number of replacements
system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use
system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks.
system.cpu.l2cache.replacements 148111 # number of replacements
system.cpu.l2cache.tagsinuse 18671.690365 # Cycle average of tags in use
system.cpu.l2cache.total_refs 132979 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 173456 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.766644 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits
system.cpu.l2cache.occ_blocks::writebacks 15657.217235 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1374.269041 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1640.204088 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.477820 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.041939 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.050055 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.569815 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 77946 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 26999 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 104945 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 161215 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 161215 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits
system.cpu.l2cache.overall_hits::total 115564 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses
system.cpu.l2cache.demand_hits::cpu.inst 77946 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 39269 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 117215 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 77946 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 39269 # number of overall hits
system.cpu.l2cache.overall_hits::total 117215 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 9410 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 42988 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses
system.cpu.l2cache.overall_misses::total 174439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 489614500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_misses::cpu.inst 9410 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 165078 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 174488 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 9410 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 165078 # number of overall misses
system.cpu.l2cache.overall_misses::total 174488 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 492013000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752923000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2244936000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854378000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6854378000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 492013000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8607301000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9099314000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 492013000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8607301000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9099314000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 87356 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 147933 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 161215 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 161215 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 87356 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 291703 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 87356 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::total 291703 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.107720 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554303 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.107720 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.807832 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.107720 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.807832 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.184910 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52204.508905 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.547529 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.184910 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.812222 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -369,44 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks
system.cpu.l2cache.writebacks::total 120515 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses
system.cpu.l2cache.writebacks::writebacks 120516 # number of writebacks
system.cpu.l2cache.writebacks::total 120516 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9410 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 42988 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 9410 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 165078 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 174488 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9410 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 165078 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 174488 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 377128500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343464000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1720592500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262752500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262752500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 377128500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606216500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6983345000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 377128500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606216500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6983345000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554303 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.107720 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807832 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40077.417641 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.244803 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.931559 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40077.417641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.757799 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:19:29
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:42:57
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 21259532000 because target called exit()
Exiting @ tick 21302882000 because target called exit()

1048
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:25:27
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:47:12
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 31189496500 because target called exit()
Exiting @ tick 30746529500 because target called exit()

1111
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:25:39
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:49:22
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1009857089500 because target called exit()
Exiting @ tick 1009998808500 because target called exit()

508
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,46 +1,46 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.009857 # Number of seconds simulated
sim_ticks 1009857089500 # Number of ticks simulated
final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 1.009999 # Number of seconds simulated
sim_ticks 1009998808500 # Number of ticks simulated
final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 137029 # Simulator instruction rate (inst/s)
host_op_rate 137029 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 76042102 # Simulator tick rate (ticks/s)
host_mem_usage 209964 # Number of bytes of host memory used
host_seconds 13280.24 # Real time elapsed on the host
host_inst_rate 135204 # Simulator instruction rate (inst/s)
host_op_rate 135204 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 75039783 # Simulator tick rate (ticks/s)
host_mem_usage 209960 # Number of bytes of host memory used
host_seconds 13459.51 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 172617984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_read 172618048 # Number of bytes read from this memory
system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written 74938304 # Number of bytes written to this memory
system.physmem.num_reads 2697156 # Number of read requests responded to by this memory
system.physmem.num_reads 2697157 # Number of read requests responded to by this memory
system.physmem.num_writes 1170911 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444614420 # DTB read hits
system.cpu.dtb.read_hits 444614444 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449511498 # DTB read accesses
system.cpu.dtb.write_hits 160920903 # DTB write hits
system.cpu.dtb.read_accesses 449511522 # DTB read accesses
system.cpu.dtb.write_hits 160920906 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162622207 # DTB write accesses
system.cpu.dtb.data_hits 605535323 # DTB hits
system.cpu.dtb.write_accesses 162622210 # DTB write accesses
system.cpu.dtb.data_hits 605535350 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612133705 # DTB accesses
system.cpu.itb.fetch_hits 233080732 # ITB hits
system.cpu.dtb.data_accesses 612133732 # DTB accesses
system.cpu.itb.fetch_hits 231980230 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 233080754 # ITB accesses
system.cpu.itb.fetch_accesses 231980252 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2019714180 # number of cpu cycles simulated
system.cpu.numCycles 2019997618 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed.
system.cpu.activity 78.072669 # Percentage of cycles cpu is active
system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed.
system.cpu.activity 78.063714 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
@ -75,158 +75,158 @@ system.cpu.committedInsts 1819780127 # Nu
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads
system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads
system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits
system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617252269 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed.
system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617989652 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use
system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use
system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits
system.cpu.icache.overall_hits::total 233079667 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses
system.cpu.icache.overall_misses::total 1062 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses
system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits
system.cpu.icache.overall_hits::total 231979155 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses
system.cpu.icache.overall_misses::total 1072 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107352 # number of replacements
system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use
system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use
system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_percent::total 0.996731 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::total 437271428 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157798653 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157798653 # number of WriteReq hits
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system.cpu.dcache.demand_hits::total 595070081 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595070081 # number of overall hits
system.cpu.dcache.overall_hits::total 595070081 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324235 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324235 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2929849 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2929849 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10254084 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10254084 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10254084 # number of overall misses
system.cpu.dcache.overall_misses::total 10254084 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 180892053500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110288339500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 291180393000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles
system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits
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system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits
system.cpu.dcache.overall_hits::total 595069970 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses
system.cpu.dcache.overall_misses::total 10254195 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
@ -239,28 +239,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks
system.cpu.dcache.writebacks::total 3058572 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses
@ -269,36 +269,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111448
system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191835500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191835500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215279506500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686299 # number of replacements
system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy
system.cpu.l2cache.replacements 2686301 # number of replacements
system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits
@ -309,41 +309,41 @@ system.cpu.l2cache.demand_hits::cpu.data 6415150 # nu
system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits
system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 858 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2697156 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 858 # number of overall misses
system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses
system.cpu.l2cache.overall_misses::total 2697156 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44903500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94408605500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94453509000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46507390000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46507390000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses
@ -351,13 +351,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
@ -368,28 +368,28 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks
system.cpu.l2cache.writebacks::total 1170911 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses
@ -397,13 +397,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:26:22
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:50:00
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 615292058500 because target called exit()
Exiting @ tick 614317285000 because target called exit()

1030
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:28:08
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:51:32
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 483300356500 because target called exit()
Exiting @ tick 464073050000 because target called exit()

1076
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,10 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:36:18
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:58:42
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 41833966000 because target called exit()
122 123 124 Exiting @ tick 42005374000 because target called exit()

490
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.041834 # Number of seconds simulated
sim_ticks 41833966000 # Number of ticks simulated
final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.042005 # Number of seconds simulated
sim_ticks 42005374000 # Number of ticks simulated
final_tick 42005374000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 151560 # Simulator instruction rate (inst/s)
host_op_rate 151560 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 68989742 # Simulator tick rate (ticks/s)
host_inst_rate 147839 # Simulator instruction rate (inst/s)
host_op_rate 147839 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 67571644 # Simulator tick rate (ticks/s)
host_mem_usage 213560 # Number of bytes of host memory used
host_seconds 606.38 # Real time elapsed on the host
host_seconds 621.64 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 316032 # Number of bytes read from this memory
@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 4938 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 7554436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 4274421 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 7554436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 7523609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 4256979 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 7523609 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 26498119 # DT
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498152 # DTB accesses
system.cpu.itb.fetch_hits 9991202 # ITB hits
system.cpu.itb.fetch_hits 10037351 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 9991251 # ITB accesses
system.cpu.itb.fetch_accesses 10037400 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 83667933 # number of cpu cycles simulated
system.cpu.numCycles 84010749 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 83632403 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed.
system.cpu.activity 90.796172 # Percentage of cycles cpu is active
system.cpu.timesIdled 11097 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7735993 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 76274756 # Number of cycles cpu stages are processed.
system.cpu.activity 90.791663 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
@ -74,158 +74,158 @@ system.cpu.committedInsts 91903056 # Nu
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 0.914124 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads
system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 0.914124 # CPI: Total CPI of All Threads
system.cpu.ipc 1.093944 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits
system.cpu.ipc_total 1.093944 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 13563923 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 9779691 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 4496836 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 7950423 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 3848158 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File
system.cpu.branch_predictor.RASInCorrect 123 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 48.401928 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5997418 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7566505 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73742077 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File
system.cpu.regfile_manager.intRegFileAccesses 136317549 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206798 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26652325 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed
system.cpu.regfile_manager.floatRegFileAccesses 8058686 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38530251 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26765541 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3521133 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 974845 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4495978 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5744724 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 43.903025 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57471384 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458266 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 7551 # number of replacements
system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use
system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks.
system.cpu.stage0.idleCycles 27790213 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 56220536 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.920646 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34560671 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49450078 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 58.861608 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 34032650 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49978099 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.490124 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65981194 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18029555 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.461010 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 30068425 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53942324 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.208836 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 8111 # number of replacements
system.cpu.icache.tagsinuse 1492.322334 # Cycle average of tags in use
system.cpu.icache.total_refs 10025618 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 9996 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1002.962985 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits
system.cpu.icache.overall_hits::total 9979713 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses
system.cpu.icache.overall_misses::total 11486 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency
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system.cpu.icache.ReadReq_hits::total 10025618 # number of ReadReq hits
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system.cpu.icache.demand_hits::total 10025618 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10025618 # number of overall hits
system.cpu.icache.overall_hits::total 10025618 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11728 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11728 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 11728 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11728 # number of overall misses
system.cpu.icache.overall_misses::total 11728 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 295393500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 295393500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 295393500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 295393500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 295393500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 295393500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 10037346 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 10037346 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 10037346 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 10037346 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 10037346 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 10037346 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001168 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001168 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001168 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 97000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667 # average number of cycles each access was blocked
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system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1732 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1732 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1732 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1732 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1732 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1732 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9996 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9996 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9996 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9996 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9996 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9996 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228898000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 228898000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228898000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 228898000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228898000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 228898000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000996 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1441.511431 # Cycle average of tags in use
system.cpu.dcache.total_refs 26491208 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 11916.872695 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits
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system.cpu.dcache.overall_hits::cpu.data 26491206 # number of overall hits
system.cpu.dcache.overall_hits::total 26491206 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 553 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 553 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5542 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5542 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6095 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6095 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6095 # number of overall misses
system.cpu.dcache.overall_misses::total 6095 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28393500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28393500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 303801000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 303801000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 332194500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 332194500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 332194500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 332194500 # number of overall miss cycles
system.cpu.dcache.occ_blocks::cpu.data 1441.511431 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.351932 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.351932 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 19995646 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 19995646 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6495562 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6495562 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 26491208 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26491208 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26491208 # number of overall hits
system.cpu.dcache.overall_hits::total 26491208 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 552 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 552 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5541 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5541 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 6093 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6093 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 6093 # number of overall misses
system.cpu.dcache.overall_misses::total 6093 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 28391500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 28391500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 303790500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 303790500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 332182000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 332182000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 332182000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 332182000 # number of overall miss cycles
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system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
@ -238,28 +238,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000852 # miss rate for WriteReq accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.000230 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 41043500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3794 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3794 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3872 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3872 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3872 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3872 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3793 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3793 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3870 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3870 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3870 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3870 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
@ -268,49 +268,49 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23213000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23213000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 92997500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116210500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 116210500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116210500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 116210500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23216000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23216000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92995500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 92995500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 116211500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 116211500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 116211500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 116211500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use
system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2189.730470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7264 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 2.213285 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.838059 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1820.375269 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.040274 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.055553 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010713 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066811 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 6642 # number of ReadReq hits
system.cpu.l2cache.occ_blocks::writebacks 17.847253 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1820.879596 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 351.003621 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055569 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 7202 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6695 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7255 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 6642 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 7202 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6721 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 6642 # number of overall hits
system.cpu.l2cache.demand_hits::total 7281 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 7202 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 6721 # number of overall hits
system.cpu.l2cache.overall_hits::total 7281 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2794 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
@ -322,44 +322,44 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146193000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22134500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 168327500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90565000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 90565000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 146193000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112699500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 258892500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 146193000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112699500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 258892500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 146177000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22139000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 168316000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90566000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 90566000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 146177000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 112705000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 258882000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 146177000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 112705000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 258882000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9996 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 9911 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 10471 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 9436 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 9996 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 11659 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 9436 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 12219 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 9996 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 11659 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.296100 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::total 12219 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.279512 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296100 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.279512 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296100 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.279512 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -379,31 +379,31 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112072000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129053500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69344000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69344000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112072000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86325500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 198397500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112072000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86325500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 198397500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112070000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16981000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 129051000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69345500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69345500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112070000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86326500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 198396500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112070000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86326500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 198396500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.279512 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

8
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
View file

@ -1,10 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:45:24
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 18:07:15
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 29167093500 because target called exit()
122 123 124 Exiting @ tick 23638033500 because target called exit()

1012
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
View file

@ -1,10 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 16:37:09
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 20:58:01
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -21,4 +23,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 105850842000 because target called exit()
122 123 124 Exiting @ tick 88632152500 because target called exit()

1055
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

8
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 15:02:46
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 19:27:36
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -22,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 96266258000 because target called exit()
122 123 124 Exiting @ tick 87727531000 because target called exit()

964
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

98
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
View file

@ -1,6 +1,7 @@
[root]
type=Root
children=system
full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
memories=system.physmem system.nvmem
memories=system.nvmem system.physmem
midr_regval=890224640
num_work_ids=16
physmem=system.physmem
@ -93,6 +93,7 @@ simulate_inst_stalls=false
system=system
tracer=system.cpu0.tracer
width=1
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
@ -107,20 +108,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@ -152,20 +146,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@ -220,6 +207,7 @@ simulate_inst_stalls=false
system=system
tracer=system.cpu1.tracer
width=1
workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
@ -234,20 +222,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@ -279,20 +260,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
@ -344,20 +318,13 @@ is_top_level=false
latency=50000
max_miss_count=0
mshrs=20
num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=500000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
@ -376,20 +343,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
num_cpus=2
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
prefetch_on_access=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
@ -415,7 +375,6 @@ fake_mem=false
pio_addr=0
pio_latency=1000
pio_size=8
platform=system.realview
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
@ -457,7 +416,6 @@ system=system
type=A9SCU
pio_addr=520093696
pio_latency=1000
platform=system.realview
system=system
pio=system.membus.port[5]
@ -467,7 +425,6 @@ amba_id=0
ignore_access=false
pio_addr=268451840
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[24]
@ -537,7 +494,6 @@ max_backoff_delay=10000000
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
platform=system.realview
system=system
vnc=system.vncserver
dma=system.iobus.port[6]
@ -549,7 +505,6 @@ amba_id=0
ignore_access=false
pio_addr=268632064
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[12]
@ -559,7 +514,6 @@ fake_mem=true
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@ -588,7 +542,6 @@ amba_id=0
ignore_access=false
pio_addr=268513280
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[19]
@ -598,7 +551,6 @@ amba_id=0
ignore_access=false
pio_addr=268517376
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[20]
@ -608,7 +560,6 @@ amba_id=0
ignore_access=false
pio_addr=268521472
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[21]
@ -621,7 +572,6 @@ int_num=52
is_mouse=false
pio_addr=268460032
pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[7]
@ -635,7 +585,6 @@ int_num=53
is_mouse=true
pio_addr=268464128
pio_latency=1000
platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[8]
@ -646,7 +595,6 @@ fake_mem=false
pio_addr=520101888
pio_latency=1000
pio_size=4095
platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@ -665,7 +613,6 @@ int_num_timer=29
int_num_watchdog=30
pio_addr=520095232
pio_latency=1000
platform=system.realview
system=system
pio=system.membus.port[6]
@ -675,7 +622,6 @@ amba_id=0
ignore_access=false
pio_addr=268455936
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[25]
@ -684,7 +630,6 @@ type=RealViewCtrl
idreg=0
pio_addr=268435456
pio_latency=1000
platform=system.realview
proc_id0=201326592
proc_id1=201327138
system=system
@ -696,7 +641,6 @@ amba_id=266289
ignore_access=false
pio_addr=268529664
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[26]
@ -706,7 +650,6 @@ amba_id=0
ignore_access=false
pio_addr=268492800
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[23]
@ -716,7 +659,6 @@ amba_id=0
ignore_access=false
pio_addr=269357056
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[16]
@ -726,7 +668,6 @@ amba_id=0
ignore_access=true
pio_addr=268439552
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[17]
@ -736,7 +677,6 @@ amba_id=0
ignore_access=false
pio_addr=268488704
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[22]
@ -750,7 +690,6 @@ int_num0=36
int_num1=36
pio_addr=268505088
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[3]
@ -764,7 +703,6 @@ int_num0=37
int_num1=37
pio_addr=268509184
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[4]
@ -787,7 +725,6 @@ amba_id=0
ignore_access=false
pio_addr=268476416
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[13]
@ -797,7 +734,6 @@ amba_id=0
ignore_access=false
pio_addr=268480512
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[14]
@ -807,7 +743,6 @@ amba_id=0
ignore_access=false
pio_addr=268484608
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[15]
@ -817,7 +752,6 @@ amba_id=0
ignore_access=false
pio_addr=268500992
pio_latency=1000
platform=system.realview
system=system
pio=system.iobus.port[18]

29
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
View file

@ -1,11 +1,18 @@
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main
exec filecode in scope
File "tests/run.py", line 70, in <module>
execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module>
system.l2c.num_cpus = 2
File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__
% (self.__class__.__name__, attr)
AttributeError: Class L2 has no parameter num_cpus
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: The ccsidr register isn't implemented and always reads as 0.
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here

9
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
View file

@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:37:03
gem5 compiled Feb 12 2012 23:53:51
gem5 started Feb 12 2012 23:54:00
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2411694099500 because m5_exit instruction encountered

571
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
View file

@ -0,0 +1,571 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.411694 # Number of seconds simulated
sim_ticks 2411694099500 # Number of ticks simulated
final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2070187 # Simulator instruction rate (inst/s)
host_op_rate 2676186 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 81119350138 # Simulator tick rate (ticks/s)
host_mem_usage 376104 # Number of bytes of host memory used
host_seconds 29.73 # Real time elapsed on the host
sim_insts 61546998 # Number of instructions simulated
sim_ops 79563488 # Number of ops (including micro ops) simulated
system.nvmem.bytes_read 68 # Number of bytes read from this memory
system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
system.nvmem.bytes_written 0 # Number of bytes written to this memory
system.nvmem.num_reads 17 # Number of read requests responded to by this memory
system.nvmem.num_writes 0 # Number of write requests responded to by this memory
system.nvmem.num_other 0 # Number of other requests responded to by this memory
system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s)
system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s)
system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read 123270308 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10185232 # Number of bytes written to this memory
system.physmem.num_reads 14146769 # Number of read requests responded to by this memory
system.physmem.num_writes 869038 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 127720 # number of replacements
system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
system.l2c.total_refs 1498989 # Total number of references to valid blocks.
system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 14919.913596 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 3116.154269 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 1287.935030 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2080.961375 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 4136.957345 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.047549 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.019652 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.031753 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.063125 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.389830 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 5051 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2156 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 493019 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 368109 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 131706 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 580461 # number of Writeback hits
system.l2c.Writeback_hits::total 580461 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 147 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 202 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 64831 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 37797 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 5051 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 2156 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 493019 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 278002 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 4123 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1590 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 368109 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 169503 # number of demand (read+write) hits
system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 5051 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2156 # number of overall hits
system.l2c.overall_hits::cpu0.inst 493019 # number of overall hits
system.l2c.overall_hits::cpu0.data 278002 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 4123 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1590 # number of overall hits
system.l2c.overall_hits::cpu1.inst 368109 # number of overall hits
system.l2c.overall_hits::cpu1.data 169503 # number of overall hits
system.l2c.overall_hits::total 1321553 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 10289 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 9386 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 13 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 5094 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 10130 # number of ReadReq misses
system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 6349 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3492 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 791 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 531 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99048 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48785 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 10289 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 108434 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 5094 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 58915 # number of demand (read+write) misses
system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses
system.l2c.overall_misses::cpu0.inst 10289 # number of overall misses
system.l2c.overall_misses::cpu0.data 108434 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 13 # number of overall misses
system.l2c.overall_misses::cpu1.inst 5094 # number of overall misses
system.l2c.overall_misses::cpu1.data 58915 # number of overall misses
system.l2c.overall_misses::total 182784 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 5062 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 2163 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 503308 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 222557 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4144 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1603 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 373203 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 141836 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 580461 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 7125 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 4015 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 733 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 163879 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 86582 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 5062 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 2163 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 503308 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 386436 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 4144 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1603 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 373203 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 228418 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 5062 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 2163 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 503308 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 386436 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 4144 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1603 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 373203 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 228418 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003236 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.020443 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.042173 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.008110 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.013649 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.071421 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.891088 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.869738 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843284 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724420 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.604397 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.563454 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.003236 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.020443 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.280600 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.008110 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.013649 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.257926 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.003236 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.020443 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.280600 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.008110 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.013649 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.257926 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 111818 # number of writebacks
system.l2c.writebacks::total 111818 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 9339288 # DTB read hits
system.cpu0.dtb.read_misses 5153 # DTB read misses
system.cpu0.dtb.write_hits 6907876 # DTB write hits
system.cpu0.dtb.write_misses 1048 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 16247164 # DTB hits
system.cpu0.dtb.misses 6201 # DTB misses
system.cpu0.dtb.accesses 16253365 # DTB accesses
system.cpu0.itb.inst_hits 34822552 # ITB inst hits
system.cpu0.itb.inst_misses 2978 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
system.cpu0.itb.hits 34822552 # DTB hits
system.cpu0.itb.misses 2978 # DTB misses
system.cpu0.itb.accesses 34825530 # DTB accesses
system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 34068103 # Number of instructions committed
system.cpu0.committedOps 44975797 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
system.cpu0.num_int_insts 39858123 # number of integer instructions
system.cpu0.num_fp_insts 4945 # number of float instructions
system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
system.cpu0.num_mem_refs 17030946 # number of memory refs
system.cpu0.num_load_insts 9786549 # Number of load instructions
system.cpu0.num_store_insts 7244397 # Number of store instructions
system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
system.cpu0.icache.replacements 504460 # number of replacements
system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 34319155 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 34319155 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 34319155 # number of overall hits
system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses
system.cpu0.icache.overall_misses::total 504973 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824128 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 34824128 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 34824128 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 24728 # number of writebacks
system.cpu0.icache.writebacks::total 24728 # number of writebacks
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 380107 # number of replacements
system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use
system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7803296 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 6534059 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 14337355 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 14337355 # number of overall hits
system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 237350 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9878 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7293 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 420930 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 420930 # number of overall misses
system.cpu0.dcache.overall_misses::total 420930 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040646 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717639 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 14758285 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14758285 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040036 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028522 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028522 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 339627 # number of writebacks
system.cpu0.dcache.writebacks::total 339627 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 6258230 # DTB read hits
system.cpu1.dtb.read_misses 2159 # DTB read misses
system.cpu1.dtb.write_hits 4713962 # DTB write hits
system.cpu1.dtb.write_misses 1181 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 6260389 # DTB read accesses
system.cpu1.dtb.write_accesses 4715143 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 10972192 # DTB hits
system.cpu1.dtb.misses 3340 # DTB misses
system.cpu1.dtb.accesses 10975532 # DTB accesses
system.cpu1.itb.inst_hits 27739434 # ITB inst hits
system.cpu1.itb.inst_misses 1388 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses
system.cpu1.itb.hits 27739434 # DTB hits
system.cpu1.itb.misses 1388 # DTB misses
system.cpu1.itb.accesses 27740822 # DTB accesses
system.cpu1.numCycles 4822838236 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 27478895 # Number of instructions committed
system.cpu1.committedOps 34587691 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses
system.cpu1.num_func_calls 758024 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls
system.cpu1.num_int_insts 30998246 # number of integer instructions
system.cpu1.num_fp_insts 5772 # number of float instructions
system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read
system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written
system.cpu1.num_mem_refs 11415835 # number of memory refs
system.cpu1.num_load_insts 6478994 # Number of load instructions
system.cpu1.num_store_insts 4936841 # Number of store instructions
system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles
system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles
system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed
system.cpu1.icache.replacements 374406 # number of replacements
system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use
system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 27365572 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 27365572 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 27365572 # number of overall hits
system.cpu1.icache.overall_hits::total 27365572 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 374920 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 374920 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 374920 # number of overall misses
system.cpu1.icache.overall_misses::total 374920 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740492 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 27740492 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 27740492 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks
system.cpu1.icache.writebacks::total 13905 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 247434 # number of replacements
system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 444.903488 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.868952 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 5955973 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3777038 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60090 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 9733011 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 9733011 # number of overall hits
system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 165799 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 277266 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 277266 # number of overall misses
system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121772 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888505 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 70318 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70288 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 10010277 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 10010277 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027083 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027698 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027698 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 202201 # number of writebacks
system.cpu1.dcache.writebacks::total 202201 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:09:12
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:02
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 21216000 because target called exit()
Exiting @ tick 21234500 because target called exit()

326
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 21216000 # Number of ticks simulated
final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 21234500 # Number of ticks simulated
final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 38129 # Simulator instruction rate (inst/s)
host_op_rate 38124 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 126288909 # Simulator tick rate (ticks/s)
host_mem_usage 209388 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_inst_rate 95244 # Simulator instruction rate (inst/s)
host_op_rate 95219 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 315647941 # Simulator tick rate (ticks/s)
host_mem_usage 209384 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30016 # Number of bytes read from this memory
@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 469 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 2084 # DT
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2094 # DTB accesses
system.cpu.itb.fetch_hits 929 # ITB hits
system.cpu.itb.fetch_hits 908 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 946 # ITB accesses
system.cpu.itb.fetch_accesses 925 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 42433 # number of cpu cycles simulated
system.cpu.numCycles 42470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7383 # Number of cycles cpu stages are processed.
system.cpu.activity 17.399194 # Percentage of cycles cpu is active
system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7391 # Number of cycles cpu stages are processed.
system.cpu.activity 17.402873 # Percentage of cycles cpu is active
system.cpu.comLoads 1185 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1051 # Number of Branches instructions committed
@ -74,92 +74,92 @@ system.cpu.committedInsts 6404 # Nu
system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads
system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1670 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted
system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1608 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2138 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2183 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4447 # Number of Instructions Executed.
system.cpu.execution_unit.executions 4474 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use
system.cpu.icache.total_refs 581 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use
system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits
system.cpu.icache.overall_hits::total 581 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses
system.cpu.icache.overall_misses::total 348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
system.cpu.icache.overall_hits::total 558 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -168,40 +168,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use
system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits
@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 347 # n
system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses
system.cpu.dcache.overall_misses::total 347 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
@ -238,10 +238,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -266,34 +266,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -311,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
@ -340,13 +340,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -367,16 +367,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 301
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
@ -385,12 +385,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:09:12
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:02
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 12004500 because target called exit()
Exiting @ tick 12450500 because target called exit()

896
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:09:23
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:03
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 6833000 because target called exit()
Exiting @ tick 7015000 because target called exit()

855
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
View file

@ -1,45 +1,45 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000007 # Number of seconds simulated
sim_ticks 6833000 # Number of ticks simulated
final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 7015000 # Number of ticks simulated
final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 16400 # Simulator instruction rate (inst/s)
host_op_rate 16398 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46934615 # Simulator tick rate (ticks/s)
host_mem_usage 209144 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
host_inst_rate 73930 # Simulator instruction rate (inst/s)
host_op_rate 73884 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 217009042 # Simulator tick rate (ticks/s)
host_mem_usage 209140 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 17280 # Number of bytes read from this memory
system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory
system.physmem.bytes_read 17600 # Number of bytes read from this memory
system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 270 # Number of read requests responded to by this memory
system.physmem.num_reads 275 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 679 # DTB read hits
system.cpu.dtb.read_misses 26 # DTB read misses
system.cpu.dtb.read_hits 711 # DTB read hits
system.cpu.dtb.read_misses 43 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.dtb.read_accesses 705 # DTB read accesses
system.cpu.dtb.write_hits 356 # DTB write hits
system.cpu.dtb.write_misses 18 # DTB write misses
system.cpu.dtb.read_accesses 754 # DTB read accesses
system.cpu.dtb.write_hits 380 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 374 # DTB write accesses
system.cpu.dtb.data_hits 1035 # DTB hits
system.cpu.dtb.data_misses 44 # DTB misses
system.cpu.dtb.write_accesses 403 # DTB write accesses
system.cpu.dtb.data_hits 1091 # DTB hits
system.cpu.dtb.data_misses 66 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_accesses 1079 # DTB accesses
system.cpu.itb.fetch_hits 941 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.dtb.data_accesses 1157 # DTB accesses
system.cpu.itb.fetch_hits 1067 # ITB hits
system.cpu.itb.fetch_misses 33 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 971 # ITB accesses
system.cpu.itb.fetch_accesses 1100 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -53,245 +53,246 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 13667 # number of cpu cycles simulated
system.cpu.numCycles 14031 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 1038 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits
system.cpu.BPredUnit.lookups 1201 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked
system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 941 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1081 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking
system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1197 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 995 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename
system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups
system.cpu.rename.RunCycles 1115 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle
system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 3881 # Type of FU issued
system.cpu.iq.rate 0.283969 # Inst issue rate
system.cpu.iq.fu_busy_cnt 41 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 4206 # Type of FU issued
system.cpu.iq.rate 0.299765 # Inst issue rate
system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute
system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 338 # number of nop insts executed
system.cpu.iew.exec_refs 1080 # number of memory reference insts executed
system.cpu.iew.exec_branches 629 # Number of branches executed
system.cpu.iew.exec_stores 374 # Number of stores executed
system.cpu.iew.exec_rate 0.274310 # Inst execution rate
system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3579 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1702 # num instructions producing a value
system.cpu.iew.wb_consumers 2165 # num instructions consuming a value
system.cpu.iew.exec_nop 368 # number of nop insts executed
system.cpu.iew.exec_refs 1160 # number of memory reference insts executed
system.cpu.iew.exec_branches 681 # Number of branches executed
system.cpu.iew.exec_stores 403 # Number of stores executed
system.cpu.iew.exec_rate 0.285439 # Inst execution rate
system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3813 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1793 # num instructions producing a value
system.cpu.iew.wb_consumers 2339 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back
system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -302,63 +303,63 @@ system.cpu.commit.branches 396 # Nu
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 10645 # The number of ROB reads
system.cpu.rob.rob_writes 10410 # The number of ROB writes
system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 11567 # The number of ROB reads
system.cpu.rob.rob_writes 11753 # The number of ROB writes
system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads
system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4520 # number of integer regfile reads
system.cpu.int_regfile_writes 2768 # number of integer regfile writes
system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads
system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4832 # number of integer regfile reads
system.cpu.int_regfile_writes 2958 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use
system.cpu.icache.total_refs 700 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use
system.cpu.icache.total_refs 817 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits
system.cpu.icache.overall_hits::total 700 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
system.cpu.icache.overall_misses::total 241 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits
system.cpu.icache.overall_hits::total 817 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
system.cpu.icache.overall_misses::total 250 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency
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@ -367,80 +368,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses
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system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency
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system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -449,83 +450,83 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency
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system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks.
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system.cpu.l2cache.overall_misses::total 275 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
@ -533,13 +534,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -548,28 +549,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
@ -577,13 +578,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:10:40
gem5 started Feb 11 2012 15:35:50
gem5 compiled Feb 12 2012 17:19:56
gem5 started Feb 12 2012 19:57:12
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 10000500 because target called exit()
Exiting @ tick 10389500 because target called exit()

897
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:07:32
gem5 started Feb 11 2012 13:54:30
gem5 compiled Feb 12 2012 17:16:48
gem5 started Feb 12 2012 18:16:47
gem5 executing on zizzer
command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 19785000 because target called exit()
Exiting @ tick 19775000 because target called exit()

298
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19785000 # Number of ticks simulated
final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 19775000 # Number of ticks simulated
final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 101976 # Simulator instruction rate (inst/s)
host_op_rate 101944 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 346042004 # Simulator tick rate (ticks/s)
host_mem_usage 210372 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
host_inst_rate 108846 # Simulator instruction rate (inst/s)
host_op_rate 108810 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 369151681 # Simulator tick rate (ticks/s)
host_mem_usage 210376 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29120 # Number of bytes read from this memory
@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 455 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -39,16 +39,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 39571 # number of cpu cycles simulated
system.cpu.numCycles 39551 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5405 # Number of cycles cpu stages are processed.
system.cpu.activity 13.658993 # Percentage of cycles cpu is active
system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5368 # Number of cycles cpu stages are processed.
system.cpu.activity 13.572350 # Percentage of cycles cpu is active
system.cpu.comLoads 1164 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 916 # Number of Branches instructions committed
@ -60,92 +60,92 @@ system.cpu.committedInsts 5827 # Nu
system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total)
system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads
system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads
system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1185 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits
system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1152 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2228 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3132 # Number of Instructions Executed.
system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2238 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 320 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 65.065502 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3155 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use
system.cpu.icache.total_refs 443 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use
system.cpu.icache.total_refs 411 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits
system.cpu.icache.overall_hits::total 443 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses
system.cpu.icache.overall_misses::total 341 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits
system.cpu.icache.overall_hits::total 411 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses
system.cpu.icache.overall_misses::total 343 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -154,40 +154,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use
system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits
@ -206,12 +206,12 @@ system.cpu.dcache.overall_misses::cpu.data 251 #
system.cpu.dcache.overall_misses::total 251 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
@ -225,9 +225,9 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135
system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -254,32 +254,32 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -297,17 +297,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 455 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
@ -326,13 +326,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked

6
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:07:32
gem5 started Feb 11 2012 13:54:39
gem5 compiled Feb 12 2012 17:16:48
gem5 started Feb 12 2012 18:16:57
gem5 executing on zizzer
command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 12272500 because target called exit()
Exiting @ tick 12671500 because target called exit()

820
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

@ -1,25 +1,25 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 12272500 # Number of ticks simulated
final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 12671500 # Number of ticks simulated
final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 97350 # Simulator instruction rate (inst/s)
host_op_rate 97317 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 230983195 # Simulator tick rate (ticks/s)
host_mem_usage 211060 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_inst_rate 93816 # Simulator instruction rate (inst/s)
host_op_rate 93786 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 229841550 # Simulator tick rate (ticks/s)
host_mem_usage 211032 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
sim_ops 5169 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30400 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory
system.physmem.bytes_read 30912 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 475 # Number of read requests responded to by this memory
system.physmem.num_reads 483 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 24546 # number of cpu cycles simulated
system.cpu.numCycles 25344 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 1975 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits
system.cpu.BPredUnit.lookups 2242 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered
system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked
system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2857 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2740 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename
system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups
system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3128 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2966 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename
system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit.
system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 7815 # Type of FU issued
system.cpu.iq.rate 0.318382 # Inst issue rate
system.cpu.iq.fu_busy_cnt 146 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 8177 # Type of FU issued
system.cpu.iq.rate 0.322640 # Inst issue rate
system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions
system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1378 # number of nop insts executed
system.cpu.iew.exec_refs 3087 # number of memory reference insts executed
system.cpu.iew.exec_branches 1271 # Number of branches executed
system.cpu.iew.exec_stores 1059 # Number of stores executed
system.cpu.iew.exec_rate 0.306812 # Inst execution rate
system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7118 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2758 # num instructions producing a value
system.cpu.iew.wb_consumers 3946 # num instructions consuming a value
system.cpu.iew.exec_nop 1464 # number of nop insts executed
system.cpu.iew.exec_refs 3166 # number of memory reference insts executed
system.cpu.iew.exec_branches 1317 # Number of branches executed
system.cpu.iew.exec_stores 1061 # Number of stores executed
system.cpu.iew.exec_rate 0.306305 # Inst execution rate
system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7307 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2841 # num instructions producing a value
system.cpu.iew.wb_consumers 4060 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back
system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5826 # Number of instructions committed
system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -288,63 +288,63 @@ system.cpu.commit.branches 916 # Nu
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
system.cpu.commit.function_calls 87 # Number of function calls committed.
system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 21779 # The number of ROB reads
system.cpu.rob.rob_writes 20794 # The number of ROB writes
system.cpu.rob.rob_reads 22904 # The number of ROB reads
system.cpu.rob.rob_writes 22029 # The number of ROB writes
system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5169 # Number of Instructions Simulated
system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads
system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10280 # number of integer regfile reads
system.cpu.int_regfile_writes 4987 # number of integer regfile writes
system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads
system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10565 # number of integer regfile reads
system.cpu.int_regfile_writes 5131 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 153 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use
system.cpu.icache.total_refs 1363 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks.
system.cpu.misc_regfile_reads 151 # number of misc regfile reads
system.cpu.icache.replacements 19 # number of replacements
system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use
system.cpu.icache.total_refs 1592 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits
system.cpu.icache.overall_hits::total 1363 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses
system.cpu.icache.overall_misses::total 418 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits
system.cpu.icache.overall_hits::total 1592 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses
system.cpu.icache.overall_misses::total 447 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -353,80 +353,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits
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@ -437,12 +437,12 @@ system.cpu.dcache.fast_writes 0 # nu
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@ -451,87 +451,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142
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system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -540,42 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:07:55
gem5 started Feb 11 2012 13:55:01
gem5 compiled Feb 12 2012 17:17:52
gem5 started Feb 12 2012 18:17:19
gem5 executing on zizzer
command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 10910500 because target called exit()
Exiting @ tick 11243500 because target called exit()

905
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:33
gem5 started Feb 11 2012 13:55:12
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:17:30
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 18201500 because target called exit()
Hello World!Exiting @ tick 18196500 because target called exit()

274
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18201500 # Number of ticks simulated
final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 18196500 # Number of ticks simulated
final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 71915 # Simulator instruction rate (inst/s)
host_op_rate 71898 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 245008016 # Simulator tick rate (ticks/s)
host_mem_usage 211144 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
host_inst_rate 90140 # Simulator instruction rate (inst/s)
host_op_rate 90112 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 306976844 # Simulator tick rate (ticks/s)
host_mem_usage 211148 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27072 # Number of bytes read from this memory
@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 423 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 36404 # number of cpu cycles simulated
system.cpu.numCycles 36394 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6274 # Number of cycles cpu stages are processed.
system.cpu.activity 17.234370 # Percentage of cycles cpu is active
system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 6227 # Number of cycles cpu stages are processed.
system.cpu.activity 17.109963 # Percentage of cycles cpu is active
system.cpu.comLoads 716 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1116 # Number of Branches instructions committed
@ -42,98 +42,98 @@ system.cpu.committedInsts 5340 # Nu
system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total)
system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads
system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads
system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1662 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted
system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 1617 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 1473 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 1487 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3977 # Number of Instructions Executed.
system.cpu.execution_unit.executions 3979 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use
system.cpu.icache.total_refs 791 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use
system.cpu.icache.total_refs 827 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits
system.cpu.icache.overall_hits::total 791 # number of overall hits
system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits
system.cpu.icache.overall_hits::total 827 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses
system.cpu.icache.overall_misses::total 347 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
@ -148,28 +148,28 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use
system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits
@ -186,14 +186,14 @@ system.cpu.dcache.demand_misses::cpu.data 340 # n
system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses
system.cpu.dcache.overall_misses::total 340 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
@ -206,10 +206,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -234,31 +234,31 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy
@ -282,17 +282,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
@ -311,13 +311,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked

6
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:53
gem5 started Feb 11 2012 14:04:05
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:26:23
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
Exiting @ tick 11989500 because target called exit()
Exiting @ tick 12299500 because target called exit()

834
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,264 +1,264 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000012 # Number of seconds simulated
sim_ticks 11989500 # Number of ticks simulated
final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 12299500 # Number of ticks simulated
final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 61798 # Simulator instruction rate (inst/s)
host_op_rate 111900 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 136747555 # Simulator tick rate (ticks/s)
host_mem_usage 218292 # Number of bytes of host memory used
host_inst_rate 59298 # Simulator instruction rate (inst/s)
host_op_rate 107375 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 134612595 # Simulator tick rate (ticks/s)
host_mem_usage 218308 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 5416 # Number of instructions simulated
sim_ops 9809 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28288 # Number of bytes read from this memory
system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory
system.physmem.bytes_read 28864 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 442 # Number of read requests responded to by this memory
system.physmem.num_reads 451 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 23980 # number of cpu cycles simulated
system.cpu.numCycles 24600 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 3019 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits
system.cpu.BPredUnit.lookups 3225 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3508 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3329 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups
system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 3795 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 3571 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing
system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle
system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 16792 # Type of FU issued
system.cpu.iq.rate 0.700250 # Inst issue rate
system.cpu.iq.fu_busy_cnt 133 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 17955 # Type of FU issued
system.cpu.iq.rate 0.729878 # Inst issue rate
system.cpu.iq.fu_busy_cnt 198 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 3065 # number of memory reference insts executed
system.cpu.iew.exec_branches 1589 # Number of branches executed
system.cpu.iew.exec_stores 1340 # Number of stores executed
system.cpu.iew.exec_rate 0.664804 # Inst execution rate
system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 15612 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10251 # num instructions producing a value
system.cpu.iew.wb_consumers 15131 # num instructions consuming a value
system.cpu.iew.exec_refs 3212 # number of memory reference insts executed
system.cpu.iew.exec_branches 1649 # Number of branches executed
system.cpu.iew.exec_stores 1365 # Number of stores executed
system.cpu.iew.exec_rate 0.686504 # Inst execution rate
system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 16456 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10670 # num instructions producing a value
system.cpu.iew.wb_consumers 15796 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back
system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions
system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5416 # Number of instructions committed
system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -269,62 +269,62 @@ system.cpu.commit.branches 1214 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9714 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 34653 # The number of ROB reads
system.cpu.rob.rob_writes 42403 # The number of ROB writes
system.cpu.rob.rob_reads 36584 # The number of ROB reads
system.cpu.rob.rob_writes 45550 # The number of ROB writes
system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5416 # Number of Instructions Simulated
system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5416 # Number of Instructions Simulated
system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads
system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 23430 # number of integer regfile reads
system.cpu.int_regfile_writes 14518 # number of integer regfile writes
system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads
system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 24791 # number of integer regfile reads
system.cpu.int_regfile_writes 15157 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
system.cpu.misc_regfile_reads 7406 # number of misc regfile reads
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use
system.cpu.icache.total_refs 1498 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use
system.cpu.icache.total_refs 1576 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits
system.cpu.icache.overall_hits::total 1498 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
system.cpu.icache.overall_misses::total 368 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits
system.cpu.icache.overall_hits::total 1576 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 392 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 392 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 392 # number of overall misses
system.cpu.icache.overall_misses::total 392 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13905000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 13905000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 13905000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 13905000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 13905000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 13905000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199187 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.199187 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -333,80 +333,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10684500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10684500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10684500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10684500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10684500 # number of overall MSHR miss cycles
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@ -415,101 +415,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -518,42 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4535500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13737500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9393500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2262000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

6
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:05:17
gem5 started Feb 11 2012 13:09:24
gem5 compiled Feb 12 2012 17:15:14
gem5 started Feb 12 2012 17:33:14
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -11,4 +11,4 @@ info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
Exiting @ tick 13202000 because target called exit()
Exiting @ tick 13973500 because target called exit()

1095
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

6
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:33
gem5 started Feb 11 2012 13:55:34
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:17:51
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
@ -18,4 +18,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 25058500 because target called exit()
Exiting @ tick 25007500 because target called exit()

280
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
View file

@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
sim_ticks 25058500 # Number of ticks simulated
final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 25007500 # Number of ticks simulated
final_tick 25007500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 93467 # Simulator instruction rate (inst/s)
host_op_rate 93457 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 154309649 # Simulator tick rate (ticks/s)
host_mem_usage 211048 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
host_inst_rate 100667 # Simulator instruction rate (inst/s)
host_op_rate 100655 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 165855291 # Simulator tick rate (ticks/s)
host_mem_usage 211052 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27904 # Number of bytes read from this memory
@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu
system.physmem.num_reads 436 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1113554283 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 761099028 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1113554283 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 1115825252 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 762651205 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1115825252 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 50118 # number of cpu cycles simulated
system.cpu.numCycles 50016 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 21887 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17625 # Number of cycles cpu stages are processed.
system.cpu.activity 35.167006 # Percentage of cycles cpu is active
system.cpu.timesIdled 453 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32683 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17333 # Number of cycles cpu stages are processed.
system.cpu.activity 34.654910 # Percentage of cycles cpu is active
system.cpu.comLoads 2226 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3359 # Number of Branches instructions committed
@ -42,106 +42,106 @@ system.cpu.committedInsts 15175 # Nu
system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total)
system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi 3.295947 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads
system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 3.295947 # CPI: Total CPI of All Threads
system.cpu.ipc 0.303403 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 5166 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target.
system.cpu.ipc_total 0.303403 # IPC: Total IPC of All Threads
system.cpu.branch_predictor.lookups 5015 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 3353 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 2379 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 3332 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 2040 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File
system.cpu.branch_predictor.BTBHitPct 61.224490 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 2214 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2801 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14401 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 25512 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3845 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 11051 # Number of Instructions Executed.
system.cpu.regfile_manager.regForwards 4993 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3952 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 1316 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1000 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 2316 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 1043 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 68.949092 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 11084 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed.
system.cpu.stage0.idleCycles 36923 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13093 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 26.177623 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 40814 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9202 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 18.398113 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 41191 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8825 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 17.644354 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 47132 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.utilization 5.766155 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 40690 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9326 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 18.646033 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use
system.cpu.icache.total_refs 3085 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 165.557258 # Cycle average of tags in use
system.cpu.icache.total_refs 2602 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 8.702341 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits
system.cpu.icache.overall_hits::total 3085 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
system.cpu.icache.overall_misses::total 366 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 165.557258 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.080839 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.080839 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2602 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2602 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2602 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2602 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2602 # number of overall hits
system.cpu.icache.overall_hits::total 2602 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
system.cpu.icache.overall_misses::total 368 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20203500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 20203500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 20203500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 20203500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 20203500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 20203500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2970 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2970 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2970 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2970 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2970 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2970 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123906 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123906 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123906 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
@ -154,22 +154,22 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15872000
system.cpu.icache.demand_mshr_miss_latency::total 15872000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15872000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15872000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.087221 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101347 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use
system.cpu.dcache.tagsinuse 97.041769 # Cycle average of tags in use
system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 97.082868 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023702 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023702 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::cpu.data 97.041769 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.023692 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2168 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2168 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1142 # number of WriteReq hits
@ -188,14 +188,14 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n
system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
system.cpu.dcache.overall_misses::total 358 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3282500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3282500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16398000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16398000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19680500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19680500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19680500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19680500 # number of overall miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3281500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3281500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16397000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 16397000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 19678500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 19678500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 19678500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 19678500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
@ -210,10 +210,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026056
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208044 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.097601 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.097601 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54660 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -238,34 +238,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2838000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2838000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2837000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2837000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4545000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4545000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7382000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7382000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7382000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 196.205624 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 165.036640 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.270807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005037 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 164.948941 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 31.256684 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.005034 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005991 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005988 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
@ -284,16 +284,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 299 #
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15533000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2777500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18310500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2776500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18309500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4442500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4442500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15533000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7220000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7219000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15533000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7220000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7219000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
@ -313,12 +313,12 @@ system.cpu.l2cache.demand_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked

6
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:33
gem5 started Feb 11 2012 13:55:35
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:17:52
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@ -18,4 +18,4 @@ LDTX: Passed
LDTW: Passed
STTW: Passed
Done
Exiting @ tick 18114000 because target called exit()
Exiting @ tick 19744500 because target called exit()

802
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000018 # Number of seconds simulated
sim_ticks 18114000 # Number of ticks simulated
final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 19744500 # Number of ticks simulated
final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 120891 # Simulator instruction rate (inst/s)
host_op_rate 120873 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 151511225 # Simulator tick rate (ticks/s)
host_mem_usage 211580 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_inst_rate 108489 # Simulator instruction rate (inst/s)
host_op_rate 108474 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 148211557 # Simulator tick rate (ticks/s)
host_mem_usage 211612 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 14449 # Number of instructions simulated
sim_ops 14449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30464 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory
system.physmem.bytes_read 30976 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 476 # Number of read requests responded to by this memory
system.physmem.num_reads 484 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 36229 # number of cpu cycles simulated
system.cpu.numCycles 39490 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 5641 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits
system.cpu.BPredUnit.lookups 6899 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed
system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked
system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 7524 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7253 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups
system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 8680 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 8245 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 639 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit.
system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 705 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle
system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 18581 # Type of FU issued
system.cpu.iq.rate 0.512876 # Inst issue rate
system.cpu.iq.fu_busy_cnt 139 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses
system.cpu.iq.FU_type_0::total 21701 # Type of FU issued
system.cpu.iq.rate 0.549532 # Inst issue rate
system.cpu.iq.fu_busy_cnt 179 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed
system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking
system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute
system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1102 # number of nop insts executed
system.cpu.iew.exec_refs 4620 # number of memory reference insts executed
system.cpu.iew.exec_branches 3963 # Number of branches executed
system.cpu.iew.exec_stores 1758 # Number of stores executed
system.cpu.iew.exec_rate 0.492837 # Inst execution rate
system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 17429 # cumulative count of insts written-back
system.cpu.iew.wb_producers 8123 # num instructions producing a value
system.cpu.iew.wb_consumers 9726 # num instructions consuming a value
system.cpu.iew.exec_nop 1163 # number of nop insts executed
system.cpu.iew.exec_refs 5392 # number of memory reference insts executed
system.cpu.iew.exec_branches 4300 # Number of branches executed
system.cpu.iew.exec_stores 2114 # Number of stores executed
system.cpu.iew.exec_rate 0.519397 # Inst execution rate
system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 19916 # cumulative count of insts written-back
system.cpu.iew.wb_producers 9270 # num instructions producing a value
system.cpu.iew.wb_consumers 11399 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back
system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15175 # Number of instructions committed
system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@ -267,62 +267,62 @@ system.cpu.commit.branches 3359 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 46300 # The number of ROB reads
system.cpu.rob.rob_writes 43308 # The number of ROB writes
system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.rob.rob_reads 52944 # The number of ROB reads
system.cpu.rob.rob_writes 51625 # The number of ROB writes
system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads
system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 28557 # number of integer regfile reads
system.cpu.int_regfile_writes 15938 # number of integer regfile writes
system.cpu.misc_regfile_reads 6251 # number of misc regfile reads
system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads
system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 32680 # number of integer regfile reads
system.cpu.int_regfile_writes 18187 # number of integer regfile writes
system.cpu.misc_regfile_reads 7045 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use
system.cpu.icache.total_refs 4151 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use
system.cpu.icache.total_refs 5020 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits
system.cpu.icache.overall_hits::total 4151 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses
system.cpu.icache.overall_misses::total 457 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits
system.cpu.icache.overall_hits::total 5020 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses
system.cpu.icache.overall_misses::total 486 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -331,84 +331,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use
system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use
system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 102.149831 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.024939 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.024939 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2672 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 2672 # number of ReadReq hits
system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 3706 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 3706 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 3706 # number of overall hits
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system.cpu.dcache.overall_hits::total 4077 # number of overall hits
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system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles
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system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::total 4228 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096 # average overall miss latency
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system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -417,14 +417,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
@ -433,87 +433,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
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system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
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system.cpu.l2cache.occ_blocks::cpu.data 35.889452 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397 # average ReadReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -522,42 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

56
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 11 2012 13:08:33
gem5 started Feb 11 2012 13:55:55
gem5 compiled Feb 12 2012 17:18:12
gem5 started Feb 12 2012 18:18:13
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
@ -10,10 +10,10 @@ info: Entering event queue @ 0. Starting simulation...
Init done
[Iteration 1, Thread 2] Got lock
[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 1, Thread 1] Got lock
[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 1, Thread 3] Got lock
[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 1, Thread 1] Got lock
[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
Iteration 1 completed
[Iteration 2, Thread 1] Got lock
[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
@ -22,12 +22,12 @@ Iteration 1 completed
[Iteration 2, Thread 2] Got lock
[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
Iteration 2 completed
[Iteration 3, Thread 2] Got lock
[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 3, Thread 3] Got lock
[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 3, Thread 1] Got lock
[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 3, Thread 3] Got lock
[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 3, Thread 2] Got lock
[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
Iteration 3 completed
[Iteration 4, Thread 1] Got lock
[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
@ -36,19 +36,19 @@ Iteration 3 completed
[Iteration 4, Thread 3] Got lock
[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
Iteration 4 completed
[Iteration 5, Thread 2] Got lock
[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 5, Thread 1] Got lock
[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 5, Thread 3] Got lock
[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 5, Thread 2] Got lock
[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
Iteration 5 completed
[Iteration 6, Thread 3] Got lock
[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 6, Thread 1] Got lock
[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 6, Thread 2] Got lock
[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 6, Thread 3] Got lock
[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
Iteration 6 completed
[Iteration 7, Thread 1] Got lock
[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
@ -57,26 +57,26 @@ Iteration 6 completed
[Iteration 7, Thread 3] Got lock
[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
Iteration 7 completed
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 8, Thread 2] Got lock
[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 8, Thread 1] Got lock
[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
[Iteration 8, Thread 3] Got lock
[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
Iteration 8 completed
[Iteration 9, Thread 3] Got lock
[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
[Iteration 9, Thread 1] Got lock
[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 9, Thread 2] Got lock
[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
[Iteration 9, Thread 1] Got lock
[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
Iteration 9 completed
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
[Iteration 10, Thread 3] Got lock
[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
[Iteration 10, Thread 1] Got lock
[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
[Iteration 10, Thread 3] Got lock
[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
[Iteration 10, Thread 2] Got lock
[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
Iteration 10 completed
PASSED :-)
Exiting @ tick 104317500 because target called exit()
Exiting @ tick 111402500 because target called exit()

3519
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
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