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stats: Update stats for syscall emulation Linux kernel changes.

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This commit is contained in:
Ali Saidi 2012-08-15 10:38:05 -04:00
parent dd1b346584
commit 73e9e923d0
160 changed files with 10099 additions and 10112 deletions
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4
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
View file

@ -489,7 +489,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
@ -512,7 +512,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:54:18
gem5 started Jul 2 2012 11:32:18
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:13:42
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 389181871500 because target called exit()
Exiting @ tick 389171398000 because target called exit()

994
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:45:41
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:13:47
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 744764119000 because target called exit()
Exiting @ tick 744764112500 because target called exit()

68
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.744764 # Number of seconds simulated
sim_ticks 744764119000 # Number of ticks simulated
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 3186892 # Simulator instruction rate (inst/s)
host_op_rate 3196366 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1598188492 # Simulator tick rate (ticks/s)
host_mem_usage 214172 # Number of bytes of host memory used
host_seconds 466.01 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940452044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1385817593 # Number of bytes read from this memory
system.physmem.bytes_read::total 7326269637 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5940452044 # Number of instructions bytes read from this memory
host_inst_rate 3155762 # Simulator instruction rate (inst/s)
host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1582576951 # Simulator tick rate (ticks/s)
host_mem_usage 222108 # Number of bytes of host memory used
host_seconds 470.60 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1385817592 # Number of bytes read from this memory
system.physmem.bytes_read::total 7326269584 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5940451992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5940451992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 614672063 # Number of bytes written to this memory
system.physmem.bytes_written::total 614672063 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1485113011 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 402512844 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1887625855 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 1485112998 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 402512843 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1887625841 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 166846816 # Number of write requests responded to by this memory
system.physmem.num_writes::total 166846816 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 1326 # Number of other requests responded to by this memory
system.physmem.num_other::total 1326 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7976286575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1860746990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9837033566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1860747005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9837033580 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7976286575 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 825324485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 825324492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 825324492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358051 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numCycles 1489528226 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108101 # Number of instructions committed
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.committedInsts 1485108088 # Number of instructions committed
system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481286 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343158 # number of times the integer registers were written
system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343145 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365766 # number of memory refs
system.cpu.num_load_insts 402515345 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1489528239 # Number of busy cycles
system.cpu.num_busy_cycles 1489528226 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
View file

@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:54:18
gem5 started Jul 2 2012 12:13:11
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:13:49
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -38,4 +38,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2063177751000 because target called exit()
Exiting @ tick 2063177737000 because target called exit()

114
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.063178 # Number of seconds simulated
sim_ticks 2063177751000 # Number of ticks simulated
final_tick 2063177751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2063177737000 # Number of ticks simulated
final_tick 2063177737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1349558 # Simulator instruction rate (inst/s)
host_op_rate 1353570 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1874864984 # Simulator tick rate (ticks/s)
host_mem_usage 222108 # Number of bytes of host memory used
host_seconds 1100.44 # Real time elapsed on the host
sim_insts 1485108101 # Number of instructions simulated
sim_ops 1489523295 # Number of ops (including micro ops) simulated
host_inst_rate 1527975 # Simulator instruction rate (inst/s)
host_op_rate 1532517 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2122729697 # Simulator tick rate (ticks/s)
host_mem_usage 231576 # Number of bytes of host memory used
host_seconds 971.95 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1672576 # Number of bytes read from this memory
system.physmem.bytes_read::total 1738304 # Number of bytes read from this memory
@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 31858 # To
system.physmem.bw_total::cpu.data 810680 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 920801 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4126355502 # number of cpu cycles simulated
system.cpu.numCycles 4126355474 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1485108101 # Number of instructions committed
system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.committedInsts 1485108088 # Number of instructions committed
system.cpu.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481286 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481298 # number of integer instructions
system.cpu.num_conditional_control_insts 78161762 # number of instructions that are conditional controls
system.cpu.num_int_insts 1319481286 # number of integer instructions
system.cpu.num_fp_insts 8454127 # number of float instructions
system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written
system.cpu.num_int_register_reads 2499743560 # number of times the integer registers were read
system.cpu.num_int_register_writes 1234343144 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read
system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written
system.cpu.num_mem_refs 569365767 # number of memory refs
system.cpu.num_load_insts 402515346 # Number of load instructions
system.cpu.num_mem_refs 569365766 # number of memory refs
system.cpu.num_load_insts 402515345 # Number of load instructions
system.cpu.num_store_insts 166850421 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 4126355502 # Number of busy cycles
system.cpu.num_busy_cycles 4126355474 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.tagsinuse 906.409372 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 906.409378 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111892 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1341564.491418 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 906.409372 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 906.409378 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.442583 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.442583 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1485111905 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1485111905 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1485111905 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1485111905 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1485111905 # number of overall hits
system.cpu.icache.overall_hits::total 1485111905 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 1485111892 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1485111892 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1485111892 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1485111892 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1485111892 # number of overall hits
system.cpu.icache.overall_hits::total 1485111892 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 58777000
system.cpu.icache.demand_miss_latency::total 58777000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 58777000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 58777000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485113012 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1485113012 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1485113012 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1485112999 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1485112999 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1485112999 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1485112999 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1485112999 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291
system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.205153 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4095.205181 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 588945000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.205153 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 588931000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4095.205181 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 402319358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319358 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 166587088 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 568906446 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 568906446 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 568906446 # number of overall hits
system.cpu.dcache.overall_hits::total 568906446 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 568906445 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 568906445 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 568906445 # number of overall hits
system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 193486 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 259728 # number of WriteReq misses
@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7443302000
system.cpu.dcache.demand_miss_latency::total 7443302000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7443302000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7443302000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512844 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 402512843 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 569359660 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 569359660 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 569359660 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359660 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 569359659 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 569359659 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 569359659 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 569359659 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001557 # miss rate for WriteReq accesses
@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2614 # number of replacements
system.cpu.l2cache.tagsinuse 22185.384662 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 22185.384813 # Cycle average of tags in use
system.cpu.l2cache.total_refs 527657 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23998 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.987541 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 20828.536366 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 857.441703 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 499.406594 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 20828.536507 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 857.441709 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 499.406597 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.635636 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.026167 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.015241 # Average percentage of cache occupancy

4
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
View file

@ -510,7 +510,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
@ -533,7 +533,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

10
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 12:44:41
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:23:13
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -19,12 +19,12 @@ info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
info: Increasing stack size by one page.
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
info: Increasing stack size by one page.
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@ -40,4 +40,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 636963896500 because target called exit()
Exiting @ tick 636923447500 because target called exit()

1002
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
View file

@ -120,8 +120,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]

6
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:08:17
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:24:05
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 963992704000 because target called exit()
Exiting @ tick 963992671000 because target called exit()

76
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.963993 # Number of seconds simulated
sim_ticks 963992704000 # Number of ticks simulated
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 963992671000 # Number of ticks simulated
final_tick 963992671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1254577 # Simulator instruction rate (inst/s)
host_op_rate 2311626 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1374282564 # Simulator tick rate (ticks/s)
host_mem_usage 216676 # Number of bytes of host memory used
host_seconds 701.45 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452913 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586825 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133912 # Number of instructions bytes read from this memory
host_inst_rate 1263596 # Simulator instruction rate (inst/s)
host_op_rate 2328243 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1384161146 # Simulator tick rate (ticks/s)
host_mem_usage 224820 # Number of bytes of host memory used
host_seconds 696.45 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1842452909 # Number of bytes read from this memory
system.physmem.bytes_read::total 11334586469 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 9492133560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 864451000 # Number of bytes written to this memory
system.physmem.bytes_written::total 864451000 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1186516739 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558864 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 1186516695 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 419042121 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1605558816 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 188186057 # Number of write requests responded to by this memory
system.physmem.num_writes::total 188186057 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9846686466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686466 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740189 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686466 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012863 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 9846686438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1911272735 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 11757959173 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9846686438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9846686438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 896740220 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 896740220 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9846686438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012955 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699393 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numCycles 1927985343 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025313 # Number of instructions committed
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354436 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228178 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
system.cpu.num_busy_cycles 1927985343 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
View file

@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
@ -202,7 +202,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

8
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 13:03:08
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:30:12
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -39,4 +39,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1801979727000 because target called exit()
Exiting @ tick 1801979679000 because target called exit()

114
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.801980 # Number of seconds simulated
sim_ticks 1801979727000 # Number of ticks simulated
final_tick 1801979727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1801979679000 # Number of ticks simulated
final_tick 1801979679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 622629 # Simulator instruction rate (inst/s)
host_op_rate 1147227 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1274922997 # Simulator tick rate (ticks/s)
host_mem_usage 228496 # Number of bytes of host memory used
host_seconds 1413.40 # Real time elapsed on the host
sim_insts 880025313 # Number of instructions simulated
sim_ops 1621493983 # Number of ops (including micro ops) simulated
host_inst_rate 670221 # Simulator instruction rate (inst/s)
host_op_rate 1234919 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1372375195 # Simulator tick rate (ticks/s)
host_mem_usage 233400 # Number of bytes of host memory used
host_seconds 1313.04 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1682368 # Number of bytes read from this memory
system.physmem.bytes_read::total 1728576 # Number of bytes read from this memory
@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 25643 # To
system.physmem.bw_total::cpu.data 933622 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1048411 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3603959454 # number of cpu cycles simulated
system.cpu.numCycles 3603959358 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 880025313 # Number of instructions committed
system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.committedInsts 880025278 # Number of instructions committed
system.cpu.committedOps 1621493926 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354436 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_conditional_control_insts 99478856 # number of instructions that are conditional controls
system.cpu.num_int_insts 1621354436 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 5129484088 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860970 # number of times the integer registers were written
system.cpu.num_int_register_reads 5129483910 # number of times the integer registers were read
system.cpu.num_int_register_writes 2493860878 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 607228182 # number of memory refs
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228178 # number of memory refs
system.cpu.num_load_insts 419042121 # Number of load instructions
system.cpu.num_store_insts 188186057 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3603959454 # Number of busy cycles
system.cpu.num_busy_cycles 3603959358 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.tagsinuse 660.169533 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 660.169550 # Cycle average of tags in use
system.cpu.icache.total_refs 1186515974 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 1643373.925208 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 660.169533 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 660.169550 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.322348 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.322348 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits
system.cpu.icache.overall_hits::total 1186516018 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 1186515974 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1186515974 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1186515974 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1186515974 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1186515974 # number of overall hits
system.cpu.icache.overall_hits::total 1186515974 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 40521000
system.cpu.icache.demand_miss_latency::total 40521000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40521000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40521000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1186516696 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1186516696 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1186516696 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1186516696 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1186516696 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000001 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698
system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.884021 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4094.884130 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786130 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 788858000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.884021 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 1372.670230 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 788810000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4094.884130 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999728 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999728 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 418844799 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844799 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 187941335 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 187941335 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 606786134 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786134 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786134 # number of overall hits
system.cpu.dcache.overall_hits::total 606786134 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 606786130 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 606786130 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 606786130 # number of overall hits
system.cpu.dcache.overall_hits::total 606786130 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7311185000
system.cpu.dcache.demand_miss_latency::total 7311185000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7311185000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7311185000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042125 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 607228182 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228182 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228182 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228182 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 607228178 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 607228178 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 607228178 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 607228178 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2581 # number of replacements
system.cpu.l2cache.tagsinuse 22161.849584 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 22161.850174 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506758 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 23832 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.263763 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21018.400125 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 596.832039 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.617420 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 21018.400685 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 596.832055 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 546.617434 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.018214 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016681 # Average percentage of cache occupancy

4
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:53:37
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:13:50
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 122215830000 because target called exit()
Exiting @ tick 122215823500 because target called exit()

68
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.122216 # Number of seconds simulated
sim_ticks 122215830000 # Number of ticks simulated
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2951739 # Simulator instruction rate (inst/s)
host_op_rate 2951861 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1479540198 # Simulator tick rate (ticks/s)
host_mem_usage 346528 # Number of bytes of host memory used
host_seconds 82.60 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977686044 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674009 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977686044 # Number of instructions bytes read from this memory
host_inst_rate 2900370 # Simulator instruction rate (inst/s)
host_op_rate 2900489 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1453791405 # Simulator tick rate (ticks/s)
host_mem_usage 355144 # Number of bytes of host memory used
host_seconds 84.07 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory
system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory
system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 244421511 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220434 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641945 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory
system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory
system.physmem.num_other::total 3886 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543566 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835198 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503032 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451567 # number of times the integer registers were written
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 244431661 # Number of busy cycles
system.cpu.num_busy_cycles 244431648 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
View file

@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:54:18
gem5 started Jul 2 2012 12:31:43
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:15:25
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 362481577000 because target called exit()
Exiting @ tick 362481563000 because target called exit()

114
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.362482 # Number of seconds simulated
sim_ticks 362481577000 # Number of ticks simulated
final_tick 362481577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 362481563000 # Number of ticks simulated
final_tick 362481563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1217197 # Simulator instruction rate (inst/s)
host_op_rate 1217247 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1809539933 # Simulator tick rate (ticks/s)
host_mem_usage 354248 # Number of bytes of host memory used
host_seconds 200.32 # Real time elapsed on the host
sim_insts 243825163 # Number of instructions simulated
sim_ops 243835278 # Number of ops (including micro ops) simulated
host_inst_rate 1415125 # Simulator instruction rate (inst/s)
host_op_rate 1415183 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2103788292 # Simulator tick rate (ticks/s)
host_mem_usage 363728 # Number of bytes of host memory used
host_seconds 172.30 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 155197 # To
system.physmem.bw_total::cpu.data 2599680 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2754877 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 724963154 # number of cpu cycles simulated
system.cpu.numCycles 724963126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 243825163 # Number of instructions committed
system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.committedInsts 243825150 # Number of instructions committed
system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18619960 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726506 # number of integer instructions
system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
system.cpu.num_int_insts 194726494 # number of integer instructions
system.cpu.num_fp_insts 11630 # number of float instructions
system.cpu.num_int_register_reads 456819010 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451566 # number of times the integer registers were written
system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
system.cpu.num_mem_refs 105711442 # number of memory refs
system.cpu.num_load_insts 82803522 # Number of load instructions
system.cpu.num_mem_refs 105711441 # number of memory refs
system.cpu.num_load_insts 82803521 # Number of load instructions
system.cpu.num_store_insts 22907920 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 724963154 # Number of busy cycles
system.cpu.num_busy_cycles 724963126 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.tagsinuse 725.564686 # Cycle average of tags in use
system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 725.564713 # Cycle average of tags in use
system.cpu.icache.total_refs 244420617 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 277120.880952 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 725.564686 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 725.564713 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.354280 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.354280 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
system.cpu.icache.overall_hits::total 244420630 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 49333000
system.cpu.icache.demand_miss_latency::total 49333000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 49333000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 49333000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576
system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.804804 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 3563.804941 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134384281000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3563.804804 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134384267000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3563.804941 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.870070 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.870070 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182818 # number of overall hits
system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 13778134000
system.cpu.dcache.demand_miss_latency::total 13778134000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13778134000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13778134000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 105122385 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122385 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122385 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122385 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9744.633089 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 9744.633464 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813121 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 15586 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 116.330104 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 8861.504688 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 738.799807 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 144.328594 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 8861.505031 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 738.799835 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 144.328599 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.270432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.022546 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004405 # Average percentage of cache occupancy

4
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -510,7 +510,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
@ -533,7 +533,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

10
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 13:12:36
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:35:52
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -23,6 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Exiting @ tick 68340167000 because target called exit()
Exiting @ tick 68408131000 because target called exit()

1004
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -120,8 +120,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]

6
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:20:09
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:40:35
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 168950072000 because target called exit()
Exiting @ tick 168950039000 because target called exit()

76
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.168950 # Number of seconds simulated
sim_ticks 168950072000 # Number of ticks simulated
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 168950039000 # Number of ticks simulated
final_tick 168950039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1244063 # Simulator instruction rate (inst/s)
host_op_rate 2190595 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1330377575 # Simulator tick rate (ticks/s)
host_mem_usage 351912 # Number of bytes of host memory used
host_seconds 126.99 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246015 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815679 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569664 # Number of instructions bytes read from this memory
host_inst_rate 1227990 # Simulator instruction rate (inst/s)
host_op_rate 2162293 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1313189467 # Simulator tick rate (ticks/s)
host_mem_usage 359036 # Number of bytes of host memory used
host_seconds 128.66 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 717246011 # Number of bytes read from this memory
system.physmem.bytes_read::total 2458815323 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 243173115 # Number of bytes written to this memory
system.physmem.bytes_written::total 243173115 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 217696208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779450 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475658 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 90779446 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308475610 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 31439751 # Number of write requests responded to by this memory
system.physmem.num_writes::total 31439751 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10308191310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245313462 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553504772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191310 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684632854 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992824164 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 10308191240 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 4245314267 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14553505507 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10308191240 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10308191240 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1439319674 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1439319674 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10308191240 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633941 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825181 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numCycles 337900079 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186171 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written
system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219135 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 337900145 # Number of busy cycles
system.cpu.num_busy_cycles 337900079 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
View file

@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
@ -202,7 +202,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

8
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 13:28:56
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:42:54
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -23,4 +23,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 368209254000 because target called exit()
Exiting @ tick 368209206000 because target called exit()

122
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.368209 # Number of seconds simulated
sim_ticks 368209254000 # Number of ticks simulated
final_tick 368209254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 368209206000 # Number of ticks simulated
final_tick 368209206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 606195 # Simulator instruction rate (inst/s)
host_op_rate 1067413 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1412802854 # Simulator tick rate (ticks/s)
host_mem_usage 363612 # Number of bytes of host memory used
host_seconds 260.62 # Real time elapsed on the host
sim_insts 157988583 # Number of instructions simulated
sim_ops 278192520 # Number of ops (including micro ops) simulated
host_inst_rate 651126 # Simulator instruction rate (inst/s)
host_op_rate 1146527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1517517563 # Simulator tick rate (ticks/s)
host_mem_usage 367484 # Number of bytes of host memory used
host_seconds 242.64 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1879680 # Number of bytes read from this memory
system.physmem.bytes_read::total 1931392 # Number of bytes read from this memory
@ -24,54 +24,54 @@ system.physmem.num_reads::total 30178 # Nu
system.physmem.num_writes::writebacks 227 # Number of write requests responded to by this memory
system.physmem.num_writes::total 227 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 140442 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5104923 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5245365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5104924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 5245366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 140442 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 39456 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 39456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 140442 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5104923 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5284821 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5104924 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5284822 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 736418508 # number of cpu cycles simulated
system.cpu.numCycles 736418412 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 157988583 # Number of instructions committed
system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.committedInsts 157988548 # Number of instructions committed
system.cpu.committedOps 278192463 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186171 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
system.cpu.num_int_insts 278186171 # number of integer instructions
system.cpu.num_fp_insts 40 # number of float instructions
system.cpu.num_int_register_reads 834011910 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010914 # number of times the integer registers were written
system.cpu.num_int_register_reads 834011732 # number of times the integer registers were read
system.cpu.num_int_register_writes 341010822 # number of times the integer registers were written
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
system.cpu.num_mem_refs 122219139 # number of memory refs
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219135 # number of memory refs
system.cpu.num_load_insts 90779384 # Number of load instructions
system.cpu.num_store_insts 31439751 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 736418508 # Number of busy cycles
system.cpu.num_busy_cycles 736418412 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 665.897663 # Cycle average of tags in use
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 665.897748 # Cycle average of tags in use
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 665.897663 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 665.897748 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.325145 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.325145 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
system.cpu.icache.overall_hits::total 217695401 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
system.cpu.icache.overall_hits::total 217695357 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 45336000
system.cpu.icache.demand_miss_latency::total 45336000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 45336000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 45336000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891
system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2062733 # number of replacements
system.cpu.dcache.tagsinuse 4076.463091 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4076.463619 # Cycle average of tags in use
system.cpu.dcache.total_refs 120152368 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126234114000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.463091 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 58.133676 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 126234066000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4076.463619 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.995230 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818730 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 31333642 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 31333642 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 120152372 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152372 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152372 # number of overall hits
system.cpu.dcache.overall_hits::total 120152372 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 120152368 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 120152368 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 120152368 # number of overall hits
system.cpu.dcache.overall_hits::total 120152368 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 30195678000
system.cpu.dcache.demand_miss_latency::total 30195678000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30195678000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30195678000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779450 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 122219201 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219201 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219201 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219201 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 122219197 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 122219197 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 122219197 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 122219197 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1081 # number of replacements
system.cpu.l2cache.tagsinuse 19722.096664 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 19722.099231 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3991053 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 30157 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 132.342508 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 19370.042647 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 209.723692 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 142.330324 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 19370.045173 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 209.723718 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 142.330341 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.591127 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.006400 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.004344 # Average percentage of cache occupancy

23
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -1,28 +1,15 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 26 2012 21:30:36
gem5 started Jul 26 2012 23:13:36
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:47:07
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: ***********************info: Increasing stack size by one page.
***************info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
***********
**************************
58924 words stored in 3784810 bytes
@ -35,6 +22,8 @@ Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
info: Increasing stack size by one page.
info: Increasing stack size by one page.
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
* how fast the program is it
* I am wondering whether to invite to the party
@ -80,4 +69,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 460506550000 because target called exit()
Exiting @ tick 460397003000 because target called exit()

1096
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -120,8 +120,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]

6
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:38:11
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 18:52:16
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -69,4 +69,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 885229360000 because target called exit()
Exiting @ tick 885229327000 because target called exit()

76
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.885229 # Number of seconds simulated
sim_ticks 885229360000 # Number of ticks simulated
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 885229327000 # Number of ticks simulated
final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1285236 # Simulator instruction rate (inst/s)
host_op_rate 2376545 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1375933868 # Simulator tick rate (ticks/s)
host_mem_usage 220604 # Number of bytes of host memory used
host_seconds 643.37 # Real time elapsed on the host
sim_insts 826877145 # Number of instructions simulated
sim_ops 1528988757 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655660 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432532 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776872 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776872 # Number of instructions bytes read from this memory
host_inst_rate 1279506 # Simulator instruction rate (inst/s)
host_op_rate 2365950 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1369799774 # Simulator tick rate (ticks/s)
host_mem_usage 228100 # Number of bytes of host memory used
host_seconds 646.25 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory
system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory
system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1068347109 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102189 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 9654872803 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443475 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443475 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872803 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308881 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numCycles 1770458655 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877145 # Number of instructions committed
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317558 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262341 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
system.cpu.num_busy_cycles 1770458655 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr
@ -202,7 +202,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

8
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 13:47:25
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 19:03:12
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -69,4 +69,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 1652606875000 because target called exit()
Exiting @ tick 1652606827000 because target called exit()

128
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.652607 # Number of seconds simulated
sim_ticks 1652606875000 # Number of ticks simulated
final_tick 1652606875000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 1652606827000 # Number of ticks simulated
final_tick 1652606827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 673883 # Simulator instruction rate (inst/s)
host_op_rate 1246085 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1346830511 # Simulator tick rate (ticks/s)
host_mem_usage 232676 # Number of bytes of host memory used
host_seconds 1227.03 # Real time elapsed on the host
sim_insts 826877145 # Number of instructions simulated
sim_ops 1528988757 # Number of ops (including micro ops) simulated
host_inst_rate 715148 # Simulator instruction rate (inst/s)
host_op_rate 1322389 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1429304042 # Simulator tick rate (ticks/s)
host_mem_usage 236556 # Number of bytes of host memory used
host_seconds 1156.23 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory
system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory
@ -24,54 +24,54 @@ system.physmem.num_reads::total 429429 # Nu
system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory
system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74781 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 16555584 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16630365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 16555585 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16630366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74781 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74781 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 12530796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12530796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12530796 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 12530797 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 12530797 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 12530797 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74781 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 16555584 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 16555585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 29161162 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3305213750 # number of cpu cycles simulated
system.cpu.numCycles 3305213654 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 826877145 # Number of instructions committed
system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.committedInsts 826877110 # Number of instructions committed
system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls
system.cpu.num_int_insts 1528317558 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 4441632810 # number of times the integer registers were read
system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written
system.cpu.num_int_register_reads 4441632632 # number of times the integer registers were read
system.cpu.num_int_register_writes 1993077392 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 533262345 # number of memory refs
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262341 # number of memory refs
system.cpu.num_load_insts 384102156 # Number of load instructions
system.cpu.num_store_insts 149160185 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 3305213750 # Number of busy cycles
system.cpu.num_busy_cycles 3305213654 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1253 # number of replacements
system.cpu.icache.tagsinuse 881.608185 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 881.608211 # Cycle average of tags in use
system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 881.608185 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 881.608211 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.430473 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.430473 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits
system.cpu.icache.overall_hits::total 1068344296 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits
system.cpu.icache.overall_hits::total 1068344252 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 120792000
system.cpu.icache.demand_miss_latency::total 120792000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 120792000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 120792000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134
system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2514362 # number of replacements
system.cpu.dcache.tagsinuse 4086.431953 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4086.432071 # Cycle average of tags in use
system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8218697000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.431953 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 8218649000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4086.432071 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997664 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997664 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits
system.cpu.dcache.overall_hits::total 530743932 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits
system.cpu.dcache.overall_hits::total 530743928 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 53256878500
system.cpu.dcache.demand_miss_latency::total 53256878500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 53256878500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 53256878500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 403150 # number of replacements
system.cpu.l2cache.tagsinuse 29113.385052 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 29113.385897 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3572765 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 435501 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 8.203804 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 773011530000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21035.861184 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 79.696348 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 7997.827520 # Average occupied blocks per requestor
system.cpu.l2cache.warmup_cycle 773011482000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21035.861795 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 79.696350 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 7997.827752 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.641964 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.002432 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.244074 # Average percentage of cache occupancy

4
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 14:58:33
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:18:28
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 68148678500 because target called exit()
Exiting @ tick 68148672000 because target called exit()

76
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.068149 # Number of seconds simulated
sim_ticks 68148678500 # Number of ticks simulated
final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2876458 # Simulator instruction rate (inst/s)
host_op_rate 2913702 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1458542737 # Simulator tick rate (ticks/s)
host_mem_usage 222372 # Number of bytes of host memory used
host_seconds 46.72 # Real time elapsed on the host
sim_insts 134398975 # Number of instructions simulated
sim_ops 136139203 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 538214332 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559361 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773693 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214332 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214332 # Number of instructions bytes read from this memory
host_inst_rate 2819750 # Simulator instruction rate (inst/s)
host_op_rate 2856259 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1429788311 # Simulator tick rate (ticks/s)
host_mem_usage 230172 # Number of bytes of host memory used
host_seconds 47.66 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory
system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory
system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 134553583 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 37231301 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784884 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory
system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory
system.physmem.num_other::total 15916 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7897648844 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905226 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648844 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648844 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648844 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484180709 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297358 # number of cpu cycles simulated
system.cpu.numCycles 136297345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398975 # Number of instructions committed
system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
system.cpu.committedInsts 134398962 # Number of instructions committed
system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187758 # number of integer instructions
system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187746 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147747 # number of times the integer registers were written
system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160249 # number of memory refs
system.cpu.num_load_insts 37275868 # Number of load instructions
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 136297358 # Number of busy cycles
system.cpu.num_busy_cycles 136297345 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
View file

@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
View file

@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:54:18
gem5 started Jul 2 2012 12:32:55
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:19:26
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 204097192000 because target called exit()
Exiting @ tick 204097178000 because target called exit()

130
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.204097 # Number of seconds simulated
sim_ticks 204097192000 # Number of ticks simulated
final_tick 204097192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 204097178000 # Number of ticks simulated
final_tick 204097178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1236624 # Simulator instruction rate (inst/s)
host_op_rate 1252636 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1877926206 # Simulator tick rate (ticks/s)
host_mem_usage 229284 # Number of bytes of host memory used
host_seconds 108.68 # Real time elapsed on the host
sim_insts 134398975 # Number of instructions simulated
sim_ops 136139203 # Number of ops (including micro ops) simulated
host_inst_rate 1441199 # Simulator instruction rate (inst/s)
host_op_rate 1459859 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2188591939 # Simulator tick rate (ticks/s)
host_mem_usage 238748 # Number of bytes of host memory used
host_seconds 93.26 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory
system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory
@ -24,54 +24,54 @@ system.physmem.num_reads::total 133934 # Nu
system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 3261505 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38736995 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41998500 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 38736998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 41998503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3261505 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3261505 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 25974762 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 25974762 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 25974762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_write::writebacks 25974764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 25974764 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 25974764 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 3261505 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38736995 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67973262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38736998 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67973267 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 408194384 # number of cpu cycles simulated
system.cpu.numCycles 408194356 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 134398975 # Number of instructions committed
system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
system.cpu.committedInsts 134398962 # Number of instructions committed
system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8898970 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187758 # number of integer instructions
system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls
system.cpu.num_int_insts 115187746 # number of integer instructions
system.cpu.num_fp_insts 2326977 # number of float instructions
system.cpu.num_int_register_reads 263032383 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147746 # number of times the integer registers were written
system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read
system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written
system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written
system.cpu.num_mem_refs 58160249 # number of memory refs
system.cpu.num_load_insts 37275868 # Number of load instructions
system.cpu.num_mem_refs 58160248 # number of memory refs
system.cpu.num_load_insts 37275867 # Number of load instructions
system.cpu.num_store_insts 20884381 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 408194384 # Number of busy cycles
system.cpu.num_busy_cycles 408194356 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.tagsinuse 2004.409813 # Cycle average of tags in use
system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 2004.409949 # Cycle average of tags in use
system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 145330300000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 2004.409813 # Average occupied blocks per requestor
system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 145330286000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 2004.409949 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.978716 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.978716 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 134366560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366560 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 134366560 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 134366560 # number of overall hits
system.cpu.icache.overall_hits::total 134366560 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits
system.cpu.icache.overall_hits::total 134366547 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 3060544000
system.cpu.icache.demand_miss_latency::total 3060544000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 3060544000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 3060544000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 134553584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 134553584 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 134553584 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 134553584 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses
@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205
system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.tagsinuse 4087.412837 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4087.413116 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 812044000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.412837 # Average occupied blocks per requestor
system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 812030000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.413116 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997904 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997904 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 37185802 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185802 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 57944942 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944942 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944942 # number of overall hits
system.cpu.dcache.overall_hits::total 57944942 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7299977000
system.cpu.dcache.demand_miss_latency::total 7299977000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7299977000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7299977000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 37231301 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 58095605 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 58095605 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 58095605 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 58095605 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 101560 # number of replacements
system.cpu.l2cache.tagsinuse 29278.940429 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 29278.942435 # Cycle average of tags in use
system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 24760.226438 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3263.271337 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1255.442654 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::writebacks 24760.228137 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3263.271559 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 1255.442739 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.755622 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.099587 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.038313 # Average percentage of cache occupancy

4
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
View file

@ -120,8 +120,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]

6
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 15:49:05
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 19:04:29
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 2846007259500 because target called exit()
Exiting @ tick 2846007226500 because target called exit()

76
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.846007 # Number of seconds simulated
sim_ticks 2846007259500 # Number of ticks simulated
final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2846007226500 # Number of ticks simulated
final_tick 2846007226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1390065 # Simulator instruction rate (inst/s)
host_op_rate 2165848 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1315169413 # Simulator tick rate (ticks/s)
host_mem_usage 216596 # Number of bytes of host memory used
host_seconds 2163.99 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868347 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731755 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863408 # Number of instructions bytes read from this memory
host_inst_rate 1386030 # Simulator instruction rate (inst/s)
host_op_rate 2159560 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1311351119 # Simulator tick rate (ticks/s)
host_mem_usage 224788 # Number of bytes of host memory used
host_seconds 2170.29 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862594 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5023868343 # Number of bytes read from this memory
system.physmem.bytes_read::total 37129731399 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 1544656790 # Number of bytes written to this memory
system.physmem.bytes_written::total 1544656790 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4013232926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184749 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417675 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1239184745 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5252417627 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 438528337 # Number of write requests responded to by this memory
system.physmem.num_writes::total 438528337 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 11281019506 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233848 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253354 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019506 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979052 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 11281019513 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13046253380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 11281019513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 11281019513 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 542745210 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 542745210 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 11281019513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998590 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
system.cpu.numCycles 5692014454 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862523 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713086 # number of memory refs
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_mem_refs 1677713082 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
system.cpu.num_busy_cycles 5692014454 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
View file

@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
@ -202,7 +202,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

8
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 14:08:03
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 19:22:39
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -24,4 +24,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 5901048931000 because target called exit()
Exiting @ tick 5901048883000 because target called exit()

112
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 5.901049 # Number of seconds simulated
sim_ticks 5901048931000 # Number of ticks simulated
final_tick 5901048931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 5901048883000 # Number of ticks simulated
final_tick 5901048883000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 821481 # Simulator instruction rate (inst/s)
host_op_rate 1279942 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1611526350 # Simulator tick rate (ticks/s)
host_mem_usage 228472 # Number of bytes of host memory used
host_seconds 3661.78 # Real time elapsed on the host
sim_insts 3008081057 # Number of instructions simulated
sim_ops 4686862651 # Number of ops (including micro ops) simulated
host_inst_rate 766833 # Simulator instruction rate (inst/s)
host_op_rate 1194795 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1504320663 # Simulator tick rate (ticks/s)
host_mem_usage 233368 # Number of bytes of host memory used
host_seconds 3922.73 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862594 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 139043584 # Number of bytes read from this memory
system.physmem.bytes_read::total 139086784 # Number of bytes read from this memory
@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst 7321 # To
system.physmem.bw_total::cpu.data 23562520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 34990498 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11802097862 # number of cpu cycles simulated
system.cpu.numCycles 11802097766 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 3008081057 # Number of instructions committed
system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.committedInsts 3008081022 # Number of instructions committed
system.cpu.committedOps 4686862594 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862523 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
system.cpu.num_int_insts 4686862523 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 14165752766 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691823 # number of times the integer registers were written
system.cpu.num_int_register_reads 14165752588 # number of times the integer registers were read
system.cpu.num_int_register_writes 6716691731 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1677713086 # number of memory refs
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_mem_refs 1677713082 # number of memory refs
system.cpu.num_load_insts 1239184745 # Number of load instructions
system.cpu.num_store_insts 438528337 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 11802097862 # Number of busy cycles
system.cpu.num_busy_cycles 11802097766 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.tagsinuse 555.745883 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 555.745887 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232208 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 5945529.197037 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 555.745883 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 555.745887 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.271360 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.271360 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits
system.cpu.icache.overall_hits::total 4013232208 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 37868000
system.cpu.icache.demand_miss_latency::total 37868000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 37868000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 37868000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741
system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.tagsinuse 4084.618075 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 4084.618108 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600405 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 58864243000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.618075 # Average occupied blocks per requestor
system.cpu.dcache.warmup_cycle 58864195000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4084.618108 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.997221 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.997221 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1231961899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961899 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 436638510 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 436638510 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1668600409 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600409 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600409 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600409 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1668600405 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1668600405 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1668600405 # number of overall hits
system.cpu.dcache.overall_hits::total 1668600405 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 218826366000
system.cpu.dcache.demand_miss_latency::total 218826366000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 218826366000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 218826366000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 438528337 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 438528337 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 1677713086 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713086 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713086 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713086 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 1677713082 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 1677713082 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 1677713082 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 1677713082 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2158210 # number of replacements
system.cpu.l2cache.tagsinuse 30851.471232 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 30851.471482 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8410861 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2187939 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.844194 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 1317386171000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14661.795010 # Average occupied blocks per requestor
system.cpu.l2cache.warmup_cycle 1317386123000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14661.795129 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 21.581563 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16168.094659 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 16168.094790 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.447442 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000659 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.493411 # Average percentage of cache occupancy

4
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 12:01:47
gem5 started Jun 4 2012 15:01:23
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:21:10
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
122 123 124 Exiting @ tick 96722951500 because target called exit()
122 123 124 Exiting @ tick 96722945000 because target called exit()

68
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
View file

@ -1,61 +1,61 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.096723 # Number of seconds simulated
sim_ticks 96722951500 # Number of ticks simulated
final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2785942 # Simulator instruction rate (inst/s)
host_op_rate 2785945 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1392980356 # Simulator tick rate (ticks/s)
host_mem_usage 218424 # Number of bytes of host memory used
host_seconds 69.44 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 223463414 # Number of bytes read from this memory
system.physmem.bytes_read::total 997245606 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 773782192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 773782192 # Number of instructions bytes read from this memory
host_inst_rate 2917410 # Simulator instruction rate (inst/s)
host_op_rate 2917413 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1458714810 # Simulator tick rate (ticks/s)
host_mem_usage 226640 # Number of bytes of host memory used
host_seconds 66.31 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory
system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory
system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 193445548 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 57735069 # Number of read requests responded to by this memory
system.physmem.num_reads::total 251180617 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory
system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory
system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory
system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory
system.physmem.num_other::total 22406 # Number of other requests responded to by this memory
system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2310345275 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10310330594 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 745070440 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 745070440 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415715 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445904 # number of cpu cycles simulated
system.cpu.numCycles 193445891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444531 # Number of instructions committed
system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.committedInsts 193444518 # Number of instructions committed
system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974818 # number of integer instructions
system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974806 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060137 # number of times the integer registers were written
system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733959 # number of memory refs
system.cpu.num_load_insts 57735092 # Number of load instructions
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 193445904 # Number of busy cycles
system.cpu.num_busy_cycles 193445891 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
View file

@ -158,7 +158,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

12
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:54:18
gem5 started Jul 2 2012 12:35:14
gem5 compiled Aug 13 2012 17:04:37
gem5 started Aug 13 2012 18:21:48
gem5 executing on zizzer
command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
122 123 124 Exiting @ tick 270628681000 because target called exit()
122 123 124 Exiting @ tick 270628667000 because target called exit()

110
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.270629 # Number of seconds simulated
sim_ticks 270628681000 # Number of ticks simulated
final_tick 270628681000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 270628667000 # Number of ticks simulated
final_tick 270628667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1015199 # Simulator instruction rate (inst/s)
host_op_rate 1015200 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1420261450 # Simulator tick rate (ticks/s)
host_mem_usage 225612 # Number of bytes of host memory used
host_seconds 190.55 # Real time elapsed on the host
sim_insts 193444531 # Number of instructions simulated
sim_ops 193444769 # Number of ops (including micro ops) simulated
host_inst_rate 1532509 # Simulator instruction rate (inst/s)
host_op_rate 1532510 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2143977461 # Simulator tick rate (ticks/s)
host_mem_usage 235212 # Number of bytes of host memory used
host_seconds 126.23 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory
system.physmem.bytes_read::total 331072 # Number of bytes read from this memory
@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 850642 # To
system.physmem.bw_total::cpu.data 372703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223344 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541257362 # number of cpu cycles simulated
system.cpu.numCycles 541257334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 193444531 # Number of instructions committed
system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.committedInsts 193444518 # Number of instructions committed
system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8665107 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974818 # number of integer instructions
system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls
system.cpu.num_int_insts 167974806 # number of integer instructions
system.cpu.num_fp_insts 1970372 # number of float instructions
system.cpu.num_int_register_reads 352617963 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060136 # number of times the integer registers were written
system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read
system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written
system.cpu.num_mem_refs 76733959 # number of memory refs
system.cpu.num_load_insts 57735092 # Number of load instructions
system.cpu.num_mem_refs 76733958 # number of memory refs
system.cpu.num_load_insts 57735091 # Number of load instructions
system.cpu.num_store_insts 18998867 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 541257362 # Number of busy cycles
system.cpu.num_busy_cycles 541257334 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 10362 # number of replacements
system.cpu.icache.tagsinuse 1591.549936 # Cycle average of tags in use
system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1591.550018 # Cycle average of tags in use
system.cpu.icache.total_refs 193433248 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 15741.638021 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1591.549936 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1591.550018 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.777124 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.777124 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits
system.cpu.icache.overall_hits::total 193433261 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
system.cpu.icache.overall_hits::total 193433248 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 323106000
system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2 # number of replacements
system.cpu.dcache.tagsinuse 1237.179086 # Cycle average of tags in use
system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1237.179149 # Cycle average of tags in use
system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1237.179086 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 1237.179149 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.302046 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.302046 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 57734571 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 57734571 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 76709933 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 76709933 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 76709933 # number of overall hits
system.cpu.dcache.overall_hits::total 76709933 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data 88200000
system.cpu.dcache.demand_miss_latency::total 88200000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 88200000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 88200000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 57735069 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 57735069 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 76711508 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 76711508 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 76711508 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 76711508 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2678.289467 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2678.289604 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.121308 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2275.240506 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 403.048505 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2275.240623 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 403.048526 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.069435 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy

4
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -510,7 +510,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr
@ -533,7 +533,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

12
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 14:16:35
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 19:40:50
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -24,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 87870590500 because target called exit()
122 123 124 Exiting @ tick 87745680500 because target called exit()

1032
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

4
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
View file

@ -120,8 +120,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.physmem]

6
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 13:44:28
gem5 started Jun 4 2012 16:58:23
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 20:10:43
gem5 executing on zizzer
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
@ -24,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 131393100000 because target called exit()
122 123 124 Exiting @ tick 131393067000 because target called exit()

76
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.131393 # Number of seconds simulated
sim_ticks 131393100000 # Number of ticks simulated
final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 131393067000 # Number of ticks simulated
final_tick 131393067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1290267 # Simulator instruction rate (inst/s)
host_op_rate 2162601 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1283641901 # Simulator tick rate (ticks/s)
host_mem_usage 223844 # Number of bytes of host memory used
host_seconds 102.36 # Real time elapsed on the host
sim_insts 132071228 # Number of instructions simulated
sim_ops 221363018 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387955288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423754 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698379042 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1387955288 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387955288 # Number of instructions bytes read from this memory
host_inst_rate 1300121 # Simulator instruction rate (inst/s)
host_op_rate 2179118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1293445391 # Simulator tick rate (ticks/s)
host_mem_usage 231396 # Number of bytes of host memory used
host_seconds 101.58 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 310423750 # Number of bytes read from this memory
system.physmem.bytes_read::total 1698378686 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 99822189 # Number of bytes written to this memory
system.physmem.bytes_written::total 99822189 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 173494411 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682008 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176419 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 56682004 # Number of read requests responded to by this memory
system.physmem.num_reads::total 230176371 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 20515730 # Number of write requests responded to by this memory
system.physmem.num_writes::total 20515730 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10563380330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362557501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925937831 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563380330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563380330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759721698 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759721698 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563380330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685659529 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 10563380304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2362558064 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12925938368 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10563380304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10563380304 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 759721889 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 759721889 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10563380304 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279953 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685660256 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786201 # number of cpu cycles simulated
system.cpu.numCycles 262786135 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071228 # Number of instructions committed
system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339607 # number of integer instructions
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339550 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read
system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written
system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read
system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165306 # number of memory refs
system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_mem_refs 77165302 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
system.cpu.num_store_insts 20515716 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 262786201 # Number of busy cycles
system.cpu.num_busy_cycles 262786135 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
View file

@ -179,7 +179,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
@ -202,7 +202,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]

12
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:58:39
gem5 started Jul 2 2012 14:50:18
gem5 compiled Aug 13 2012 17:08:22
gem5 started Aug 13 2012 20:12:35
gem5 executing on zizzer
command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -24,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 250981042000 because target called exit()
122 123 124 Exiting @ tick 250980994000 because target called exit()

110
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.250981 # Number of seconds simulated
sim_ticks 250981042000 # Number of ticks simulated
final_tick 250981042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 250980994000 # Number of ticks simulated
final_tick 250980994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 522050 # Simulator instruction rate (inst/s)
host_op_rate 875003 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 992076486 # Simulator tick rate (ticks/s)
host_mem_usage 235972 # Number of bytes of host memory used
host_seconds 252.99 # Real time elapsed on the host
sim_insts 132071228 # Number of instructions simulated
sim_ops 221363018 # Number of ops (including micro ops) simulated
host_inst_rate 746540 # Simulator instruction rate (inst/s)
host_op_rate 1251266 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1418683559 # Simulator tick rate (ticks/s)
host_mem_usage 239848 # Number of bytes of host memory used
host_seconds 176.91 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory
system.physmem.bytes_read::total 303040 # Number of bytes read from this memory
@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst 724198 # To
system.physmem.bw_total::cpu.data 483224 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207422 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501962084 # number of cpu cycles simulated
system.cpu.numCycles 501961988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 132071228 # Number of instructions committed
system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.committedInsts 132071193 # Number of instructions committed
system.cpu.committedOps 221362961 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339550 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339607 # number of integer instructions
system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls
system.cpu.num_int_insts 220339550 # number of integer instructions
system.cpu.num_fp_insts 2162459 # number of float instructions
system.cpu.num_int_register_reads 705008823 # number of times the integer registers were read
system.cpu.num_int_register_writes 318312586 # number of times the integer registers were written
system.cpu.num_int_register_reads 705008645 # number of times the integer registers were read
system.cpu.num_int_register_writes 318312494 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
system.cpu.num_mem_refs 77165306 # number of memory refs
system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_mem_refs 77165302 # number of memory refs
system.cpu.num_load_insts 56649586 # Number of load instructions
system.cpu.num_store_insts 20515716 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 501962084 # Number of busy cycles
system.cpu.num_busy_cycles 501961988 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 2836 # number of replacements
system.cpu.icache.tagsinuse 1455.271683 # Cycle average of tags in use
system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1455.271959 # Cycle average of tags in use
system.cpu.icache.total_refs 173489674 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 36959.879421 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1455.271683 # Average occupied blocks per requestor
system.cpu.icache.occ_blocks::cpu.inst 1455.271959 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.710582 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.710582 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits
system.cpu.icache.overall_hits::total 173489718 # number of overall hits
system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 173489674 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 173489674 # number of overall hits
system.cpu.icache.overall_hits::total 173489674 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 185042500
system.cpu.icache.demand_miss_latency::total 185042500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 185042500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 185042500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 173494368 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 173494368 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 173494368 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 173494368 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 173494368 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 41 # number of replacements
system.cpu.dcache.tagsinuse 1363.438791 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1363.439047 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195829 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 40522.744882 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 1363.438791 # Average occupied blocks per requestor
system.cpu.dcache.occ_blocks::cpu.data 1363.439047 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.332871 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.332871 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 56681681 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681681 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20514152 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20514152 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 77195833 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195833 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195833 # number of overall hits
system.cpu.dcache.overall_hits::total 77195833 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 77195829 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 77195829 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 77195829 # number of overall hits
system.cpu.dcache.overall_hits::total 77195829 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
@ -161,14 +161,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 106263000
system.cpu.dcache.demand_miss_latency::total 106263000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 106263000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 106263000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 56682008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 77197738 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197738 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197738 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197738 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 77197734 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 77197734 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 77197734 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 77197734 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
@ -229,14 +229,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2058.146079 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 2058.146468 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.588496 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 0.021788 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1829.948431 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 228.175860 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1829.948778 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 228.175901 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.055846 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy

2
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
View file

@ -214,7 +214,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 09:08:18
gem5 compiled Aug 13 2012 16:51:51
gem5 started Aug 13 2012 17:17:12
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 21985500 because target called exit()
Exiting @ tick 21979500 because target called exit()

210
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
sim_ticks 21985500 # Number of ticks simulated
final_tick 21985500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 21979500 # Number of ticks simulated
final_tick 21979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 65949 # Simulator instruction rate (inst/s)
host_op_rate 65938 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 226330541 # Simulator tick rate (ticks/s)
host_mem_usage 218192 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
host_inst_rate 39186 # Simulator instruction rate (inst/s)
host_op_rate 39182 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 134757534 # Simulator tick rate (ticks/s)
host_mem_usage 222636 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
@ -19,30 +19,30 @@ system.physmem.bytes_inst_read::total 19264 # Nu
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 876213868 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 489049601 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1365263469 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 876213868 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 876213868 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 876213868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 489049601 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1365263469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 876453059 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 489183102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1365636161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 876453059 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 876453059 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 876453059 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 489183102 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1365636161 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1186 # DTB read hits
system.cpu.dtb.read_hits 1184 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1193 # DTB read accesses
system.cpu.dtb.read_accesses 1191 # DTB read accesses
system.cpu.dtb.write_hits 900 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 903 # DTB write accesses
system.cpu.dtb.data_hits 2086 # DTB hits
system.cpu.dtb.data_hits 2084 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2096 # DTB accesses
system.cpu.dtb.data_accesses 2094 # DTB accesses
system.cpu.itb.fetch_hits 908 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
@ -60,83 +60,83 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 43972 # number of cpu cycles simulated
system.cpu.numCycles 43960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1607 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1126 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
system.cpu.branch_predictor.lookups 1606 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1143 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5212 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9792 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.branch_predictor.predictedNotTaken 1142 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5205 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9772 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 2971 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2183 # Number of Address Generations
system.cpu.regfile_manager.regForwards 2961 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2181 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4474 # Number of Instructions Executed.
system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4463 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 12078 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 12066 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 36557 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7415 # Number of cycles cpu stages are processed.
system.cpu.activity 16.863004 # Percentage of cycles cpu is active
system.cpu.comLoads 1185 # Number of Load instructions committed
system.cpu.idleCycles 36556 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7404 # Number of cycles cpu stages are processed.
system.cpu.activity 16.842584 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1051 # Number of Branches instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
system.cpu.comNops 17 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 3265 # Number of Integer instructions committed
system.cpu.comInts 3254 # Number of Integer instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
system.cpu.committedInsts 6390 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
system.cpu.cpi 6.866334 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 6.879499 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 6.866334 # CPI: Total CPI of All Threads
system.cpu.ipc 0.145638 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 6.879499 # CPI: Total CPI of All Threads
system.cpu.ipc 0.145359 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.145638 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 39051 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4921 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.191213 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 40084 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3888 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.841990 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 39791 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.508323 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 42630 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1342 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.051942 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 39502 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4470 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.165560 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.145359 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 39048 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 11.173794 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 40082 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 8.821656 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 39789 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4171 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 9.488171 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 42620 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.048226 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 39501 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4459 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 10.143312 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 138.644500 # Cycle average of tags in use
system.cpu.icache.tagsinuse 138.677707 # Cycle average of tags in use
system.cpu.icache.total_refs 557 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 138.644500 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067698 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067698 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 138.677707 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.067714 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.067714 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits
@ -213,22 +213,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411
system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.468585 # Cycle average of tags in use
system.cpu.dcache.total_refs 1702 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 102.489186 # Cycle average of tags in use
system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.130952 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 102.468585 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025017 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025017 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.occ_blocks::cpu.data 102.489186 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025022 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025022 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1702 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1702 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1702 # number of overall hits
system.cpu.dcache.overall_hits::total 1702 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1700 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1700 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1700 # number of overall hits
system.cpu.dcache.overall_hits::total 1700 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses
@ -245,22 +245,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 21208000
system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.169756 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.169756 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169756 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.169756 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency
@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000
system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency
@ -319,16 +319,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 194.857279 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 194.900917 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 138.715070 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.142209 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004233 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001713 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005947 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 138.748296 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.152621 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.004234 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001714 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005948 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits

2
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -512,7 +512,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 09:08:18
gem5 compiled Aug 13 2012 16:51:51
gem5 started Aug 13 2012 17:17:12
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 12811000 because target called exit()
Exiting @ tick 12735500 because target called exit()

938
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
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File diff suppressed because it is too large Load diff

4
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:50:11
gem5 started Jun 4 2012 13:46:44
gem5 compiled Aug 13 2012 16:51:51
gem5 started Aug 13 2012 17:17:12
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 3215000 because target called exit()
Exiting @ tick 3208000 because target called exit()

88
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
View file

@ -1,58 +1,58 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 3215000 # Number of ticks simulated
final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1264163 # Simulator instruction rate (inst/s)
host_op_rate 1259559 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 630191855 # Simulator tick rate (ticks/s)
host_mem_usage 205200 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_inst_rate 57981 # Simulator instruction rate (inst/s)
host_op_rate 57971 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29099028 # Simulator tick rate (ticks/s)
host_mem_usage 214184 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7980093313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2738413686 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10718506998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980093313 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980093313 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2082737170 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2082737170 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980093313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4821150855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12801244168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 7980049875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2739401496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 10719451372 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7980049875 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2087281796 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6400 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.fetch_accesses 6417 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -66,26 +66,26 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 6431 # number of cpu cycles simulated
system.cpu.numCycles 6417 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 6431 # Number of busy cycles
system.cpu.num_busy_cycles 6417 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

4
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:30:15
gem5 started Jul 28 2012 11:35:39
gem5 compiled Aug 13 2012 16:55:16
gem5 started Aug 13 2012 18:08:58
gem5 executing on zizzer
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second

74
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
View file

@ -4,35 +4,35 @@ sim_seconds 0.000279 # Nu
sim_ticks 279353 # Number of ticks simulated
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 24063 # Simulator instruction rate (inst/s)
host_op_rate 24061 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1049533 # Simulator tick rate (ticks/s)
host_inst_rate 30486 # Simulator instruction rate (inst/s)
host_op_rate 30483 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1332529 # Simulator tick rate (ticks/s)
host_mem_usage 233960 # Number of bytes of host memory used
host_seconds 0.27 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_seconds 0.21 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 91840789 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 31515681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 123356470 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91840789 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91840789 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 91640326 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 31458406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 123098732 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 91640326 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91640326 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 23969673 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 23969673 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 91640326 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 55428078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 147068404 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 279353 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 279353 # Number of busy cycles

4
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:32:56
gem5 started Jul 28 2012 11:35:52
gem5 compiled Aug 13 2012 16:57:01
gem5 started Aug 13 2012 18:09:22
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second

76
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,35 +4,35 @@ sim_seconds 0.000224 # Nu
sim_ticks 223694 # Number of ticks simulated
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 2880 # Simulator instruction rate (inst/s)
host_op_rate 2880 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 100591 # Simulator tick rate (ticks/s)
host_mem_usage 235160 # Number of bytes of host memory used
host_seconds 2.22 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_inst_rate 29074 # Simulator instruction rate (inst/s)
host_op_rate 29072 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1017648 # Simulator tick rate (ticks/s)
host_mem_usage 235156 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 114692392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39357336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 154049729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 114692392 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 114692392 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 114442050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39285810 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 153727860 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 114442050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 114442050 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 29933749 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 29933749 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 114442050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 69219559 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 183661609 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 223694 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 223694 # Number of busy cycles

4
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
View file

@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:35:39
gem5 started Jul 28 2012 11:35:54
gem5 compiled Aug 13 2012 16:58:46
gem5 started Aug 13 2012 18:10:55
gem5 executing on zizzer
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second

74
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,35 +4,35 @@ sim_seconds 0.000232 # Nu
sim_ticks 231701 # Number of ticks simulated
final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 46536 # Simulator instruction rate (inst/s)
host_op_rate 46530 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1683295 # Simulator tick rate (ticks/s)
host_inst_rate 37740 # Simulator instruction rate (inst/s)
host_op_rate 37736 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1368171 # Simulator tick rate (ticks/s)
host_mem_usage 233016 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_seconds 0.17 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 110728914 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 37997246 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 148726160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 110728914 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 110728914 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 110487223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 37928192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 148415415 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 110487223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 110487223 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 28899314 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 28899314 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 110487223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 66827506 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 177314729 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 231701 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 231701 # Number of busy cycles

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 28 2012 11:27:37
gem5 started Jul 28 2012 11:35:39
gem5 compiled Aug 13 2012 16:53:31
gem5 started Aug 13 2012 18:06:43
gem5 executing on zizzer
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 208400 because target called exit()
Exiting @ tick 208110 because target called exit()

88
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000208 # Number of seconds simulated
sim_ticks 208400 # Number of ticks simulated
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 208110 # Number of ticks simulated
final_tick 208110 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 49772 # Simulator instruction rate (inst/s)
host_op_rate 49764 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1619227 # Simulator tick rate (ticks/s)
host_mem_usage 231924 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_inst_rate 43199 # Simulator instruction rate (inst/s)
host_op_rate 43194 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1406596 # Simulator tick rate (ticks/s)
host_mem_usage 231928 # Number of bytes of host memory used
host_seconds 0.15 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 123109405 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 42245681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 165355086 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 123109405 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 32130518 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 123011869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 42227668 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 165239537 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 123011869 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 123011869 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 32175292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 32175292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 123011869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 74402960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 197414829 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -61,22 +61,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -90,26 +90,26 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 208400 # number of cpu cycles simulated
system.cpu.numCycles 208110 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 208400 # Number of busy cycles
system.cpu.num_busy_cycles 208110 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864

6
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 10 2012 16:32:12
gem5 started Jul 10 2012 17:16:10
gem5 executing on sc2b0605
gem5 compiled Aug 13 2012 16:51:51
gem5 started Aug 13 2012 17:17:12
gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

76
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View file

@ -4,35 +4,35 @@ sim_seconds 0.000343 # Nu
sim_ticks 342698 # Number of ticks simulated
final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 38554 # Simulator instruction rate (inst/s)
host_op_rate 38550 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2062706 # Simulator tick rate (ticks/s)
host_mem_usage 234872 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
system.physmem.bytes_read::total 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25656 # Number of instructions bytes read from this memory
host_inst_rate 30637 # Simulator instruction rate (inst/s)
host_op_rate 30634 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1642762 # Simulator tick rate (ticks/s)
host_mem_usage 233644 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 6414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7599 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 74864750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 25690258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 100555008 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74864750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74864750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 74701341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 25643570 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 100344910 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 74701341 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 74701341 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 19539069 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 19539069 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74864750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 45229327 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 120094077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 74701341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 45182639 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 119883979 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@ -43,22 +43,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -75,20 +75,20 @@ system.cpu.workload.num_syscalls 17 # Nu
system.cpu.numCycles 342698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 342698 # Number of busy cycles

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:30:56
gem5 started Jul 2 2012 09:08:22
gem5 compiled Aug 13 2012 16:51:51
gem5 started Aug 13 2012 17:17:12
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 34425000 because target called exit()
Exiting @ tick 34409000 because target called exit()

200
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000034 # Number of seconds simulated
sim_ticks 34425000 # Number of ticks simulated
final_tick 34425000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 34409000 # Number of ticks simulated
final_tick 34409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 6722 # Simulator instruction rate (inst/s)
host_op_rate 6722 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 36133024 # Simulator tick rate (ticks/s)
host_mem_usage 217168 # Number of bytes of host memory used
host_seconds 0.95 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
sim_ops 6404 # Number of ops (including micro ops) simulated
host_inst_rate 55813 # Simulator instruction rate (inst/s)
host_op_rate 55804 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 300451871 # Simulator tick rate (ticks/s)
host_mem_usage 222640 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 17792 # Nu
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 516833696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 312331155 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 829164851 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 516833696 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 516833696 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 516833696 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 312331155 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 829164851 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 517074021 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 312476387 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 829550408 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 517074021 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 517074021 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 517074021 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 312476387 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 829550408 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_hits 2048 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2060 # DTB accesses
system.cpu.itb.fetch_hits 6415 # ITB hits
system.cpu.dtb.data_accesses 2058 # DTB accesses
system.cpu.itb.fetch_hits 6401 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 6432 # ITB accesses
system.cpu.itb.fetch_accesses 6418 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -60,43 +60,43 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 68850 # number of cpu cycles simulated
system.cpu.numCycles 68818 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6404 # Number of instructions committed
system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.committedInsts 6390 # Number of instructions committed
system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
system.cpu.num_int_insts 6331 # number of integer instructions
system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
system.cpu.num_int_insts 6317 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
system.cpu.num_mem_refs 2060 # number of memory refs
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_mem_refs 2058 # number of memory refs
system.cpu.num_load_insts 1190 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 68850 # Number of busy cycles
system.cpu.num_busy_cycles 68818 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 128.155444 # Cycle average of tags in use
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 128.208060 # Cycle average of tags in use
system.cpu.icache.total_refs 6122 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 21.942652 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 128.155444 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.062576 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.062576 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits
system.cpu.icache.overall_hits::total 6136 # number of overall hits
system.cpu.icache.occ_blocks::cpu.inst 128.208060 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.062602 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.062602 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
system.cpu.icache.overall_hits::total 6122 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
@ -109,18 +109,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 15582000
system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
@ -147,12 +147,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000
system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
@ -161,22 +161,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 103.856385 # Cycle average of tags in use
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 103.892123 # Cycle average of tags in use
system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 103.856385 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025356 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025356 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.occ_blocks::cpu.data 103.892123 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.025364 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.025364 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
system.cpu.dcache.overall_hits::total 1882 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
system.cpu.dcache.overall_hits::total 1880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
@ -193,22 +193,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 9408000
system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
@ -241,14 +241,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000
system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.699061 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 184.769601 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 128.168283 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.530778 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.003911 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001725 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005637 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::cpu.inst 128.220906 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 56.548695 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.003913 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.001726 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005639 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits

2
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
View file

@ -214,7 +214,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:47:33
gem5 started Jul 2 2012 11:28:42
gem5 compiled Aug 13 2012 17:00:38
gem5 started Aug 13 2012 18:11:29
gem5 executing on zizzer
command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 20520000 because target called exit()
Exiting @ tick 20518000 because target called exit()

336
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000021 # Number of seconds simulated
sim_ticks 20520000 # Number of ticks simulated
final_tick 20520000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 20518000 # Number of ticks simulated
final_tick 20518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 67788 # Simulator instruction rate (inst/s)
host_op_rate 67774 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 238625492 # Simulator tick rate (ticks/s)
host_mem_usage 219036 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
sim_ops 5827 # Number of ops (including micro ops) simulated
host_inst_rate 56112 # Simulator instruction rate (inst/s)
host_op_rate 56102 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 197957466 # Simulator tick rate (ticks/s)
host_mem_usage 223380 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 29120 # Number of bytes read from this memory
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 988693957 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 430409357 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1419103314 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 988693957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 988693957 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 988693957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 430409357 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1419103314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 988790330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 430451311 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1419241641 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 988790330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 988790330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 988790330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 430451311 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1419241641 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -46,83 +46,83 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 41041 # number of cpu cycles simulated
system.cpu.numCycles 41037 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 1151 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 850 # Number of conditional branches predicted
system.cpu.branch_predictor.lookups 1146 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 844 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 866 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 310 # Number of BTB hits
system.cpu.branch_predictor.BTBLookups 861 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 300 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 35.796767 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 403 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 748 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5102 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8510 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5095 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 8491 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 1331 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2237 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.regfile_manager.regForwards 1321 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2235 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 320 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 65.065502 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3155 # Number of Instructions Executed.
system.cpu.execution_unit.predicted 319 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 65.136612 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 3144 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 9765 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.threadCycles 9756 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 35643 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5398 # Number of cycles cpu stages are processed.
system.cpu.activity 13.152701 # Percentage of cycles cpu is active
system.cpu.comLoads 1164 # Number of Load instructions committed
system.cpu.idleCycles 35650 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 5387 # Number of cycles cpu stages are processed.
system.cpu.activity 13.127178 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 916 # Number of Branches instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
system.cpu.comNops 657 # Number of Nop instructions committed
system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
system.cpu.comInts 2155 # Number of Integer instructions committed
system.cpu.comInts 2144 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread)
system.cpu.committedInsts 5814 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total)
system.cpu.cpi 7.043247 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
system.cpu.cpi 7.058308 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 7.043247 # CPI: Total CPI of All Threads
system.cpu.ipc 0.141980 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.cpi_total 7.058308 # CPI: Total CPI of All Threads
system.cpu.ipc 0.141677 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.141980 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 37403 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3638 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 8.864306 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38212 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 6.893107 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38251 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2790 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 6.798080 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 39798 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.028679 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38136 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.078288 # Percentage of cycles stage was utilized (processing insts).
system.cpu.ipc_total 0.141677 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 37412 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 8.833492 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 38215 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 6.876721 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2785 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 6.786558 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 39795 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 3.026537 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 38135 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 7.071667 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.tagsinuse 147.235290 # Cycle average of tags in use
system.cpu.icache.tagsinuse 147.247157 # Cycle average of tags in use
system.cpu.icache.total_refs 411 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 147.235290 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.071892 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.071892 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::cpu.inst 147.247157 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.071898 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.071898 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits
@ -135,12 +135,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n
system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses
system.cpu.icache.overall_misses::total 344 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19612500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19612500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19612500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19612500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19612500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19612500 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19614000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 19614000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 19614000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 19614000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 19614000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 19614000 # number of overall miss cycles
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@ -153,12 +153,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.455629
system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 57013.081395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 57013.081395 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57017.441860 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 57017.441860 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 57017.441860 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 57017.441860 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 57017.441860 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -179,42 +179,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319
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system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17428000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17428000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 17428000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17428000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17428000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17429500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 17429500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17429500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 17429500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17429500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17429500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54633.228840 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54633.228840 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54637.931034 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54637.931034 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 54637.931034 # average overall mshr miss latency
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system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks.
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system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses
@ -223,38 +223,38 @@ system.cpu.dcache.demand_misses::cpu.data 254 # n
system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses
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system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 60846.153846 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60851.648352 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60851.648352 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 61759.842520 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61761.811024 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61761.811024 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61761.811024 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -279,40 +279,40 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8051500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8051500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8051500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.overall_mshr_miss_latency::total 8052000 # number of overall MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59057.471264 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59057.471264 # average ReadReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58344.202899 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58344.202899 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58347.826087 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58347.826087 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 204.292602 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 204.307813 # Cycle average of tags in use
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system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst 148.846889 # Average occupied blocks per requestor
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@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu
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@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 #
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53817.034700 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56992.753623 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54780.219780 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54783.516484 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53820.189274 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56996.376812 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54783.516484 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked

2
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
View file

@ -512,7 +512,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port[0]
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]

8
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 2 2012 08:47:33
gem5 started Jul 2 2012 11:28:53
gem5 compiled Aug 13 2012 17:00:38
gem5 started Aug 13 2012 18:11:40
gem5 executing on zizzer
command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 13016500 because target called exit()
Exiting @ tick 12925500 because target called exit()

832
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

@ -1,32 +1,32 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
sim_ticks 13016500 # Number of ticks simulated
final_tick 13016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 12925500 # Number of ticks simulated
final_tick 12925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 54505 # Simulator instruction rate (inst/s)
host_op_rate 54495 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 137205108 # Simulator tick rate (ticks/s)
host_mem_usage 220060 # Number of bytes of host memory used
host_inst_rate 52967 # Simulator instruction rate (inst/s)
host_op_rate 52957 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132735366 # Simulator tick rate (ticks/s)
host_mem_usage 224404 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
sim_ops 5169 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21760 # Number of bytes read from this memory
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21760 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 340 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 30720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1671724350 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 693273922 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2364998271 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1671724350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1671724350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1671724350 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 693273922 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2364998271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1678542416 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 698154810 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2376697226 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1678542416 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1678542416 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1678542416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 698154810 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2376697226 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 26034 # number of cpu cycles simulated
system.cpu.numCycles 25852 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 2148 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1448 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 450 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1662 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 462 # Number of BTB hits
system.cpu.BPredUnit.lookups 2052 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 1365 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1625 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 468 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 263 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.usedRAS 254 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8866 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13061 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2148 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 725 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3176 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1340 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 826 # Number of cycles fetch has spent blocked
system.cpu.fetch.icacheStallCycles 8806 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12660 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2052 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 722 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 3113 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1287 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 809 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13893 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.940114 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.257377 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.CacheLines 1908 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 272 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 13710 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.923414 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.233238 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10717 77.14% 77.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1298 9.34% 86.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 110 0.79% 87.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 134 0.96% 88.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 300 2.16% 90.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 103 0.74% 91.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 148 1.07% 92.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 126 0.91% 93.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 957 6.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 10597 77.29% 77.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1289 9.40% 86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 106 0.77% 87.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 138 1.01% 88.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 293 2.14% 90.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 99 0.72% 91.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 151 1.10% 92.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 124 0.90% 93.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 913 6.66% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 13893 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.082507 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.501690 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 9037 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 974 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2996 # Number of cycles decode is running
system.cpu.fetch.rateDist::total 13710 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.079375 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.489711 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8966 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 966 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2934 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 835 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 12168 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 835 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9227 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 288 # Number of cycles rename is blocking
system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 143 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 11758 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 9155 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 277 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2860 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 143 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11638 # Number of instructions processed by rename
system.cpu.rename.RunCycles 2801 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 144 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 11265 # Number of instructions processed by rename
system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 7046 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 13805 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13801 # Number of integer rename lookups
system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 13414 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13410 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 3636 # Number of HB maps that are undone due to squashing
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 3481 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 308 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2447 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit.
system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1172 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 9050 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsAdded 8819 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 8137 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3435 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1984 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqInstsIssued 8008 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 3225 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1836 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 13893 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.585691 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.249798 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::samples 13710 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.584099 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.244040 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10352 74.51% 74.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1446 10.41% 84.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 850 6.12% 91.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 537 3.87% 94.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 350 2.52% 97.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 226 1.63% 99.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 89 0.64% 99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 28 0.20% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 15 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10210 74.47% 74.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1436 10.47% 84.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 842 6.14% 91.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 525 3.83% 94.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 351 2.56% 97.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 220 1.60% 99.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 85 0.62% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 29 0.21% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13893 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 13710 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
@ -176,188 +176,188 @@ system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # at
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4825 59.30% 59.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2212 27.18% 86.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1091 13.41% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 4734 59.12% 59.12% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2177 27.19% 86.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1088 13.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 8137 # Type of FU issued
system.cpu.iq.rate 0.312553 # Inst issue rate
system.cpu.iq.FU_type_0::total 8008 # Type of FU issued
system.cpu.iq.rate 0.309763 # Inst issue rate
system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.018680 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 30361 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 12504 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7339 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fu_busy_rate 0.018981 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 29921 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 12064 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 7226 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 8287 # Number of integer alu accesses
system.cpu.iq.int_alu_accesses 8158 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed
system.cpu.iew.lsq.thread0.squashedLoads 1209 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 247 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 835 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking
system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 10551 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 78 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2447 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 10240 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 94 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1172 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 378 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 479 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7784 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2096 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 360 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 7665 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2061 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 343 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1489 # number of nop insts executed
system.cpu.iew.exec_refs 3163 # number of memory reference insts executed
system.cpu.iew.exec_branches 1325 # Number of branches executed
system.cpu.iew.exec_stores 1067 # Number of stores executed
system.cpu.iew.exec_rate 0.298994 # Inst execution rate
system.cpu.iew.wb_sent 7431 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7341 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2840 # num instructions producing a value
system.cpu.iew.wb_consumers 4066 # num instructions consuming a value
system.cpu.iew.exec_nop 1409 # number of nop insts executed
system.cpu.iew.exec_refs 3123 # number of memory reference insts executed
system.cpu.iew.exec_branches 1292 # Number of branches executed
system.cpu.iew.exec_stores 1062 # Number of stores executed
system.cpu.iew.exec_rate 0.296495 # Inst execution rate
system.cpu.iew.wb_sent 7314 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 7228 # cumulative count of insts written-back
system.cpu.iew.wb_producers 2794 # num instructions producing a value
system.cpu.iew.wb_consumers 3985 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.281977 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.698475 # average fanout of values written-back
system.cpu.iew.wb_rate 0.279592 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.701129 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4721 # The number of squashed insts skipped by commit
system.cpu.commit.commitCommittedInsts 5813 # The number of committed instructions
system.cpu.commit.commitCommittedOps 5813 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4420 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 404 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 13058 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.446163 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.225344 # Number of insts commited each cycle
system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12917 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.450027 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.233846 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10619 81.32% 81.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1036 7.93% 89.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 643 4.92% 94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 305 2.34% 96.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 154 1.18% 97.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 84 0.64% 98.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 72 0.55% 98.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 39 0.30% 99.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10496 81.26% 81.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1026 7.94% 89.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 636 4.92% 94.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 301 2.33% 96.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 148 1.15% 97.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 90 0.70% 98.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 76 0.59% 98.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 38 0.29% 99.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106 0.82% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 13058 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5826 # Number of instructions committed
system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
system.cpu.commit.committed_per_cycle::total 12917 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2089 # Number of memory references committed
system.cpu.commit.loads 1164 # Number of loads committed
system.cpu.commit.refs 2088 # Number of memory references committed
system.cpu.commit.loads 1163 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 916 # Number of branches committed
system.cpu.commit.branches 915 # Number of branches committed
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
system.cpu.commit.function_calls 87 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 23486 # The number of ROB reads
system.cpu.rob.rob_writes 21936 # The number of ROB writes
system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 12141 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5169 # Number of Instructions Simulated
system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
system.cpu.cpi 5.036564 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.036564 # CPI: Total CPI of All Threads
system.cpu.ipc 0.198548 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.198548 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10600 # number of integer regfile reads
system.cpu.int_regfile_writes 5152 # number of integer regfile writes
system.cpu.rob.rob_reads 23031 # The number of ROB reads
system.cpu.rob.rob_writes 21266 # The number of ROB writes
system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 12142 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
system.cpu.cpi 5.013964 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.013964 # CPI: Total CPI of All Threads
system.cpu.ipc 0.199443 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.199443 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 10440 # number of integer regfile reads
system.cpu.int_regfile_writes 5074 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 155 # number of misc regfile reads
system.cpu.misc_regfile_reads 150 # number of misc regfile reads
system.cpu.icache.replacements 17 # number of replacements
system.cpu.icache.tagsinuse 163.172601 # Cycle average of tags in use
system.cpu.icache.total_refs 1511 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 343 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.405248 # Average number of references to valid blocks.
system.cpu.icache.tagsinuse 161.949608 # Cycle average of tags in use
system.cpu.icache.total_refs 1474 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.309942 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 163.172601 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.079674 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.079674 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1511 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1511 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1511 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1511 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1511 # number of overall hits
system.cpu.icache.overall_hits::total 1511 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
system.cpu.icache.overall_misses::total 437 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15987000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15987000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15987000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15987000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15987000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15987000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224333 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.224333 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.224333 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.224333 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.224333 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.224333 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 36583.524027 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 36583.524027 # average overall miss latency
system.cpu.icache.occ_blocks::cpu.inst 161.949608 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.079077 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.079077 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits
system.cpu.icache.overall_hits::total 1474 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses
system.cpu.icache.overall_misses::total 434 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15909000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15909000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15909000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15909000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15909000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1908 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1908 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1908 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1908 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1908 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227463 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.227463 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.227463 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.227463 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.227463 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.227463 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36656.682028 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 36656.682028 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 36656.682028 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36656.682028 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 36656.682028 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -366,94 +366,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 343 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 343 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 343 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 343 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 343 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12452000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12452000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12452000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12452000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36308.479532 # average overall mshr miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -464,12 +464,12 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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@ -478,103 +478,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3723500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 15776500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1998000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 12086500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5736500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17823000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12086500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5736500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17823000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 343 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.demand_miss_latency::cpu.inst 12053000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 5721500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 17774500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 12053000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 5721500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 17774500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 343 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 343 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991254 # miss rate for ReadReq accesses
system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991254 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991254 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581 # average ReadReq miss latency
system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 37030.208333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 37030.208333 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10999000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14462000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10969500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3448000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14417500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10999000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5302500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16301500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10999000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5302500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16301500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10969500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5287500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 16257000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10969500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5287500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 16257000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32350 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140 # average ReadReq mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

4
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=64
master=system.physmem.port[0]
width=8
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]

6
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
View file

@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jun 4 2012 11:58:11
gem5 started Jun 4 2012 14:43:38
gem5 compiled Aug 13 2012 17:00:38
gem5 started Aug 13 2012 18:11:50
gem5 executing on zizzer
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 2913500 because target called exit()
Exiting @ tick 2907000 because target called exit()

76
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
View file

@ -1,38 +1,38 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2913500 # Number of ticks simulated
final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1277439 # Simulator instruction rate (inst/s)
host_op_rate 1267147 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 631162418 # Simulator tick rate (ticks/s)
host_mem_usage 206236 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4375 # Number of bytes read from this memory
system.physmem.bytes_read::total 27687 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23312 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23312 # Number of instructions bytes read from this memory
host_inst_rate 264545 # Simulator instruction rate (inst/s)
host_op_rate 264338 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 132069950 # Simulator tick rate (ticks/s)
host_mem_usage 214924 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4374 # Number of bytes read from this memory
system.physmem.bytes_read::total 27634 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23260 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23260 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory
system.physmem.bytes_written::total 3658 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 5828 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1164 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6992 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 5815 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6978 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory
system.physmem.num_writes::total 925 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 8001372919 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1501630342 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9503003261 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001372919 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001372919 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1255534580 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1255534580 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001372919 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2757164922 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10758537841 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 8001375989 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1504643963 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9506019952 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8001375989 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8001375989 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1258341933 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1258341933 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@ -52,26 +52,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 5828 # number of cpu cycles simulated
system.cpu.numCycles 5815 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5827 # Number of instructions committed
system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.committedInsts 5814 # Number of instructions committed
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
system.cpu.num_int_insts 5126 # number of integer instructions
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
system.cpu.num_int_insts 5113 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2090 # number of memory refs
system.cpu.num_load_insts 1164 # Number of load instructions
system.cpu.num_mem_refs 2089 # number of memory refs
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5828 # Number of busy cycles
system.cpu.num_busy_cycles 5815 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles

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