X86 Regressions: Update stats due to fence instruction
This commit is contained in:
Nilay Vaish
parent
acbc03ae46
commit
a5a2b9ecbd
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@ -500,7 +500,7 @@ egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
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executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Nov 16 2011 11:08:03
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gem5 started Nov 17 2011 13:09:16
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gem5 compiled Jan 9 2012 14:18:02
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gem5 started Jan 9 2012 14:29:08
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gem5 executing on ribera.cs.wisc.edu
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command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
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tests
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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spec_init
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@ -3,26 +3,26 @@
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sim_seconds 0.586294 # Number of seconds simulated
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sim_ticks 586294224000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 112274 # Simulator instruction rate (inst/s)
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host_tick_rate 40595683 # Simulator tick rate (ticks/s)
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host_mem_usage 244844 # Number of bytes of host memory used
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host_seconds 14442.28 # Real time elapsed on the host
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host_inst_rate 115446 # Simulator instruction rate (inst/s)
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host_tick_rate 41742717 # Simulator tick rate (ticks/s)
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host_mem_usage 244900 # Number of bytes of host memory used
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host_seconds 14045.43 # Real time elapsed on the host
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sim_insts 1621493982 # Number of instructions simulated
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 1172588449 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 142448982 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 142448982 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups
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system.cpu.BPredUnit.BTBLookups 134509888 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered
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system.cpu.fetch.Insts 1143761054 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 142448982 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing
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@ -66,32 +66,32 @@ system.cpu.rename.RenamedInsts 2043122328 # Nu
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system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups
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system.cpu.rename.RenamedOperands 2031527322 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 4954653611 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 4954649391 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing
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system.cpu.rename.UndoneMaps 413532672 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 91 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued
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system.cpu.memDep0.conflictingStores 148937436 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 1986583516 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 218 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 1781630004 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.iqSquashedOperandsExamined 670712329 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 168 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 271921709 23.19% 23.19% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 416937499 35.56% 58.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle
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@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # at
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1102052869 61.86% 63.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
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@ -171,17 +171,17 @@ system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Ty
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system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued
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system.cpu.iq.FU_type_0::total 1781630004 # Type of FU issued
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system.cpu.iq.rate 1.519399 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_reads 4738479063 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.int_inst_queue_wakeup_accesses 1760053765 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses
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system.cpu.iq.int_alu_accesses 1757334381 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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@ -208,7 +208,7 @@ system.cpu.iew.memOrderViolationEvents 216417 # Nu
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system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions
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system.cpu.iew.iewExecutedInsts 1768232808 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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@ -217,8 +217,8 @@ system.cpu.iew.exec_refs 645919458 # nu
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system.cpu.iew.exec_branches 112169596 # Number of branches executed
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system.cpu.iew.exec_stores 193872240 # Number of stores executed
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system.cpu.iew.exec_rate 1.507974 # Inst execution rate
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system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit
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system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back
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system.cpu.iew.wb_sent 1766226829 # cumulative count of insts sent to commit
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system.cpu.iew.wb_count 1760053777 # cumulative count of insts written-back
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system.cpu.iew.wb_producers 1336567337 # num instructions producing a value
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system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
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@ -268,9 +268,9 @@ system.cpu.cpi_total 0.723153 # CP
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system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle
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system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads
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system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads
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system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes
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system.cpu.int_regfile_writes 1756091292 # number of integer regfile writes
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system.cpu.fp_regfile_reads 12 # number of floating regfile reads
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system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads
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system.cpu.misc_regfile_reads 908871445 # number of misc regfile reads
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system.cpu.icache.replacements 12 # number of replacements
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system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use
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system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks.
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@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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memories=system.physmem
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physmem=system.physmem
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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@ -61,12 +62,12 @@ type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=gzip input.log 1
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cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
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cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
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executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
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gid=100
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input=cin
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max_stack_size=67108864
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@ -1,7 +1,4 @@
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warn: Sockets disabled, not accepting gdb connections
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For more information see: http://www.m5sim.org/warn/d946bea6
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warn: instruction 'fnstcw_Mw' unimplemented
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For more information see: http://www.m5sim.org/warn/437d5238
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warn: instruction 'fldcw_Mw' unimplemented
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For more information see: http://www.m5sim.org/warn/437d5238
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hack: be nice to actually delete the event here
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@ -1,14 +1,12 @@
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M5 Simulator System
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Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simout
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Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic/simerr
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Apr 19 2011 12:22:33
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M5 started Apr 19 2011 12:22:36
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M5 executing on maize
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command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
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gem5 compiled Jan 9 2012 14:18:02
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gem5 started Jan 9 2012 14:29:08
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gem5 executing on ribera.cs.wisc.edu
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command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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spec_init
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@ -1,34 +1,34 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 3280168 # Simulator instruction rate (inst/s)
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host_mem_usage 202508 # Number of bytes of host memory used
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host_seconds 494.33 # Real time elapsed on the host
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host_tick_rate 1950088412 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1621493983 # Number of instructions simulated
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sim_seconds 0.963993 # Number of seconds simulated
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sim_ticks 963992704000 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1220339 # Simulator instruction rate (inst/s)
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host_tick_rate 725502264 # Simulator tick rate (ticks/s)
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host_mem_usage 234168 # Number of bytes of host memory used
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host_seconds 1328.72 # Real time elapsed on the host
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sim_insts 1621493983 # Number of instructions simulated
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.numCycles 1927985409 # number of cpu cycles simulated
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
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system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 1621493983 # Number of instructions executed
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system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
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system.cpu.num_func_calls 0 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1621354493 # number of integer instructions
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system.cpu.num_fp_insts 0 # number of float instructions
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system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
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system.cpu.num_load_insts 419042125 # Number of load instructions
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 607228182 # number of memory refs
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system.cpu.num_load_insts 419042125 # Number of load instructions
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system.cpu.num_store_insts 188186057 # Number of store instructions
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system.cpu.workload.num_syscalls 48 # Number of system calls
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1927985409 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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---------- End Simulation Statistics ----------
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@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -164,12 +165,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=gzip input.log 1
|
||||
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:23:09
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,223 +1,223 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2023797 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210248 # Number of bytes of host memory used
|
||||
host_seconds 801.21 # Real time elapsed on the host
|
||||
host_tick_rate 2250658484 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
sim_seconds 1.803259 # Number of seconds simulated
|
||||
sim_ticks 1803258587000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 606786134 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 442048 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 396372 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1186516018 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 722 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 760773 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 846053445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242892 # Number of bytes of host memory used
|
||||
host_seconds 2131.38 # Real time elapsed on the host
|
||||
sim_insts 1621493983 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1621493983 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1621354493 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 607228182 # number of memory refs
|
||||
system.cpu.num_load_insts 419042125 # Number of load instructions
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 4 # number of replacements
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 660.186297 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 1186516018 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 437952 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 606786134 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 606786134 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 442048 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 396372 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 71208 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 353302 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 89468 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 58007 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 353302 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 89468 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 71208 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 423014 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 58007 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 3606517174 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 99478861 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 1621493983 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 1621354493 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 419042125 # Number of load instructions
|
||||
system.cpu.num_mem_refs 607228182 # number of memory refs
|
||||
system.cpu.num_store_insts 188186057 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 48 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -15,10 +15,11 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
|
|
@ -1301,7 +1302,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -1321,7 +1322,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
|
|
|
|||
|
|
@ -1,13 +1,12 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 21 2011 16:24:08
|
||||
gem5 started Nov 21 2011 23:30:30
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
|
||||
gem5 compiled Jan 9 2012 20:47:38
|
||||
gem5 started Jan 9 2012 21:13:16
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-o3-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
|
||||
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5145286546500 because m5_exit instruction encountered
|
||||
Exiting @ tick 5161177988500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458
|
|||
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
||||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
time.c: Detected 2000.004 MHz processor.
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
|
|
@ -39,7 +39,7 @@ ACPI: Core revision 20070126
|
|||
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
|
||||
ACPI: Unable to load the System Description Tables
|
||||
Using local APIC timer interrupts.
|
||||
result 7812511
|
||||
result 7812497
|
||||
Detected 7.812 MHz APIC timer.
|
||||
NET: Registered protocol family 16
|
||||
PCI: Using configuration type 1
|
||||
|
|
|
|||
|
|
@ -500,9 +500,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 16 2011 11:08:03
|
||||
gem5 started Nov 17 2011 13:09:16
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
|
||||
tests
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -3,10 +3,10 @@
|
|||
sim_seconds 0.070313 # Number of seconds simulated
|
||||
sim_ticks 70312944500 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 125815 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 31799589 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378944 # Number of bytes of host memory used
|
||||
host_seconds 2211.13 # Real time elapsed on the host
|
||||
host_inst_rate 109444 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 27661822 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 378996 # Number of bytes of host memory used
|
||||
host_seconds 2541.88 # Real time elapsed on the host
|
||||
sim_insts 278192519 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 140625890 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -61,14 +62,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:39:34
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3107267 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 337076 # Number of bytes of host memory used
|
||||
host_seconds 89.53 # Real time elapsed on the host
|
||||
host_tick_rate 1887081425 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
sim_seconds 0.168950 # Number of seconds simulated
|
||||
sim_ticks 168950072000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1147935 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 697156581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 368676 # Number of bytes of host memory used
|
||||
host_seconds 242.34 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 337900145 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 337900145 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 278192520 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 278186228 # number of integer instructions
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 90779388 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 122219139 # number of memory refs
|
||||
system.cpu.num_load_insts 90779388 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 337900145 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -164,14 +165,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=mcf mcf.in
|
||||
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:41:14
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,223 +1,223 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1776708 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 344820 # Number of bytes of host memory used
|
||||
host_seconds 156.58 # Real time elapsed on the host
|
||||
host_tick_rate 2363113199 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
sim_seconds 0.370011 # Number of seconds simulated
|
||||
sim_ticks 370010840000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 120152372 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 1437080 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 217695401 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 808 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 588786 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 783116445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377276 # Number of bytes of host memory used
|
||||
host_seconds 472.49 # Real time elapsed on the host
|
||||
sim_insts 278192520 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 740021680 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 278192520 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 278186228 # number of integer instructions
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 122219139 # number of memory refs
|
||||
system.cpu.num_load_insts 90779388 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 740021680 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 217695401 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 120152372 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1437080 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 49212 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1991062 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 76575 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 29460 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1991062 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 76575 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 49212 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 29460 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 740021680 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 740021680 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 40 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 278192520 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 278186228 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 90779388 # Number of load instructions
|
||||
system.cpu.num_mem_refs 122219139 # number of memory refs
|
||||
system.cpu.num_store_insts 31439751 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -500,9 +500,9 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -3,11 +3,10 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 16 2011 11:08:03
|
||||
gem5 started Nov 17 2011 13:09:16
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
|
||||
tests
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
@ -82,4 +81,4 @@ info: Increasing stack size by one page.
|
|||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 494093841000 because target called exit()
|
||||
Exiting @ tick 493912286000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,149 +1,149 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.494094 # Number of seconds simulated
|
||||
sim_ticks 494093841000 # Number of ticks simulated
|
||||
sim_seconds 0.493912 # Number of seconds simulated
|
||||
sim_ticks 493912286000 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 111156 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 35920075 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 281020 # Number of bytes of host memory used
|
||||
host_seconds 13755.37 # Real time elapsed on the host
|
||||
host_inst_rate 108889 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 35174673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280548 # Number of bytes of host memory used
|
||||
host_seconds 14041.70 # Real time elapsed on the host
|
||||
sim_insts 1528988756 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 988187683 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 987824573 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits
|
||||
system.cpu.BPredUnit.lookups 245766486 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 245766486 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 16576996 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 236474058 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 218464201 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.icacheStallCycles 205503020 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 1343384866 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 245766486 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 218464201 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 436676837 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 119986236 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 218554807 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 32387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 341323 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.CacheLines 194710374 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 4099618 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 964252463 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.599701 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.317490 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 531629837 55.13% 55.13% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 32377332 3.36% 58.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 38827894 4.03% 62.52% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 32536894 3.37% 65.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 21844251 2.27% 68.16% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 36448993 3.78% 71.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 49128972 5.10% 77.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 36937786 3.83% 80.86% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 184520504 19.14% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups
|
||||
system.cpu.fetch.rateDist::total 964252463 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.248796 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.359943 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 264509435 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 174554141 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 373011587 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 49033211 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 103144089 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2445932072 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 103144089 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 301738657 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 40282868 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 12225 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 383467875 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 135606749 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2393375507 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 2559 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 25131978 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 92224846 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 2227188673 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 5629907069 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 5629667957 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 239112 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle
|
||||
system.cpu.rename.UndoneMaps 799889646 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 1309 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 1288 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 318947403 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 577879232 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 226530900 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 227222440 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 65937432 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2286709085 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 12489 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1922370305 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 1306641 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 755226802 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1190125426 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 11936 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 964252463 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.993638 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.811521 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 282911384 29.34% 29.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 160280603 16.62% 45.96% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 162550496 16.86% 62.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 148847741 15.44% 78.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 109081156 11.31% 89.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 60080329 6.23% 95.80% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 30822605 3.20% 99.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 8641604 0.90% 99.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1036545 0.11% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 964252463 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 2246339 14.60% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.60% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 10026447 65.19% 79.79% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 3108042 20.21% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::No_OpClass 2420122 0.13% 0.13% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1274712167 66.31% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
|
||||
|
|
@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 463703127 24.12% 90.56% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 181534884 9.44% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued
|
||||
system.cpu.iq.rate 1.945459 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iq.FU_type_0::total 1922370305 # Type of FU issued
|
||||
system.cpu.iq.rate 1.946064 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 15380828 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.008001 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 4825675637 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3042139517 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 1874661917 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 4905 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 81824 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 136 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1935329448 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 1563 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 158391521 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 193777072 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 372742 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 283642 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 77371112 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 2379 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewSquashCycles 103144089 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 9045659 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1404502 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2286721574 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 1118432 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 577879232 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 226531297 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6081 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 1006586 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 29974 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 283642 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 15693422 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 2344063 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 18037485 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 1889150749 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 454748002 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 33219556 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 176731992 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 174531259 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.911862 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1440755706 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value
|
||||
system.cpu.iew.exec_refs 629271939 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 176719729 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 174523937 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.912435 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1882531239 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1874662053 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1440606287 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2134778201 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 1.897768 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.674827 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
|
||||
system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 757743569 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 16604349 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 861108374 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.775605 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.288022 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 338327816 39.29% 39.29% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 210551706 24.45% 63.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 75360819 8.75% 72.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 92562974 10.75% 83.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 34054041 3.95% 87.20% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 27955182 3.25% 90.44% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 16032820 1.86% 92.30% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 12266632 1.42% 93.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 53996384 6.27% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 861108374 # Number of insts commited each cycle
|
||||
system.cpu.commit.count 1528988756 # Number of instructions committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.refs 533262345 # Number of memory references committed
|
||||
|
|
@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu
|
|||
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 53996384 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3094435758 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4677260376 # The number of ROB writes
|
||||
system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 3093844315 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 4676786954 # The number of ROB writes
|
||||
system.cpu.timesIdled 606516 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 23572110 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 109 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 3 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 9996 # number of replacements
|
||||
system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks.
|
||||
system.cpu.cpi 0.646064 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.646064 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.547834 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.547834 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 3179044858 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 1744829680 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 145 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 5 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1039286160 # number of misc regfile reads
|
||||
system.cpu.icache.replacements 10045 # number of replacements
|
||||
system.cpu.icache.tagsinuse 976.337758 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 194480398 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 11548 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16841.045895 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 194495909 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 223856 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency
|
||||
system.cpu.icache.occ_blocks::0 976.337758 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.476727 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 194486608 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 194486608 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 194486608 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 223766 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 223766 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 223766 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 1539723000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1539723000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1539723000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 194710374 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 194710374 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 194710374 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001149 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.001149 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.001149 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6880.951530 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 6880.951530 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 6880.951530 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -309,136 +309,136 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 6 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2071 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits 2071 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 2071 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 221695 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 221695 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 221695 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 824417000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 824417000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 824417000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3718.699114 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3718.699114 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2527207 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.replacements 2527930 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4087.566272 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 440586260 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2532026 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 174.005425 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 439652157 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 4698243 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.occ_blocks::0 4087.566272 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997941 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 291836002 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 147579227 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 439415229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 439415229 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 3119681 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1580974 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 4700655 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 4700655 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 52079313500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 37355392500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 89434706000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 89434706000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 294955683 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 444115884 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 444115884 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.010577 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010599 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.010584 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.010584 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16693.794494 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 23628.087812 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 19026.009354 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 19026.009354 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 2229206 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses
|
||||
system.cpu.dcache.writebacks 2229595 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1359154 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits 607660 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits 1966814 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 1966814 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1760527 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 973314 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2733841 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2733841 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 14908482500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17169522000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32078004500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32078004500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005969 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006156 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006156 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8468.193047 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17640.270252 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 11733.675989 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 574699 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1957169 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 585504 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency
|
||||
system.cpu.l2cache.replacements 574945 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21597.257673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3194359 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 594122 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.376604 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 271429089000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7797.131828 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13800.125845 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.237950 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.421146 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1433279 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2229601 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits 1240 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits 524400 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1957679 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1957679 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 338611 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses 208876 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 247152 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 585763 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 585763 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11564612500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 9756500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8478074500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20042687000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20042687000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1771890 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2229601 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses 210116 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 771552 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2543442 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2543442 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191102 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 0.994098 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.320331 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.230303 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.230303 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.091601 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 46.709531 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34303.078672 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34216.375906 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34216.375906 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 411193 # number of writebacks
|
||||
system.cpu.l2cache.writebacks 411265 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 338611 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 208876 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 247152 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 585763 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 585763 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10503665500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6475353000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666739500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 18170405000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 18170405000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191102 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994098 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320331 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.230303 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.230303 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.859071 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.943143 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.341733 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31020.062722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -61,14 +62,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:30:34
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3416660 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206360 # Number of bytes of host memory used
|
||||
host_seconds 447.51 # Real time elapsed on the host
|
||||
host_tick_rate 1978121798 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
sim_seconds 0.885229 # Number of seconds simulated
|
||||
sim_ticks 885229360000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1063398 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 615669149 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 237896 # Number of bytes of host memory used
|
||||
host_seconds 1437.83 # Real time elapsed on the host
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1528988757 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317615 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262345 # number of memory refs
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1770458721 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -164,14 +165,14 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:27:05
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,223 +1,223 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2070048 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214112 # Number of bytes of host memory used
|
||||
host_seconds 738.62 # Real time elapsed on the host
|
||||
host_tick_rate 2245699490 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
sim_seconds 1.658730 # Number of seconds simulated
|
||||
sim_ticks 1658729604000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 530743932 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2223170 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1068344296 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 2814 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 746220 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 809539282 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246668 # Number of bytes of host memory used
|
||||
host_seconds 2048.98 # Real time elapsed on the host
|
||||
sim_insts 1528988757 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 1528988757 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1528317615 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 533262345 # number of memory refs
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 1253 # number of replacements
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 882.231489 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.430777 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 1068344296 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 1068344296 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 1068344296 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 2814 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 136878000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 136878000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 136878000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 1068347110 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 1068347110 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 1068347110 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 48641.791045 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 48641.791045 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 128436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 128436000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 128436000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4086.472055 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997674 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 148369157 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 530743932 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 530743932 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 38012508000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 21492013500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 59504521500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 59504521500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 533262390 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 533262390 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 23627.363053 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 2223170 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 32830264000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 19118876000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 51949140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 51949140000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 568906 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 7549.128601 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 13679.064710 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.230381 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.417452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1398652 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 2223170 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 543011 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1941663 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1941663 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 331576 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 248033 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 579609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 579609 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 17241952000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 12897722000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 30139674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 411709 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1941663 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 579609 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 568906 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 411709 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 3317459208 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 3317459208 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 1528988757 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 1528317615 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 384102160 # Number of load instructions
|
||||
system.cpu.num_mem_refs 533262345 # number of memory refs
|
||||
system.cpu.num_store_insts 149160185 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -61,12 +62,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
|
||||
cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:22:46
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2952357 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202444 # Number of bytes of host memory used
|
||||
host_seconds 1587.50 # Real time elapsed on the host
|
||||
host_tick_rate 1792761763 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4686862651 # Number of instructions simulated
|
||||
sim_seconds 2.846007 # Number of seconds simulated
|
||||
sim_ticks 2846007259500 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1508697 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 916127309 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234076 # Number of bytes of host memory used
|
||||
host_seconds 3106.56 # Real time elapsed on the host
|
||||
sim_insts 4686862651 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 4686862651 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4686862580 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1239184749 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1677713086 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184749 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5692014520 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -164,12 +165,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=bzip2 input.source 1
|
||||
cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:36:40
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -1,223 +1,223 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1878760 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210192 # Number of bytes of host memory used
|
||||
host_seconds 2494.66 # Real time elapsed on the host
|
||||
host_tick_rate 2374493636 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 4686862651 # Number of instructions simulated
|
||||
sim_seconds 5.923548 # Number of seconds simulated
|
||||
sim_ticks 5923548078000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1668600409 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 3053391 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 4013232252 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 675 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 871353 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1101269643 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242804 # Number of bytes of host memory used
|
||||
host_seconds 5378.84 # Real time elapsed on the host
|
||||
sim_insts 4686862651 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 4686862651 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4686862580 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1677713086 # number of memory refs
|
||||
system.cpu.num_load_insts 1239184749 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 10 # number of replacements
|
||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 555.713137 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 4013232252 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4084.662246 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 58862779000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 4084.662246 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.997232 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 436638510 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 1668600409 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 1668600409 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 177808540000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 63869078000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 241677618000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 241677618000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 26521.034159 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 26521.034159 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 3053391 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 58199597000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 214339587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 214339587000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 2706631 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.758083 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 15478.805498 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 11028.544571 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.472376 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.336564 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 5396930 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 3053391 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 999077 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 6396007 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 6396007 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 1826595 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 890750 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 2717345 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 2717345 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 94982940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 46319000000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 141301940000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 3053391 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.252868 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.471339 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.298172 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 1174631 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1826595 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 890750 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 2717345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73063800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35630000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 108693800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252868 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.471339 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.298172 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 6396007 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 141301940000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.298172 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 2717345 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 108693800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.298172 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 2717345 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 2706631 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2732923 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 26507.350069 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7537629 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 1324806325000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1174631 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 11847096156 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 182173305 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 4686862651 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 4686862580 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1239184749 # Number of load instructions
|
||||
system.cpu.num_mem_refs 1677713086 # number of memory refs
|
||||
system.cpu.num_store_insts 438528337 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -500,7 +500,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -3,11 +3,12 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Nov 16 2011 11:08:03
|
||||
gem5 started Nov 17 2011 13:09:16
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
|
||||
tests
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -3,10 +3,10 @@
|
|||
sim_seconds 0.096690 # Number of seconds simulated
|
||||
sim_ticks 96689893000 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 89575 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 39125952 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253168 # Number of bytes of host memory used
|
||||
host_seconds 2471.25 # Real time elapsed on the host
|
||||
host_inst_rate 71082 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 31048201 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253148 # Number of bytes of host memory used
|
||||
host_seconds 3114.19 # Real time elapsed on the host
|
||||
sim_insts 221363017 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 193379787 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -61,12 +62,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
|
||||
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,16 +1,14 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:38:23
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
|
||||
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
|
||||
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3098099 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209904 # Number of bytes of host memory used
|
||||
host_seconds 71.45 # Real time elapsed on the host
|
||||
host_tick_rate 1838915708 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 221363018 # Number of instructions simulated
|
||||
sim_seconds 0.131393 # Number of seconds simulated
|
||||
sim_ticks 131393100000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 733183 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 435191133 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241232 # Number of bytes of host memory used
|
||||
host_seconds 301.92 # Real time elapsed on the host
|
||||
sim_insts 221363018 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 262786201 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 262786201 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 221363018 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339607 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 56649590 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 77165306 # number of memory refs
|
||||
system.cpu.num_load_insts 56649590 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 262786201 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -164,12 +165,12 @@ type=ExeTracer
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=twolf smred
|
||||
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
|
||||
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,16 +1,14 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:30:33
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
|
||||
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
|
||||
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:29:08
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
|
||||
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,223 +1,223 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1944621 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217656 # Number of bytes of host memory used
|
||||
host_seconds 113.83 # Real time elapsed on the host
|
||||
host_tick_rate 2204625935 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 221363018 # Number of instructions simulated
|
||||
sim_seconds 0.250961 # Number of seconds simulated
|
||||
sim_ticks 250960631000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 77195833 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1905 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 41 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 7 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 173489718 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4694 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 461238 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 522908265 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250008 # Number of bytes of host memory used
|
||||
host_seconds 479.93 # Real time elapsed on the host
|
||||
sim_insts 221363018 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501921262 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 221363018 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 220339607 # number of integer instructions
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 77165306 # number of memory refs
|
||||
system.cpu.num_load_insts 56649590 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 501921262 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 2836 # number of replacements
|
||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1455.289108 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 173489718 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 4694 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 170928000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 170928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 170928000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1363.451495 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 1363.451495 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.332874 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 56681681 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 77195833 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 327 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 1905 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 18020000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 88242000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 106262000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 106262000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 55780.577428 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55780.577428 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 7 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 327 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 2058.146434 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_blocks::1 0.021756 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.062810 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::1 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1861 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits 1864 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1864 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 3160 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 4735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 4735 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 164335500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 246235500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 5021 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 6599 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.629357 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.717533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52003.273495 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52003.273495 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1864 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 246235500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 4735 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2058.168190 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 501921262 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 501921262 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 8268471 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 2162459 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_insts 221363018 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
|
||||
system.cpu.num_int_insts 220339607 # number of integer instructions
|
||||
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 56649590 # Number of load instructions
|
||||
system.cpu.num_mem_refs 77165306 # number of memory refs
|
||||
system.cpu.num_store_insts 20515716 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -500,7 +500,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 20 2011 13:24:14
|
||||
gem5 started Aug 20 2011 13:24:28
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:28:31
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -3,26 +3,26 @@
|
|||
sim_seconds 0.000011 # Number of seconds simulated
|
||||
sim_ticks 11087000 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51481 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 58182623 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 209228 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_inst_rate 74834 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 84571612 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239776 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 9809 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 22175 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.BPredUnit.lookups 3057 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 3057 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.lookups 3056 # Number of BP lookups
|
||||
system.cpu.BPredUnit.condPredicted 3056 # Number of conditional branches predicted
|
||||
system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect
|
||||
system.cpu.BPredUnit.BTBLookups 2732 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBLookups 2731 # Number of BTB lookups
|
||||
system.cpu.BPredUnit.BTBHits 995 # Number of BTB hits
|
||||
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
system.cpu.fetch.icacheStallCycles 5895 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 14000 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 3057 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.Insts 13997 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 3056 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 995 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 3968 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2221 # Number of cycles fetch has spent squashing
|
||||
|
|
@ -48,8 +48,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13088 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.137858 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.631342 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.137813 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.631206 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6247 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1453 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 3565 # Number of cycles decode is running
|
||||
|
|
@ -66,34 +66,34 @@ system.cpu.rename.RenamedInsts 22712 # Nu
|
|||
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 272 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 21252 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 47663 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 47647 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 21246 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 47645 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 47629 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 11884 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 11878 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 1613 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2239 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1783 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 2238 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1782 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 20542 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 16960 # Number of instructions issued
|
||||
system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 20539 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 16958 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 10220 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 12997 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 12992 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13088 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.295844 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.003369 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.295691 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.003315 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 8001 61.13% 61.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1107 8.46% 69.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1108 8.47% 69.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1006 7.69% 77.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 734 5.61% 82.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 733 5.60% 82.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 670 5.12% 88.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 725 5.54% 93.54% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 615 4.70% 98.24% # Number of insts issued each cycle
|
||||
|
|
@ -138,7 +138,7 @@ system.cpu.iq.fu_full::MemWrite 23 16.31% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 13642 80.44% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 13641 80.44% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.46% # Type of FU issued
|
||||
|
|
@ -167,28 +167,28 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.46% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1844 10.87% 91.33% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1843 10.87% 91.33% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1470 8.67% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 16960 # Type of FU issued
|
||||
system.cpu.iq.rate 0.764825 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 16958 # Type of FU issued
|
||||
system.cpu.iq.rate 0.764735 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.008314 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 47204 # Number of integer instruction queue reads
|
||||
system.cpu.iq.fu_busy_rate 0.008315 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 47200 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 30804 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 15755 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 17093 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 17091 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1183 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 848 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
|
|
@ -199,9 +199,9 @@ system.cpu.iew.iewBlockCycles 144 # Nu
|
|||
system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 20576 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 23 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2239 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1783 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2238 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1782 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
|
||||
|
|
@ -210,7 +210,7 @@ system.cpu.iew.predictedNotTakenIncorrect 523 # N
|
|||
system.cpu.iew.branchMispredicts 588 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 16100 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1742 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 860 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 858 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 3105 # number of memory reference insts executed
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -66,7 +67,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:22:35
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:28:31
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 918185 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 200072 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 520394424 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
sim_ticks 5651000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 855797 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 492033087 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 229652 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 11303 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 11303 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11303 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000
|
|||
type=System
|
||||
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -41,8 +42,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.cpu_ruby_ports.port[1]
|
||||
icache_port=system.ruby.cpu_ruby_ports.port[0]
|
||||
dcache_port=system.l1_cntrl0.sequencer.port[1]
|
||||
icache_port=system.l1_cntrl0.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -63,7 +64,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -78,11 +79,13 @@ uid=100
|
|||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
cntrl_id=1
|
||||
directory=system.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
|
|
@ -117,16 +120,43 @@ version=0
|
|||
|
||||
[system.l1_cntrl0]
|
||||
type=L1Cache_Controller
|
||||
children=cacheMemory sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.cpu_ruby_ports.dcache
|
||||
cacheMemory=system.l1_cntrl0.cacheMemory
|
||||
cache_response_latency=12
|
||||
cntrl_id=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.cpu_ruby_ports
|
||||
ruby_system=system.ruby
|
||||
sequencer=system.l1_cntrl0.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.l1_cntrl0.cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
is_icache=false
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=true
|
||||
dcache=system.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
icache=system.l1_cntrl0.cacheMemory
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
ruby_system=system.ruby
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
@ -135,44 +165,18 @@ latency_var=0
|
|||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.cpu_ruby_ports.physMemPort
|
||||
port=system.l1_cntrl0.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=cpu_ruby_ports network profiler tracer
|
||||
children=network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
no_mem_vec=false
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.cpu_ruby_ports]
|
||||
type=RubySequencer
|
||||
children=dcache
|
||||
access_phys_mem=true
|
||||
dcache=system.ruby.cpu_ruby_ports.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.cpu_ruby_ports.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
start_index_bit=6
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
|
|
@ -180,59 +184,77 @@ children=topology
|
|||
adaptive_routing=false
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
endpoint_bandwidth=1000
|
||||
number_of_virtual_networks=10
|
||||
ruby_system=system.ruby
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2
|
||||
description=Crossbar
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.l1_cntrl0
|
||||
int_node=0
|
||||
int_node=system.ruby.network.topology.routers0
|
||||
latency=1
|
||||
link_id=0
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
bw_multiplier=64
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
ext_node=system.dir_cntrl0
|
||||
int_node=1
|
||||
int_node=system.ruby.network.topology.routers1
|
||||
latency=1
|
||||
link_id=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
link_id=2
|
||||
node_a=system.ruby.network.topology.routers0
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
link_id=3
|
||||
node_a=system.ruby.network.topology.routers1
|
||||
node_b=system.ruby.network.topology.routers2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.routers0]
|
||||
type=BasicRouter
|
||||
router_id=0
|
||||
|
||||
[system.ruby.network.topology.routers1]
|
||||
type=BasicRouter
|
||||
router_id=1
|
||||
|
||||
[system.ruby.network.topology.routers2]
|
||||
type=BasicRouter
|
||||
router_id=2
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
ruby_system=system.ruby
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
ruby_system=system.ruby
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Apr/19/2011 12:26:55
|
||||
Real time: Jan/09/2012 14:28:32
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
|||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.17
|
||||
Virtual_time_in_minutes: 0.00283333
|
||||
Virtual_time_in_hours: 4.72222e-05
|
||||
Virtual_time_in_days: 1.96759e-06
|
||||
Virtual_time_in_seconds: 0.31
|
||||
Virtual_time_in_minutes: 0.00516667
|
||||
Virtual_time_in_hours: 8.61111e-05
|
||||
Virtual_time_in_days: 3.58796e-06
|
||||
|
||||
Ruby_current_time: 276484
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 276484
|
||||
|
||||
mbytes_resident: 39.5938
|
||||
mbytes_total: 212.965
|
||||
resident_ratio: 0.185935
|
||||
mbytes_resident: 40.0625
|
||||
mbytes_total: 241.918
|
||||
resident_ratio: 0.165652
|
||||
|
||||
ruby_cycles_executed: [ 276485 ]
|
||||
|
||||
|
|
@ -125,11 +125,11 @@ Resource Usage
|
|||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 10428
|
||||
page_faults: 0
|
||||
page_reclaims: 11175
|
||||
page_faults: 4
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 64
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
|
@ -142,9 +142,9 @@ total_msgs: 16500 total_bytes: 660000
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.155303
|
||||
links_utilized_percent_switch_0_link_0: 0.0622369 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.248369 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 2.48658
|
||||
links_utilized_percent_switch_0_link_0: 2.48947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 2.48369 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -153,9 +153,9 @@ links_utilized_percent_switch_0: 0.155303
|
|||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.15552
|
||||
links_utilized_percent_switch_1_link_0: 0.0620922 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.248947 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 2.48658
|
||||
links_utilized_percent_switch_1_link_0: 2.48369 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 2.48947 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
|
@ -164,27 +164,27 @@ links_utilized_percent_switch_1: 0.15552
|
|||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.248658
|
||||
links_utilized_percent_switch_2_link_0: 0.248947 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.248369 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 2.48658
|
||||
links_utilized_percent_switch_2_link_0: 2.48947 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 2.48369 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 1377
|
||||
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1377
|
||||
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
|
||||
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 1377
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 1377
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 36.2382%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 18.5185%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 45.2433%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 36.2382%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 18.5185%
|
||||
system.l1_cntrl0.cacheMemory_request_type_IFETCH: 45.2433%
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 1377 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1377 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
|
@ -230,9 +230,9 @@ Memory controller: system.dir_cntrl0.memBuffer:
|
|||
memory_reads: 1377
|
||||
memory_writes: 1373
|
||||
memory_refreshes: 576
|
||||
memory_total_request_delays: 3664
|
||||
memory_delays_per_request: 1.33236
|
||||
memory_delays_in_input_queue: 1372
|
||||
memory_total_request_delays: 3035
|
||||
memory_delays_per_request: 1.10364
|
||||
memory_delays_in_input_queue: 743
|
||||
memory_delays_behind_head_of_bank_queue: 6
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2286
|
||||
memory_stalls_for_bank_busy: 791
|
||||
|
|
@ -310,4 +310,5 @@ ID_W PUTX [0 ] 0
|
|||
ID_W PUTX_NotOwner [0 ] 0
|
||||
ID_W DMA_READ [0 ] 0
|
||||
ID_W DMA_WRITE [0 ] 0
|
||||
ID_W Memory_Ack
|
||||
ID_W Memory_Ack [0 ] 0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:26:55
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:28:31
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 147176 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218080 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 4140017 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000276 # Number of seconds simulated
|
||||
sim_ticks 276484 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 73084 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 2059440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247728 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 276484 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 276484 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 276484 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000
|
|||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
physmem=system.physmem
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
|
|
@ -169,7 +170,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
M5 Simulator System
|
||||
Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:22:33
|
||||
M5 started Apr 19 2011 12:39:44
|
||||
M5 executing on maize
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
|
||||
gem5 compiled Jan 9 2012 14:18:02
|
||||
gem5 started Jan 9 2012 14:28:31
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
|
|
|
|||
|
|
@ -1,218 +1,218 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 743049 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207784 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 2149305775 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
sim_seconds 0.000029 # Number of seconds simulated
|
||||
sim_ticks 28768000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1856 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 134 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
|
||||
system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 6683 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 228 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 361 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 524711 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 1537080573 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238628 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 9810 # Number of instructions simulated
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 57536 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.num_busy_cycles 57536 # Number of busy cycles
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 9810 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 9715 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 1990 # number of memory refs
|
||||
system.cpu.num_load_insts 1056 # Number of load instructions
|
||||
system.cpu.num_store_insts 934 # Number of store instructions
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 57536 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits 6683 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses 228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits 1856 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses 134 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
|
||||
system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses 361 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -15,9 +15,11 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=atomic
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
|
|
@ -707,6 +709,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.
|
|||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -729,6 +732,7 @@ system=system
|
|||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -745,15 +749,31 @@ pio=system.iobus.port[12]
|
|||
|
||||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
children=terminal
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
terminal=system.pc.terminal
|
||||
terminal=system.pc.com_1.terminal
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -770,6 +790,7 @@ pio=system.iobus.port[14]
|
|||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -786,6 +807,7 @@ pio=system.iobus.port[15]
|
|||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -802,6 +824,7 @@ pio=system.iobus.port[16]
|
|||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=1000
|
||||
pio_size=2
|
||||
|
|
@ -818,6 +841,7 @@ pio=system.iobus.port[17]
|
|||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=1000
|
||||
pio_size=1
|
||||
|
|
@ -846,7 +870,6 @@ type=SouthBridge
|
|||
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
|
||||
cmos=system.pc.south_bridge.cmos
|
||||
dma1=system.pc.south_bridge.dma1
|
||||
int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
|
||||
io_apic=system.pc.south_bridge.io_apic
|
||||
keyboard=system.pc.south_bridge.keyboard
|
||||
pic1=system.pc.south_bridge.pic1
|
||||
|
|
@ -858,7 +881,8 @@ speaker=system.pc.south_bridge.speaker
|
|||
|
||||
[system.pc.south_bridge.cmos]
|
||||
type=Cmos
|
||||
int_pin=system.pc.south_bridge.int_lines2.source
|
||||
children=int_pin
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -866,6 +890,9 @@ system=system
|
|||
time=Sun Jan 1 00:00:00 2012
|
||||
pio=system.iobus.port[1]
|
||||
|
||||
[system.pc.south_bridge.cmos.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
pio_addr=9223372036854775808
|
||||
|
|
@ -948,7 +975,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -968,70 +995,58 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines0.sink
|
||||
source=system.pc.south_bridge.int_lines0.source
|
||||
source=system.pc.south_bridge.pic1.output
|
||||
|
||||
[system.pc.south_bridge.int_lines0.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines0.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines1]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines1.sink
|
||||
source=system.pc.south_bridge.int_lines1.source
|
||||
source=system.pc.south_bridge.pic2.output
|
||||
|
||||
[system.pc.south_bridge.int_lines1.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
number=2
|
||||
|
||||
[system.pc.south_bridge.int_lines1.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines2]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines2.sink
|
||||
source=system.pc.south_bridge.int_lines2.source
|
||||
source=system.pc.south_bridge.cmos.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines2.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic2
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines2.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines3]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines3.sink
|
||||
source=system.pc.south_bridge.int_lines3.source
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines3.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines3.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines4]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines4.sink
|
||||
source=system.pc.south_bridge.int_lines3.source
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines4.sink]
|
||||
type=X86IntSinkPin
|
||||
|
|
@ -1040,32 +1055,26 @@ number=2
|
|||
|
||||
[system.pc.south_bridge.int_lines5]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines5.sink
|
||||
source=system.pc.south_bridge.int_lines5.source
|
||||
source=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines5.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=1
|
||||
|
||||
[system.pc.south_bridge.int_lines5.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines6]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines6.sink
|
||||
source=system.pc.south_bridge.int_lines6.source
|
||||
source=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines6.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=12
|
||||
|
||||
[system.pc.south_bridge.int_lines6.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
|
|
@ -1080,20 +1089,28 @@ pio=system.iobus.port[9]
|
|||
|
||||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
children=keyboard_int_pin mouse_int_pin
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
keyboard_int_pin=system.pc.south_bridge.int_lines5.source
|
||||
mouse_int_pin=system.pc.south_bridge.int_lines6.source
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[4]
|
||||
|
||||
[system.pc.south_bridge.keyboard.keyboard_int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.keyboard.mouse_int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.int_lines0.source
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -1101,10 +1118,14 @@ slave=system.pc.south_bridge.pic2
|
|||
system=system
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.pc.south_bridge.pic1.output]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.int_lines1.source
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -1112,15 +1133,22 @@ slave=Null
|
|||
system=system
|
||||
pio=system.iobus.port[6]
|
||||
|
||||
[system.pc.south_bridge.pic2.output]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
int_pin=system.pc.south_bridge.int_lines3.source
|
||||
children=int_pin
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.pc.south_bridge.pit.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
i8254=system.pc.south_bridge.pit
|
||||
|
|
@ -1130,13 +1158,6 @@ platform=system.pc
|
|||
system=system
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.pc.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
|
|||
|
|
@ -1,17 +1,9 @@
|
|||
warn: Sockets disabled, not accepting terminal connections
|
||||
For more information see: http://www.m5sim.org/warn/8742226b
|
||||
warn: Reading current count from inactive timer.
|
||||
For more information see: http://www.m5sim.org/warn/1ea2be46
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
For more information see: http://www.m5sim.org/warn/7fe1004f
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
For more information see: http://www.m5sim.org/warn/77378d57
|
||||
warn: Unknown mouse command 0xe1.
|
||||
For more information see: http://www.m5sim.org/warn/2447512a
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,15 +1,12 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:44:38
|
||||
M5 started Apr 19 2011 12:44:44
|
||||
M5 executing on maize
|
||||
command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
|
||||
gem5 compiled Jan 9 2012 20:47:38
|
||||
gem5 started Jan 9 2012 21:03:15
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-atomic
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5112051446000 because m5_exit instruction encountered
|
||||
Exiting @ tick 5112043255000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,79 +1,79 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112037 # Number of seconds simulated
|
||||
sim_ticks 5112036996000 # Number of ticks simulated
|
||||
sim_seconds 5.112043 # Number of seconds simulated
|
||||
sim_ticks 5112043255000 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2883648 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 36256565088 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375496 # Number of bytes of host memory used
|
||||
host_seconds 141.00 # Real time elapsed on the host
|
||||
sim_insts 406583262 # Number of instructions simulated
|
||||
system.l2c.replacements 163860 # number of replacements
|
||||
system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3334365 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 195829 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 17.026921 # Average number of references to valid blocks.
|
||||
host_inst_rate 2860366 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 35739722021 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 375540 # Number of bytes of host memory used
|
||||
host_seconds 143.04 # Real time elapsed on the host
|
||||
sim_insts 409133277 # Number of instructions simulated
|
||||
system.l2c.replacements 164044 # number of replacements
|
||||
system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3332458 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context
|
||||
system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::0 1528802 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1528802 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::0 2211867 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 10263 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2222130 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::0 2211867 # number of overall hits
|
||||
system.l2c.overall_hits::1 10263 # number of overall hits
|
||||
system.l2c.overall_hits::total 2222130 # number of overall hits
|
||||
system.l2c.ReadReq_misses::0 56047 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 29 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 56076 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::0 200438 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 29 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 200467 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::0 200438 # number of overall misses
|
||||
system.l2c.overall_misses::1 29 # number of overall misses
|
||||
system.l2c.overall_misses::total 200467 # number of overall misses
|
||||
system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context
|
||||
system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context
|
||||
system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy
|
||||
system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy
|
||||
system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::0 1529403 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::1 9538 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::0 2211865 # number of overall hits
|
||||
system.l2c.overall_hits::1 9538 # number of overall hits
|
||||
system.l2c.overall_hits::total 2221403 # number of overall hits
|
||||
system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::0 200611 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::1 27 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::0 200611 # number of overall misses
|
||||
system.l2c.overall_misses::1 27 # number of overall misses
|
||||
system.l2c.overall_misses::total 200638 # number of overall misses
|
||||
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses
|
||||
system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses
|
||||
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
|
||||
|
|
@ -88,7 +88,7 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
|
|||
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks 144360 # number of writebacks
|
||||
system.l2c.writebacks 144472 # number of writebacks
|
||||
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -109,42 +109,42 @@ system.l2c.overall_avg_mshr_uncacheable_latency no_value
|
|||
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.replacements 47572 # number of replacements
|
||||
system.iocache.tagsinuse 0.042404 # Cycle average of tags in use
|
||||
system.iocache.replacements 47570 # number of replacements
|
||||
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
|
||||
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.sampled_refs 47588 # Sample count of references to valid blocks.
|
||||
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
|
||||
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context
|
||||
system.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy
|
||||
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context
|
||||
system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy
|
||||
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
||||
system.iocache.overall_hits::0 0 # number of overall hits
|
||||
system.iocache.overall_hits::1 0 # number of overall hits
|
||||
system.iocache.overall_hits::total 0 # number of overall hits
|
||||
system.iocache.ReadReq_misses::1 907 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 907 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::1 905 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::1 47627 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47627 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::1 47625 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::0 0 # number of overall misses
|
||||
system.iocache.overall_misses::1 47627 # number of overall misses
|
||||
system.iocache.overall_misses::total 47627 # number of overall misses
|
||||
system.iocache.overall_misses::1 47625 # number of overall misses
|
||||
system.iocache.overall_misses::total 47625 # number of overall misses
|
||||
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
||||
|
|
@ -200,68 +200,68 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.cpu.numCycles 10224074013 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224086531 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 406583262 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses
|
||||
system.cpu.num_insts 409133277 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 391790000 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374297244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 836247135 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 419118732 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 38123075 # number of memory refs
|
||||
system.cpu.num_load_insts 29716799 # Number of load instructions
|
||||
system.cpu.num_store_insts 8406276 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955651 # Percentage of idle cycles
|
||||
system.cpu.num_mem_refs 35626519 # number of memory refs
|
||||
system.cpu.num_load_insts 27217784 # Number of load instructions
|
||||
system.cpu.num_store_insts 8408735 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.replacements 790768 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 253353258 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context
|
||||
system.cpu.icache.replacements 790795 # number of replacements
|
||||
system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context
|
||||
system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits
|
||||
system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::0 253353258 # number of overall hits
|
||||
system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::0 243365777 # number of overall hits
|
||||
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 253353258 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_hits::total 243365777 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::0 791287 # number of overall misses
|
||||
system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::0 791314 # number of overall misses
|
||||
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791287 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791314 # number of overall misses
|
||||
system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses
|
||||
system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 254144545 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::0 254144545 # number of overall (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.003114 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::0 0.003114 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::0 0.003114 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
|
|
@ -278,7 +278,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks 806 # number of writebacks
|
||||
system.cpu.icache.writebacks 809 # number of writebacks
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -299,50 +299,50 @@ system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
|
|||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.replacements 3656 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.021422 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7713 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3666 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.103928 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5105310674000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::1 3.021422 # Average occupied blocks per context
|
||||
system.cpu.itb_walker_cache.occ_percent::1 0.188839 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::1 7719 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7719 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.replacements 3435 # number of replacements
|
||||
system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context
|
||||
system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::1 7721 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7721 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::1 7721 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7721 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::1 4507 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4507 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::1 4507 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4507 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::1 4507 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4507 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
|
||||
system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::1 12226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::1 12228 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::1 12228 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.368641 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::1 0.368580 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::1 0.368580 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
||||
system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
|
||||
|
|
@ -358,7 +358,7 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks 405 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks 518 # number of writebacks
|
||||
system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -379,46 +379,46 @@ system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value
|
|||
system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.replacements 8177 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::1 5.011395 # Average occupied blocks per context
|
||||
system.cpu.dtb_walker_cache.occ_percent::1 0.313212 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::1 12392 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12392 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context
|
||||
system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::1 12392 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12392 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::1 12392 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12392 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::1 9345 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 9345 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::1 9345 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 9345 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::1 9345 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 9345 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::1 21737 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21737 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::1 21737 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21737 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::1 21737 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21737 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.429912 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::1 0.429912 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::1 0.429912 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
||||
system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
|
||||
|
|
@ -434,7 +434,7 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -455,52 +455,52 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value
|
|||
system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1621118 # number of replacements
|
||||
system.cpu.dcache.replacements 1621277 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 20138941 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621630 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.418949 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context
|
||||
system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::0 12055886 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12055886 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::0 8080806 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8080806 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::0 20136692 # number of demand (read+write) hits
|
||||
system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20136692 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::0 20136692 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::0 20139962 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::1 0 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20136692 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::0 1308365 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308365 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::0 315530 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315530 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::0 1623895 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1623895 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::0 1623895 # number of overall misses
|
||||
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::0 1624057 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::1 0 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1623895 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
|
||||
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::0 13364251 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13364251 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::0 8396336 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8396336 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::0 21760587 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21760587 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::0 21760587 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
|
||||
|
|
@ -517,7 +517,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks 1525259 # number of writebacks
|
||||
system.cpu.dcache.writebacks 1525559 # number of writebacks
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
||||
|
|
|
|||
|
|
@ -15,9 +15,11 @@ e820_table=system.e820_table
|
|||
init_param=0
|
||||
intel_mp_pointer=system.intel_mp_pointer
|
||||
intel_mp_table=system.intel_mp_table
|
||||
kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
load_addr_mask=18446744073709551615
|
||||
mem_mode=timing
|
||||
memories=system.physmem
|
||||
num_work_ids=16
|
||||
physmem=system.physmem
|
||||
readfile=tests/halt.sh
|
||||
smbios_table=system.smbios_table
|
||||
|
|
@ -704,6 +706,7 @@ port=system.physmem.port[0] system.bridge.side_b system.iocache.mem_side system.
|
|||
|
||||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -726,6 +729,7 @@ system=system
|
|||
|
||||
[system.pc.behind_pci]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854779128
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -742,15 +746,31 @@ pio=system.iobus.port[12]
|
|||
|
||||
[system.pc.com_1]
|
||||
type=Uart8250
|
||||
children=terminal
|
||||
pio_addr=9223372036854776824
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
terminal=system.pc.terminal
|
||||
terminal=system.pc.com_1.terminal
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.pc.com_1.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.pc.fake_com_2]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776568
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -767,6 +787,7 @@ pio=system.iobus.port[14]
|
|||
|
||||
[system.pc.fake_com_3]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776808
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -783,6 +804,7 @@ pio=system.iobus.port[15]
|
|||
|
||||
[system.pc.fake_com_4]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776552
|
||||
pio_latency=1000
|
||||
pio_size=8
|
||||
|
|
@ -799,6 +821,7 @@ pio=system.iobus.port[16]
|
|||
|
||||
[system.pc.fake_floppy]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854776818
|
||||
pio_latency=1000
|
||||
pio_size=2
|
||||
|
|
@ -815,6 +838,7 @@ pio=system.iobus.port[17]
|
|||
|
||||
[system.pc.i_dont_exist]
|
||||
type=IsaFake
|
||||
fake_mem=false
|
||||
pio_addr=9223372036854775936
|
||||
pio_latency=1000
|
||||
pio_size=1
|
||||
|
|
@ -843,7 +867,6 @@ type=SouthBridge
|
|||
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
|
||||
cmos=system.pc.south_bridge.cmos
|
||||
dma1=system.pc.south_bridge.dma1
|
||||
int_lines=system.pc.south_bridge.int_lines0 system.pc.south_bridge.int_lines1 system.pc.south_bridge.int_lines2 system.pc.south_bridge.int_lines3 system.pc.south_bridge.int_lines4 system.pc.south_bridge.int_lines5 system.pc.south_bridge.int_lines6
|
||||
io_apic=system.pc.south_bridge.io_apic
|
||||
keyboard=system.pc.south_bridge.keyboard
|
||||
pic1=system.pc.south_bridge.pic1
|
||||
|
|
@ -855,7 +878,8 @@ speaker=system.pc.south_bridge.speaker
|
|||
|
||||
[system.pc.south_bridge.cmos]
|
||||
type=Cmos
|
||||
int_pin=system.pc.south_bridge.int_lines2.source
|
||||
children=int_pin
|
||||
int_pin=system.pc.south_bridge.cmos.int_pin
|
||||
pio_addr=9223372036854775920
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -863,6 +887,9 @@ system=system
|
|||
time=Sun Jan 1 00:00:00 2012
|
||||
pio=system.iobus.port[1]
|
||||
|
||||
[system.pc.south_bridge.cmos.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.dma1]
|
||||
type=I8237
|
||||
pio_addr=9223372036854775808
|
||||
|
|
@ -945,7 +972,7 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-x86.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.ide.disks1]
|
||||
|
|
@ -965,70 +992,58 @@ table_size=65536
|
|||
|
||||
[system.pc.south_bridge.ide.disks1.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/linux-bigswap2.img
|
||||
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.pc.south_bridge.int_lines0]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines0.sink
|
||||
source=system.pc.south_bridge.int_lines0.source
|
||||
source=system.pc.south_bridge.pic1.output
|
||||
|
||||
[system.pc.south_bridge.int_lines0.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines0.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines1]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines1.sink
|
||||
source=system.pc.south_bridge.int_lines1.source
|
||||
source=system.pc.south_bridge.pic2.output
|
||||
|
||||
[system.pc.south_bridge.int_lines1.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
number=2
|
||||
|
||||
[system.pc.south_bridge.int_lines1.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines2]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines2.sink
|
||||
source=system.pc.south_bridge.int_lines2.source
|
||||
source=system.pc.south_bridge.cmos.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines2.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic2
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines2.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines3]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines3.sink
|
||||
source=system.pc.south_bridge.int_lines3.source
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines3.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.pic1
|
||||
number=0
|
||||
|
||||
[system.pc.south_bridge.int_lines3.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines4]
|
||||
type=X86IntLine
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines4.sink
|
||||
source=system.pc.south_bridge.int_lines3.source
|
||||
source=system.pc.south_bridge.pit.int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines4.sink]
|
||||
type=X86IntSinkPin
|
||||
|
|
@ -1037,32 +1052,26 @@ number=2
|
|||
|
||||
[system.pc.south_bridge.int_lines5]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines5.sink
|
||||
source=system.pc.south_bridge.int_lines5.source
|
||||
source=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines5.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=1
|
||||
|
||||
[system.pc.south_bridge.int_lines5.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.int_lines6]
|
||||
type=X86IntLine
|
||||
children=sink source
|
||||
children=sink
|
||||
sink=system.pc.south_bridge.int_lines6.sink
|
||||
source=system.pc.south_bridge.int_lines6.source
|
||||
source=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
|
||||
[system.pc.south_bridge.int_lines6.sink]
|
||||
type=X86IntSinkPin
|
||||
device=system.pc.south_bridge.io_apic
|
||||
number=12
|
||||
|
||||
[system.pc.south_bridge.int_lines6.source]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.io_apic]
|
||||
type=I82094AA
|
||||
apic_id=1
|
||||
|
|
@ -1077,20 +1086,28 @@ pio=system.iobus.port[9]
|
|||
|
||||
[system.pc.south_bridge.keyboard]
|
||||
type=I8042
|
||||
children=keyboard_int_pin mouse_int_pin
|
||||
command_port=9223372036854775908
|
||||
data_port=9223372036854775904
|
||||
keyboard_int_pin=system.pc.south_bridge.int_lines5.source
|
||||
mouse_int_pin=system.pc.south_bridge.int_lines6.source
|
||||
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
||||
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
||||
pio_addr=0
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[4]
|
||||
|
||||
[system.pc.south_bridge.keyboard.keyboard_int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.keyboard.mouse_int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pic1]
|
||||
type=I8259
|
||||
children=output
|
||||
mode=I8259Master
|
||||
output=system.pc.south_bridge.int_lines0.source
|
||||
output=system.pc.south_bridge.pic1.output
|
||||
pio_addr=9223372036854775840
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -1098,10 +1115,14 @@ slave=system.pc.south_bridge.pic2
|
|||
system=system
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.pc.south_bridge.pic1.output]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pic2]
|
||||
type=I8259
|
||||
children=output
|
||||
mode=I8259Slave
|
||||
output=system.pc.south_bridge.int_lines1.source
|
||||
output=system.pc.south_bridge.pic2.output
|
||||
pio_addr=9223372036854775968
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
|
|
@ -1109,15 +1130,22 @@ slave=Null
|
|||
system=system
|
||||
pio=system.iobus.port[6]
|
||||
|
||||
[system.pc.south_bridge.pic2.output]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.pit]
|
||||
type=I8254
|
||||
int_pin=system.pc.south_bridge.int_lines3.source
|
||||
children=int_pin
|
||||
int_pin=system.pc.south_bridge.pit.int_pin
|
||||
pio_addr=9223372036854775872
|
||||
pio_latency=1000
|
||||
platform=system.pc
|
||||
system=system
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.pc.south_bridge.pit.int_pin]
|
||||
type=X86IntSourcePin
|
||||
|
||||
[system.pc.south_bridge.speaker]
|
||||
type=PcSpeaker
|
||||
i8254=system.pc.south_bridge.pit
|
||||
|
|
@ -1127,13 +1155,6 @@ platform=system.pc
|
|||
system=system
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.pc.terminal]
|
||||
type=Terminal
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=true
|
||||
port=3456
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
|
|
|
|||
|
|
@ -1,17 +1,9 @@
|
|||
warn: Sockets disabled, not accepting terminal connections
|
||||
For more information see: http://www.m5sim.org/warn/8742226b
|
||||
warn: Reading current count from inactive timer.
|
||||
For more information see: http://www.m5sim.org/warn/1ea2be46
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
For more information see: http://www.m5sim.org/warn/7fe1004f
|
||||
warn: instruction 'fxsave' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: Tried to clear PCI interrupt 14
|
||||
For more information see: http://www.m5sim.org/warn/77378d57
|
||||
warn: Unknown mouse command 0xe1.
|
||||
For more information see: http://www.m5sim.org/warn/2447512a
|
||||
warn: instruction 'wbinvd' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,15 +1,12 @@
|
|||
M5 Simulator System
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Apr 19 2011 12:44:38
|
||||
M5 started Apr 19 2011 12:46:29
|
||||
M5 executing on maize
|
||||
command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
|
||||
gem5 compiled Jan 9 2012 20:47:38
|
||||
gem5 started Jan 9 2012 21:05:49
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86_FS/gem5.fast -d build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/quick/10.linux-boot/x86/linux/pc-simple-timing
|
||||
warning: add_child('terminal'): child 'terminal' already has parent
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5195470393000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@
|
|||
sim_seconds 5.195470 # Number of seconds simulated
|
||||
sim_ticks 5195470393000 # Number of ticks simulated
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1914891 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 37635937594 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 372104 # Number of bytes of host memory used
|
||||
host_seconds 138.05 # Real time elapsed on the host
|
||||
sim_insts 264342001 # Number of instructions simulated
|
||||
host_inst_rate 1858401 # Simulator instruction rate (inst/s)
|
||||
host_tick_rate 36414646229 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 372180 # Number of bytes of host memory used
|
||||
host_seconds 142.68 # Real time elapsed on the host
|
||||
sim_insts 265147881 # Number of instructions simulated
|
||||
system.l2c.replacements 136133 # number of replacements
|
||||
system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use
|
||||
system.l2c.total_refs 3363370 # Total number of references to valid blocks.
|
||||
|
|
@ -257,7 +257,7 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
|
|||
system.cpu.numCycles 10390940786 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.num_insts 264342001 # Number of instructions executed
|
||||
system.cpu.num_insts 265147881 # Number of instructions executed
|
||||
system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
||||
|
|
|
|||
Loading…
Reference in a new issue