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m5: merge inorder/release-notes/make_release changes

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This commit is contained in:
Korey Sewell 2011-02-18 14:35:15 -05:00
parent ab9c20cc78 e3d8d43b17
commit 66bb732c04
100 changed files with 15091 additions and 2783 deletions
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2
LICENSE
View file

@ -1,4 +1,4 @@
Copyright (c) 2000-2008 The Regents of The University of Michigan
Copyright (c) 2000-2011 The Regents of The University of Michigan
All rights reserved.
Redistribution and use in source and binary forms, with or without

34
README
View file

@ -1,4 +1,4 @@
This is release 2.0_beta6 of the M5 simulator.
This is the M5 simulator.
For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.
@ -9,13 +9,16 @@ http://www.m5sim.org/wiki/index.php/Running_M5
Short version:
1. If you don't have SCons version 0.96.91 or newer, get it from
1. If you don't have SCons version 0.98.1 or newer, get it from
http://wwww.scons.org.
2. If you don't have SWIG version 1.3.28 or newer, get it from
2. If you don't have SWIG version 1.3.31 or newer, get it from
http://wwww.swig.org.
3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This
3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer
(the dev version with header files), zlib, and the m4 preprocessor.
4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.
@ -25,18 +28,21 @@ WHAT'S INCLUDED (AND NOT)
-------------------------
The basic source release includes these subdirectories:
- m5:
- src: source code of the m5 simulator
- tests: regression tests
- m5:
- configs: simulation configuration scripts
- ext: less-common external packages needed to build m5
- src: source code of the m5 simulator
- system: source for some optional system software for simulated systems
- tests: regression tests
- util: useful utility programs and files
To run full-system simulations, you will need compiled console,
PALcode, and kernel binaries and one or more disk images. These files
are collected in a separate archive, m5_system.tar.bz2. This file
can he downloaded separately.
To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk images.
These files for Alpha are collected in a separate archive, m5_system.tar.bz2.
This file can he downloaded separately.
M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP
Tru64 version of Unix. We are able to distribute Linux and FreeBSD
bootdisks, but we are unable to distribute bootable disk images of
Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the
proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux
and FreeBSD bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-users@m5sim.org

149
RELEASE_NOTES
View file

@ -1,149 +0,0 @@
October 6, 2008: m5_2.0_beta6
--------------------
New Features
1. Support for gcc 4.3
2. Core m5 code in libm5 for integration with other simulators
3. Preliminary support for X86 SE mode
4. Additional system calls emulated
5. m5term updated to work on OS X
6. Ability to disable listen sockets
7. Event queue performance improvements and rewrite
8. Better errors for unconnected memory ports
Bug fixes
1. ALPHA_SE O3 perlbmk benchmark
2. Translation bug where O3 could fetch from uncachable memory
3. Many minor bugs
Outstanding issues for 2.0 release:
--------------------
1. Statistics cleanup
2. Improve regression system
3. Testing
4. Validation
March 1, 2008: m5_2.0_beta5
--------------------
New Features
1. Rick Strong's Simpoints config changes
2. Support for FSU ARM port
3. EXTRAS= option allow architectures to be specified
Bug fixes
1. Bus timing more realistic
2. Cache writeback, LL/SC fixes
3. Minor IGbE NIC fixes
4. O3 op latency fix
5. SPARC TLB demap fixes
6. SPARC SE memory layout fixes
7. Variety of MIPS fixes
Nov 4, 2007: m5_2.0_beta4
--------------------
New Features
1. New cache model
2. Use of a I/O cache between devices and memory
3. Ability to include compiled code with EXTRAS=
4. Python creation of params structures for initialization
5. Ability to remotely debug in SE
Bug fixes:
1. Fix SE serialization
2. SPARC_FS booting with TimingSimpleCPU
3. Rename cycles() to ticks()
4. Various SPARC ISA fixes
5. Draining code for checkpointing
6. Various performance improvements
Possible Incompatibilities:
1. Real TLBs are now used in SE mode. This is more accurate however it could
cause some problems if you've modified the way page handling is done in
SE mode.
2. There have been many changes to the way the SCons files work. SimObjects,
sources files, and trace flags are all specified in the SConscript files.
To see how to add your sources take a look at one of them.
3. Python is now used to created the parameter structs that were created
manually before. The parameters listed in a py file are turned into
a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
With this change the structs can be populated automatically and the
ugly macros to define and create SimObjects at the bottem of source
files are gone. The parameter structs also automatically inherit
parameters from their parents.
May 16, 2007: m5_2.0_beta3
--------------------
New Features
1. Some support for SPARC full-system simulation
2. Reworking of trace facitities (parameter names changed, variadic macros
removed)
3. Scons script cleanups
4. Some support for compiling with Intel CC
Bug fixes since beta 2:
1. Many SPARC linux syscall emulation support fixes
2. Multiprocessor linux boot using the detailed O3 CPU module
3. Workaround for DMA bug (final solution to be released with 2.0f)
4. Simulator performance and memory leak fixes
5. Fixed issue where console could stop printing in ALPHA_FS
6. Fix issues with remote debugging
7. Several compile fixes, including gcc 4.1
8. Many other minor fixes and enhancements
Nov. 28, 2006: m5_2.0_beta2
--------------------
Bug fixes since beta 1:
1. Many cache issues resolved
2. Uni-coherence fixes in full-system
3. LL/SC Support
4. Draining/Switchover
5. Functional Accesses
6. Bus now has real timing
7. Single config file for all SpecCPU2000 benchmarks
8. Several other minor bug fixes and enhancements
Aug. 25, 2006: m5_2.0_beta patch 1
--------------------
Handful of minor bug fixes for m5_2.0_beta,
along with a few new regression tests.
Aug. 15, 2006: m5_2.0_beta
--------------------
Major update to M5 including:
- New CPU model
- New memory system
- More extensive python integration
- Preliminary syscall emulation support for MIPS and SPARC
This is a *beta* release, meaning that some features are not complete,
and some features from M5 1.X aren't currently supported (e.g., MP
coherence). We are working to address these limitations and hope to
have a complete 2.0 release soon.
Oct. 8, 2005: m5_1.1
--------------------
Update release for IOSCA workshop mini-tutorial. New features include:
- Preliminary FreeBSD support
- Integration of regression tests into scons build framework
- Several bug fixes and better compatibility for Cygwin hosts
- Major cleanup of Alpha system code (console, PAL, etc.) to make
it easier for others to build/modify
- Fixes to enable compilation under g++ 4.0
- Numerous minor bug fixes
June 10, 2005: m5_1.0_web
-------------------------
The 1.0 release posted on Sourceforge after the ISCA tutorial contains
just a few very minor fixes relative to the CD.
June 5, 2005: m5_1.0_tutorial
-----------------------------
First non-beta release. This release was on the CD distributed at the
ISCA tutorial. Major enhancements relative to beta releases include
Linux support and Python-based configuration language.
June 17, 2004: m5_1.0_beta2
---------------------------
Stealth-mode beta bug-fix update, not widely advertised.
Oct. 17, 2003: m5_1.0_beta1
---------------------------
Early beta release.

2
src/SConscript
View file

@ -446,7 +446,7 @@ def makeInfoPyFile(target, source, env):
# Generate a file that wraps the basic top level files
env.Command('python/m5/info.py',
[ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
[ '#/AUTHORS', '#/LICENSE', '#/README', ],
MakeAction(makeInfoPyFile, Transform("INFO")))
PySource('m5', 'python/m5/info.py')

111
src/arch/generic/debugfaults.hh Normal file
View file

@ -0,0 +1,111 @@
/*
* Copyright (c) 2010 Advanced Micro Devices
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__
#define __ARCH_GENERIC_DEBUGFAULTS_HH__
#include "base/misc.hh"
#include "sim/faults.hh"
#include <string>
namespace GenericISA
{
class M5DebugFault : public FaultBase
{
public:
enum DebugFunc
{
PanicFunc,
FatalFunc,
WarnFunc,
WarnOnceFunc
};
protected:
std::string message;
DebugFunc func;
public:
M5DebugFault(DebugFunc _func, std::string _message) :
message(_message), func(_func)
{}
FaultName
name() const
{
switch (func) {
case PanicFunc:
return "panic fault";
case FatalFunc:
return "fatal fault";
case WarnFunc:
return "warn fault";
case WarnOnceFunc:
return "warn_once fault";
default:
panic("unrecognized debug function number\n");
}
}
void
invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
switch (func) {
case PanicFunc:
panic(message);
break;
case FatalFunc:
fatal(message);
break;
case WarnFunc:
warn(message);
break;
case WarnOnceFunc:
warn_once(message);
break;
default:
panic("unrecognized debug function number\n");
}
}
};
} // namespace GenericISA
#endif // __ARCH_GENERIC_DEBUGFAULTS_HH__

1
src/arch/x86/SConscript
View file

@ -46,6 +46,7 @@ if env['TARGET_ISA'] == 'x86':
Source('cpuid.cc')
Source('emulenv.cc')
Source('faults.cc')
Source('insts/badmicroop.cc')
Source('insts/microfpop.cc')
Source('insts/microldstop.cc')
Source('insts/micromediaop.cc')

55
src/arch/x86/insts/badmicroop.cc Normal file
View file

@ -0,0 +1,55 @@
/*
* Copyright (c) 2011 Advanced Micro Devices
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/insts/badmicroop.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/decoder.hh"
namespace X86ISA
{
// This microop needs to be allocated on the heap even though it could
// theoretically be statically allocated. The reference counted pointer would
// try to delete the static memory when it was destructed.
const StaticInstPtr badMicroop =
new X86ISAInst::MicroPanic(NoopMachInst, "BAD",
StaticInst::IsMicroop | StaticInst::IsLastMicroop,
"Invalid microop!", 0);
} // namespace X86ISA

52
src/arch/x86/insts/badmicroop.hh Normal file
View file

@ -0,0 +1,52 @@
/*
* Copyright (c) 2011 Advanced Micro Devices
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_BADMICROOP_HH__
#define __ARCH_X86_INSTS_BADMICROOP_HH__
class StaticInstPtr;
namespace X86ISA
{
extern const StaticInstPtr badMicroop;
} // namespace X86ISA
#endif //__ARCH_X86_INSTS_BADMICROOP_HH__

7
src/arch/x86/insts/macroop.hh
View file

@ -41,6 +41,7 @@
#define __ARCH_X86_INSTS_MACROOP_HH__
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/badmicroop.hh"
#include "arch/x86/types.hh"
#include "arch/x86/insts/static_inst.hh"
@ -76,8 +77,10 @@ class MacroopBase : public X86StaticInst
StaticInstPtr
fetchMicroop(MicroPC microPC) const
{
assert(microPC < numMicroops);
return microops[microPC];
if (microPC >= numMicroops)
return badMicroop;
else
return microops[microPC];
}
std::string

3
src/arch/x86/insts/microregop.cc
View file

@ -50,9 +50,6 @@ namespace X86ISA
bool subtract) const
{
DPRINTF(X86, "flagMask = %#x\n", flagMask);
if (_destRegIdx[0] & IntFoldBit) {
_dest >>= 8;
}
uint64_t flags = oldFlags & ~flagMask;
if(flagMask & (ECFBit | CFBit))
{

2
src/arch/x86/isa/includes.isa
View file

@ -53,6 +53,7 @@ output header {{
#include <sstream>
#include <iostream>
#include "arch/generic/debugfaults.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/macroop.hh"
#include "arch/x86/insts/microfpop.hh"
@ -113,6 +114,7 @@ output exec {{
#include "arch/x86/regs/misc.hh"
#include "arch/x86/tlb.hh"
#include "base/bigint.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"

69
src/arch/x86/isa/microops/debug.isa
View file

@ -45,16 +45,29 @@ output header {{
class MicroDebugBase : public X86ISA::X86MicroopBase
{
protected:
typedef GenericISA::M5DebugFault::DebugFunc DebugFunc;
DebugFunc func;
std::string message;
uint8_t cc;
public:
MicroDebugBase(ExtMachInst _machInst, const char * mnem,
MicroDebugBase(ExtMachInst machInst, const char * mnem,
const char * instMnem, uint64_t setFlags,
std::string _message, uint8_t _cc);
DebugFunc _func, std::string _message, uint8_t _cc) :
X86MicroopBase(machInst, mnem, instMnem, setFlags, No_OpClass),
func(_func), message(_message), cc(_cc)
{}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
response << "\"" << message << "\"";
return response.str();
}
};
}};
@ -70,53 +83,31 @@ def template MicroDebugDeclare {{
}};
def template MicroDebugExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Fault
%(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
%(op_decl)s
%(op_rd)s
if (%(cond_test)s) {
%(func)s("%s\n", message);
return new GenericISA::M5DebugFault(func, message);
} else {
return NoFault;
}
return NoFault;
}
}};
output decoder {{
inline MicroDebugBase::MicroDebugBase(
ExtMachInst machInst, const char * mnem, const char * instMnem,
uint64_t setFlags, std::string _message, uint8_t _cc) :
X86MicroopBase(machInst, mnem, instMnem,
setFlags, No_OpClass),
message(_message), cc(_cc)
{
}
}};
def template MicroDebugConstructor {{
inline %(class_name)s::%(class_name)s(
%(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
std::string _message, uint8_t _cc) :
%(base_class)s(machInst, "%(func)s", instMnem,
setFlags, _message, _cc)
setFlags, %(func_num)s, _message, _cc)
{
%(constructor)s;
}
}};
output decoder {{
std::string MicroDebugBase::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
response << "\"" << message << "\"";
return response.str();
}
}};
let {{
class MicroDebug(X86Microop):
def __init__(self, message, flags=None):
@ -142,13 +133,14 @@ let {{
header_output = ""
decoder_output = ""
def buildDebugMicro(func):
def buildDebugMicro(func, func_num):
global exec_output, header_output, decoder_output
iop = InstObjParams(func, "Micro%sFlags" % func.capitalize(),
"MicroDebugBase",
{"code": "",
"func": func,
"func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "checkCondition(ccFlagBits, cc)"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
@ -158,6 +150,7 @@ let {{
"MicroDebugBase",
{"code": "",
"func": func,
"func_num": "GenericISA::M5DebugFault::%s" % func_num,
"cond_test": "true"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
@ -169,8 +162,8 @@ let {{
global microopClasses
microopClasses[func] = MicroDebugChild
buildDebugMicro("panic")
buildDebugMicro("fatal")
buildDebugMicro("warn")
buildDebugMicro("warn_once")
buildDebugMicro("panic", "PanicFunc")
buildDebugMicro("fatal", "FatalFunc")
buildDebugMicro("warn", "WarnFunc")
buildDebugMicro("warn_once", "WarnOnceFunc")
}};

78
src/arch/x86/isa/microops/ldstop.isa
View file

@ -301,6 +301,46 @@ let {{
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
"memFlags" : self.memFlags}
return allocator
class BigLdStOp(X86Microop):
def __init__(self, data, segment, addr, disp,
dataSize, addressSize, baseFlags, atCPL0, prefetch):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
self.segment = segment
self.dataSize = dataSize
self.addressSize = addressSize
self.memFlags = baseFlags
if atCPL0:
self.memFlags += " | (CPL0FlagBit << FlagShift)"
if prefetch:
self.memFlags += " | Request::PREFETCH"
self.memFlags += " | (machInst.legacy.addr ? " + \
"(AddrSizeFlagBit << FlagShift) : 0)"
def getAllocator(self, microFlags):
allocString = '''
(%(dataSize)s >= 4) ?
(StaticInstPtr)(new %(class_name)sBig(machInst,
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
%(base)s, %(disp)s, %(segment)s, %(data)s,
%(dataSize)s, %(addressSize)s, %(memFlags)s)) :
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
%(base)s, %(disp)s, %(segment)s, %(data)s,
%(dataSize)s, %(addressSize)s, %(memFlags)s))
'''
allocator = allocString % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),
"scale" : self.scale, "index" : self.index,
"base" : self.base,
"disp" : self.disp,
"segment" : self.segment, "data" : self.data,
"dataSize" : self.dataSize, "addressSize" : self.addressSize,
"memFlags" : self.memFlags}
return allocator
}};
let {{
@ -315,7 +355,8 @@ let {{
EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0);
'''
def defineMicroLoadOp(mnemonic, code, mem_flags="0"):
def defineMicroLoadOp(mnemonic, code, bigCode='',
mem_flags="0", big=True):
global header_output
global decoder_output
global exec_output
@ -324,16 +365,22 @@ let {{
name = mnemonic.lower()
# Build up the all register version of this micro op
iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
{"code": code,
"ea_code": calculateEA})
header_output += MicroLdStOpDeclare.subst(iop)
decoder_output += MicroLdStOpConstructor.subst(iop)
exec_output += MicroLoadExecute.subst(iop)
exec_output += MicroLoadInitiateAcc.subst(iop)
exec_output += MicroLoadCompleteAcc.subst(iop)
iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
{"code": code, "ea_code": calculateEA})]
if big:
iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
{"code": bigCode, "ea_code": calculateEA})]
for iop in iops:
header_output += MicroLdStOpDeclare.subst(iop)
decoder_output += MicroLdStOpConstructor.subst(iop)
exec_output += MicroLoadExecute.subst(iop)
exec_output += MicroLoadInitiateAcc.subst(iop)
exec_output += MicroLoadCompleteAcc.subst(iop)
class LoadOp(LdStOp):
base = LdStOp
if big:
base = BigLdStOp
class LoadOp(base):
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize",
addressSize="env.addressSize",
@ -346,12 +393,15 @@ let {{
microopClasses[name] = LoadOp
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
'Data = Mem & mask(dataSize * 8);')
defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
'(StoreCheck << FlagShift)')
'Data = Mem & mask(dataSize * 8);',
'(StoreCheck << FlagShift)')
defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
'(StoreCheck << FlagShift) | Request::LOCKED')
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
'Data = Mem & mask(dataSize * 8);',
'(StoreCheck << FlagShift) | Request::LOCKED')
defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False)
def defineMicroStoreOp(mnemonic, code, \
postCode="", completeCode="", mem_flags="0"):

27
src/arch/x86/isa/microops/limmop.isa
View file

@ -114,8 +114,16 @@ let {{
self.dataSize = dataSize
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % {
allocString = '''
(%(dataSize)s >= 4) ?
(StaticInstPtr)(new %(class_name)sBig(machInst,
macrocodeBlock, %(flags)s, %(dest)s, %(imm)s,
%(dataSize)s)) :
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s, %(dest)s, %(imm)s,
%(dataSize)s))
'''
allocator = allocString % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
"flags" : self.microFlagsText(microFlags),
@ -152,12 +160,15 @@ let {{
let {{
# Build up the all register version of this micro op
iop = InstObjParams("limm", "Limm", 'X86MicroopBase',
{"code" : "DestReg = merge(DestReg, imm, dataSize);"})
header_output += MicroLimmOpDeclare.subst(iop)
decoder_output += MicroLimmOpConstructor.subst(iop)
decoder_output += MicroLimmOpDisassembly.subst(iop)
exec_output += MicroLimmOpExecute.subst(iop)
iops = [InstObjParams("limm", "Limm", 'X86MicroopBase',
{"code" : "DestReg = merge(DestReg, imm, dataSize);"}),
InstObjParams("limm", "LimmBig", 'X86MicroopBase',
{"code" : "DestReg = imm & mask(dataSize * 8);"})]
for iop in iops:
header_output += MicroLimmOpDeclare.subst(iop)
decoder_output += MicroLimmOpConstructor.subst(iop)
decoder_output += MicroLimmOpDisassembly.subst(iop)
exec_output += MicroLimmOpExecute.subst(iop)
iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase',
{"code" : "FpDestReg.uqw = imm"})

293
src/arch/x86/isa/microops/regop.isa
View file

@ -51,6 +51,8 @@ def template MicroRegOpExecute {{
%(op_decl)s;
%(op_rd)s;
IntReg result M5_VAR_USED;
if(%(cond_check)s)
{
%(code)s;
@ -79,6 +81,8 @@ def template MicroRegOpImmExecute {{
%(op_decl)s;
%(op_rd)s;
IntReg result M5_VAR_USED;
if(%(cond_check)s)
{
%(code)s;
@ -224,8 +228,8 @@ let {{
MicroRegOpExecute)
class RegOpMeta(type):
def buildCppClasses(self, name, Name, suffix, \
code, flag_code, cond_check, else_code, cond_control_flag_init):
def buildCppClasses(self, name, Name, suffix, code, big_code, \
flag_code, cond_check, else_code, cond_control_flag_init):
# Globals to stick the output in
global header_output
@ -235,11 +239,13 @@ let {{
# Stick all the code together so it can be searched at once
allCode = "|".join((code, flag_code, cond_check, else_code,
cond_control_flag_init))
allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
cond_control_flag_init))
# If op2 is used anywhere, make register and immediate versions
# of this code.
matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
match = matcher.search(allCode)
match = matcher.search(allCode + allBigCode)
if match:
typeQual = ""
if match.group("typeQual"):
@ -247,6 +253,7 @@ let {{
src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
self.buildCppClasses(name, Name, suffix,
matcher.sub(src2_name, code),
matcher.sub(src2_name, big_code),
matcher.sub(src2_name, flag_code),
matcher.sub(src2_name, cond_check),
matcher.sub(src2_name, else_code),
@ -254,6 +261,7 @@ let {{
imm_name = "%simm8" % match.group("prefix")
self.buildCppClasses(name + "i", Name, suffix + "Imm",
matcher.sub(imm_name, code),
matcher.sub(imm_name, big_code),
matcher.sub(imm_name, flag_code),
matcher.sub(imm_name, cond_check),
matcher.sub(imm_name, else_code),
@ -264,27 +272,32 @@ let {{
# a version without it and fix up this version to use it.
if flag_code != "" or cond_check != "true":
self.buildCppClasses(name, Name, suffix,
code, "", "true", else_code, "")
code, big_code, "", "true", else_code, "")
suffix = "Flags" + suffix
# If psrc1 or psrc2 is used, we need to actually insert code to
# compute it.
matcher = re.compile("(?<!\w)psrc1(?!\w)")
if matcher.search(allCode):
code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
matcher = re.compile("(?<!\w)psrc2(?!\w)")
if matcher.search(allCode):
code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
# Also make available versions which do sign extension
matcher = re.compile("(?<!\w)spsrc1(?!\w)")
if matcher.search(allCode):
code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
matcher = re.compile("(?<!\w)spsrc2(?!\w)")
if matcher.search(allCode):
code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
matcher = re.compile("(?<!\w)simm8(?!\w)")
if matcher.search(allCode):
code = "int8_t simm8 = imm8;" + code
for (big, all) in ((False, allCode), (True, allBigCode)):
prefix = ""
for (rex, decl) in (
("(?<!\w)psrc1(?!\w)",
"uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
("(?<!\w)psrc2(?!\w)",
"uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
("(?<!\w)spsrc1(?!\w)",
"int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
("(?<!\w)spsrc2(?!\w)",
"int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
("(?<!\w)simm8(?!\w)",
"int8_t simm8 = imm8;")):
matcher = re.compile(rex)
if matcher.search(all):
prefix += decl + "\n"
if big:
if big_code != "":
big_code = prefix + big_code
else:
code = prefix + code
base = "X86ISA::RegOp"
@ -297,17 +310,26 @@ let {{
templates = immTemplates
# Get everything ready for the substitution
iop = InstObjParams(name, Name + suffix, base,
iops = [InstObjParams(name, Name + suffix, base,
{"code" : code,
"flag_code" : flag_code,
"cond_check" : cond_check,
"else_code" : else_code,
"cond_control_flag_init": cond_control_flag_init})
"cond_control_flag_init" : cond_control_flag_init})]
if big_code != "":
iops += [InstObjParams(name, Name + suffix + "Big", base,
{"code" : big_code,
"flag_code" : flag_code,
"cond_check" : cond_check,
"else_code" : else_code,
"cond_control_flag_init" :
cond_control_flag_init})]
# Generate the actual code (finally!)
header_output += templates[0].subst(iop)
decoder_output += templates[1].subst(iop)
exec_output += templates[2].subst(iop)
for iop in iops:
header_output += templates[0].subst(iop)
decoder_output += templates[1].subst(iop)
exec_output += templates[2].subst(iop)
def __new__(mcls, Name, bases, dict):
@ -322,14 +344,16 @@ let {{
cls.className = Name
cls.base_mnemonic = name
code = cls.code
big_code = cls.big_code
flag_code = cls.flag_code
cond_check = cls.cond_check
else_code = cls.else_code
cond_control_flag_init = cls.cond_control_flag_init
# Set up the C++ classes
mcls.buildCppClasses(cls, name, Name, "", code, flag_code,
cond_check, else_code, cond_control_flag_init)
mcls.buildCppClasses(cls, name, Name, "", code, big_code,
flag_code, cond_check, else_code,
cond_control_flag_init)
# Hook into the microassembler dict
global microopClasses
@ -352,6 +376,7 @@ let {{
abstract = True
# Default template parameter values
big_code = ""
flag_code = ""
cond_check = "true"
else_code = ";"
@ -372,26 +397,48 @@ let {{
self.className += "Flags"
def getAllocator(self, microFlags):
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(op2)s, %(dest)s,
%(dataSize)s, %(ext)s)''' % {
"class_name" : className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "op2" : self.op2,
"dest" : self.dest,
"dataSize" : self.dataSize,
"ext" : self.ext}
return allocator
if self.big_code != "":
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
allocString = '''
(%(dataSize)s >= 4) ?
(StaticInstPtr)(new %(class_name)sBig(machInst,
macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
%(dest)s, %(dataSize)s, %(ext)s)) :
(StaticInstPtr)(new %(class_name)s(machInst,
macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
%(dest)s, %(dataSize)s, %(ext)s))
'''
allocator = allocString % {
"class_name" : className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "op2" : self.op2,
"dest" : self.dest,
"dataSize" : self.dataSize,
"ext" : self.ext}
return allocator
else:
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(op2)s, %(dest)s,
%(dataSize)s, %(ext)s)''' % {
"class_name" : className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "op2" : self.op2,
"dest" : self.dest,
"dataSize" : self.dataSize,
"ext" : self.ext}
return allocator
class LogicRegOp(RegOp):
abstract = True
flag_code = '''
//Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit;
ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
//If a logic microop wants to set these, it wants to set them to 0.
ccFlagBits &= ~(CFBit & ext);
ccFlagBits &= ~(ECFBit & ext);
@ -401,12 +448,12 @@ let {{
class FlagRegOp(RegOp):
abstract = True
flag_code = \
"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
"ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
class SubRegOp(RegOp):
abstract = True
flag_code = \
"ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
"ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
class CondRegOp(RegOp):
abstract = True
@ -428,31 +475,44 @@ let {{
src1, src2, flags, dataSize)
class Add(FlagRegOp):
code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
class Or(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
class Adc(FlagRegOp):
code = '''
CCFlagBits flags = ccFlagBits;
DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
'''
big_code = '''
CCFlagBits flags = ccFlagBits;
DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
'''
class Sbb(SubRegOp):
code = '''
CCFlagBits flags = ccFlagBits;
DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
'''
big_code = '''
CCFlagBits flags = ccFlagBits;
DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
'''
class And(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
class Sub(SubRegOp):
code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
class Xor(LogicRegOp):
code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
class Mul1s(WrRegOp):
code = '''
@ -505,6 +565,7 @@ let {{
class Mulel(RdRegOp):
code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
class Muleh(RdRegOp):
def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
@ -513,6 +574,7 @@ let {{
super(RdRegOp, self).__init__(dest, src1, \
"InstRegIndex(NUM_INTREGS)", flags, dataSize)
code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
# One or two bit divide
class Div1(WrRegOp):
@ -540,7 +602,7 @@ let {{
# Step divide
class Div2(RegOp):
code = '''
divCode = '''
uint64_t dividend = Remainder;
uint64_t divisor = Divisor;
uint64_t quotient = Quotient;
@ -587,11 +649,13 @@ let {{
}
}
//Keep track of how many bits there are still to pull in.
DestReg = merge(DestReg, remaining, dataSize);
%s
//Record the final results
Remainder = remainder;
Quotient = quotient;
'''
code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
flag_code = '''
if (remaining == 0)
ccFlagBits = ccFlagBits | (ext & EZFBit);
@ -601,9 +665,11 @@ let {{
class Divq(RdRegOp):
code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
big_code = 'DestReg = Quotient & mask(dataSize * 8);'
class Divr(RdRegOp):
code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
big_code = 'DestReg = Remainder & mask(dataSize * 8);'
class Mov(CondRegOp):
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
@ -616,6 +682,10 @@ let {{
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@ -641,14 +711,19 @@ let {{
'''
class Srl(RegOp):
# Because what happens to the bits shift -in- on a right shift
# is not defined in the C/C++ standard, we have to mask them out
# to be sure they're zero.
code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to mask them out
// to be sure they're zero.
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
DestReg = (psrc1 >> shiftAmt) & logicalMask;
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@ -671,15 +746,21 @@ let {{
'''
class Sra(RegOp):
# Because what happens to the bits shift -in- on a right shift
# is not defined in the C/C++ standard, we have to sign extend
# them manually to be sure.
code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to sign extend
// them manually to be sure.
uint64_t arithMask = (shiftAmt == 0) ? 0 :
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t arithMask = (shiftAmt == 0) ? 0 :
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@ -704,13 +785,11 @@ let {{
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
if(realShiftAmt)
{
if (realShiftAmt) {
uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
DestReg = merge(DestReg, top | bottom, dataSize);
}
else
} else
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
@ -739,16 +818,14 @@ let {{
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
if(realShiftAmt)
{
if (realShiftAmt) {
CCFlagBits flags = ccFlagBits;
uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
if (realShiftAmt > 1)
top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
DestReg = merge(DestReg, top | bottom, dataSize);
}
else
} else
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
@ -780,14 +857,12 @@ let {{
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
if(realShiftAmt)
{
if (realShiftAmt) {
uint64_t top = psrc1 << realShiftAmt;
uint64_t bottom =
bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
DestReg = merge(DestReg, top | bottom, dataSize);
}
else
} else
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
@ -816,8 +891,7 @@ let {{
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
if(realShiftAmt)
{
if (realShiftAmt) {
CCFlagBits flags = ccFlagBits;
uint64_t top = psrc1 << realShiftAmt;
uint64_t bottom = flags.cf << (realShiftAmt - 1);
@ -826,8 +900,7 @@ let {{
bits(psrc1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
DestReg = merge(DestReg, top | bottom, dataSize);
}
else
} else
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
@ -853,10 +926,10 @@ let {{
'''
class Sld(RegOp):
code = '''
sldCode = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t dataBits = dataSize * 8;
uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
uint64_t result;
if (realShiftAmt == 0) {
result = psrc1;
@ -867,8 +940,10 @@ let {{
result = (DoubleBits << (realShiftAmt - dataBits)) |
(psrc1 >> (2 * dataBits - realShiftAmt));
}
DestReg = merge(DestReg, result, dataSize);
%s
'''
code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@ -899,10 +974,10 @@ let {{
'''
class Srd(RegOp):
code = '''
srdCode = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint8_t dataBits = dataSize * 8;
uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
uint64_t result;
if (realShiftAmt == 0) {
result = psrc1;
@ -919,8 +994,10 @@ let {{
logicalMask) |
(psrc1 << (2 * dataBits - realShiftAmt));
}
DestReg = merge(DestReg, result, dataSize);
%s
'''
code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@ -986,6 +1063,12 @@ let {{
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
(ccFlagBits & ~EZFBit);
'''
big_code = '''
int flag = bits(ccFlagBits, imm8);
DestReg = flag & mask(dataSize * 8);
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
(ccFlagBits & ~EZFBit);
'''
def __init__(self, dest, imm, flags=None, \
dataSize="env.dataSize"):
super(Ruflag, self).__init__(dest, \
@ -1000,6 +1083,14 @@ let {{
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
(ccFlagBits & ~EZFBit);
'''
big_code = '''
MiscReg flagMask = 0x3F7FDD5;
MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
int flag = bits(flags, imm8);
DestReg = flag & mask(dataSize * 8);
ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
(ccFlagBits & ~EZFBit);
'''
def __init__(self, dest, imm, flags=None, \
dataSize="env.dataSize"):
super(Rflag, self).__init__(dest, \
@ -1015,6 +1106,15 @@ let {{
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
DestReg = merge(DestReg, val, dataSize);
'''
big_code = '''
IntReg val = psrc1;
// Mask the bit position so that it wraps.
int bitPos = op2 & (dataSize * 8 - 1);
int sign_bit = bits(val, bitPos, bitPos);
uint64_t maskVal = mask(bitPos+1);
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
DestReg = val & mask(dataSize * 8);
'''
flag_code = '''
if (!sign_bit)
ccFlagBits = ccFlagBits &
@ -1026,12 +1126,13 @@ let {{
class Zext(RegOp):
code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
class Rddr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rddr, self).__init__(dest, \
src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
code = '''
rdrCode = '''
CR4 cr4 = CR4Op;
DR7 dr7 = DR7Op;
if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
@ -1039,9 +1140,11 @@ let {{
} else if (dr7.gd) {
fault = new DebugException();
} else {
DestReg = merge(DestReg, DebugSrc1, dataSize);
%s
}
'''
code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
class Wrdr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
@ -1066,13 +1169,15 @@ let {{
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
super(Rdcr, self).__init__(dest, \
src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
code = '''
rdcrCode = '''
if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
fault = new InvalidOpcode();
} else {
DestReg = merge(DestReg, ControlSrc1, dataSize);
%s
}
'''
code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
class Wrcr(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
@ -1154,24 +1259,20 @@ let {{
'''
class Rdbase(SegOp):
code = '''
DestReg = merge(DestReg, SegBaseSrc1, dataSize);
'''
code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
class Rdlimit(SegOp):
code = '''
DestReg = merge(DestReg, SegLimitSrc1, dataSize);
'''
code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
class RdAttr(SegOp):
code = '''
DestReg = merge(DestReg, SegAttrSrc1, dataSize);
'''
code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
class Rdsel(SegOp):
code = '''
DestReg = merge(DestReg, SegSelSrc1, dataSize);
'''
code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
class Rdval(RegOp):
def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):

7
src/arch/x86/microcode_rom.hh
View file

@ -32,6 +32,7 @@
#define __ARCH_X86_MICROCODE_ROM_HH__
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/badmicroop.hh"
#include "cpu/static_inst.hh"
namespace X86ISAInst
@ -60,8 +61,10 @@ namespace X86ISAInst
fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop)
{
microPC = normalMicroPC(microPC);
assert(microPC < numMicroops);
return genFuncs[microPC](curMacroop);
if (microPC >= numMicroops)
return X86ISA::badMicroop;
else
return genFuncs[microPC](curMacroop);
}
};
}

6
src/arch/x86/predecoder.hh
View file

@ -225,7 +225,11 @@ namespace X86ISA
{
assert(emiIsReady);
emiIsReady = false;
nextPC.npc(nextPC.pc() + getInstSize());
if (!nextPC.size()) {
Addr size = getInstSize();
nextPC.size(size);
nextPC.npc(nextPC.pc() + size);
}
return emi;
}
};

56
src/arch/x86/types.hh
View file

@ -222,7 +222,61 @@ namespace X86ISA
return true;
}
typedef GenericISA::UPCState<MachInst> PCState;
class PCState : public GenericISA::UPCState<MachInst>
{
protected:
typedef GenericISA::UPCState<MachInst> Base;
uint8_t _size;
public:
void
set(Addr val)
{
Base::set(val);
_size = 0;
}
PCState() {}
PCState(Addr val) { set(val); }
uint8_t size() const { return _size; }
void size(uint8_t newSize) { _size = newSize; }
bool
branching() const
{
return this->npc() != this->pc() + size();
}
void
advance()
{
Base::advance();
_size = 0;
}
void
uEnd()
{
Base::uEnd();
_size = 0;
}
void
serialize(std::ostream &os)
{
Base::serialize(os);
SERIALIZE_SCALAR(_size);
}
void
unserialize(Checkpoint *cp, const std::string &section)
{
Base::unserialize(cp, section);
UNSERIALIZE_SCALAR(_size);
}
};
struct CoreSpecific {
int core_type;

17
src/cpu/o3/fetch_impl.hh
View file

@ -1070,6 +1070,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
Addr pcOffset = fetchOffset[tid];
Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
bool inRom = isRomMicroPC(thisPC.microPC());
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
// to tick() function.
@ -1083,7 +1085,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
Addr block_PC = icacheBlockAlignPC(fetchAddr);
// Unless buffer already got the block, fetch it from icache.
if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) {
if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
"instruction, starting at PC %s.\n", tid, thisPC);
@ -1155,7 +1157,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
!predictedBranch) {
// If we need to process more memory, do it now.
if (!curMacroop && !predecoder.extMachInstReady()) {
if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
// Walk past any annulled delay slot instructions.
Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
@ -1181,7 +1183,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Extract as many instructions and/or microops as we can from
// the memory we've processed so far.
do {
if (!curMacroop) {
if (!(curMacroop || inRom)) {
if (predecoder.extMachInstReady()) {
ExtMachInst extMachInst;
@ -1202,8 +1204,13 @@ DefaultFetch<Impl>::fetch(bool &status_change)
break;
}
}
if (curMacroop) {
staticInst = curMacroop->fetchMicroop(thisPC.microPC());
if (curMacroop || inRom) {
if (inRom) {
staticInst = cpu->microcodeRom.fetchMicroop(
thisPC.microPC(), curMacroop);
} else {
staticInst = curMacroop->fetchMicroop(thisPC.microPC());
}
if (staticInst->isLastMicroop()) {
curMacroop = NULL;
pcOffset = 0;

2
src/cpu/o3/inst_queue_impl.hh
View file

@ -749,7 +749,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
DynInstPtr deferred_mem_inst;
int total_deferred_mem_issued = 0;
while (total_deferred_mem_issued < totalWidth &&
(deferred_mem_inst = getDeferredMemInstToExecute()) != NULL) {
(deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
issueToExecuteQueue->access(0)->size++;
instsToExecute.push_back(deferred_mem_inst);
total_deferred_mem_issued++;

35
src/mem/protocol/MESI_CMP_directory-L1cache.sm
View file

@ -287,20 +287,21 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
if (in_msg.Type == CacheRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
}
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The tag matches for the L1, so the L1 asks the L2 for it.
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
} else {
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
}
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
@ -313,21 +314,23 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
}
}
} else {
// *** DATA ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
}
// *** DATA ACCESS ***
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 ask the L2 for it
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
} else {
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
}
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,

32
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View file

@ -338,14 +338,6 @@ machine(L1Cache, "Directory protocol")
if (in_msg.Type == CacheRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
// Check to see if it is in the OTHER L1
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry,
TBEs[in_msg.LineAddress]);
}
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The tag matches for the L1, so the L1 asks the L2 for it.
@ -353,6 +345,14 @@ machine(L1Cache, "Directory protocol")
in_msg.LineAddress, L1Icache_entry,
TBEs[in_msg.LineAddress]);
} else {
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
// Check to see if it is in the OTHER L1
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry,
TBEs[in_msg.LineAddress]);
}
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type),
@ -369,14 +369,6 @@ machine(L1Cache, "Directory protocol")
} else {
// *** DATA ACCESS ***
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
// Check to see if it is in the OTHER L1
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, TBEs[in_msg.LineAddress]);
}
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 ask the L2 for it
@ -384,6 +376,14 @@ machine(L1Cache, "Directory protocol")
in_msg.LineAddress, L1Dcache_entry,
TBEs[in_msg.LineAddress]);
} else {
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
// Check to see if it is in the OTHER L1
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, put the request on the queue to the shared L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, TBEs[in_msg.LineAddress]);
}
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
trigger(mandatory_request_type_to_event(in_msg.Type),

35
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -647,20 +647,21 @@ machine(L1Cache, "Token protocol")
if (in_msg.Type == CacheRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, try to write it to the L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Dcache_entry, tbe);
}
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Icache_entry, tbe);
} else {
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, try to write it to the L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Dcache_entry, tbe);
}
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
trigger(mandatory_request_type_to_event(in_msg.Type),
@ -676,21 +677,21 @@ machine(L1Cache, "Token protocol")
} else {
// *** DATA ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, try to write it to the L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, tbe);
}
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, try to write it to the L2
trigger(Event:L1_Replacement, in_msg.LineAddress,
L1Icache_entry, tbe);
}
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
trigger(mandatory_request_type_to_event(in_msg.Type),

57
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -377,26 +377,26 @@ machine(L1Cache, "AMD Hammer-like protocol")
if (in_msg.Type == CacheRequestType:IFETCH) {
// ** INSTRUCTION ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, try to write it to the L2
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.LineAddress),
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
}
}
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Icache_entry, tbe);
} else {
// Check to see if it is in the OTHER L1
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, try to write it to the L2
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.LineAddress),
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
}
}
if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
@ -430,26 +430,27 @@ machine(L1Cache, "AMD Hammer-like protocol")
} else {
// *** DATA ACCESS ***
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, try to write it to the L2
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
} else {
trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.LineAddress),
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
}
}
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
// Check to see if it is in the OTHER L1
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, try to write it to the L2
if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe);
} else {
trigger(Event:L2_Replacement,
L2cacheMemory.cacheProbe(in_msg.LineAddress),
getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)),
TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]);
}
}
if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);

3
src/mem/ruby/buffers/MessageBuffer.cc
View file

@ -58,6 +58,8 @@ MessageBuffer::MessageBuffer(const string &name)
m_name = name;
m_stall_msg_map.clear();
m_input_link_id = 0;
m_vnet_id = 0;
}
int
@ -228,6 +230,7 @@ MessageBuffer::enqueue(MsgPtr message, Time delta)
// Schedule the wakeup
if (m_consumer_ptr != NULL) {
g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time);
m_consumer_ptr->storeEventInfo(m_vnet_id);
} else {
panic("No consumer: %s name: %s\n", *this, m_name);
}

6
src/mem/ruby/buffers/MessageBuffer.hh
View file

@ -142,6 +142,9 @@ class MessageBuffer
void printStats(std::ostream& out);
void clearStats() { m_not_avail_count = 0; m_msg_counter = 0; }
void setIncomingLink(int link_id) { m_input_link_id = link_id; }
void setVnet(int net) { m_vnet_id = net; }
private:
//added by SS
int m_recycle_latency;
@ -184,6 +187,9 @@ class MessageBuffer
bool m_ordering_set;
bool m_randomization;
Time m_last_arrival_time;
int m_input_link_id;
int m_vnet_id;
};
inline std::ostream&

1
src/mem/ruby/common/Consumer.hh
View file

@ -67,6 +67,7 @@ class Consumer
virtual void wakeup() = 0;
virtual void print(std::ostream& out) const = 0;
virtual void storeEventInfo(int info) {}
const Time&
getLastScheduledWakeup() const

299
src/mem/ruby/network/simple/PerfectSwitch.cc
View file

@ -54,6 +54,11 @@ PerfectSwitch::PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr)
m_round_robin_start = 0;
m_network_ptr = network_ptr;
m_wakeups_wo_switch = 0;
for(int i = 0;i < m_virtual_networks;++i)
{
m_pending_message_count.push_back(0);
}
}
void
@ -62,12 +67,15 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in)
assert(in.size() == m_virtual_networks);
NodeID port = m_in.size();
m_in.push_back(in);
for (int j = 0; j < m_virtual_networks; j++) {
m_in[port][j]->setConsumer(this);
string desc = csprintf("[Queue from port %s %s %s to PerfectSwitch]",
NodeIDToString(m_switch_id), NodeIDToString(port),
NodeIDToString(j));
m_in[port][j]->setDescription(desc);
m_in[port][j]->setIncomingLink(port);
m_in[port][j]->setVnet(j);
}
}
@ -154,160 +162,169 @@ PerfectSwitch::wakeup()
m_round_robin_start = 0;
}
// for all input ports, use round robin scheduling
for (int counter = 0; counter < m_in.size(); counter++) {
// Round robin scheduling
incoming++;
if (incoming >= m_in.size()) {
incoming = 0;
}
// temporary vectors to store the routing results
vector<LinkID> output_links;
vector<NetDest> output_link_destinations;
// Is there a message waiting?
while (m_in[incoming][vnet]->isReady()) {
DPRINTF(RubyNetwork, "incoming: %d\n", incoming);
// Peek at message
msg_ptr = m_in[incoming][vnet]->peekMsgPtr();
net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get());
DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr));
output_links.clear();
output_link_destinations.clear();
NetDest msg_dsts =
net_msg_ptr->getInternalDestination();
// Unfortunately, the token-protocol sends some
// zero-destination messages, so this assert isn't valid
// assert(msg_dsts.count() > 0);
assert(m_link_order.size() == m_routing_table.size());
assert(m_link_order.size() == m_out.size());
if (m_network_ptr->getAdaptiveRouting()) {
if (m_network_ptr->isVNetOrdered(vnet)) {
// Don't adaptively route
for (int out = 0; out < m_out.size(); out++) {
m_link_order[out].m_link = out;
m_link_order[out].m_value = 0;
}
} else {
// Find how clogged each link is
for (int out = 0; out < m_out.size(); out++) {
int out_queue_length = 0;
for (int v = 0; v < m_virtual_networks; v++) {
out_queue_length += m_out[out][v]->getSize();
}
int value =
(out_queue_length << 8) | (random() & 0xff);
m_link_order[out].m_link = out;
m_link_order[out].m_value = value;
}
// Look at the most empty link first
sort(m_link_order.begin(), m_link_order.end());
}
if(m_pending_message_count[vnet] > 0) {
// for all input ports, use round robin scheduling
for (int counter = 0; counter < m_in.size(); counter++) {
// Round robin scheduling
incoming++;
if (incoming >= m_in.size()) {
incoming = 0;
}
for (int i = 0; i < m_routing_table.size(); i++) {
// pick the next link to look at
int link = m_link_order[i].m_link;
NetDest dst = m_routing_table[link];
DPRINTF(RubyNetwork, "dst: %s\n", dst);
// temporary vectors to store the routing results
vector<LinkID> output_links;
vector<NetDest> output_link_destinations;
if (!msg_dsts.intersectionIsNotEmpty(dst))
continue;
// Is there a message waiting?
while (m_in[incoming][vnet]->isReady()) {
DPRINTF(RubyNetwork, "incoming: %d\n", incoming);
// Remember what link we're using
output_links.push_back(link);
// Need to remember which destinations need this
// message in another vector. This Set is the
// intersection of the routing_table entry and the
// current destination set. The intersection must
// not be empty, since we are inside "if"
output_link_destinations.push_back(msg_dsts.AND(dst));
// Next, we update the msg_destination not to
// include those nodes that were already handled
// by this link
msg_dsts.removeNetDest(dst);
}
assert(msg_dsts.count() == 0);
//assert(output_links.size() > 0);
// Check for resources - for all outgoing queues
bool enough = true;
for (int i = 0; i < output_links.size(); i++) {
int outgoing = output_links[i];
if (!m_out[outgoing][vnet]->areNSlotsAvailable(1))
enough = false;
DPRINTF(RubyNetwork, "Checking if node is blocked\n"
"outgoing: %d, vnet: %d, enough: %d\n",
outgoing, vnet, enough);
}
// There were not enough resources
if (!enough) {
g_eventQueue_ptr->scheduleEvent(this, 1);
DPRINTF(RubyNetwork, "Can't deliver message since a node "
"is blocked\n"
"Message: %s\n", (*net_msg_ptr));
break; // go to next incoming port
}
MsgPtr unmodified_msg_ptr;
if (output_links.size() > 1) {
// If we are sending this message down more than
// one link (size>1), we need to make a copy of
// the message so each branch can have a different
// internal destination we need to create an
// unmodified MsgPtr because the MessageBuffer
// enqueue func will modify the message
// This magic line creates a private copy of the
// message
unmodified_msg_ptr = msg_ptr->clone();
}
// Enqueue it - for all outgoing queues
for (int i=0; i<output_links.size(); i++) {
int outgoing = output_links[i];
if (i > 0) {
// create a private copy of the unmodified
// message
msg_ptr = unmodified_msg_ptr->clone();
}
// Change the internal destination set of the
// message so it knows which destinations this
// link is responsible for.
// Peek at message
msg_ptr = m_in[incoming][vnet]->peekMsgPtr();
net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get());
net_msg_ptr->getInternalDestination() =
output_link_destinations[i];
DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr));
// Enqeue msg
DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from "
"inport[%d][%d] to outport [%d][%d] time: %lld.\n",
m_switch_id, incoming, vnet, outgoing, vnet,
g_eventQueue_ptr->getTime());
output_links.clear();
output_link_destinations.clear();
NetDest msg_dsts =
net_msg_ptr->getInternalDestination();
m_out[outgoing][vnet]->enqueue(msg_ptr);
// Unfortunately, the token-protocol sends some
// zero-destination messages, so this assert isn't valid
// assert(msg_dsts.count() > 0);
assert(m_link_order.size() == m_routing_table.size());
assert(m_link_order.size() == m_out.size());
if (m_network_ptr->getAdaptiveRouting()) {
if (m_network_ptr->isVNetOrdered(vnet)) {
// Don't adaptively route
for (int out = 0; out < m_out.size(); out++) {
m_link_order[out].m_link = out;
m_link_order[out].m_value = 0;
}
} else {
// Find how clogged each link is
for (int out = 0; out < m_out.size(); out++) {
int out_queue_length = 0;
for (int v = 0; v < m_virtual_networks; v++) {
out_queue_length += m_out[out][v]->getSize();
}
int value =
(out_queue_length << 8) | (random() & 0xff);
m_link_order[out].m_link = out;
m_link_order[out].m_value = value;
}
// Look at the most empty link first
sort(m_link_order.begin(), m_link_order.end());
}
}
for (int i = 0; i < m_routing_table.size(); i++) {
// pick the next link to look at
int link = m_link_order[i].m_link;
NetDest dst = m_routing_table[link];
DPRINTF(RubyNetwork, "dst: %s\n", dst);
if (!msg_dsts.intersectionIsNotEmpty(dst))
continue;
// Remember what link we're using
output_links.push_back(link);
// Need to remember which destinations need this
// message in another vector. This Set is the
// intersection of the routing_table entry and the
// current destination set. The intersection must
// not be empty, since we are inside "if"
output_link_destinations.push_back(msg_dsts.AND(dst));
// Next, we update the msg_destination not to
// include those nodes that were already handled
// by this link
msg_dsts.removeNetDest(dst);
}
assert(msg_dsts.count() == 0);
//assert(output_links.size() > 0);
// Check for resources - for all outgoing queues
bool enough = true;
for (int i = 0; i < output_links.size(); i++) {
int outgoing = output_links[i];
if (!m_out[outgoing][vnet]->areNSlotsAvailable(1))
enough = false;
DPRINTF(RubyNetwork, "Checking if node is blocked\n"
"outgoing: %d, vnet: %d, enough: %d\n",
outgoing, vnet, enough);
}
// There were not enough resources
if (!enough) {
g_eventQueue_ptr->scheduleEvent(this, 1);
DPRINTF(RubyNetwork, "Can't deliver message since a node "
"is blocked\n"
"Message: %s\n", (*net_msg_ptr));
break; // go to next incoming port
}
MsgPtr unmodified_msg_ptr;
if (output_links.size() > 1) {
// If we are sending this message down more than
// one link (size>1), we need to make a copy of
// the message so each branch can have a different
// internal destination we need to create an
// unmodified MsgPtr because the MessageBuffer
// enqueue func will modify the message
// This magic line creates a private copy of the
// message
unmodified_msg_ptr = msg_ptr->clone();
}
// Enqueue it - for all outgoing queues
for (int i=0; i<output_links.size(); i++) {
int outgoing = output_links[i];
if (i > 0) {
// create a private copy of the unmodified
// message
msg_ptr = unmodified_msg_ptr->clone();
}
// Change the internal destination set of the
// message so it knows which destinations this
// link is responsible for.
net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get());
net_msg_ptr->getInternalDestination() =
output_link_destinations[i];
// Enqeue msg
DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from "
"inport[%d][%d] to outport [%d][%d] time: %lld.\n",
m_switch_id, incoming, vnet, outgoing, vnet,
g_eventQueue_ptr->getTime());
m_out[outgoing][vnet]->enqueue(msg_ptr);
}
// Dequeue msg
m_in[incoming][vnet]->pop();
m_pending_message_count[vnet]--;
}
// Dequeue msg
m_in[incoming][vnet]->pop();
}
}
}
}
void
PerfectSwitch::storeEventInfo(int info)
{
m_pending_message_count[info]++;
}
void
PerfectSwitch::printStats(std::ostream& out) const
{

2
src/mem/ruby/network/simple/PerfectSwitch.hh
View file

@ -69,6 +69,7 @@ class PerfectSwitch : public Consumer
int getOutLinks() const { return m_out.size(); }
void wakeup();
void storeEventInfo(int info);
void printStats(std::ostream& out) const;
void clearStats();
@ -92,6 +93,7 @@ class PerfectSwitch : public Consumer
int m_round_robin_start;
int m_wakeups_wo_switch;
SimpleNetwork* m_network_ptr;
std::vector<int> m_pending_message_count;
};
inline std::ostream&

2
src/mem/ruby/slicc_interface/Message.hh
View file

@ -57,6 +57,8 @@ class Message : public RefCounted
virtual Message* clone() const = 0;
virtual void print(std::ostream& out) const = 0;
virtual void setIncomingLink(int) {}
virtual void setVnet(int) {}
void setDelayedCycles(const int& cycles) { m_DelayedCycles = cycles; }
const int& getDelayedCycles() const {return m_DelayedCycles;}

7
src/mem/ruby/slicc_interface/NetworkMessage.hh
View file

@ -82,9 +82,16 @@ class NetworkMessage : public Message
virtual void print(std::ostream& out) const = 0;
int getIncomingLink() const { return incoming_link; }
void setIncomingLink(int link) { incoming_link = link; }
int getVnet() const { return vnet; }
void setVnet(int net) { vnet = net; }
private:
NetDest m_internal_dest;
bool m_internal_dest_valid;
int incoming_link;
int vnet;
};
inline std::ostream&

9
src/python/m5/main.py
View file

@ -61,8 +61,6 @@ add_option('-C', "--copyright", action="store_true", default=False,
help="Show full copyright information")
add_option('-R', "--readme", action="store_true", default=False,
help="Show the readme")
add_option('-N', "--release-notes", action="store_true", default=False,
help="Show the release notes")
# Options for configuring the base simulator
add_option('-d', "--outdir", metavar="DIR", default="m5out",
@ -207,13 +205,6 @@ def main():
print info.README
print
if options.release_notes:
done = True
print 'Release Notes:'
print
print info.RELEASE_NOTES
print
if options.trace_help:
done = True
check_tracing()

60
system/alpha/console/Makefile Normal file
View file

@ -0,0 +1,60 @@
# Copyright (c) 2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan L. Binkert
# Ali G. Saidi
# Point to the M5 diretory so we can get some headers
M5?=../../..
### If we are not compiling on an alpha, we must use cross tools ###
ifneq ($(shell uname -m), alpha)
CROSS_COMPILE?=alpha-unknown-linux-gnu-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
DBMENTRY= fffffc0000010000
CFLAGS=-I . -I ../h -I$(M5)/src/dev/alpha -I$(M5)/util/m5/ -fno-builtin -Wa,-m21164
OBJS=dbmentry.o printf.o paljtokern.o paljtoslave.o console.o m5op.o
all: console
m5op.o: $(M5)/util/m5/m5op_alpha.S
$(CC) $(CFLAGS) -nostdinc -o $@ -c $<
%.o: %.S
$(CC) $(CFLAGS) -nostdinc -o $@ -c $<
%.o: %.c
$(CC) -g3 $(CFLAGS) -o $@ -c $<
console: $(OBJS)
$(LD) -o console -N -Ttext $(DBMENTRY) -non_shared $(OBJS) -lc
clean:
rm -f *.o console

1074
system/alpha/console/console.c Normal file
View file

File diff suppressed because it is too large Load diff

213
system/alpha/console/dbmentry.S Normal file
View file

@ -0,0 +1,213 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Debug Monitor Entry code
*/
#include "fromHudsonOsf.h"
.extern myAlphaAccess
.text
/* return address and padding to octaword align */
#define STARTFRM 16
.globl _start
.ent _start, 0
_start:
_entry:
br t0, 2f # get the current PC
2: ldgp gp, 0(t0) # init gp
/* Processor 0 start stack frame is begining of physical memory (0)
Other processors spin here waiting to get their stacks from
Processor 0, then they can progress as normal.
*/
call_pal PAL_WHAMI_ENTRY
beq v0, cpuz
ldq t3, m5AlphaAccess
addq t3,0x70,t3 # *** If offset in console alpha access struct changes
# This must be changed as well!
bis zero,8,t4
mulq t4,v0,t4
addq t3,t4,t3
ldah a0, 3(zero) # load arg0 with 65536*3
cpuwait: .long 0x6000002 # jsr quiesceNs
ldq t4, 0(t3)
beq t4, cpuwait
bis t4,t4,sp
cpuz: bis sp,sp,s0 /* save sp */
slave: lda v0,(8*1024)(sp) /* end of page */
subq zero, 1, t0
sll t0, 42, t0
bis t0, v0, sp
lda sp, -STARTFRM(sp) # Create a stack frame
stq ra, 0(sp) # Place return address on the stack
.mask 0x84000000, -8
.frame sp, STARTFRM, ra
/*
* Enable the Floating Point Unit
*/
lda a0, 1(zero)
call_pal PAL_WRFEN_ENTRY
/*
* Every good C program has a main()
*/
/* If stack pointer was 0, then this is CPU0*/
beq s0,master
call_pal PAL_WHAMI_ENTRY
bis v0,v0,a0
jsr ra, SlaveLoop
master:
jsr ra, main
/*
* The Debug Monitor should never return.
* However, just incase...
*/
ldgp gp, 0(ra)
bsr zero, _exit
.end _start
.globl _exit
.ent _exit, 0
_exit:
ldq ra, 0(sp) # restore return address
lda sp, STARTFRM(sp) # prune back the stack
ret zero, (ra) # Back from whence we came
.end _exit
.globl cServe
.ent cServe 2
cServe:
.option O1
.frame sp, 0, ra
call_pal PAL_CSERVE_ENTRY
ret zero, (ra)
.end cServe
.globl wrfen
.ent wrfen 2
wrfen:
.option O1
.frame sp, 0, ra
call_pal PAL_WRFEN_ENTRY
ret zero, (ra)
.end wrfen
.globl consoleCallback
.ent consoleCallback 2
consoleCallback:
br t0, 2f # get the current PC
2: ldgp gp, 0(t0) # init gp
lda sp,-64(sp)
stq ra,0(sp)
jsr CallBackDispatcher
ldq ra,0(sp)
lda sp,64(sp)
ret zero,(ra)
.end consoleCallback
.globl consoleFixup
.ent consoleFixup 2
consoleFixup:
br t0, 2f # get the current PC
2: ldgp gp, 0(t0) # init gp
lda sp,-64(sp)
stq ra,0(sp)
jsr CallBackFixup
ldq ra,0(sp)
lda sp,64(sp)
ret zero,(ra)
.end consoleFixup
.globl SpinLock
.ent SpinLock 2
SpinLock:
1:
ldq_l a1,0(a0) # interlock complete lock state
subl ra,3,v0 # get calling addr[31:0] + 1
blbs a1,2f # branch if lock is busy
stq_c v0,0(a0) # attempt to acquire lock
beq v0,2f # branch if lost atomicity
mb # ensure memory coherence
ret zero,(ra) # return to caller (v0 is 1)
2:
br zero,1b
.end SpinLock
.globl loadContext
.ent loadContext 2
loadContext:
.option O1
.frame sp, 0, ra
call_pal PAL_SWPCTX_ENTRY
ret zero, (ra)
.end loadContext
.globl SlaveSpin # Very carefully spin wait
.ent SlaveSpin 2 # and swap context without
SlaveSpin: # using any stack space
.option O1
.frame sp, 0, ra
mov a0, t0 # cpu number
mov a1, t1 # cpu rpb pointer (virtual)
mov a2, t2 # what to spin on
ldah a0, 3(zero) # load arg0 with 65536
test: .long 0x6000002 # jsr quiesceNs # wait 65us*3
ldl t3, 0(t2)
beq t3, test
zapnot t1,0x1f,a0 # make rpb physical
call_pal PAL_SWPCTX_ENTRY # switch to pcb
mov t0, a0 # setup args for SlaveCmd
mov t1, a1
jsr SlaveCmd # call SlaveCmd
ret zero, (ra) # Should never be reached
.end SlaveSpin

174
system/alpha/console/paljtokern.S Normal file
View file

@ -0,0 +1,174 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
#include "ev5_defs.h"
#include "fromHudsonOsf.h" // OSF/1 specific definitions
#include "fromHudsonMacros.h" // Global macro definitions
/* Jump to kernel
* args:
* Kernel address - a0
* PCBB - a1
* First free PFN - a3?
*
* Enable kseg addressing in ICSR
* Enable kseg addressing in MCSR
* Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
* Set PCBB -- pass pointer in arg
* Set PTBR -- get it out of PCB
* Set KSP -- get it out of PCB
*
* Jump to kernel address
*
* Kernel args-
* s0 first free PFN
* s1 ptbr
* s2 argc 0
* s3 argv NULL
* s5 osf_param (sysconfigtab) NULL
*/
.global palJToKern
.text 3
palJToKern:
ALIGN_BRANCH
ldq_p a0, 0(zero)
ldq_p a1, 8(zero)
ldq_p a3, 16(zero)
/* Point the Vptbr at 8GB */
lda t0, 0x1(zero)
sll t0, 33, t0
mtpr t0, mVptBr // Load Mbox copy
mtpr t0, iVptBr // Load Ibox copy
STALL // don't dual issue the load with mtpr -pb
/* Turn on superpage mapping in the mbox and icsr */
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
STALL // don't dual issue the load with mtpr -pb
mtpr t0, mcsr // Set the super page mode enable bit
STALL // don't dual issue the load with mtpr -pb
lda t0, 0(zero)
mtpr t0, dtbAsn
mtpr t0, itbAsn
LDLI (t1,0x20000000)
STALL // don't dual issue the load with mtpr -pb
mfpr t0, icsr // Enable superpage mapping
STALL // don't dual issue the load with mtpr -pb
bis t0, t1, t0
mtpr t0, icsr
STALL // Required stall to update chip ...
STALL
STALL
STALL
STALL
ldq_p s0, PCB_Q_PTBR(a1)
sll s0, VA_S_OFF, s0 // Shift PTBR into position
STALL // don't dual issue the load with mtpr -pb
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
STALL // don't dual issue the load with mtpr -pb
ldq_p sp, PCB_Q_KSP(a1)
mtpr a0, excAddr // Load the dispatch address.
STALL // don't dual issue the load with mtpr -pb
bis a3, zero, a0 // first free PFN
ldq_p a1, PCB_Q_PTBR(a1) // ptbr
ldq_p a2, 24(zero) // argc
ldq_p a3, 32(zero) // argv
ldq_p a4, 40(zero) // environ
lda a5, 0(zero) // osf_param
STALL // don't dual issue the load with mtpr -pb
mtpr zero, dtbIa // Flush all D-stream TB entries
mtpr zero, itbIa // Flush all I-stream TB entries
br zero, 2f
ALIGN_BLOCK
2: NOP
mtpr zero, icFlush // Flush the icache.
NOP
NOP
NOP // Required NOPs ... 1-10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 11-20
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 21-30
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 31-40
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 41-44
NOP
NOP
NOP
hw_rei_stall // Dispatch to kernel

161
system/alpha/console/paljtoslave.S Normal file
View file

@ -0,0 +1,161 @@
/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
#include "ev5_defs.h"
#include "fromHudsonOsf.h" // OSF/1 specific definitions
#include "fromHudsonMacros.h" // Global macro definitions
/*
* args:
* a0: here
* a1: boot location
* a2: CSERVE_J_KTOPAL
* a3: restrart_pv
* a4: vptb
* a5: my_rpb
*
* SRM Console Architecture III 3-26
*/
.global palJToSlave
.text 3
palJToSlave:
ALIGN_BRANCH
bis a3, zero, pv
bis zero, zero, t11
bis zero, zero, ra
/* Point the Vptbr to a2 */
mtpr a4, mVptBr // Load Mbox copy
mtpr a4, iVptBr // Load Ibox copy
STALL // don't dual issue the load with mtpr -pb
/* Turn on superpage mapping in the mbox and icsr */
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
STALL // don't dual issue the load with mtpr -pb
mtpr t0, mcsr // Set the super page mode enable bit
STALL // don't dual issue the load with mtpr -pb
lda t0, 0(zero)
mtpr t0, dtbAsn
mtpr t0, itbAsn
LDLI (t1,0x20000000)
STALL // don't dual issue the load with mtpr -pb
mfpr t0, icsr // Enable superpage mapping
STALL // don't dual issue the load with mtpr -pb
bis t0, t1, t0
mtpr t0, icsr
STALL // Required stall to update chip ...
STALL
STALL
STALL
STALL
ldq_p s0, PCB_Q_PTBR(a5)
sll s0, VA_S_OFF, s0 // Shift PTBR into position
STALL // don't dual issue the load with mtpr -pb
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
STALL // don't dual issue the load with mtpr -pb
ldq_p sp, PCB_Q_KSP(a5)
mtpr zero, dtbIa // Flush all D-stream TB entries
mtpr zero, itbIa // Flush all I-stream TB entries
mtpr a1, excAddr // Load the dispatch address.
STALL // don't dual issue the load with mtpr -pb
STALL // don't dual issue the load with mtpr -pb
mtpr zero, dtbIa // Flush all D-stream TB entries
mtpr zero, itbIa // Flush all I-stream TB entries
br zero, 2f
ALIGN_BLOCK
2: NOP
mtpr zero, icFlush // Flush the icache.
NOP
NOP
NOP // Required NOPs ... 1-10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 11-20
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 21-30
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 31-40
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP // Required NOPs ... 41-44
NOP
NOP
NOP
hw_rei_stall // Dispatch to kernel

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/*
* Copyright (c) 2003-2004 The Regents of The University of Michigan
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/types.h>
#include <stdarg.h>
#include <stdint.h>
#include "m5op.h"
/* The string s is terminated by a '\0' */
void
PutString(const char *s)
{
while (*s)
PutChar(*s++);
}
/* print c count times */
void
PutRepChar(char c, int count)
{
while (count--)
PutChar(c);
}
/* put string reverse */
void
PutStringReverse(const char *s, int index)
{
while (index-- > 0)
PutChar(s[index]);
}
/*
* prints value in radix, in a field width width, with fill
* character fill
* if radix is negative, print as signed quantity
* if width is negative, left justify
* if width is 0, use whatever is needed
* if fill is 0, use ' '
*/
void
PutNumber(long value, int radix, int width, char fill)
{
char buffer[40];
uint bufferindex = 0;
ulong uvalue;
ushort digit;
ushort left = 0;
ushort negative = 0;
if (fill == 0)
fill = ' ';
if (width < 0) {
width = -width;
left = 1;
}
if (width < 0 || width > 80)
width = 0;
if (radix < 0) {
radix = -radix;
if (value < 0) {
negative = 1;
value = -value;
}
}
switch (radix) {
case 8:
case 10:
case 16:
break;
default:
PutString("****");
return;
}
uvalue = value;
do {
if (radix != 16) {
digit = (ushort)(uvalue % radix);
uvalue /= radix;
} else {
digit = (ushort)(uvalue & 0xf);
uvalue = uvalue >> 4;
}
buffer[bufferindex] = digit + ((digit <= 9) ? '0' : ('A' - 10));
bufferindex += 1;
} while (uvalue != 0);
/* fill # ' ' and negative cannot happen at once */
if (negative) {
buffer[bufferindex] = '-';
bufferindex += 1;
}
if ((uint)width <= bufferindex) {
PutStringReverse(buffer, bufferindex);
} else {
width -= bufferindex;
if (!left)
PutRepChar(fill, width);
PutStringReverse(buffer, bufferindex);
if (left)
PutRepChar(fill, width);
}
}
ulong
power(long base, long n)
{
ulong p;
for (p = 1; n > 0; --n)
p = p * base;
return p;
}
void
putFloat(double a, int fieldwidth, char fill)
{
int i;
ulong b;
/*
* Put out everything before the decimal place.
*/
PutNumber(((ulong) a), 10, fieldwidth, fill);
/*
* Output the decimal place.
*/
PutChar('.' & 0x7f);
/*
* Output the n digits after the decimal place.
*/
for (i = 1; i < 6; i++) {
b = (ulong)(power(10, i) * (double)(a - (ulong) a));
PutChar((char)(b % 10) + '0');
}
}
const char *
FormatItem(const char *f, va_list *ap)
{
char c;
int fieldwidth = 0;
int leftjust = 0;
int radix = 0;
char fill = ' ';
if (*f == '0')
fill = '0';
while (c = *f++) {
if (c >= '0' && c <= '9') {
fieldwidth = (fieldwidth * 10) + (c - '0');
} else {
switch (c) {
case '\000':
return(--f);
case '%':
PutChar('%');
return(f);
case '-':
leftjust = 1;
break;
case 'c': {
char a = (char)va_arg(*ap, int);
if (leftjust)
PutChar(a & 0x7f);
if (fieldwidth > 0)
PutRepChar(fill, fieldwidth - 1);
if (!leftjust)
PutChar(a & 0x7f);
return(f);
}
case 's': {
const char *a = va_arg(*ap, const char *);
if (leftjust)
PutString((const char *) a);
if (fieldwidth > strlen((const char *) a))
PutRepChar(fill, fieldwidth - strlen((const char *)a));
if (!leftjust)
PutString((const char *) a);
return(f);
}
case 'd':
radix = -10;
break;
case 'u':
radix = 10;
break;
case 'x':
radix = 16;
break;
case 'X':
radix = 16;
break;
case 'o':
radix = 8;
break;
case 'f': {
double a = va_arg(*ap, double);
putFloat(a, fieldwidth, fill);
return(f);
}
default: /* unknown switch! */
radix = 3;
break;
}
}
if (radix)
break;
}
if (leftjust)
fieldwidth = -fieldwidth;
long a = va_arg(*ap, long);
PutNumber(a, radix, fieldwidth, fill);
return(f);
}
int
printf(const char *f, ...)
{
va_list ap;
va_start(ap, f);
while (*f) {
if (*f == '%')
f = FormatItem(f + 1, &ap);
else
PutChar(*f++);
}
if (*(f - 1) == '\n') {
/* add a line-feed (SimOS console output goes to shell */
PutChar('\r');
}
va_end(ap); /* clean up */
return 0;
}
void
panic(const char *f, ...)
{
va_list ap;
va_start(ap, f);
printf("CONSOLE PANIC (looping): ");
while (*f) {
if (*f == '%')
f = FormatItem(f + 1, &ap);
else
PutChar(*f++);
}
va_end(ap); /* clean up */
m5_panic();
}

52
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/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define __CSERVE_LOADED 1
/*
* Console Service (cserve) sub-function codes:
*/
#define CSERVE_K_LDQP 0x01
#define CSERVE_K_STQP 0x02
#define CSERVE_K_JTOPAL 0x09
#define CSERVE_K_WR_INT 0x0A
#define CSERVE_K_RD_IMPURE 0x0B
#define CSERVE_K_PUTC 0x0F
#define CSERVE_K_WR_ICSR 0x10
#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */
#define CSERVE_K_RD_ICSR 0x11
#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */
#define CSERVE_K_RD_BCCTL 0x12
#define CSERVE_K_RD_BCCFG 0x13
#define CSERVE_K_WR_BCACHE 0x16
#define CSERVE_K_RD_BCCFG_OFF 0x17
#define CSERVE_K_JTOKERN 0x18

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/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DC21164FROMGASSOURCES_INCLUDED
#define DC21164FROMGASSOURCES_INCLUDED 1
/*
**
** INTERNAL PROCESSOR REGISTER DEFINITIONS
**
** The internal processor register definitions below are annotated
** with one of the following symbols:
**
** RW - The register may be read and written
** RO - The register may only be read
** WO - The register may only be written
**
** For RO and WO registers, all bits and fields within the register are
** also read-only or write-only. For RW registers, each bit or field
** within the register is annotated with one of the following:
**
** RW - The bit/field may be read and written
** RO - The bit/field may be read; writes are ignored
** WO - The bit/field may be written; reads return UNPREDICTABLE
** WZ - The bit/field may be written; reads return a zero value
** W0C - The bit/field may be read; write-zero-to-clear
** W1C - The bit/field may be read; write-one-to-clear
** WA - The bit/field may be read; write-anything-to-clear
** RC - The bit/field may be read, causing state to clear;
** writes are ignored
**
*/
/*
**
** Ibox IPR Definitions:
**
*/
// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */
#define itbTag 0x101 /* WO - ITB Tag */
#define itbPte 0x102 /* RW - ITB Page Table Entry */
#define itbAsn 0x103 /* RW - ITB Address Space Number */
#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */
#define itbIa 0x105 /* WO - ITB Invalidate All */
#define itbIap 0x106 /* WO - ITB Invalidate All Process */
#define itbIs 0x107 /* WO - ITB Invalidate Single */
// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */
// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */
// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */
#define excAddr 0x10B /* RW - Exception Address */
#define excSum 0x10C /* RW - Exception Summary */
#define excMask 0x10D /* RO - Exception Mask */
#define palBase 0x10E /* RW - PAL Base */
#define ips 0x10F /* RW - Processor Status */
// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */
#define intId 0x111 /* RO - Interrupt ID */
#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */
#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */
#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */
#define slXmit 0x116 /* WO - Serial Line Transmit */
#define slRcv 0x117 /* RO - Serial Line Receive */
// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */
#define icFlush 0x119 /* WO - I-Cache Flush Control */
#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */
#define icPerr 0x11A /* RW - I-Cache Parity Error Status */
#define PmCtr 0x11C /* RW - Performance Counter */
/*
**
** Ibox Control/Status Register (ICSR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <39> 1 TST RW,0 Assert Test Status
** <38> 1 ISTA RO I-Cache BIST Status
** <37> 1 DBS RW,1 Debug Port Select
** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity
** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity
** <34> 1 FMS RW,0 Force I-Cache Miss
** <33> 1 SLE RW,0 Enable Serial Line Interrupts
** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts
** <30> 1 SDE RW,0 Enable PAL Shadow Registers
** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode
** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode
** <26> 1 FPE RW,0 Enable Floating Point Instructions
** <25> 1 TMD RW,0 Disable Ibox Timeout Counter
** <24> 1 TMM RW,0 Timeout Counter Mode
**
*/
#define ICSR_V_TST 39
#define ICSR_M_TST (1<<ICSR_V_TST)
#define ICSR_V_ISTA 38
#define ICSR_M_ISTA (1<<ICSR_V_ISTA)
#define ICSR_V_DBS 37
#define ICSR_M_DBS (1<<ICSR_V_DBS)
#define ICSR_V_FBD 36
#define ICSR_M_FBD (1<<ICSR_V_FBD)
#define ICSR_V_FBT 35
#define ICSR_M_FBT (1<<ICSR_V_FBT)
#define ICSR_V_FMS 34
#define ICSR_M_FMS (1<<ICSR_V_FMS)
#define ICSR_V_SLE 33
#define ICSR_M_SLE (1<<ICSR_V_SLE)
#define ICSR_V_CRDE 32
#define ICSR_M_CRDE (1<<ICSR_V_CRDE)
#define ICSR_V_SDE 30
#define ICSR_M_SDE (1<<ICSR_V_SDE)
#define ICSR_V_SPE 28
#define ICSR_M_SPE (3<<ICSR_V_SPE)
#define ICSR_V_HWE 27
#define ICSR_M_HWE (1<<ICSR_V_HWE)
#define ICSR_V_FPE 26
#define ICSR_M_FPE (1<<ICSR_V_FPE)
#define ICSR_V_TMD 25
#define ICSR_M_TMD (1<<ICSR_V_TMD)
#define ICSR_V_TMM 24
#define ICSR_M_TMM (1<<ICSR_V_TMM)
/*
**
** Serial Line Tranmit Register (SL_XMIT)
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <7> 1 TMT WO,1 Serial line transmit data
**
*/
#define SLXMIT_V_TMT 7
#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT)
/*
**
** Serial Line Receive Register (SL_RCV)
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <6> 1 RCV RO Serial line receive data
**
*/
#define SLRCV_V_RCV 6
#define SLRCV_M_RCV (1<<SLRCV_V_RCV)
/*
**
** Icache Parity Error Status Register (ICPERR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <13> 1 TMR W1C Timeout reset error
** <12> 1 TPE W1C Tag parity error
** <11> 1 DPE W1C Data parity error
**
*/
#define ICPERR_V_TMR 13
#define ICPERR_M_TMR (1<<ICPERR_V_TMR)
#define ICPERR_V_TPE 12
#define ICPERR_M_TPE (1<<ICPERR_V_TPE)
#define ICPERR_V_DPE 11
#define ICPERR_M_DPE (1<<ICPERR_V_DPE)
#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE)
/*
**
** Exception Summary Register (EXC_SUM) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <16> 1 IOV WA Integer overflow
** <15> 1 INE WA Inexact result
** <14> 1 UNF WA Underflow
** <13> 1 FOV WA Overflow
** <12> 1 DZE WA Division by zero
** <11> 1 INV WA Invalid operation
** <10> 1 SWC WA Software completion
**
*/
#define EXC_V_IOV 16
#define EXC_M_IOV (1<<EXC_V_IOV)
#define EXC_V_INE 15
#define EXC_M_INE (1<<EXC_V_INE)
#define EXC_V_UNF 14
#define EXC_M_UNF (1<<EXC_V_UNF)
#define EXC_V_FOV 13
#define EXC_M_FOV (1<<EXC_V_FOV)
#define EXC_V_DZE 12
#define EXC_M_DZE (1<<EXC_V_DZE)
#define EXC_V_INV 11
#define EXC_M_INV (1<<EXC_V_INV)
#define EXC_V_SWC 10
#define EXC_M_SWC (1<<EXC_V_SWC)
/*
**
** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <33> 1 SLC W1C Clear Serial Line interrupt
** <32> 1 CRDC W1C Clear Correctable Read Data interrupt
** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt
** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt
** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt
**
*/
#define HWINT_V_SLC 33
#define HWINT_M_SLC (1<<HWINT_V_SLC)
#define HWINT_V_CRDC 32
#define HWINT_M_CRDC (1<<HWINT_V_CRDC)
#define HWINT_V_PC2C 29
#define HWINT_M_PC2C (1<<HWINT_V_PC2C)
#define HWINT_V_PC1C 28
#define HWINT_M_PC1C (1<<HWINT_V_PC1C)
#define HWINT_V_PC0C 27
#define HWINT_M_PC0C (1<<HWINT_V_PC0C)
/*
**
** Interrupt Summary Register (ISR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <34> 1 HLT RO External Halt interrupt
** <33> 1 SLI RO Serial Line interrupt
** <32> 1 CRD RO Correctable ECC errors
** <31> 1 MCK RO System Machine Check
** <30> 1 PFL RO Power Fail
** <29> 1 PC2 RO Performance Counter 2 interrupt
** <28> 1 PC1 RO Performance Counter 1 interrupt
** <27> 1 PC0 RO Performance Counter 0 interrupt
** <23> 1 I23 RO External Hardware interrupt
** <22> 1 I22 RO External Hardware interrupt
** <21> 1 I21 RO External Hardware interrupt
** <20> 1 I20 RO External Hardware interrupt
** <19> 1 ATR RO Async. System Trap request
** <18:4> 15 SIRR RO,0 Software Interrupt request
** <3:0> 4 ASTRR RO Async. System Trap request (USEK)
**
**/
#define ISR_V_HLT 34
#define ISR_M_HLT (1<<ISR_V_HLT)
#define ISR_V_SLI 33
#define ISR_M_SLI (1<<ISR_V_SLI)
#define ISR_V_CRD 32
#define ISR_M_CRD (1<<ISR_V_CRD)
#define ISR_V_MCK 31
#define ISR_M_MCK (1<<ISR_V_MCK)
#define ISR_V_PFL 30
#define ISR_M_PFL (1<<ISR_V_PFL)
#define ISR_V_PC2 29
#define ISR_M_PC2 (1<<ISR_V_PC2)
#define ISR_V_PC1 28
#define ISR_M_PC1 (1<<ISR_V_PC1)
#define ISR_V_PC0 27
#define ISR_M_PC0 (1<<ISR_V_PC0)
#define ISR_V_I23 23
#define ISR_M_I23 (1<<ISR_V_I23)
#define ISR_V_I22 22
#define ISR_M_I22 (1<<ISR_V_I22)
#define ISR_V_I21 21
#define ISR_M_I21 (1<<ISR_V_I21)
#define ISR_V_I20 20
#define ISR_M_I20 (1<<ISR_V_I20)
#define ISR_V_ATR 19
#define ISR_M_ATR (1<<ISR_V_ATR)
#define ISR_V_SIRR 4
#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR)
#define ISR_V_ASTRR 0
#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR)
/*
**
** Mbox and D-Cache IPR Definitions:
**
*/
#define dtbAsn 0x200 /* WO - DTB Address Space Number */
#define dtbCm 0x201 /* WO - DTB Current Mode */
#define dtbTag 0x202 /* WO - DTB Tag */
#define dtbPte 0x203 /* RW - DTB Page Table Entry */
#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */
#define mmStat 0x205 /* RO - D-Stream MM Fault Status */
// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */
#define vaForm 0x207 /* RO - Formatted Virtual Address */
#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */
#define dtbIap 0x209 /* WO - DTB Invalidate All Process */
#define dtbIa 0x20A /* WO - DTB Invalidate All */
#define dtbIs 0x20B /* WO - DTB Invalidate Single */
#define altMode 0x20C /* WO - Alternate Mode */
// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */
#define ccCtl 0x20E /* WO - Cycle Counter Control */
// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */
#define dcFlush 0x210 /* WO - Dcache Flush */
#define dcPerr 0x212 /* RW - Dcache Parity Error Status */
#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */
#define dcTestTag 0x214 /* RW - Dcache Test Tag */
#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */
#define dcMode 0x216 /* RW - Dcache Mode */
#define mafMode 0x217 /* RW - Miss Address File Mode */
/*
**
** D-Stream MM Fault Status Register (MM_STAT) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <16:11> 6 OPCODE RO Opcode of faulting instruction
** <10:06> 5 RA RO Ra field of faulting instruction
** <5> 1 BAD_VA RO Bad virtual address
** <4> 1 DTB_MISS RO Reference resulted in DTB miss
** <3> 1 FOW RO Fault on write
** <2> 1 FOR RO Fault on read
** <1> 1 ACV RO Access violation
** <0> 1 WR RO Reference type
**
*/
#define MMSTAT_V_OPC 11
#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC)
#define MMSTAT_V_RA 6
#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA)
#define MMSTAT_V_BAD_VA 5
#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA)
#define MMSTAT_V_DTB_MISS 4
#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS)
#define MMSTAT_V_FOW 3
#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW)
#define MMSTAT_V_FOR 2
#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR)
#define MMSTAT_V_ACV 1
#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV)
#define MMSTAT_V_WR 0
#define MMSTAT_M_WR (1<<MMSTAT_V_WR)
/*
**
** Mbox Control Register (MCSR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <5> 1 DBG1 RW,0 Mbox Debug Packet Select
** <4> 1 E_BE RW,0 Ebox Big Endian mode enable
** <3> 1 DBG0 RW,0 Debug Test Select
** <2:1> 2 SP RW,0 Superpage mode enable
** <0> 1 M_BE RW,0 Mbox Big Endian mode enable
**
*/
#define MCSR_V_DBG1 5
#define MCSR_M_DBG1 (1<<MCSR_V_DBG1)
#define MCSR_V_E_BE 4
#define MCSR_M_E_BE (1<<MCSR_V_E_BE)
#define MCSR_V_DBG0 3
#define MCSR_M_DBG0 (1<<MCSR_V_DBG0)
#define MCSR_V_SP 1
#define MCSR_M_SP (3<<MCSR_V_SP)
#define MCSR_V_M_BE 0
#define MCSR_M_M_BE (1<<MCSR_V_M_BE)
/*
**
** Dcache Parity Error Status Register (DCPERR) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ------------------------------------
** <5> 1 TP1 RO Dcache bank 1 tag parity error
** <4> 1 TP0 RO Dcache bank 0 tag parity error
** <3> 1 DP1 RO Dcache bank 1 data parity error
** <2> 1 DP0 RO Dcache bank 0 data parity error
** <1> 1 LOCK W1C Locks/clears bits <5:2>
** <0> 1 SEO W1C Second Dcache parity error occurred
**
*/
#define DCPERR_V_TP1 5
#define DCPERR_M_TP1 (1<<DCPERR_V_TP1)
#define DCPERR_V_TP0 4
#define DCPERR_M_TP0 (1<<DCPERR_V_TP0)
#define DCPERR_V_DP1 3
#define DCPERR_M_DP1 (1<<DCPERR_V_DP1)
#define DCPERR_V_DP0 2
#define DCPERR_M_DP0 (1<<DCPERR_V_DP0)
#define DCPERR_V_LOCK 1
#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK)
#define DCPERR_V_SEO 0
#define DCPERR_M_SEO (1<<DCPERR_V_SEO)
#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO)
/*
**
** Dcache Mode Register (DC_MODE) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <4> 1 DOA RO Hardware Dcache Disable
** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting
** <2> 1 BAD_DP RW,0 Force Dcache data bad parity
** <1> 1 FHIT RW,0 Force Dcache hit
** <0> 1 ENA RW,0 Software Dcache Enable
**
*/
#define DC_V_DOA 4
#define DC_M_DOA (1<<DC_V_DOA)
#define DC_V_PERR_DIS 3
#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS)
#define DC_V_BAD_DP 2
#define DC_M_BAD_DP (1<<DC_V_BAD_DP)
#define DC_V_FHIT 1
#define DC_M_FHIT (1<<DC_V_FHIT)
#define DC_V_ENA 0
#define DC_M_ENA (1<<DC_V_ENA)
/*
**
** Miss Address File Mode Register (MAF_MODE) Bit Summay
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <7> 1 WB RO,0 If set, pending WB request
** <6> 1 DREAD RO,0 If set, pending D-read request
**
*/
#define MAF_V_WB_PENDING 7
#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING)
#define MAF_V_DREAD_PENDING 6
#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING)
/*
**
** Cbox IPR Definitions:
**
*/
#define scCtl 0x0A8 /* RW - Scache Control */
#define scStat 0x0E8 /* RO - Scache Error Status */
#define scAddr 0x188 /* RO - Scache Error Address */
#define bcCtl 0x128 /* WO - Bcache/System Interface Control */
#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */
#define bcTagAddr 0x108 /* RO - Bcache Tag */
#define eiStat 0x168 /* RO - Bcache/System Error Status */
#define eiAddr 0x148 /* RO - Bcache/System Error Address */
#define fillSyn 0x068 /* RO - Fill Syndrome */
#define ldLock 0x1E8 /* RO - LDx_L Address */
/*
**
** Scache Control Register (SC_CTL) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <15:13> 3 SET_EN RW,1 Set enable
** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select
** <11:08> 4 FB_DP RW,0 Force bad data parity
** <07:02> 6 TAG_STAT RW Tag status and parity
** <1> 1 FLUSH RW,0 If set, clear all tag valid bits
** <0> 1 FHIT RW,0 Force hits
**
*/
#define SC_V_SET_EN 13
#define SC_M_SET_EN (7<<SC_V_SET_EN)
#define SC_V_BLK_SIZE 12
#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE)
#define SC_V_FB_DP 8
#define SC_M_FB_DP (0xF<<SC_V_FB_DP)
#define SC_V_TAG_STAT 2
#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT)
#define SC_V_FLUSH 1
#define SC_M_FLUSH (1<<SC_V_FLUSH)
#define SC_V_FHIT 0
#define SC_M_FHIT (1<<SC_V_FHIT)
/*
**
** Bcache Control Register (BC_CTL) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer
** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads
** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select
** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select
** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining
** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins
** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error
** <14:13> 2 BC_BAD_DAT WO,0 Force bad data
** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity
** <7> 1 BC_FHIT WO,0 Bcache force hit
** <6> 1 EI_ECC WO,1 ECC or byte parity mode
** <5> 1 VTM_FIRST WO,1 Drive out victim block address first
** <4> 1 CORR_FILL_DAT WO,1 Correct fill data
** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins
** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins
** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs.
** <0> 1 BC_ENA W0,0 Bcache enable
**
*/
#define BC_V_DIS_SC_VIC_BUF 27
#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF)
#define BC_V_DIS_BAF_BYP 26
#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP)
#define BC_V_DBG_MUX_SEL 25
#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL)
#define BC_V_PM_MUX_SEL 19
#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL)
#define BC_V_BC_WAVE 17
#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE)
#define BC_V_TL_PIPE_LATCH 16
#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH)
#define BC_V_EI_DIS_ERR 15
#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR)
#define BC_V_BC_BAD_DAT 13
#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT)
#define BC_V_BC_TAG_STAT 8
#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT)
#define BC_V_BC_FHIT 7
#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT)
#define BC_V_EI_ECC_OR_PARITY 6
#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY)
#define BC_V_VTM_FIRST 5
#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST)
#define BC_V_CORR_FILL_DAT 4
#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT)
#define BC_V_EI_CMD_GRP3 3
#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3)
#define BC_V_EI_CMD_GRP2 2
#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2)
#define BC_V_ALLOC_CYC 1
#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC)
#define BC_V_BC_ENA 0
#define BC_M_BC_ENA (1<<BC_V_BC_ENA)
#define BC_K_DFAULT \
(((BC_M_EI_DIS_ERR) | \
(BC_M_EI_ECC_OR_PARITY) | \
(BC_M_VTM_FIRST) | \
(BC_M_CORR_FILL_DAT))>>1)
/*
**
** Bcache Configuration Register (BC_CONFIG) Bit Summary
**
** Extent Size Name Type Function
** ------ ---- ---- ---- ---------------------------------
** <35:29> 7 RSVD WO Reserved - Must Be Zero
** <28:20> 9 WE_CTL WO,0 Bcache write enable control
** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero
** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset
** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero
** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing
** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles
** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles
** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero
** <02:00> 3 SIZE WO,1 Bcache size
*/
#define BC_V_WE_CTL 20
#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL)
#define BC_V_WE_OFF 16
#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF)
#define BC_V_RD_WR_SPC 12
#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC)
#define BC_V_WR_SPD 8
#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD)
#define BC_V_RD_SPD 4
#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD)
#define BC_V_SIZE 0
#define BC_M_SIZE (0x7<<BC_V_SIZE)
#define BC_K_CONFIG \
((0x1<<BC_V_WE_OFF) | \
(0x7<<BC_V_RD_WR_SPC) | \
(0x4<<BC_V_WR_SPD) | \
(0x4<<BC_V_RD_SPD) | \
(0x1<<BC_V_SIZE))
/*
**
** DECchip 21164 Privileged Architecture Library Entry Offsets:
**
** Entry Name Offset (Hex)
**
** RESET 0000
** IACCVIO 0080
** INTERRUPT 0100
** ITB_MISS 0180
** DTB_MISS (Single) 0200
** DTB_MISS (Double) 0280
** UNALIGN 0300
** D_FAULT 0380
** MCHK 0400
** OPCDEC 0480
** ARITH 0500
** FEN 0580
** CALL_PAL (Privileged) 2000
** CALL_PAL (Unprivileged) 3000
**
*/
#define PAL_RESET_ENTRY 0x0000
#define PAL_IACCVIO_ENTRY 0x0080
#define PAL_INTERRUPT_ENTRY 0x0100
#define PAL_ITB_MISS_ENTRY 0x0180
#define PAL_DTB_MISS_ENTRY 0x0200
#define PAL_DOUBLE_MISS_ENTRY 0x0280
#define PAL_UNALIGN_ENTRY 0x0300
#define PAL_D_FAULT_ENTRY 0x0380
#define PAL_MCHK_ENTRY 0x0400
#define PAL_OPCDEC_ENTRY 0x0480
#define PAL_ARITH_ENTRY 0x0500
#define PAL_FEN_ENTRY 0x0580
#define PAL_CALL_PAL_PRIV_ENTRY 0x2000
#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000
/*
**
** Architecturally Reserved Opcode (PALRES) Definitions:
**
*/
#define mtpr hw_mtpr
#define mfpr hw_mfpr
#define ldl_a hw_ldl/a
#define ldq_a hw_ldq/a
#define stq_a hw_stq/a
#define stl_a hw_stl/a
#define ldl_p hw_ldl/p
#define ldq_p hw_ldq/p
#define stl_p hw_stl/p
#define stq_p hw_stq/p
/*
** Virtual PTE fetch variants of HW_LD.
*/
#define ld_vpte hw_ldq/v
/*
** Physical mode load-lock and store-conditional variants of
** HW_LD and HW_ST.
*/
#define ldq_lp hw_ldq/pl
#define stq_cp hw_stq/pc
/*
**
** General Purpose Register Definitions:
**
*/
#define r0 $0
#define r1 $1
#define r2 $2
#define r3 $3
#define r4 $4
#define r5 $5
#define r6 $6
#define r7 $7
#define r8 $8
#define r9 $9
#define r10 $10
#define r11 $11
#define r12 $12
#define r13 $13
#define r14 $14
#define r15 $15
#define r16 $16
#define r17 $17
#define r18 $18
#define r19 $19
#define r20 $20
#define r21 $21
#define r22 $22
#define r23 $23
#define r24 $24
#define r25 $25
#define r26 $26
#define r27 $27
#define r28 $28
#define r29 $29
#define r30 $30
#define r31 $31
/*
**
** Floating Point Register Definitions:
**
*/
#define f0 $f0
#define f1 $f1
#define f2 $f2
#define f3 $f3
#define f4 $f4
#define f5 $f5
#define f6 $f6
#define f7 $f7
#define f8 $f8
#define f9 $f9
#define f10 $f10
#define f11 $f11
#define f12 $f12
#define f13 $f13
#define f14 $f14
#define f15 $f15
#define f16 $f16
#define f17 $f17
#define f18 $f18
#define f19 $f19
#define f20 $f20
#define f21 $f21
#define f22 $f22
#define f23 $f23
#define f24 $f24
#define f25 $f25
#define f26 $f26
#define f27 $f27
#define f28 $f28
#define f29 $f29
#define f30 $f30
#define f31 $f31
/*
**
** PAL Temporary Register Definitions:
**
*/
// covered by fetch distribution..pb Nov/95
// #define pt0 0x140
// #define pt1 0x141
// #define pt2 0x142
// #define pt3 0x143
// #define pt4 0x144
// #define pt5 0x145
// #define pt6 0x146
// #define pt7 0x147
// #define pt8 0x148
// #define pt9 0x149
// #define pt10 0x14A
// #define pt11 0x14B
// #define pt12 0x14C
// #define pt13 0x14D
// #define pt14 0x14E
// #define pt15 0x14F
// #define pt16 0x150
// #define pt17 0x151
// #define pt18 0x152
// #define pt19 0x153
// #define pt20 0x154
// #define pt21 0x155
// #define pt22 0x156
// #define pt23 0x157
/*
** PAL Shadow Registers:
**
** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and
** ICSR<SDE> = 1.
*/
#define p0 r8 /* ITB/DTB Miss Scratch */
#define p1 r9 /* ITB/DTB Miss Scratch */
#define p2 r10 /* ITB/DTB Miss Scratch */
#define p3 r11
// #define ps r11 /* Processor Status */
#define p4 r12 /* Local Scratch */
#define p5 r13 /* Local Scratch */
#define p6 r14 /* Local Scratch */
#define p7 r25 /* Local Scratch */
/*
** SRM Defined State Definitions:
*/
/*
** This table is an accounting of the DECchip 21164 storage used to
** implement the SRM defined state for OSF/1.
**
** IPR Name Internal Storage
** -------- ----------------
** Processor Status ps, dtbCm, ipl, r11
** Program Counter Ibox
** Interrupt Entry ptEntInt
** Arith Trap Entry ptEntArith
** MM Fault Entry ptEntMM
** Unaligned Access Entry ptEntUna
** Instruction Fault Entry ptEntIF
** Call System Entry ptEntSys
** User Stack Pointer ptUsp
** Kernel Stack Pointer ptKsp
** Kernel Global Pointer ptKgp
** System Value ptSysVal
** Page Table Base Register ptPtbr
** Virtual Page Table Base iVptBr, mVptBr
** Process Control Block Base ptPcbb
** Address Space Number itbAsn, dtbAsn
** Cycle Counter cc, ccCtl
** Float Point Enable icsr
** Lock Flag Cbox/System
** Unique PCB
** Who-Am-I ptWhami
*/
#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */
#define ptImpure pt3 /* Pointer To PAL Scratch Area */
#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */
#define ptIntMask pt8 /* Interrupt Enable Mask */
#define ptEntSys pt9 /* Call System Dispatch Entry */
#define ptTrap pt11
#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */
#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */
#if defined(KDEBUG)
#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */
#endif /* KDEBUG */
#define ptMisc pt16 /* Miscellaneous Flags */
#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */
#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */
#define ptSysVal pt17 /* Per-Processor System Value */
#define ptUsp pt18 /* User Stack Pointer */
#define ptKsp pt19 /* Kernel Stack Pointer */
#define ptPtbr pt20 /* Page Table Base Register */
#define ptEntMM pt21 /* MM Fault Dispatch Entry */
#define ptKgp pt22 /* Kernel Global Pointer */
#define ptPcbb pt23 /* Process Control Block Base */
/*
**
** Miscellaneous PAL State Flags (ptMisc) Bit Summary
**
** Extent Size Name Function
** ------ ---- ---- ---------------------------------
** <55:48> 8 SWAP Swap PALcode flag -- character 'S'
** <47:32> 16 MCHK Machine Check Error code
** <31:16> 16 SCB System Control Block vector
** <15:08> 8 WHAMI Who-Am-I identifier
** <04:00> 5 MCES Machine Check Error Summary bits
**
*/
#define PT16_V_MCES 0
#define PT16_V_WHAMI 8
#define PT16_V_SCB 16
#define PT16_V_MCHK 32
#define PT16_V_SWAP 48
#endif /* DC21164FROMGASSOURCES_INCLUDED */

314
system/alpha/h/ev5_alpha_defs.h Normal file
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@ -0,0 +1,314 @@
/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EV5_ALPHA_DEFS_INCLUDED
#define EV5_ALPHA_DEFS_INCLUDED 1
// from ev5_alpha_defs.mar from Lance's fetch directory
// Lower-caseified and $ signs removed ... pb Nov/95
//
// PS Layout - PS
// Loc Size name function
// ------ ------ ______ -----------------------------------
// <31:29> 3 SA stack alignment
// <31:13> 24 RES Reserved MBZ
// <12:8> 5 IPL Priority level
// <7> 1 VMM Virtual Mach Monitor
// <6:5> 2 RES Reserved MBZ
// <4:3> 2 CM Current Mode
// <2> 1 IP Interrupt Pending
// <1:0> 2 SW Software bits
//
#define ps_v_sw 0
#define ps_m_sw (3<<ps_v_sw)
#define ps_v_ip 2
#define ps_m_ip (1<<ps_v_ip)
#define ps_v_cm 3
#define ps_m_cm (3<<ps_v_cm)
#define ps_v_vmm 7
#define ps_m_vmm (1<<ps_v_vmm)
#define ps_v_ipl 8
#define ps_m_ipl (0x1f<<ps_v_ipl)
#define ps_v_sp (0x38)
#define ps_m_sp (0x3f<<ps_v_sp)
#define ps_c_kern (0x00)
#define ps_c_exec (0x08)
#define ps_c_supr (0x10)
#define ps_c_user (0x18)
#define ps_c_ipl0 (0x0000)
#define ps_c_ipl1 (0x0100)
#define ps_c_ipl2 (0x0200)
#define ps_c_ipl3 (0x0300)
#define ps_c_ipl4 (0x0400)
#define ps_c_ipl5 (0x0500)
#define ps_c_ipl6 (0x0600)
#define ps_c_ipl7 (0x0700)
#define ps_c_ipl8 (0x0800)
#define ps_c_ipl9 (0x0900)
#define ps_c_ipl10 (0x0A00)
#define ps_c_ipl11 (0x0B00)
#define ps_c_ipl12 (0x0C00)
#define ps_c_ipl13 (0x0D00)
#define ps_c_ipl14 (0x0E00)
#define ps_c_ipl15 (0x0F00)
#define ps_c_ipl16 (0x1000)
#define ps_c_ipl17 (0x1100)
#define ps_c_ipl18 (0x1200)
#define ps_c_ipl19 (0x1300)
#define ps_c_ipl20 (0x1400)
#define ps_c_ipl21 (0x1500)
#define ps_c_ipl22 (0x1600)
#define ps_c_ipl23 (0x1700)
#define ps_c_ipl24 (0x1800)
#define ps_c_ipl25 (0x1900)
#define ps_c_ipl26 (0x1A00)
#define ps_c_ipl27 (0x1B00)
#define ps_c_ipl28 (0x1C00)
#define ps_c_ipl29 (0x1D00)
#define ps_c_ipl30 (0x1E00)
#define ps_c_ipl31 (0x1F00)
//
// PTE layout - symbol prefix PTE_
//
// Loc Size name function
// ------ ------ ------ -----------------------------------
// <63:32> 32 PFN Page Frame Number
// <31:16> 16 SOFT Bits reserved for software use
// <15> 1 UWE User write enable
// <14> 1 SWE Super write enable
// <13> 1 EWE Exec write enable
// <12> 1 KWE Kernel write enable
// <11> 1 URE User read enable
// <10> 1 SRE Super read enable
// <9> 1 ERE Exec read enable
// <8> 1 KRE Kernel read enable
// <7:6> 2 RES Reserved SBZ
// <5> 1 HPF Huge Page Flag
// <4> 1 ASM Wild card address space number match
// <3> 1 FOE Fault On execute
// <2> 1 FOW Fault On Write
// <1> 1 FOR Fault On Read
// <0> 1 V valid bit
//
#define pte_v_pfn 32
#define pte_m_soft (0xFFFF0000)
#define pte_v_soft 16
#define pte_m_uwe (0x8000)
#define pte_v_uwe 15
#define pte_m_swe (0x4000)
#define pte_v_swe 14
#define pte_m_ewe (0x2000)
#define pte_v_ewe 13
#define pte_m_kwe (0x1000)
#define pte_v_kwe 12
#define pte_m_ure (0x0800)
#define pte_v_ure 11
#define pte_m_sre (0x0400)
#define pte_v_sre 10
#define pte_m_ere (0x0200)
#define pte_v_ere 9
#define pte_m_kre (0x0100)
#define pte_v_kre 8
#define pte_m_hpf (0x0020)
#define pte_v_hpf 5
#define pte_m_asm (0x0010)
#define pte_v_asm 4
#define pte_m_foe (0x0008)
#define pte_v_foe 3
#define pte_m_fow (0x0004)
#define pte_v_fow 2
#define pte_m_for (0x0002)
#define pte_v_for 1
#define pte_m_v (0x0001)
#define pte_v_v 0
//
// VA layout - symbol prefix VA_
//
// Loc Size name function
// ------ ------ ------- -----------------------------------
// <42:33> 10 SEG1 First seg table offset for mapping
// <32:23> 10 SEG2 Second seg table offset for mapping
// <22:13> 10 SEG3 Third seg table offset for mapping
// <12:0> 13 OFFSET Byte within page
//
#define va_m_offset (0x000000001FFF)
#define va_v_offset 0
#define va_m_seg3 (0x0000007FE000)
#define va_v_seg3 13
#define va_m_seg2 (0x0001FF800000)
#define va_v_seg2 23
#define va_m_seg1 (0x7FE00000000)
#define va_v_seg1 33
//
//PRIVILEGED CONTEXT BLOCK (PCB)
//
#define pcb_q_ksp 0
#define pcb_q_esp 8
#define pcb_q_ssp 16
#define pcb_q_usp 24
#define pcb_q_ptbr 32
#define pcb_q_asn 40
#define pcb_q_ast 48
#define pcb_q_fen 56
#define pcb_q_cc 64
#define pcb_q_unq 72
#define pcb_q_sct 80
#define pcb_v_asten 0
#define pcb_m_asten (0x0f<<pcb_v_asten)
#define pcb_v_astsr 4
#define pcb_m_astsr (0x0f<<pcb_v_astsr)
#define pcb_v_dat 63
#define pcb_v_pme 62
//
// SYSTEM CONTROL BLOCK (SCB)
//
#define scb_v_fen (0x0010)
#define scb_v_acv (0x0080)
#define scb_v_tnv (0x0090)
#define scb_v_for (0x00A0)
#define scb_v_fow (0x00B0)
#define scb_v_foe (0x00C0)
#define scb_v_arith (0x0200)
#define scb_v_kast (0x0240)
#define scb_v_east (0x0250)
#define scb_v_sast (0x0260)
#define scb_v_uast (0x0270)
#define scb_v_unalign (0x0280)
#define scb_v_bpt (0x0400)
#define scb_v_bugchk (0x0410)
#define scb_v_opcdec (0x0420)
#define scb_v_illpal (0x0430)
#define scb_v_trap (0x0440)
#define scb_v_chmk (0x0480)
#define scb_v_chme (0x0490)
#define scb_v_chms (0x04A0)
#define scb_v_chmu (0x04B0)
#define scb_v_sw0 (0x0500)
#define scb_v_sw1 (0x0510)
#define scb_v_sw2 (0x0520)
#define scb_v_sw3 (0x0530)
#define scb_v_sw4 (0x0540)
#define scb_v_sw5 (0x0550)
#define scb_v_sw6 (0x0560)
#define scb_v_sw7 (0x0570)
#define scb_v_sw8 (0x0580)
#define scb_v_sw9 (0x0590)
#define scb_v_sw10 (0x05A0)
#define scb_v_sw11 (0x05B0)
#define scb_v_sw12 (0x05C0)
#define scb_v_sw13 (0x05D0)
#define scb_v_sw14 (0x05E0)
#define scb_v_sw15 (0x05F0)
#define scb_v_clock (0x0600)
#define scb_v_inter (0x0610)
#define scb_v_sys_corr_err (0x0620)
#define scb_v_proc_corr_err (0x0630)
#define scb_v_pwrfail (0x0640)
#define scb_v_perfmon (0x0650)
#define scb_v_sysmchk (0x0660)
#define scb_v_procmchk (0x0670)
#define scb_v_passive_rel (0x06F0)
//
// Stack frame (FRM)
//
#define frm_v_r2 (0x0000)
#define frm_v_r3 (0x0008)
#define frm_v_r4 (0x0010)
#define frm_v_r5 (0x0018)
#define frm_v_r6 (0x0020)
#define frm_v_r7 (0x0028)
#define frm_v_pc (0x0030)
#define frm_v_ps (0x0038)
//
// Exeception summary register (EXS)
//
// exs_v_swc <0> ; Software completion
// exs_v_inv <1> ; Ivalid operation
// exs_v_dze <2> ; Div by zero
// exs_v_fov <3> ; Floating point overflow
// exs_v_unf <4> ; Floating point underflow
// exs_v_ine <5> ; Floating point inexact
// exs_v_iov <6> ; Floating convert to integer overflow
#define exs_v_swc 0
#define exs_v_inv 1
#define exs_v_dze 2
#define exs_v_fov 3
#define exs_v_unf 4
#define exs_v_ine 5
#define exs_v_iov 6
#define exs_m_swc (1<<exs_v_swc)
#define exs_m_inv (1<<exs_v_inv)
#define exs_m_dze (1<<exs_v_dze)
#define exs_m_fov (1<<exs_v_fov)
#define exs_m_unf (1<<exs_v_unf)
#define exs_m_ine (1<<exs_v_ine)
#define exs_m_iov (1<<exs_v_iov)
//
// machine check error summary register (mces)
//
// mces_v_mchk <0> ; machine check in progress
// mces_v_sce <1> ; system correctable error
// mces_v_pce <2> ; processor correctable error
// mces_v_dpc <3> ; disable reporting of processor correctable errors
// mces_v_dsc <4> ; disable reporting of system correctable errors
#define mces_v_mchk 0
#define mces_v_sce 1
#define mces_v_pce 2
#define mces_v_dpc 3
#define mces_v_dsc 4
#define mces_m_mchk (1<<mces_v_mchk)
#define mces_m_sce (1<<mces_v_sce)
#define mces_m_pce (1<<mces_v_pce)
#define mces_m_dpc (1<<mces_v_dpc)
#define mces_m_dsc (1<<mces_v_dsc)
#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc))
#endif

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/*
* Copyright (c) 1995 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EV5_DEFS_INCLUDED
#define EV5_DEFS_INCLUDED 1
// adapted from the version emailed to lance..pb Nov/95
// In the definitions below, registers are annotated with one of the
// following symbols:
//
// RW - The register may be read and written
// RO - The register may only be read
// WO - The register may only be written
//
// For RO and WO registers, all bits and fields within the register
// are also read-only or write-only. For RW registers, each bit or
// field within the register is annotated with one of the following:
//
// RW - The bit/field may be read and written
// RO - The bit/field may be read; writes are ignored
// WO - The bit/field may be written; reads return an UNPREDICTABLE result
// WZ - The bit/field may be written; reads return a 0
// WC - The bit/field may be read; writes cause state to clear
// RC - The bit/field may be read, which also causes state to clear;
// writes are ignored
// Architecturally-defined (SRM) registers for EVMS
#define pt0 320
#define pt1 321
#define pt2 322
#define pt3 323
#define pt4 324
#define pt5 325
#define pt6 326
#define pt7 327
#define pt8 328
#define pt9 329
#define pt10 330
#define pt11 331
#define pt12 332
#define pt13 333
#define pt14 334
#define pt15 335
#define pt16 336
#define pt17 337
#define pt18 338
#define pt19 339
#define pt20 340
#define pt21 341
#define pt22 342
#define pt23 343
#define cbox_ipr_offset 16777200
#define sc_ctl 168
#define sc_stat 232
#define sc_addr 392
#define sc_addr_nm 392
#define sc_addr_fhm 392
#define bc_ctl 296
#define bc_config 456
#define ei_stat 360
#define ei_addr 328
#define fill_syn 104
#define bc_tag_addr 264
#define ld_lock 488
#define aster 266
#define astrr 265
#define exc_addr 267
#define exc_sum 268
#define exc_mask 269
#define hwint_clr 277
#define ic_flush_ctl 281
#define icperr_stat 282
#define ic_perr_stat 282
#define ic_row_map 283
#define icsr 280
#define ifault_va_form 274
#define intid 273
#define ipl 272
#define isr 256
#define itb_is 263
#define itb_asn 259
#define itb_ia 261
#define itb_iap 262
#define itb_pte 258
#define itb_pte_temp 260
#define itb_tag 257
#define ivptbr 275
#define pal_base 270
#define pmctr 284
// this is not the register ps .. pb #define ps 271
#define sirr 264
#define sl_txmit 278
#define sl_rcv 279
#define alt_mode 524
#define cc 525
#define cc_ctl 526
#define dc_flush 528
#define dcperr_stat 530
#define dc_test_ctl 531
#define dc_test_tag 532
#define dc_test_tag_temp 533
#define dtb_asn 512
#define dtb_cm 513
#define dtb_ia 522
#define dtb_iap 521
#define dtb_is 523
#define dtb_pte 515
#define dtb_pte_temp 516
#define dtb_tag 514
#define mcsr 527
#define dc_mode 534
#define maf_mode 535
#define mm_stat 517
#define mvptbr 520
#define va 518
#define va_form 519
#define ev5_srm__ps 0
#define ev5_srm__pc 0
#define ev5_srm__asten 0
#define ev5_srm__astsr 0
#define ev5_srm__ipir 0
#define ev5_srm__ipl 0
#define ev5_srm__mces 0
#define ev5_srm__pcbb 0
#define ev5_srm__prbr 0
#define ev5_srm__ptbr 0
#define ev5_srm__scbb 0
#define ev5_srm__sirr 0
#define ev5_srm__sisr 0
#define ev5_srm__tbchk 0
#define ev5_srm__tb1a 0
#define ev5_srm__tb1ap 0
#define ev5_srm__tb1ad 0
#define ev5_srm__tb1ai 0
#define ev5_srm__tbis 0
#define ev5_srm__ksp 0
#define ev5_srm__esp 0
#define ev5_srm__ssp 0
#define ev5_srm__usp 0
#define ev5_srm__vptb 0
#define ev5_srm__whami 0
#define ev5_srm__cc 0
#define ev5_srm__unq 0
// processor-specific iprs.
#define ev5__sc_ctl 168
#define ev5__sc_stat 232
#define ev5__sc_addr 392
#define ev5__bc_ctl 296
#define ev5__bc_config 456
#define bc_config_k_size_1mb 1
#define bc_config_k_size_2mb 2
#define bc_config_k_size_4mb 3
#define bc_config_k_size_8mb 4
#define bc_config_k_size_16mb 5
#define bc_config_k_size_32mb 6
#define bc_config_k_size_64mb 7
#define ev5__ei_stat 360
#define ev5__ei_addr 328
#define ev5__fill_syn 104
#define ev5__bc_tag_addr 264
#define ev5__aster 266
#define ev5__astrr 265
#define ev5__exc_addr 267
#define exc_addr_v_pa 2
#define exc_addr_s_pa 62
#define ev5__exc_sum 268
#define ev5__exc_mask 269
#define ev5__hwint_clr 277
#define ev5__ic_flush_ctl 281
#define ev5__icperr_stat 282
#define ev5__ic_perr_stat 282
#define ev5__ic_row_map 283
#define ev5__icsr 280
#define ev5__ifault_va_form 274
#define ev5__ifault_va_form_nt 274
#define ifault_va_form_nt_v_vptb 30
#define ifault_va_form_nt_s_vptb 34
#define ev5__intid 273
#define ev5__ipl 272
#define ev5__itb_is 263
#define ev5__itb_asn 259
#define ev5__itb_ia 261
#define ev5__itb_iap 262
#define ev5__itb_pte 258
#define ev5__itb_pte_temp 260
#define ev5__itb_tag 257
#define ev5__ivptbr 275
#define ivptbr_v_vptb 30
#define ivptbr_s_vptb 34
#define ev5__pal_base 270
#define ev5__pmctr 284
#define ev5__ps 271
#define ev5__isr 256
#define ev5__sirr 264
#define ev5__sl_txmit 278
#define ev5__sl_rcv 279
#define ev5__alt_mode 524
#define ev5__cc 525
#define ev5__cc_ctl 526
#define ev5__dc_flush 528
#define ev5__dcperr_stat 530
#define ev5__dc_test_ctl 531
#define ev5__dc_test_tag 532
#define ev5__dc_test_tag_temp 533
#define ev5__dtb_asn 512
#define ev5__dtb_cm 513
#define ev5__dtb_ia 522
#define ev5__dtb_iap 521
#define ev5__dtb_is 523
#define ev5__dtb_pte 515
#define ev5__dtb_pte_temp 516
#define ev5__dtb_tag 514
#define ev5__mcsr 527
#define ev5__dc_mode 534
#define ev5__maf_mode 535
#define ev5__mm_stat 517
#define ev5__mvptbr 520
#define ev5__va 518
#define ev5__va_form 519
#define ev5__va_form_nt 519
#define va_form_nt_s_va 19
#define va_form_nt_v_vptb 30
#define va_form_nt_s_vptb 34
#define ev5s_ev5_def 10
#define ev5_def 0
// cbox registers.
#define sc_ctl_v_sc_fhit 0
#define sc_ctl_v_sc_flush 1
#define sc_ctl_s_sc_tag_stat 6
#define sc_ctl_v_sc_tag_stat 2
#define sc_ctl_s_sc_fb_dp 4
#define sc_ctl_v_sc_fb_dp 8
#define sc_ctl_v_sc_blk_size 12
#define sc_ctl_s_sc_set_en 3
#define sc_ctl_v_sc_set_en 13
#define sc_ctl_s_sc_soft_repair 3
#define sc_ctl_v_sc_soft_repair 16
#define sc_stat_s_sc_tperr 3
#define sc_stat_v_sc_tperr 0
#define sc_stat_s_sc_dperr 8
#define sc_stat_v_sc_dperr 3
#define sc_stat_s_cbox_cmd 5
#define sc_stat_v_cbox_cmd 11
#define sc_stat_v_sc_scnd_err 16
#define sc_addr_fhm_v_sc_tag_parity 4
#define sc_addr_fhm_s_tag_stat_sb0 3
#define sc_addr_fhm_v_tag_stat_sb0 5
#define sc_addr_fhm_s_tag_stat_sb1 3
#define sc_addr_fhm_v_tag_stat_sb1 8
#define sc_addr_fhm_s_ow_mod0 2
#define sc_addr_fhm_v_ow_mod0 11
#define sc_addr_fhm_s_ow_mod1 2
#define sc_addr_fhm_v_ow_mod1 13
#define sc_addr_fhm_s_tag_lo 17
#define sc_addr_fhm_v_tag_lo 15
#define sc_addr_fhm_s_tag_hi 7
#define sc_addr_fhm_v_tag_hi 32
#define bc_ctl_v_bc_enabled 0
#define bc_ctl_v_alloc_cyc 1
#define bc_ctl_v_ei_opt_cmd 2
#define bc_ctl_v_ei_opt_cmd_mb 3
#define bc_ctl_v_corr_fill_dat 4
#define bc_ctl_v_vtm_first 5
#define bc_ctl_v_ei_ecc_or_parity 6
#define bc_ctl_v_bc_fhit 7
#define bc_ctl_s_bc_tag_stat 5
#define bc_ctl_v_bc_tag_stat 8
#define bc_ctl_s_bc_bad_dat 2
#define bc_ctl_v_bc_bad_dat 13
#define bc_ctl_v_ei_dis_err 15
#define bc_ctl_v_tl_pipe_latch 16
#define bc_ctl_s_bc_wave_pipe 2
#define bc_ctl_v_bc_wave_pipe 17
#define bc_ctl_s_pm_mux_sel 6
#define bc_ctl_v_pm_mux_sel 19
#define bc_ctl_v_dbg_mux_sel 25
#define bc_ctl_v_dis_baf_byp 26
#define bc_ctl_v_dis_sc_vic_buf 27
#define bc_ctl_v_dis_sys_addr_par 28
#define bc_ctl_v_read_dirty_cln_shr 29
#define bc_ctl_v_write_read_bubble 30
#define bc_ctl_v_bc_wave_pipe_2 31
#define bc_ctl_v_auto_dack 32
#define bc_ctl_v_dis_byte_word 33
#define bc_ctl_v_stclk_delay 34
#define bc_ctl_v_write_under_miss 35
#define bc_config_s_bc_size 3
#define bc_config_v_bc_size 0
#define bc_config_s_bc_rd_spd 4
#define bc_config_v_bc_rd_spd 4
#define bc_config_s_bc_wr_spd 4
#define bc_config_v_bc_wr_spd 8
#define bc_config_s_bc_rd_wr_spc 3
#define bc_config_v_bc_rd_wr_spc 12
#define bc_config_s_fill_we_offset 3
#define bc_config_v_fill_we_offset 16
#define bc_config_s_bc_we_ctl 9
#define bc_config_v_bc_we_ctl 20
// cbox registers, continued
#define ei_stat_s_sys_id 4
#define ei_stat_v_sys_id 24
#define ei_stat_v_bc_tperr 28
#define ei_stat_v_bc_tc_perr 29
#define ei_stat_v_ei_es 30
#define ei_stat_v_cor_ecc_err 31
#define ei_stat_v_unc_ecc_err 32
#define ei_stat_v_ei_par_err 33
#define ei_stat_v_fil_ird 34
#define ei_stat_v_seo_hrd_err 35
//
#define bc_tag_addr_v_hit 12
#define bc_tag_addr_v_tagctl_p 13
#define bc_tag_addr_v_tagctl_d 14
#define bc_tag_addr_v_tagctl_s 15
#define bc_tag_addr_v_tagctl_v 16
#define bc_tag_addr_v_tag_p 17
#define bc_tag_addr_s_bc_tag 19
#define bc_tag_addr_v_bc_tag 20
// ibox and icache registers.
#define aster_v_kar 0
#define aster_v_ear 1
#define aster_v_sar 2
#define aster_v_uar 3
#define astrr_v_kar 0
#define astrr_v_ear 1
#define astrr_v_sar 2
#define astrr_v_uar 3
#define exc_addr_v_pal 0
#define exc_sum_v_swc 10
#define exc_sum_v_inv 11
#define exc_sum_v_dze 12
#define exc_sum_v_fov 13
#define exc_sum_v_unf 14
#define exc_sum_v_ine 15
#define exc_sum_v_iov 16
#define hwint_clr_v_pc0c 27
#define hwint_clr_v_pc1c 28
#define hwint_clr_v_pc2c 29
#define hwint_clr_v_crdc 32
#define hwint_clr_v_slc 33
// ibox and icache registers, continued
#define icperr_stat_v_dpe 11
#define icperr_stat_v_tpe 12
#define icperr_stat_v_tmr 13
#define ic_perr_stat_v_dpe 11
#define ic_perr_stat_v_tpe 12
#define ic_perr_stat_v_tmr 13
#define icsr_v_pma 8
#define icsr_v_pmp 9
#define icsr_v_byt 17
#define icsr_v_fmp 18
#define icsr_v_im0 20
#define icsr_v_im1 21
#define icsr_v_im2 22
#define icsr_v_im3 23
#define icsr_v_tmm 24
#define icsr_v_tmd 25
#define icsr_v_fpe 26
#define icsr_v_hwe 27
#define icsr_s_spe 2
#define icsr_v_spe 28
#define icsr_v_sde 30
#define icsr_v_crde 32
#define icsr_v_sle 33
#define icsr_v_fms 34
#define icsr_v_fbt 35
#define icsr_v_fbd 36
#define icsr_v_dbs 37
#define icsr_v_ista 38
#define icsr_v_tst 39
#define ifault_va_form_s_va 30
#define ifault_va_form_v_va 3
#define ifault_va_form_s_vptb 31
#define ifault_va_form_v_vptb 33
#define ifault_va_form_nt_s_va 19
#define ifault_va_form_nt_v_va 3
#define intid_s_intid 5
#define intid_v_intid 0
// ibox and icache registers, continued
#define ipl_s_ipl 5
#define ipl_v_ipl 0
#define itb_is_s_va 30
#define itb_is_v_va 13
#define itb_asn_s_asn 7
#define itb_asn_v_asn 4
#define itb_pte_v_asm 4
#define itb_pte_s_gh 2
#define itb_pte_v_gh 5
#define itb_pte_v_kre 8
#define itb_pte_v_ere 9
#define itb_pte_v_sre 10
#define itb_pte_v_ure 11
#define itb_pte_s_pfn 27
#define itb_pte_v_pfn 32
#define itb_pte_temp_v_asm 13
#define itb_pte_temp_v_kre 18
#define itb_pte_temp_v_ere 19
#define itb_pte_temp_v_sre 20
#define itb_pte_temp_v_ure 21
#define itb_pte_temp_s_gh 3
#define itb_pte_temp_v_gh 29
#define itb_pte_temp_s_pfn 27
#define itb_pte_temp_v_pfn 32
// ibox and icache registers, continued
#define itb_tag_s_va 30
#define itb_tag_v_va 13
#define pal_base_s_pal_base 26
#define pal_base_v_pal_base 14
#define pmctr_s_sel2 4
#define pmctr_v_sel2 0
#define pmctr_s_sel1 4
#define pmctr_v_sel1 4
#define pmctr_v_killk 8
#define pmctr_v_killp 9
#define pmctr_s_ctl2 2
#define pmctr_v_ctl2 10
#define pmctr_s_ctl1 2
#define pmctr_v_ctl1 12
#define pmctr_s_ctl0 2
#define pmctr_v_ctl0 14
#define pmctr_s_ctr2 14
#define pmctr_v_ctr2 16
#define pmctr_v_killu 30
#define pmctr_v_sel0 31
#define pmctr_s_ctr1 16
#define pmctr_v_ctr1 32
#define pmctr_s_ctr0 16
#define pmctr_v_ctr0 48
#define ps_v_cm0 3
#define ps_v_cm1 4
#define isr_s_astrr 4
#define isr_v_astrr 0
#define isr_s_sisr 15
#define isr_v_sisr 4
#define isr_v_atr 19
#define isr_v_i20 20
#define isr_v_i21 21
#define isr_v_i22 22
#define isr_v_i23 23
#define isr_v_pc0 27
#define isr_v_pc1 28
#define isr_v_pc2 29
#define isr_v_pfl 30
#define isr_v_mck 31
#define isr_v_crd 32
#define isr_v_sli 33
#define isr_v_hlt 34
#define sirr_s_sirr 15
#define sirr_v_sirr 4
// ibox and icache registers, continued
#define sl_txmit_v_tmt 7
#define sl_rcv_v_rcv 6
// mbox and dcache registers.
#define alt_mode_v_am0 3
#define alt_mode_v_am1 4
#define cc_ctl_v_cc_ena 32
#define dcperr_stat_v_seo 0
#define dcperr_stat_v_lock 1
#define dcperr_stat_v_dp0 2
#define dcperr_stat_v_dp1 3
#define dcperr_stat_v_tp0 4
#define dcperr_stat_v_tp1 5
// the following two registers are used exclusively for test and diagnostics.
// they should not be referenced in normal operation.
#define dc_test_ctl_v_bank0 0
#define dc_test_ctl_v_bank1 1
#define dc_test_ctl_v_fill_0 2
#define dc_test_ctl_s_index 10
#define dc_test_ctl_v_index 3
#define dc_test_ctl_s_fill_1 19
#define dc_test_ctl_v_fill_1 13
#define dc_test_ctl_s_fill_2 32
#define dc_test_ctl_v_fill_2 32
// mbox and dcache registers, continued.
#define dc_test_tag_v_tag_par 2
#define dc_test_tag_v_ow0 11
#define dc_test_tag_v_ow1 12
#define dc_test_tag_s_tag 26
#define dc_test_tag_v_tag 13
#define dc_test_tag_temp_v_tag_par 2
#define dc_test_tag_temp_v_d0p0 3
#define dc_test_tag_temp_v_d0p1 4
#define dc_test_tag_temp_v_d1p0 5
#define dc_test_tag_temp_v_d1p1 6
#define dc_test_tag_temp_v_ow0 11
#define dc_test_tag_temp_v_ow1 12
#define dc_test_tag_temp_s_tag 26
#define dc_test_tag_temp_v_tag 13
#define dtb_asn_s_asn 7
#define dtb_asn_v_asn 57
#define dtb_cm_v_cm0 3
#define dtb_cm_v_cm1 4
#define dtbis_s_va0 30
#define dtbis_v_va0 13
#define dtb_pte_v_for 1
#define dtb_pte_v_fow 2
#define dtb_pte_v_asm 4
#define dtb_pte_s_gh 2
#define dtb_pte_v_gh 5
#define dtb_pte_v_kre 8
#define dtb_pte_v_ere 9
#define dtb_pte_v_sre 10
#define dtb_pte_v_ure 11
#define dtb_pte_v_kwe 12
#define dtb_pte_v_ewe 13
#define dtb_pte_v_swe 14
#define dtb_pte_v_uwe 15
#define dtb_pte_s_pfn 27
#define dtb_pte_v_pfn 32
// mbox and dcache registers, continued.
#define dtb_pte_temp_v_for 0
#define dtb_pte_temp_v_fow 1
#define dtb_pte_temp_v_kre 2
#define dtb_pte_temp_v_ere 3
#define dtb_pte_temp_v_sre 4
#define dtb_pte_temp_v_ure 5
#define dtb_pte_temp_v_kwe 6
#define dtb_pte_temp_v_ewe 7
#define dtb_pte_temp_v_swe 8
#define dtb_pte_temp_v_uwe 9
#define dtb_pte_temp_v_asm 10
#define dtb_pte_temp_s_fill_0 2
#define dtb_pte_temp_v_fill_0 11
#define dtb_pte_temp_s_pfn 27
#define dtb_pte_temp_v_pfn 13
#define dtb_tag_s_va 30
#define dtb_tag_v_va 13
// most mcsr bits are used for testability and diagnostics only.
// for normal operation, they will be supported in the following configuration:
// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0,
// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0
#define mcsr_v_big_endian 0
#define mcsr_v_sp0 1
#define mcsr_v_sp1 2
#define mcsr_v_mbox_sel 3
#define mcsr_v_e_big_endian 4
#define mcsr_v_dbg_packet_sel 5
#define dc_mode_v_dc_ena 0
#define dc_mode_v_dc_fhit 1
#define dc_mode_v_dc_bad_parity 2
#define dc_mode_v_dc_perr_dis 3
#define dc_mode_v_dc_doa 4
#define maf_mode_v_maf_nomerge 0
#define maf_mode_v_wb_flush_always 1
#define maf_mode_v_wb_nomerge 2
#define maf_mode_v_io_nomerge 3
#define maf_mode_v_wb_cnt_disable 4
#define maf_mode_v_maf_arb_disable 5
#define maf_mode_v_dread_pending 6
#define maf_mode_v_wb_pending 7
// mbox and dcache registers, continued.
#define mm_stat_v_wr 0
#define mm_stat_v_acv 1
#define mm_stat_v_for 2
#define mm_stat_v_fow 3
#define mm_stat_v_dtb_miss 4
#define mm_stat_v_bad_va 5
#define mm_stat_s_ra 5
#define mm_stat_v_ra 6
#define mm_stat_s_opcode 6
#define mm_stat_v_opcode 11
#define mvptbr_s_vptb 31
#define mvptbr_v_vptb 33
#define va_form_s_va 30
#define va_form_v_va 3
#define va_form_s_vptb 31
#define va_form_v_vptb 33
#define va_form_nt_s_va 19
#define va_form_nt_v_va 3
//.endm
#endif

420
system/alpha/h/ev5_impure.h Normal file
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/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EV5_IMPURE_INCLUDED
#define EV5_IMPURE_INCLUDED
// This uses the Hudson file format from "impure.h" but with the fields from
// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
// file: impure.sdl
//
// PAL impure scratch area and logout area data structure definitions for
// Alpha firmware.
//
//
// module $pal_impure;
//
// Edit Date Who Description
// ---- --------- --- ---------------------
// 1 7-Jul-93 JEM Initial Entry
// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area
// Delete mvptbr
// Calculate pal$logout from end of impure area
// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions
// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl,
// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat,
// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat,
// ei_addr, fill_syn, ld_lock
// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be
// consistent with ev4
// add cns$ipr_offset
// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again.
// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant
// to mchk logout frame
//
//
// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file
//orig
/*
** Macros for saving/restoring data to/from the PAL impure scratch
** area.
**
** The console save state area is larger than the addressibility
** of the HW_LD/ST instructions (10-bit signed byte displacement),
** so some adjustments to the base offsets, as well as the offsets
** within each base region, are necessary.
**
** The console save state area is divided into two segments; the
** CPU-specific segment and the platform-specific segment. The
** state that is saved in the CPU-specific segment includes GPRs,
** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved
** in the platform-specific segment.
**
** The impure pointer will need to be adjusted by a different offset
** value for each region within a given segment. The SAVE and RESTORE
** macros will auto-magically adjust the offsets accordingly.
**
*/
//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
#define SEXT10(X) ((X) & 0x3ff)
//#define SEXT10(X) (((X) << 55) >> 55)
#define SAVE_GPR(reg,offset,base) \
stq_p reg, (SEXT10(offset-0x200))(base)
#define RESTORE_GPR(reg,offset,base) \
ldq_p reg, (SEXT10(offset-0x200))(base)
#define SAVE_FPR(reg,offset,base) \
stt reg, (SEXT10(offset-0x200))(base)
#define RESTORE_FPR(reg,offset,base) \
ldt reg, (SEXT10(offset-0x200))(base)
#define SAVE_IPR(reg,offset,base) \
mfpr v0, reg; \
stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base)
#define RESTORE_IPR(reg,offset,base) \
ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \
mtpr v0, reg
#define SAVE_SHADOW(reg,offset,base) \
stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
#define RESTORE_SHADOW(reg,offset,base)\
ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
/* Structure of the processor-specific impure area */
/* aggregate impure struct prefix "" tag "";
* cns$flag quadword;
* cns$hlt quadword;
*/
/* Define base for debug monitor compatibility */
#define CNS_Q_BASE 0x000
#define CNS_Q_FLAG 0x100
#define CNS_Q_HALT 0x108
/* constant (
* cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
* cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
* cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
* cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
* ) equals . increment 8 prefix "" tag "";
* cns$gpr quadword dimension 32;
*/
/* Offset to base of saved GPR area - 32 quadword */
#define CNS_Q_GPR 0x110
#define cns_gpr CNS_Q_GPR
/* constant (
* cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
* cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
* cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
* cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
* ) equals . increment 8 prefix "" tag "";
* cns$fpr quadword dimension 32;
*/
/* Offset to base of saved FPR area - 32 quadwords */
#define CNS_Q_FPR 0x210
/* #t=.;
* cns$mchkflag quadword;
*/
#define CNS_Q_MCHK 0x310
/* constant cns$pt_offset equals .;
* constant (
* cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
* cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
* cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
* cns$pt21,cns$pt22,cns$pt23
* ) equals . increment 8 prefix "" tag "";
* cns$pt quadword dimension 24;
*/
/* Offset to base of saved PALtemp area - 25 quadwords */
#define CNS_Q_PT 0x318
/* cns$shadow8 quadword;
* cns$shadow9 quadword;
* cns$shadow10 quadword;
* cns$shadow11 quadword;
* cns$shadow12 quadword;
* cns$shadow13 quadword;
* cns$shadow14 quadword;
* cns$shadow25 quadword;
*/
/* Offset to base of saved PALshadow area - 8 quadwords */
#define CNS_Q_SHADOW 0x3D8
/* Offset to base of saved IPR area */
#define CNS_Q_IPR 0x418
/* constant cns$ipr_offset equals .; */
/* cns$exc_addr quadword; */
#define CNS_Q_EXC_ADDR 0x418
/* cns$pal_base quadword; */
#define CNS_Q_PAL_BASE 0x420
/* cns$mm_stat quadword; */
#define CNS_Q_MM_STAT 0x428
/* cns$va quadword; */
#define CNS_Q_VA 0x430
/* cns$icsr quadword; */
#define CNS_Q_ICSR 0x438
/* cns$ipl quadword; */
#define CNS_Q_IPL 0x440
/* cns$ps quadword; // Ibox current mode */
#define CNS_Q_IPS 0x448
/* cns$itb_asn quadword; */
#define CNS_Q_ITB_ASN 0x450
/* cns$aster quadword; */
#define CNS_Q_ASTER 0x458
/* cns$astrr quadword; */
#define CNS_Q_ASTRR 0x460
/* cns$isr quadword; */
#define CNS_Q_ISR 0x468
/* cns$ivptbr quadword; */
#define CNS_Q_IVPTBR 0x470
/* cns$mcsr quadword; */
#define CNS_Q_MCSR 0x478
/* cns$dc_mode quadword; */
#define CNS_Q_DC_MODE 0x480
/* cns$maf_mode quadword; */
#define CNS_Q_MAF_MODE 0x488
/* cns$sirr quadword; */
#define CNS_Q_SIRR 0x490
/* cns$fpcsr quadword; */
#define CNS_Q_FPCSR 0x498
/* cns$icperr_stat quadword; */
#define CNS_Q_ICPERR_STAT 0x4A0
/* cns$pmctr quadword; */
#define CNS_Q_PM_CTR 0x4A8
/* cns$exc_sum quadword; */
#define CNS_Q_EXC_SUM 0x4B0
/* cns$exc_mask quadword; */
#define CNS_Q_EXC_MASK 0x4B8
/* cns$intid quadword; */
#define CNS_Q_INT_ID 0x4C0
/* cns$dcperr_stat quadword; */
#define CNS_Q_DCPERR_STAT 0x4C8
/* cns$sc_stat quadword; */
#define CNS_Q_SC_STAT 0x4D0
/* cns$sc_addr quadword; */
#define CNS_Q_SC_ADDR 0x4D8
/* cns$sc_ctl quadword; */
#define CNS_Q_SC_CTL 0x4E0
/* cns$bc_tag_addr quadword; */
#define CNS_Q_BC_TAG_ADDR 0x4E8
/* cns$ei_stat quadword; */
#define CNS_Q_EI_STAT 0x4F0
/* cns$ei_addr quadword; */
#define CNS_Q_EI_ADDR 0x4F8
/* cns$fill_syn quadword; */
#define CNS_Q_FILL_SYN 0x500
/* cns$ld_lock quadword; */
#define CNS_Q_LD_LOCK 0x508
/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */
#define CNS_Q_BC_CTL 0x510
/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */
#define CNS_Q_PM_CTL 0x518
/* cns$bc_config quadword; // shadow of on chip bc_config */
#define CNS_Q_BC_CFG 0x520
/* constant cns$size equals .;
*
* constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
* constant pal$impure_specific_size equals (.+7) & %xfff8;
* constant cns$mchksize equals (.+7-#t) & %xfff8;
* constant pal$logout_area equals pal$impure_specific_size ;
* end impure;
*/
/* This next set of stuff came from the old code ..pb */
#define CNS_Q_SROM_REV 0x528
#define CNS_Q_PROC_ID 0x530
#define CNS_Q_MEM_SIZE 0x538
#define CNS_Q_CYCLE_CNT 0x540
#define CNS_Q_SIGNATURE 0x548
#define CNS_Q_PROC_MASK 0x550
#define CNS_Q_SYSCTX 0x558
#define MACHINE_CHECK_CRD_BASE 0
#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8)
/*
* aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
* SPROCESS bitfield length 1 ;
* FILL_0 bitfield length 3 fill tag $$;
* FRQ2 bitfield length 2 ;
* FRQ1 bitfield length 2 ;
* FRQ0 bitfield length 2 ;
* CTL2 bitfield length 2 ;
* CTL1 bitfield length 2 ;
* CTL0 bitfield length 2 ;
* FILL_1 bitfield length 16 fill tag $$;
* FILL_2 bitfield length 32 fill tag $$;
* end EV5PMCTRCTL_BITS;
*
* end_module $pal_impure;
*
* module $pal_logout;
*
* //
* // Start definition of Corrected Error Frame
* //
*/
/*
* aggregate crd_logout struct prefix "" tag "";
*/
#define pal_logout_area 0x600
#define mchk_crd_base 0
/* mchk$crd_flag quadword; */
#define mchk_crd_flag 0
/* mchk$crd_offsets quadword; */
#define mchk_crd_offsets 8
/*
* // Pal-specific information */
#define mchk_crd_mchk_code 0x10
/* mchk$crd_mchk_code quadword;
*
* // CPU-specific information
* constant mchk$crd_cpu_base equals . ;
* mchk$crd_ei_addr quadword; */
#define mchk_crd_ei_addr 0x18
/* mchk$crd_fill_syn quadword; */
#define mchk_crd_fill_syn 0x20
/* mchk$crd_ei_stat quadword; */
#define mchk_crd_ei_stat 0x28
/* mchk$crd_isr quadword; */
#define mchk_crd_isr 0x30
/*
* Hacked up constants for the turbolaser build. Hope
* this is moreless correct
*/
#define mchk_crd_whami 0x38
#define mchk_crd_tldev 0x40
#define mchk_crd_tlber 0x48
#define mchk_crd_tlesr0 0x50
#define mchk_crd_tlesr1 0x58
#define mchk_crd_tlesr2 0x60
#define mchk_crd_tlesr3 0x68
#define mchk_crd_rsvd 0x70
/*
* mchk area seems different for tlaser
*/
#define mchk_crd_size 0x80
#define mchk_mchk_base (mchk_crd_size)
#define mchk_tlber 0x0
#define mchk_tlepaerr 0x8
#define mchk_tlepderr 0x10
#define mchk_tlepmerr 0x18
/*
* // System-specific information
* constant mchk$crd_sys_base equals . ;
* constant mchk$crd_size equals (.+7) & %xfff8;
*
* end crd_logout;
* //
* // Start definition of Machine check logout Frame
* //
* aggregate logout struct prefix "" tag "";
* mchk$flag quadword; */
/* mchk$offsets quadword; */
/*
* // Pal-specific information
* mchk$mchk_code quadword; */
/*
* mchk$pt quadword dimension 24;
*
* // CPU-specific information
* constant mchk$cpu_base equals . ;
* mchk$exc_addr quadword;
* mchk$exc_sum quadword;
* mchk$exc_mask quadword;
* mchk$pal_base quadword;
* mchk$isr quadword;
* mchk$icsr quadword;
* mchk$ic_perr_stat quadword;
* mchk$dc_perr_stat quadword;
* mchk$va quadword;
* mchk$mm_stat quadword;
* mchk$sc_addr quadword;
* mchk$sc_stat quadword;
* mchk$bc_tag_addr quadword;
* mchk$ei_addr quadword;
* mchk$fill_syn quadword;
* mchk$ei_stat quadword;
* mchk$ld_lock quadword;
*
* // System-specific information
*
* constant mchk$sys_base equals . ;
* mchk$sys_ipr1 quadword ; // Holder for system-specific stuff
*
* constant mchk$size equals (.+7) & %xfff8;
*
*
* constant mchk$crd_base equals 0 ;
* constant mchk$mchk_base equals mchk$crd_size ;
*
*
* end logout;
*
* end_module $pal_logout;
*/
/*
* this is lingering in the old ladbx code but looks like it was from
* ev4 days. This was 0x160 in the old days..pb
*/
#define LAF_K_SIZE MACHINE_CHECK_SIZE
#endif

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/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EV5_OSFALPHA_DEFS_INCLUDED
#define EV5_OSFALPHA_DEFS_INCLUDED 1
// from ev5_osfalpha_defs.mar from Lance's fetch directory
// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95
//
// PS Layout - PS
// Loc Size name function
// ------ ------ ----- -----------------------------------
// <0:2> 3 IPL Prio level
// <3> 1 CM Current Mode
//
#define osfps_v_mode 3
#define osfps_m_mode (1<<osfps_v_mode)
#define osfps_v_ipl 0
#define osfps_m_ipl (7<<osfps_v_ipl)
#define osfipl_c_mchk 7
#define osfipl_c_rt 6
#define osfipl_c_clk 5
#define osfipl_c_dev1 4
#define osfipl_c_dev0 3
#define osfipl_c_sw1 2
#define osfipl_c_sw0 1
#define osfipl_c_zero 0
#define osfint_c_mchk 2
#define osfint_c_clk 1
#define osfint_c_dev 3
#define osfint_c_ip 0
#define osfint_c_perf 4
#define osfint_c_passrel 5
//
// PTE layout - symbol prefix osfpte_
//
// Loc Size name function
// ------ ------ ------ -----------------------------------
// <63:32> 32 PFN Page Frame Number
// <31:16> 16 SOFT Bits reserved for software use
// <15:14> 2
// <13> 1 UWE User write enable
// <12> 1 KWE Kernel write enable
// <11:10> 2
// <9> 1 URE User read enable
// <8> 1 KRE Kernel read enable
// <7:6> 2 RES Reserved SBZ
// <5> 1 HPF Huge Page Flag
// <4> 1 ASM Wild card address space number match
// <3> 1 FOE Fault On execute
// <2> 1 FOW Fault On Write
// <1> 1 FOR Fault On Read
// <0> 1 V valid bit
//
#define osfpte_v_pfn 32
#define osfpte_m_soft (0xFFFF0000)
#define osfpte_v_soft 16
#define osfpte_m_uwe (0x2000)
#define osfpte_v_uwe 13
#define osfpte_m_kwe (0x1000)
#define osfpte_v_kwe 12
#define osfpte_m_ure (0x0200)
#define osfpte_v_ure 9
#define osfpte_m_kre (0x0100)
#define osfpte_v_kre 8
#define osfpte_m_hpf (0x0020)
#define osfpte_v_hpf 5
#define osfpte_m_asm (0x0010)
#define osfpte_v_asm 4
#define osfpte_m_foe (0x0008)
#define osfpte_v_foe 3
#define osfpte_m_fow (0x0004)
#define osfpte_v_fow 2
#define osfpte_m_for (0x0002)
#define osfpte_v_for 1
#define osfpte_m_v (0x0001)
#define osfpte_v_v 0
#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm)
#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe)
//
// VA layout - symbol prefix VA_
//
// Loc Size name function
// ------ ------ ------- -----------------------------------
// <42:33> 10 SEG1 First seg table offset for mapping
// <32:23> 10 SEG2 Second seg table offset for mapping
// <22:13> 10 SEG3 Third seg table offset for mapping
// <12:0> 13 OFFSET Byte within page
//
#define osfva_m_offset (0x000000001FFF)
#define osfva_v_offset 0
#define osfva_m_seg3 (0x0000007FE000)
#define osfva_v_seg3 13
#define osfva_m_seg2 (0x0001FF800000)
#define osfva_v_seg2 23
#define osfva_m_seg1 (0x7FE00000000)
#define osfva_v_seg1 33
#define osfpcb_q_ksp (0x0000)
#define osfpcb_q_usp (0x0008)
#define osfpcb_q_Usp (0x0008)
#define osfpcb_q_mmptr (0x0010)
#define osfpcb_q_Mmptr (0x0010)
#define osfpcb_l_cc (0x0018)
#define osfpcb_l_asn (0x001C)
#define osfpcb_q_unique (0x0020)
#define osfpcb_q_fen (0x0028)
#define osfpcb_v_pme 62
#define osfsf_ps (0x00)
#define osfsf_pc (0x08)
#define osfsf_gp (0x10)
#define osfsf_a0 (0x18)
#define osfsf_a1 (0x20)
#define osfsf_a2 (0x28)
#define osfsf_c_size (0x30)
#endif

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/*
* Copyright (c) 1993 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef EV5_PALDEF_INCLUDED
#define EV5_PALDEF_INCLUDED 1
// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95
// some entries have been superceeded by the more recent evt_defs.h
// These are lower-caseified and have the $ signs (unnecessarily we
// now discover) removed.
// Note that at the bottom of this file is the version of ev5_defs.mar
// which is more recent than the top part of the file and contains
// overlapping information...pb Nov/95
#define hlt_c_reset 0
#define hlt_c_hw_halt 1
#define hlt_c_ksp_inval 2
#define hlt_c_scbb_inval 3
#define hlt_c_ptbr_inval 4
#define hlt_c_sw_halt 5
#define hlt_c_dbl_mchk 6
#define hlt_c_mchk_from_pal 7
#define hlt_c_start 32
#define hlt_c_callback 33
#define hlt_c_mpstart 34
#define hlt_c_lfu_start 35
#define mchk_c_tperr (64<<1)
#define mchk_c_tcperr (65<<1)
#define mchk_c_herr (66<<1)
#define mchk_c_ecc_c (67<<1)
#define mchk_c_ecc_nc (68<<1)
#define mchk_c_unknown (69<<1)
#define mchk_c_cacksoft (70<<1)
#define mchk_c_bugcheck (71<<1)
#define mchk_c_os_bugcheck (72<<1)
#define mchk_c_dcperr (73<<1)
#define mchk_c_icperr (74<<1)
#define mchk_c_retryable_ird (75<<1)
#define mchk_c_proc_hrd_error (76<<1)
#define mchk_c_scperr (77<<1)
#define mchk_c_bcperr (78<<1)
//; mchk codes above 255 reserved for platform specific errors
#define mchk_c_read_nxm (256<<1)
#define mchk_c_sys_hrd_error (257<<1)
#define mchk_c_sys_ecc (258<<1)
#define page_seg_size_bits 10
#define page_offset_size_bits 13
#define page_size_bytes 8192
#define va_size_bits 43
#define pa_size_bits 45
// replaced by ev5_defs.h #define pt0 (0x140)
// replaced by ev5_defs.h #define pt1 (0x141)
// replaced by ev5_defs.h #define pt2 (0x142)
#define pt_entuna (0x142)
// replaced by ev5_defs.h #define pt3 (0x143)
#define pt_impure (0x143)
// replaced by ev5_defs.h #define pt4 (0x144)
// replaced by ev5_defs.h #define pt5 (0x145)
// replaced by ev5_defs.h #define pt6 (0x146)
// replaced by ev5_defs.h #define pt7 (0x147)
#define pt_entif (0x147)
// replaced by ev5_defs.h #define pt8 (0x148)
#define pt_intmask (0x148)
// replaced by ev5_defs.h #define pt9 (0x149)
#define pt_entsys (0x149)
#define pt_ps (0x149)
// replaced by ev5_defs.h #define pt10 (0x14a)
// replaced by ev5_defs.h #define pt11 (0x14b)
#define pt_trap (0x14b)
#define pt_entint (0x14b)
// replaced by ev5_defs.h #define pt12 (0x14c)
#define pt_entarith (0x14c)
// replaced by ev5_defs.h #define pt13 (0x14d)
#define pt_sys0 (0x14d)
// replaced by ev5_defs.h #define pt14 (0x14e)
#define pt_sys1 (0x14e)
// replaced by ev5_defs.h #define pt15 (0x14f)
#define pt_sys2 (0x14f)
// replaced by ev5_defs.h #define pt16 (0x150)
#define pt_whami (0x150)
#define pt_mces (0x150)
#define pt_misc (0x150)
// replaced by ev5_defs.h #define pt17 (0x151)
#define pt_scc (0x151)
#define pt_sysval (0x151)
// replaced by ev5_defs.h #define pt18 (0x152)
#define pt_prbr (0x152)
#define pt_usp (0x152)
// replaced by ev5_defs.h #define pt19 (0x153)
#define pt_ksp (0x153)
// replaced by ev5_defs.h #define pt20 (0x154)
#define pt_ptbr (0x154)
// replaced by ev5_defs.h #define pt21 (0x155)
#define pt_vptbr (0x155)
#define pt_entmm (0x155)
// replaced by ev5_defs.h #define pt22 (0x156)
#define pt_scbb (0x156)
#define pt_kgp (0x156)
// replaced by ev5_defs.h #define pt23 (0x157)
#define pt_pcbb (0x157)
#define pt_misc_v_switch 48
#define pt_misc_v_cm 56
#define mmcsr_c_tnv 0
#define mmcsr_c_acv 1
#define mmcsr_c_for 2
#define mmcsr_c_foe 3
#define mmcsr_c_fow 4
#define mm_stat_m_opcode (0x3F)
#define mm_stat_m_ra (0x1F)
#define evx_opc_sync (0x18)
#define EVX_OPC_SYNC (0x18)
#define evx_opc_hw_ld (0x1B)
#define osf_a0_bpt (0x0)
#define osf_a0_bugchk (0x1)
#define osf_a0_gentrap (0x2)
#define osf_a0_fen (0x3)
#define osf_a0_opdec (0x4)
#define ipl_machine_check 31
#define ipl_powerfail 30
#define ipl_perf_count 29
#define ipl_clock 22
#define ipl_interprocessor 22
#endif

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/*
* Copyright (c) 1993-1994 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef HUDSON_MACROS_LOADED
#define HUDSON_MACROS_LOADED 1
#define STALL \
mfpr r31, pt0
#define NOP \
bis $31, $31, $31
/*
** Align code on an 8K byte page boundary.
*/
#define ALIGN_PAGE \
.align 13
/*
** Align code on a 32 byte block boundary.
*/
#define ALIGN_BLOCK \
.align 5
/*
** Align code on a quadword boundary.
*/
#define ALIGN_BRANCH \
.align 3
/*
** Hardware vectors go in .text 0 sub-segment.
*/
#define HDW_VECTOR(offset) \
. = offset
/*
** Privileged CALL_PAL functions are in .text 1 sub-segment.
*/
#define CALL_PAL_PRIV(vector) \
. = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6))
/*
** Unprivileged CALL_PAL functions are in .text 1 sub-segment,
** the privileged bit is removed from these vectors.
*/
#define CALL_PAL_UNPRIV(vector) \
. = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6))
/*
** Implements a load "immediate" longword function
*/
#define LDLI(reg,val) \
ldah reg, ((val+0x8000) >> 16)(zero); \
lda reg, (val&0xffff)(reg)
#endif

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/*
* Copyright (c) 1993-1994 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef FROMHUDSONOSF_INCLUDED
#define FROMHUDSONOSF_INCLUDED 1
#define __OSF_LOADED 1
/*
** Seg0 and Seg1 Virtual Address (VA) Format
**
** Loc Size Name Function
** ----- ---- ---- ---------------------------------
** <42:33> 10 SEG1 First level page table offset
** <32:23> 10 SEG2 Second level page table offset
** <22:13> 10 SEG3 Third level page table offset
** <12:00> 13 OFFSET Byte within page offset
*/
#define VA_V_SEG1 33
#define VA_M_SEG1 (0x3FF<<VA_V_SEG1)
#define VA_V_SEG2 23
#define VA_M_SEG2 (0x3FF<<VA_V_SEG2)
#define VA_V_SEG3 13
#define VA_M_SEG3 (0x3FF<<VA_V_SEG3)
#define VA_V_OFFSET 0
#define VA_M_OFFSET 0x1FFF
/*
** Virtual Address Options: 8K byte page size
*/
#define VA_S_SIZE 43
#define VA_S_OFF 13
#define va_s_off 13
#define VA_S_SEG 10
#define VA_S_PAGE_SIZE 8192
/*
** Page Table Entry (PTE) Format
**
** Extent Size Name Function
** ------ ---- ---- ---------------------------------
** <63:32> 32 PFN Page Frame Number
** <31:16> 16 SW Reserved for software
** <15:14> 2 RSV0 Reserved for hardware SBZ
** <13> 1 UWE User Write Enable
** <12> 1 KWE Kernel Write Enable
** <11:10> 2 RSV1 Reserved for hardware SBZ
** <9> 1 URE User Read Enable
** <8> 1 KRE Kernel Read Enable
** <7> 1 RSV2 Reserved for hardware SBZ
** <6:5> 2 GH Granularity Hint
** <4> 1 ASM Address Space Match
** <3> 1 FOE Fault On Execute
** <2> 1 FOW Fault On Write
** <1> 1 FOR Fault On Read
** <0> 1 V Valid
*/
#define PTE_V_PFN 32
#define PTE_M_PFN 0xFFFFFFFF00000000
#define PTE_V_SW 16
#define PTE_M_SW 0x00000000FFFF0000
#define PTE_V_UWE 13
#define PTE_M_UWE (1<<PTE_V_UWE)
#define PTE_V_KWE 12
#define PTE_M_KWE (1<<PTE_V_KWE)
#define PTE_V_URE 9
#define PTE_M_URE (1<<PTE_V_URE)
#define PTE_V_KRE 8
#define PTE_M_KRE (1<<PTE_V_KRE)
#define PTE_V_GH 5
#define PTE_M_GH (3<<PTE_V_GH)
#define PTE_V_ASM 4
#define PTE_M_ASM (1<<PTE_V_ASM)
#define PTE_V_FOE 3
#define PTE_M_FOE (1<<PTE_V_FOE)
#define PTE_V_FOW 2
#define PTE_M_FOW (1<<PTE_V_FOW)
#define PTE_V_FOR 1
#define PTE_M_FOR (1<<PTE_V_FOR)
#define PTE_V_VALID 0
#define PTE_M_VALID (1<<PTE_V_VALID)
#define PTE_M_KSEG 0x1111
#define PTE_M_PROT 0x3300
#define pte_m_prot 0x3300
/*
** System Entry Instruction Fault (entIF) Constants:
*/
#define IF_K_BPT 0x0
#define IF_K_BUGCHK 0x1
#define IF_K_GENTRAP 0x2
#define IF_K_FEN 0x3
#define IF_K_OPCDEC 0x4
/*
** System Entry Hardware Interrupt (entInt) Constants:
*/
#define INT_K_IP 0x0
#define INT_K_CLK 0x1
#define INT_K_MCHK 0x2
#define INT_K_DEV 0x3
#define INT_K_PERF 0x4
/*
** System Entry MM Fault (entMM) Constants:
*/
#define MM_K_TNV 0x0
#define MM_K_ACV 0x1
#define MM_K_FOR 0x2
#define MM_K_FOE 0x3
#define MM_K_FOW 0x4
/*
** Process Control Block (PCB) Offsets:
*/
#define PCB_Q_KSP 0x0000
#define PCB_Q_USP 0x0008
#define PCB_Q_PTBR 0x0010
#define PCB_L_PCC 0x0018
#define PCB_L_ASN 0x001C
#define PCB_Q_UNIQUE 0x0020
#define PCB_Q_FEN 0x0028
#define PCB_Q_RSV0 0x0030
#define PCB_Q_RSV1 0x0038
/*
** Processor Status Register (PS) Bit Summary
**
** Extent Size Name Function
** ------ ---- ---- ---------------------------------
** <3> 1 CM Current Mode
** <2:0> 3 IPL Interrupt Priority Level
**/
#define PS_V_CM 3
#define PS_M_CM (1<<PS_V_CM)
#define PS_V_IPL 0
#define PS_M_IPL (7<<PS_V_IPL)
#define PS_K_KERN (0<<PS_V_CM)
#define PS_K_USER (1<<PS_V_CM)
#define IPL_K_ZERO 0x0
#define IPL_K_SW0 0x1
#define IPL_K_SW1 0x2
#define IPL_K_DEV0 0x3
#define IPL_K_DEV1 0x4
#define IPL_K_CLK 0x5
#define IPL_K_RT 0x6
#define IPL_K_PERF 0x6
#define IPL_K_PFAIL 0x6
#define IPL_K_MCHK 0x7
#define IPL_K_LOW 0x0
#define IPL_K_HIGH 0x7
/*
** SCB Offset Definitions:
*/
#define SCB_Q_FEN 0x0010
#define SCB_Q_ACV 0x0080
#define SCB_Q_TNV 0x0090
#define SCB_Q_FOR 0x00A0
#define SCB_Q_FOW 0x00B0
#define SCB_Q_FOE 0x00C0
#define SCB_Q_ARITH 0x0200
#define SCB_Q_KAST 0x0240
#define SCB_Q_EAST 0x0250
#define SCB_Q_SAST 0x0260
#define SCB_Q_UAST 0x0270
#define SCB_Q_UNALIGN 0x0280
#define SCB_Q_BPT 0x0400
#define SCB_Q_BUGCHK 0x0410
#define SCB_Q_OPCDEC 0x0420
#define SCB_Q_ILLPAL 0x0430
#define SCB_Q_TRAP 0x0440
#define SCB_Q_CHMK 0x0480
#define SCB_Q_CHME 0x0490
#define SCB_Q_CHMS 0x04A0
#define SCB_Q_CHMU 0x04B0
#define SCB_Q_SW0 0x0500
#define SCB_Q_SW1 0x0510
#define SCB_Q_SW2 0x0520
#define SCB_Q_SW3 0x0530
#define SCB_Q_SW4 0x0540
#define SCB_Q_SW5 0x0550
#define SCB_Q_SW6 0x0560
#define SCB_Q_SW7 0x0570
#define SCB_Q_SW8 0x0580
#define SCB_Q_SW9 0x0590
#define SCB_Q_SW10 0x05A0
#define SCB_Q_SW11 0x05B0
#define SCB_Q_SW12 0x05C0
#define SCB_Q_SW13 0x05D0
#define SCB_Q_SW14 0x05E0
#define SCB_Q_SW15 0x05F0
#define SCB_Q_CLOCK 0x0600
#define SCB_Q_INTER 0x0610
#define SCB_Q_SYSERR 0x0620
#define SCB_Q_PROCERR 0x0630
#define SCB_Q_PWRFAIL 0x0640
#define SCB_Q_PERFMON 0x0650
#define SCB_Q_SYSMCHK 0x0660
#define SCB_Q_PROCMCHK 0x0670
#define SCB_Q_PASSREL 0x0680
/*
** Stack Frame (FRM) Offsets:
**
** There are two types of system entries for OSF/1 - those for the
** callsys CALL_PAL function and those for exceptions and interrupts.
** Both entry types use the same stack frame layout. The stack frame
** contains space for the PC, the PS, the saved GP, and the saved
** argument registers a0, a1, and a2. On entry, SP points to the
** saved PS.
*/
#define FRM_Q_PS 0x0000
#define FRM_Q_PC 0x0008
#define FRM_Q_GP 0x0010
#define FRM_Q_A0 0x0018
#define FRM_Q_A1 0x0020
#define FRM_Q_A2 0x0028
#define FRM_K_SIZE 48
#define STACK_FRAME(tmp1,tmp2) \
sll ps, 63-PS_V_CM, p7; \
bge p7, 0f; \
bis zero, zero, ps; \
mtpr sp, ptUsp; \
mfpr sp, ptKsp; \
0: lda sp, 0-FRM_K_SIZE(sp); \
stq tmp1, FRM_Q_PS(sp); \
stq tmp2, FRM_Q_PC(sp); \
stq gp, FRM_Q_GP(sp); \
stq a0, FRM_Q_A0(sp); \
stq a1, FRM_Q_A1(sp); \
stq a2, FRM_Q_A2(sp)
/*
** Halt Codes:
*/
#define HLT_K_RESET 0x0000
#define HLT_K_HW_HALT 0x0001
#define HLT_K_KSP_INVAL 0x0002
#define HLT_K_SCBB_INVAL 0x0003
#define HLT_K_PTBR_INVAL 0x0004
#define HLT_K_SW_HALT 0x0005
#define HLT_K_DBL_MCHK 0x0006
#define HLT_K_MCHK_FROM_PAL 0x0007
/*
** Machine Check Codes:
*/
#define MCHK_K_TPERR 0x0080
#define MCHK_K_TCPERR 0x0082
#define MCHK_K_HERR 0x0084
#define MCHK_K_ECC_C 0x0086
#define MCHK_K_ECC_NC 0x0088
#define MCHK_K_UNKNOWN 0x008A
#define MCHK_K_CACKSOFT 0x008C
#define MCHK_K_BUGCHECK 0x008E
#define MCHK_K_OS_BUGCHECK 0x0090
#define MCHK_K_DCPERR 0x0092
#define MCHK_K_ICPERR 0x0094
#define MCHK_K_RETRY_IRD 0x0096
#define MCHK_K_PROC_HERR 0x0098
/*
** System Machine Check Codes:
*/
#define MCHK_K_READ_NXM 0x0200
#define MCHK_K_SYS_HERR 0x0202
/*
** Machine Check Error Status Summary (MCES) Register Format
**
** Extent Size Name Function
** ------ ---- ---- ---------------------------------
** <0> 1 MIP Machine check in progress
** <1> 1 SCE System correctable error in progress
** <2> 1 PCE Processor correctable error in progress
** <3> 1 DPC Disable PCE error reporting
** <4> 1 DSC Disable SCE error reporting
*/
#define MCES_V_MIP 0
#define MCES_M_MIP (1<<MCES_V_MIP)
#define MCES_V_SCE 1
#define MCES_M_SCE (1<<MCES_V_SCE)
#define MCES_V_PCE 2
#define MCES_M_PCE (1<<MCES_V_PCE)
#define MCES_V_DPC 3
#define MCES_M_DPC (1<<MCES_V_DPC)
#define MCES_V_DSC 4
#define MCES_M_DSC (1<<MCES_V_DSC)
#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
| MCES_M_DSC)
/*
** Who-Am-I (WHAMI) Register Format
**
** Extent Size Name Function
** ------ ---- ---- ---------------------------------
** <7:0> 8 ID Who-Am-I identifier
** <15:8> 1 SWAP Swap PALcode flag - character 'S'
*/
#define WHAMI_V_SWAP 8
#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP)
#define WHAMI_V_ID 0
#define WHAMI_M_ID 0xFF
#define WHAMI_K_SWAP 0x53 /* Character 'S' */
/*
** Conventional Register Usage Definitions
**
** Assembler temporary `at' is `AT' so it doesn't conflict with the
** `.set at' assembler directive.
*/
#define v0 $0 /* Function Return Value Register */
#define t0 $1 /* Scratch (Temporary) Registers ... */
#define t1 $2
#define t2 $3
#define t3 $4
#define t4 $5
#define t5 $6
#define t6 $7
#define t7 $8
#define s0 $9 /* Saved (Non-Volatile) Registers ... */
#define s1 $10
#define s2 $11
#define s3 $12
#define s4 $13
#define s5 $14
#define fp $15 /* Frame Pointer Register, Or S6 */
#define s6 $15
#define a0 $16 /* Argument Registers ... */
#define a1 $17
#define a2 $18
#define a3 $19
#define a4 $20
#define a5 $21
#define t8 $22 /* Scratch (Temporary) Registers ... */
#define t9 $23
#define t10 $24
#define t11 $25
#define ra $26 /* Return Address Register */
#define pv $27 /* Procedure Value Register, Or T12 */
#define t12 $27
#define AT $28 /* Assembler Temporary (Volatile) Register */
#define gp $29 /* Global Pointer Register */
#define sp $30 /* Stack Pointer Register */
#define zero $31 /* Zero Register */
/*
** OSF/1 Unprivileged CALL_PAL Entry Offsets:
**
** Entry Name Offset (Hex)
**
** bpt 0080
** bugchk 0081
** callsys 0083
** imb 0086
** rdunique 009E
** wrunique 009F
** gentrap 00AA
** dbgstop 00AD
*/
#define UNPRIV 0x80
#define PAL_BPT_ENTRY 0x80
#define PAL_BUGCHK_ENTRY 0x81
#define PAL_CALLSYS_ENTRY 0x83
#define PAL_IMB_ENTRY 0x86
#define PAL_RDUNIQUE_ENTRY 0x9E
#define PAL_WRUNIQUE_ENTRY 0x9F
#define PAL_GENTRAP_ENTRY 0xAA
#if defined(KDEBUG)
#define PAL_DBGSTOP_ENTRY 0xAD
/* #define NUM_UNPRIV_CALL_PALS 10 */
#else
/* #define NUM_UNPRIV_CALL_PALS 9 */
#endif /* KDEBUG */
/*
** OSF/1 Privileged CALL_PAL Entry Offsets:
**
** Entry Name Offset (Hex)
**
** halt 0000
** cflush 0001
** draina 0002
** cserve 0009
** swppal 000A
** rdmces 0010
** wrmces 0011
** wrfen 002B
** wrvptptr 002D
** swpctx 0030
** wrval 0031
** rdval 0032
** tbi 0033
** wrent 0034
** swpipl 0035
** rdps 0036
** wrkgp 0037
** wrusp 0038
** rdusp 003A
** whami 003C
** retsys 003D
** rti 003F
*/
#define PAL_HALT_ENTRY 0x0000
#define PAL_CFLUSH_ENTRY 0x0001
#define PAL_DRAINA_ENTRY 0x0002
#define PAL_CSERVE_ENTRY 0x0009
#define PAL_SWPPAL_ENTRY 0x000A
#define PAL_WRIPIR_ENTRY 0x000D
#define PAL_RDMCES_ENTRY 0x0010
#define PAL_WRMCES_ENTRY 0x0011
#define PAL_WRFEN_ENTRY 0x002B
#define PAL_WRVPTPTR_ENTRY 0x002D
#define PAL_SWPCTX_ENTRY 0x0030
#define PAL_WRVAL_ENTRY 0x0031
#define PAL_RDVAL_ENTRY 0x0032
#define PAL_TBI_ENTRY 0x0033
#define PAL_WRENT_ENTRY 0x0034
#define PAL_SWPIPL_ENTRY 0x0035
#define PAL_RDPS_ENTRY 0x0036
#define PAL_WRKGP_ENTRY 0x0037
#define PAL_WRUSP_ENTRY 0x0038
#define PAL_RDUSP_ENTRY 0x003A
#define PAL_WHAMI_ENTRY 0x003C
#define PAL_RETSYS_ENTRY 0x003D
#define PAL_RTI_ENTRY 0x003F
#define NUM_PRIV_CALL_PALS 23
#endif

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/*
* Copyright (c) 1990 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Keith Bostic, Chris G. Demetriou
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
/*
* Defines for the architected startup addresses.
*/
#define HWRPB_ADDR 0x10000000 /* 256 MB */
#define BOOT_ADDR 0x20000000 /* 512 MB */
#define PGTBL_ADDR 0x40000000 /* 1 GB */
/*
* Values for the "haltcode" field in the per-cpu portion of the HWRPB
*
* Bit defines for the "sysvar" field in the HWRPB.
* Each platform has different values for SYSBOARD and IOBOARD bits.
*/
#define HALT_PWRUP 0 /* power up */
#define HALT_OPR 1 /* operator issued halt cmd */
#define HALT_KSTK 2 /* kernel stack not valid */
#define HALT_SCBB 3 /* invalid SCBB */
#define HALT_PTBR 4 /* invalid PTBR */
#define HALT_EXE 5 /* kernel executed halt instruction */
#define HALT_DBLE 6 /* double error abort */
/*
* Bit defines for the "state" field in the per-cpu portion of the HWRPB
*/
#define STATE_BIP 0x00000001 /* bootstrap in progress */
#define STATE_RC 0x00000002 /* restart capable */
#define STATE_PA 0x00000004 /* processor available to OS */
#define STATE_PP 0x00000008 /* processor present */
#define STATE_OH 0x00000010 /* operator halted */
#define STATE_CV 0x00000020 /* context valid */
#define STATE_PV 0x00000040 /* PALcode valid */
#define STATE_PMV 0x00000080 /* PALcode memory valid */
#define STATE_PL 0x00000100 /* PALcode loaded */
#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */
#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */
#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */
#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */
#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */
#define STATE_HALT 0x00040000 /* Remain halted (no restart) */
#define SV_PF_RSVD 0x00000000 /* RESERVED */
#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */
#define SV_MPCAP 0x00000001 /* MP capable */
#define SV_PF_UNITED 0x00000020 /* United */
#define SV_PF_SEPARATE 0x00000040 /* Separate */
#define SV_PF_FULLBB 0x00000060 /* Full battery backup */
#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */
#define SV_PF_RESTART 0x00000100 /* Powerfail restart */
#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */
#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
#define SV_SANDPIPER 0x00000400 /* others define system platforms */
#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */
#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */
#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */
#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */
#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */
#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */
#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */
#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */
#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */
/*
* Values for the "console type" field in the CTB portion of the HWRPB
*/
#define CONS_NONE 0 /* no console present */
#define CONS_SRVC 1 /* console is service processor */
#define CONS_DZ 2 /* console is dz/dl VT device */
#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/
#define CONS_REM 4 /* cons is remote, protocal enet/MOP */
/*
* PALcode variants that we're interested in.
* Used as indices into the "palrev_avail" array in the per-cpu portion
* of the HWRPB.
*/
#define PALvar_reserved 0
#define PALvar_OpenVMS 1
#define PALvar_OSF1 2
/*
* The Alpha restart parameter block, which is a page or 2 in low memory
*/
struct rpb {
struct rpb *rpb_selfref; /* 000: physical self-reference */
long rpb_string; /* 008: contains string "HWRPB" */
long rpb_vers; /* 010: HWRPB version number */
ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
ulong rpb_cpuid; /* 020: primary cpu id */
ulong rpb_pagesize; /* 028: page size in bytes */
ulong rpb_addrbits; /* 030: number of phys addr bits */
ulong rpb_maxasn; /* 038: max valid ASN */
char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
ulong grpb_systype; /* 050: system type */
long rpb_sysvar; /* 058: system variation */
long rpb_sysrev; /* 060: system revision */
ulong rpb_clock; /* 068: scaled interval clock intr freq */
ulong rpb_counter; /* 070: cycle counter frequency */
ulong rpb_vptb; /* 078: virtual page table base */
long rpb_res1; /* 080: reserved */
ulong rpb_trans_off; /* 088: offset to translation buffer hint */
ulong rpb_numprocs; /* 090: number of processor slots */
ulong rpb_slotsize; /* 098: per-cpu slot size */
ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */
ulong rpb_num_ctb; /* 0A8: number of CTBs */
ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */
ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */
ulong rpb_config_off; /* 0D0: offset to config data block */
ulong rpb_fru_off; /* 0D8: offset to FRU table */
void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
long rpb_restart_pv; /* 108: proc value for CPU restart routine */
long rpb_software; /* 110: used to determine presence of kdebug */
long rpb_hardware; /* 118: reserved for hardware */
long rpb_checksum; /* 120: checksum of prior entries in rpb */
long rpb_rxrdy; /* 128: receive ready bitmask */
long rpb_txrdy; /* 130: transmit ready bitmask */
ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */
};
#define rpb_kdebug rpb_software
#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23))
/*
* This is the format for the boot/restart HWPCB. It must match the
* initial fields of the pcb structure as defined in pcb.h, but must
* additionally contain the appropriate amount of padding to line up
* with formats used by other palcode types.
*/
struct bootpcb {
long rpb_ksp; /* 000: kernel stack pointer */
long rpb_usp; /* 008: user stack pointer */
long rpb_ptbr; /* 010: page table base register */
int rpb_cc; /* 018: cycle counter */
int rpb_asn; /* 01C: address space number */
long rpb_proc_uniq; /* 020: proc/thread unique value */
long rpb_fen; /* 028: floating point enable */
long rpb_palscr[2]; /* 030: pal scratch area */
long rpb_pcbpad[8]; /* 040: padding for fixed size */
};
/*
* Inter-Console Communications Buffer
* Used for the primary processor to communcate with the console
* of secondary processors.
*/
struct iccb {
uint iccb_rxlen; /* receive length in bytes */
uint iccb_txlen; /* transmit length in bytes */
char iccb_rxbuf[80]; /* receive buffer */
char iccb_txbuf[80]; /* transmit buffer */
};
/*
* The per-cpu portion of the Alpha HWRPB.
* Note that the main portion of the HWRPB is of variable size,
* hence this must be a separate structure.
*
*/
struct rpb_percpu {
struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */
long rpb_state; /* 080: per-cpu state bits */
long rpb_palmem; /* 088: palcode memory length */
long rpb_palscratch; /* 090: palcode scratch length */
long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
long rpb_palrev; /* 0A8: PALcode rev required */
long rpb_proctype; /* 0B0: processor type */
long rpb_procvar; /* 0B8: processor variation */
long rpb_procrev; /* 0C0: processor revision */
char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
long rpb_logout; /* 0D8: phys addr of logout area */
long rpb_logout_len; /* 0E0: length in bytes of logout area */
long rpb_haltpb; /* 0E8: halt pcb base */
long rpb_haltpc; /* 0F0: halt pc */
long rpb_haltps; /* 0F8: halt ps */
long rpb_haltal; /* 100: halt arg list (R25) */
long rpb_haltra; /* 108: halt return address (R26) */
long rpb_haltpv; /* 110: halt procedure value (R27) */
long rpb_haltcode; /* 118: reason for halt */
long rpb_software; /* 120: for software */
struct iccb rpb_iccb; /* 128: inter-console communications buffer */
long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */
long rpb_pcrsvd[6]; /* 250: reserved for arch use */
/* the dump stack grows from the end of the rpb page not to reach here */
};
/* The firmware revision is in the (unused) first entry of palrevs available */
#define rpb_firmrev rpb_palrev_avail[0]
/*
* The memory cluster descriptor.
*/
struct rpb_cluster {
long rpb_pfn; /* 000: starting PFN of this cluster */
long rpb_pfncount; /* 008: count of PFNs in this cluster */
long rpb_pfntested; /* 010: count of tested PFNs in cluster */
long rpb_va; /* 018: va of bitmap */
long rpb_pa; /* 020: pa of bitmap */
long rpb_checksum; /* 028: checksum of bitmap */
long rpb_usage; /* 030: usage of cluster */
};
#define CLUSTER_USAGE_OS ((long)0)
#define CLUSTER_USAGE_PAL ((long)1)
#define CLUSTER_USAGE_NVRAM ((long)2)
/*
* The "memory descriptor table" portion of the HWRPB.
* Note that the main portion of the HWRPB is of variable size and there is a
* variable number of per-cpu slots, hence this must be a separate structure.
* Also note that the memory descriptor table contains a fixed portion plus
* a variable number of "memory cluster descriptors" (one for each "cluster"
* of memory).
*/
struct rpb_mdt {
long rpb_checksum; /* 000: checksum of entire mem desc table */
long rpb_impaddr; /* 008: PA of implementation dep info */
long rpb_numcl; /* 010: number of clusters */
struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */
};
/*
* The "Console Terminal Block" portion of the HWRPB, for serial line
* UART console device.
*/
struct ctb_tt {
long ctb_type; /* 0: always 4 */
long ctb_unit; /* 8: */
long ctb_reserved; /* 16: */
long ctb_len; /* 24: bytes of info */
long ctb_ipl; /* 32: console ipl level */
long ctb_tintr_vec; /* 40: transmit vec (0x800) */
long ctb_rintr_vec; /* 48: receive vec (0x800) */
#define CTB_GRAPHICS 3 /* graphics device */
#define CTB_NETWORK 0xC0 /* network device */
#define CTB_PRINTERPORT 2 /* printer port on the SCC */
long ctb_term_type; /* 56: terminal type */
long ctb_keybd_type; /* 64: keyboard nationality */
long ctb_keybd_trans; /* 72: trans. table addr */
long ctb_keybd_map; /* 80: map table addr */
long ctb_keybd_state; /* 88: keyboard flags */
long ctb_keybd_last; /* 96: last key entered */
long ctb_font_us; /* 104: US font table addr */
long ctb_font_mcs; /* 112: MCS font table addr */
long ctb_font_width; /* 120: font width, height */
long ctb_font_height; /* 128: in pixels */
long ctb_mon_width; /* 136: monitor width, height */
long ctb_mon_height; /* 144: in pixels */
long ctb_dpi; /* 152: monitor dots per inch */
long ctb_planes; /* 160: # of planes */
long ctb_cur_width; /* 168: cursor width, height */
long ctb_cur_height; /* 176: in pixels */
long ctb_head_cnt; /* 184: # of heads */
long ctb_opwindow; /* 192: opwindow on screen */
long ctb_head_offset; /* 200: offset to head info */
long ctb_putchar; /* 208: output char to TURBO */
long ctb_io_state; /* 216: I/O flags */
long ctb_listen_state; /* 224: listener flags */
long ctb_xaddr; /* 232: extended info addr */
long ctb_turboslot; /* 248: TURBOchannel slot # */
long ctb_server_off; /* 256: offset to server info */
long ctb_line_off; /* 264: line parameter offset */
char ctb_csd; /* 272: console specific data */
};
/*
* The "Console Terminal Block" portion of the HWRPB.
*/
struct rpb_ctb {
long rpb_type; /* 000: console type */
long rpb_unit; /* 008: console unit */
long rpb_resv; /* 010: reserved */
long rpb_length; /* 018: byte length of device dep portion */
long rpb_first; /* 000: first field of device dep portion */
};
/*
* The physical/virtual map for the console routine block.
*/
struct rpb_map {
long rpb_virt; /* virtual address for map entry */
long rpb_phys; /* phys address for map entry */
long rpb_pgcount; /* page count for map entry */
};
/*
* The "Console Routine Block" portion of the HWRPB.
* Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
*/
struct rpb_crb {
long rpb_va_disp; /* va of call-back dispatch rtn */
long rpb_pa_disp; /* pa of call-back dispatch rtn */
long rpb_va_fixup; /* va of call-back fixup rtn */
long rpb_pa_fixup; /* pa of call-back fixup rtn */
long rpb_num; /* number of entries in phys/virt map */
long rpb_mapped_pages; /* Number of pages to be mapped */
struct rpb_map rpb_map[1]; /* first instance of a map entry */
};
/*
* These macros define where within the HWRPB the CTB and CRB are located.
*/
#define CTB_SETUP \
((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
#define CRB_SETUP \
((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
/*
* The "Dynamic System Recognition" portion of the HWRPB.
* It is used to obtain the platform specific data need to allow
* the platform define the platform name, the platform SMM and LURT
* data for software licensing
*/
struct rpb_dsr {
long rpb_smm; /* SMM nubber used by LMF */
ulong rpb_lurt_off; /* offset to LURT table */
ulong rpb_sysname_off; /* offset to sysname char count */
int lurt[10]; /* XXM has one LURT entry */
};

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/*
* Copyright (c) 1990 Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define tlsb_tlber 0x40
#define tlsb_tldev 0x00
#define tlsb_tlesr0 0x680
#define tlsb_tlesr1 0x6C0
#define tlsb_tlesr2 0x700
#define tlsb_tlesr3 0x740

92
system/alpha/palcode/Makefile Normal file
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@ -0,0 +1,92 @@
# Copyright (c) 2003, 2004
# The Regents of The University of Michigan
# All Rights Reserved
#
# This code is part of the M5 simulator.
#
# Permission is granted to use, copy, create derivative works and
# redistribute this software and such derivative works for any purpose,
# so long as the copyright notice above, this grant of permission, and
# the disclaimer below appear in all copies made; and so long as the
# name of The University of Michigan is not used in any advertising or
# publicity pertaining to the use or distribution of this software
# without specific, written prior authorization.
#
# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
#
# Authors: Nathan L. Binkert
# Ali G. Saidi
# Makefile for palcode
# Works on alpha-linux and builds elf executable
### If we are not compiling on an alpha, we must use cross tools ###
ifneq ($(shell uname -m), alpha)
CROSS_COMPILE?=alpha-unknown-linux-gnu-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
CFLAGS=-I . -I ../h -nostdinc -nostdinc++ -Wa,-m21164
LDFLAGS=-Ttext 0x4000
TLOBJS = osfpal.o platform_tlaser.o
TLOBJS_COPY = osfpal_cache_copy.o platform_tlaser.o
TLOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_tlaser.o
TSOBJS = osfpal.o platform_tsunami.o
TSBOBJS = osfpal.o platform_bigtsunami.o
TSOBJS_COPY = osfpal_cache_copy.o platform_tsunami.o
TSOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_bigtsunami.o
all: tlaser tsunami tsunami_b64
all_copy: tlaser tlaser_copy tsunami tsunami_b64 tsunami_copy
osfpal.o: osfpal.S
$(CC) $(CFLAGS) -o $@ -c $<
osfpal_cache_copy.o: osfpal.S
$(CC) $(CFLAGS) -DCACHE_COPY -o $@ -c $<
osfpal_cache_copy_unaligned.o: osfpal.S
$(CC) $(CFLAGS) -DCACHE_COPY -DCACHE_COPY_UNALIGNED -o $@ -c $<
platform_tlaser.o: platform.S
$(CC) $(CFLAGS) -DTLASER -o $@ -c $<
platform_tsunami.o: platform.S
$(CC) $(CFLAGS) -DTSUNAMI -o $@ -c $<
platform_bigtsunami.o: platform.S
$(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $<
tlaser: $(TLOBJS)
$(LD) $(LDFLAGS) -o tl_osfpal $(TLOBJS)
tlaser_copy: $(TLOBJS_COPY) $(TLOBJS_COPY_UNALIGNED)
$(LD) $(LDFLAGS) -o tl_osfpal_cache $(TLOBJS_COPY)
$(LD) $(LDFLAGS) -o tl_osfpal_unalign $(TLOBJS_COPY_UNALIGNED)
tsunami: $(TSOBJS)
$(LD) $(LDFLAGS) -o ts_osfpal $(TSOBJS)
tsunami_b64: $(TSBOBJS)
$(LD) $(LDFLAGS) -o tsb_osfpal $(TSBOBJS)
tsunami_copy: $(TSOBJS_COPY) $(TSOBJS_COPY_UNALIGNED)
$(LD) $(LDFLAGS) -o ts_osfpal_cache $(TSOBJS_COPY)
$(LD) $(LDFLAGS) -o ts_osfpal_unalign $(TSOBJS_COPY_UNALIGNED)
clean:
rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \
ts_osfpal_cache ts_osfpal_unalign tsb_osfpal

4202
system/alpha/palcode/osfpal.S Normal file
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File diff suppressed because it is too large Load diff

2337
system/alpha/palcode/platform.S Normal file
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File diff suppressed because it is too large Load diff

2
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
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@ -488,7 +488,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr

10
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 12 2011 02:22:23
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@ -1067,4 +1067,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 772390499500 because target called exit()
Exiting @ tick 766217705000 because target called exit()

736
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
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@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 168346 # Simulator instruction rate (inst/s)
host_mem_usage 232444 # Number of bytes of host memory used
host_seconds 9631.89 # Real time elapsed on the host
host_tick_rate 80190939 # Simulator tick rate (ticks/s)
host_inst_rate 123498 # Simulator instruction rate (inst/s)
host_mem_usage 236748 # Number of bytes of host memory used
host_seconds 13129.74 # Real time elapsed on the host
host_tick_rate 58357436 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493982 # Number of instructions simulated
sim_seconds 0.772390 # Number of seconds simulated
sim_ticks 772390499500 # Number of ticks simulated
sim_seconds 0.766218 # Number of seconds simulated
sim_ticks 766217705000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 126254885 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 126894033 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 5933287 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 126894073 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 126894073 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 107161579 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 3710402 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1511501895 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.072770 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.173458 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 505879323 33.47% 33.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 677452709 44.82% 78.29% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 153213861 10.14% 88.43% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 112394621 7.44% 95.86% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 32585093 2.16% 98.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 19016713 1.26% 99.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 5421676 0.36% 99.63% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1827497 0.12% 99.75% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 3710402 0.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle
system.cpu.commit.COM:count 1621493982 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 607228182 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 5933318 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 227874068 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.cpi 0.952690 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.952690 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 326327666 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10363.748203 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7391.735933 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 326125265 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2097633000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000620 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 202401 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1725 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1483344000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000615 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 200676 # number of ReadReq MSHR misses
system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 19667.198248 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10021.451346 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 186945733 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 24393698000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006591 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1240324 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 994745 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2461058000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001305 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 245579 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 15789.833755 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1149.728625 # Average number of references to valid blocks.
system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29234 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 461600000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 514513723 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18362.010085 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency
system.cpu.dcache.demand_hits 513070998 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26491331000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002804 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1442725 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 996470 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 3944402000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000867 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 446255 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses
system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.101758 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 514513723 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18362.010085 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 513070998 # number of overall hits
system.cpu.dcache.overall_miss_latency 26491331000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002804 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1442725 # number of overall misses
system.cpu.dcache.overall_mshr_hits 996470 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 3944402000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000867 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 446255 # number of overall MSHR misses
system.cpu.dcache.overall_hits 517710070 # number of overall hits
system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses
system.cpu.dcache.overall_misses 1455125 # number of overall misses
system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 442158 # number of replacements
system.cpu.dcache.sampled_refs 446254 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 460779 # number of replacements
system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4095.101758 # Cycle average of tags in use
system.cpu.dcache.total_refs 513070998 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 331552000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 398281 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 176333648 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 1886463332 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 320369444 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 981528406 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 33063147 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 33270397 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 126894073 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 119630706 # Number of cache lines fetched
system.cpu.fetch.Cycles 1056772647 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 432705 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1026147627 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 9324994 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.082144 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 119630706 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 126254885 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.664267 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1544565042 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.230490 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.292215 # Number of instructions fetched each cycle (Total)
system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use
system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 411288 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched
system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 522111775 33.80% 33.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 496583342 32.15% 65.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 273451194 17.70% 83.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 224891951 14.56% 98.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8280335 0.54% 98.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1557581 0.10% 98.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 722 0.00% 98.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8665 0.00% 98.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 17679477 1.14% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 119629787 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 34161000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000008 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 919 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 127 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 28063500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 151047.710859 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 119630706 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 37171.926007 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency
system.cpu.icache.demand_hits 119629787 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 34161000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000008 # miss rate for demand accesses
system.cpu.icache.demand_misses 919 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 127 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 28063500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency
system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.352078 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 721.055018 # Average occupied blocks per context
system.cpu.icache.overall_accesses 119630706 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37171.926007 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context
system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 119629787 # number of overall hits
system.cpu.icache.overall_miss_latency 34161000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000008 # miss rate for overall accesses
system.cpu.icache.overall_misses 919 # number of overall misses
system.cpu.icache.overall_mshr_hits 127 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 28063500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses
system.cpu.icache.overall_hits 168862206 # number of overall hits
system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_misses 1223 # number of overall misses
system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks.
system.cpu.icache.replacements 11 # number of replacements
system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 721.055018 # Cycle average of tags in use
system.cpu.icache.total_refs 119629787 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use
system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 215958 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 108586362 # Number of branches executed
system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 111314295 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.090888 # Inst execution rate
system.cpu.iew.EXEC:refs 624680336 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 190102881 # Number of stores executed
system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate
system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 191312994 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 2506292363 # num instructions consuming a value
system.cpu.iew.WB:count 1680860111 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.529936 # average fanout of values written-back
system.cpu.iew.WB:consumers 2089450315 # num instructions consuming a value
system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1328173821 # num instructions producing a value
system.cpu.iew.WB:rate 1.088090 # insts written-back per cycle
system.cpu.iew.WB:sent 1681411195 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 6122546 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1253236 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 492554241 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 66 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3215387 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 210212351 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1849358863 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 434577455 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 8332046 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1685183738 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 18939 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1430463261 # num instructions producing a value
system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle
system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 33063147 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 72665 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 29234 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 108234700 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 16690 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 3968261 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 73512116 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 22026294 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads
system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes
system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1040578234 61.44% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.87% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 438214492 25.88% 88.75% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 190565591 11.25% 100.00% # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads
system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes
system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1693515784 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 252744 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000149 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 40 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 250833 99.24% 99.26% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1871 0.74% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1544565042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096435 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.983023 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 454758636 29.44% 29.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 667103033 43.19% 72.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 281275831 18.21% 90.84% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 105166888 6.81% 97.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 33264638 2.15% 99.81% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 2679834 0.17% 99.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 311387 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 3979 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 816 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 226765112 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1273 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 584800312 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 245580 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34276.926221 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.745964 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 186864 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2012604000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.239091 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58716 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1824643500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.239091 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58716 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 201467 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34133.939861 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.577487 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 169042 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1106793000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.160944 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32425 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1005291000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.160944 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 32425 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 398281 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 398281 # number of Writeback hits
system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate
system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 2351086128 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1543114171 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 4.844642 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 447047 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34226.056330 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 355906 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3119397000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.203873 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91141 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2829934500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.203873 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91141 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.058867 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.490866 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1928.938344 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16084.711341 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 447047 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34226.056330 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 355906 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3119397000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.203873 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91141 # number of overall misses
system.cpu.l2cache.overall_hits 373812 # number of overall hits
system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91930 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2829934500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.203873 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 91141 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 72873 # number of replacements
system.cpu.l2cache.sampled_refs 88473 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 73661 # number of replacements
system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 18013.649684 # Cycle average of tags in use
system.cpu.l2cache.total_refs 428620 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use
system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 58405 # number of writebacks
system.cpu.memDep0.conflictingLoads 289036318 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads
system.cpu.numCycles 1544781000 # number of cpu cycles simulated
system.cpu.l2cache.writebacks 58542 # number of writebacks
system.cpu.memDep0.conflictingLoads 537232404 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads
system.cpu.numCycles 1532435411 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking
system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 361165681 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 36822801 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 5668050381 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 1874385455 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1871676358 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 968560202 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3357159543 # The number of ROB reads
system.cpu.rob.rob_writes 3732197477 # The number of ROB writes
system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3775835718 # The number of ROB reads
system.cpu.rob.rob_writes 4802062478 # The number of ROB writes
system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:38:48
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

10
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1066510 # Simulator instruction rate (inst/s)
host_mem_usage 223440 # Number of bytes of host memory used
host_seconds 1520.37 # Real time elapsed on the host
host_tick_rate 634049597 # Simulator tick rate (ticks/s)
host_inst_rate 2470310 # Simulator instruction rate (inst/s)
host_mem_usage 224012 # Number of bytes of host memory used
host_seconds 656.39 # Real time elapsed on the host
host_tick_rate 1468620897 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated
sim_seconds 0.963993 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 1621493983 # Number of instructions executed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read
system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs

6
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:35
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

10
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 685934 # Simulator instruction rate (inst/s)
host_mem_usage 231240 # Number of bytes of host memory used
host_seconds 2363.92 # Real time elapsed on the host
host_tick_rate 762824620 # Simulator tick rate (ticks/s)
host_inst_rate 1667736 # Simulator instruction rate (inst/s)
host_mem_usage 231728 # Number of bytes of host memory used
host_seconds 972.27 # Real time elapsed on the host
host_tick_rate 1854683738 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493983 # Number of instructions simulated
sim_seconds 1.803259 # Number of seconds simulated
@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 1621493983 # Number of instructions executed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_int_insts 1621354493 # number of integer instructions
system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read
system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read
system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written
system.cpu.num_load_insts 419042125 # Number of load instructions
system.cpu.num_mem_refs 607228182 # number of memory refs

9
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
View file

@ -5,13 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:04:06
M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch
M5 started Feb 7 2011 01:04:09
M5 compiled Feb 8 2011 00:58:27
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:30
M5 executing on burrito
command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic
command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112051463500 because m5_exit instruction encountered

10
tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 2329852 # Simulator instruction rate (inst/s)
host_mem_usage 370744 # Number of bytes of host memory used
host_seconds 174.53 # Real time elapsed on the host
host_tick_rate 29290692573 # Simulator tick rate (ticks/s)
host_inst_rate 1892986 # Simulator instruction rate (inst/s)
host_mem_usage 370804 # Number of bytes of host memory used
host_seconds 214.81 # Real time elapsed on the host
host_tick_rate 23798444654 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 406624453 # Number of instructions simulated
sim_seconds 5.112051 # Number of seconds simulated
@ -341,7 +341,7 @@ system.cpu.num_idle_cycles 9770620811.997942
system.cpu.num_insts 406624453 # Number of instructions executed
system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses
system.cpu.num_int_insts 391833833 # number of integer instructions
system.cpu.num_int_register_reads 1007515486 # number of times the integer registers were read
system.cpu.num_int_register_reads 836347867 # number of times the integer registers were read
system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written
system.cpu.num_load_insts 29720540 # Number of load instructions
system.cpu.num_mem_refs 38133606 # number of memory refs

9
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
View file

@ -5,13 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 01:04:06
M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch
M5 started Feb 7 2011 01:04:09
M5 compiled Feb 8 2011 00:58:27
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:30
M5 executing on burrito
command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing
command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5187506658000 because m5_exit instruction encountered

10
tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1700985 # Simulator instruction rate (inst/s)
host_mem_usage 367580 # Number of bytes of host memory used
host_seconds 155.42 # Real time elapsed on the host
host_tick_rate 33377224644 # Simulator tick rate (ticks/s)
host_inst_rate 1227876 # Simulator instruction rate (inst/s)
host_mem_usage 367348 # Number of bytes of host memory used
host_seconds 215.31 # Real time elapsed on the host
host_tick_rate 24093749418 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 264367743 # Number of instructions simulated
sim_seconds 5.187507 # Number of seconds simulated
@ -395,7 +395,7 @@ system.cpu.num_idle_cycles 9771315874.126116
system.cpu.num_insts 264367743 # Number of instructions executed
system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses
system.cpu.num_int_insts 249584659 # number of integer instructions
system.cpu.num_int_register_reads 660399505 # number of times the integer registers were read
system.cpu.num_int_register_reads 543556622 # number of times the integer registers were read
system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written
system.cpu.num_load_insts 14817593 # Number of load instructions
system.cpu.num_mem_refs 23178416 # number of memory refs

2
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
View file

@ -488,7 +488,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr

10
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:24
M5 compiled Feb 12 2011 02:22:23
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -28,4 +28,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 170680631000 because target called exit()
Exiting @ tick 98622214000 because target called exit()

749
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 83481 # Simulator instruction rate (inst/s)
host_mem_usage 366872 # Number of bytes of host memory used
host_seconds 3332.41 # Real time elapsed on the host
host_tick_rate 51218385 # Simulator tick rate (ticks/s)
host_inst_rate 133029 # Simulator instruction rate (inst/s)
host_mem_usage 371192 # Number of bytes of host memory used
host_seconds 2091.22 # Real time elapsed on the host
host_tick_rate 47160241 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192519 # Number of instructions simulated
sim_seconds 0.170681 # Number of seconds simulated
sim_ticks 170680631000 # Number of ticks simulated
sim_seconds 0.098622 # Number of seconds simulated
sim_ticks 98622214000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 50810617 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 51416767 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 4328981 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 51416803 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 51416803 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 29309710 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 2488105 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 321793097 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.864507 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.425920 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 183622049 57.06% 57.06% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 75902754 23.59% 80.65% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 27223254 8.46% 89.11% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 17908154 5.57% 94.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 5463718 1.70% 96.37% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 3630830 1.13% 97.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 4674698 1.45% 98.95% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 879535 0.27% 99.23% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2488105 0.77% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle
system.cpu.commit.COM:count 278192519 # Number of instructions committed
system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
@ -44,421 +44,430 @@ system.cpu.commit.COM:loads 90779388 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 122219139 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 4328992 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 111464423 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 1.227068 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.227068 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 82779625 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5978.815311 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2941.059048 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 80764514 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12047976500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.024343 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 2015111 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 45360 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5793154000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.023795 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1969751 # number of ReadReq MSHR misses
system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 20696.077989 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 15440.513442 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 31284703 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3208885500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.004932 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 155048 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 48629 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1643164000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003385 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106419 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 53.969218 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 114219376 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7030.296858 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency
system.cpu.dcache.demand_hits 112049217 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 15256862000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.019000 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2170159 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 93989 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7436318000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.018177 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2076170 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995143 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4076.104755 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 114219376 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7030.296858 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 112049217 # number of overall hits
system.cpu.dcache.overall_miss_latency 15256862000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.019000 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2170159 # number of overall misses
system.cpu.dcache.overall_mshr_hits 93989 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7436318000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.018177 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2076170 # number of overall MSHR misses
system.cpu.dcache.overall_hits 98554006 # number of overall hits
system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2344618 # number of overall misses
system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2072073 # number of replacements
system.cpu.dcache.sampled_refs 2076169 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 2074218 # number of replacements
system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4076.104755 # Cycle average of tags in use
system.cpu.dcache.total_refs 112049217 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 66009760000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1440063 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 922031 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 437195268 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 92021485 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 228705655 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 19453848 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 143926 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 51416803 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 39245397 # Number of cache lines fetched
system.cpu.fetch.Cycles 242939967 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 793923 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 249694241 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 9845420 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.150623 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 39245397 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 50810617 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.731466 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 341246945 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.321737 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.251135 # Number of instructions fetched each cycle (Total)
system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use
system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1442059 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched
system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 105340577 30.87% 30.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 115413940 33.82% 64.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 47580781 13.94% 78.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 58732555 17.21% 95.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7189604 2.11% 97.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 6451059 1.89% 99.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 527277 0.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 932 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10220 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 44 # number of floating regfile reads
system.cpu.fp_regfile_writes 31 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 39244337 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 39441000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1060 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 32279000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 914 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 41 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 42936.911379 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 39245397 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 37208.490566 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency
system.cpu.icache.demand_hits 39244337 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 39441000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
system.cpu.icache.demand_misses 1060 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 32279000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000023 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 914 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses
system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.360466 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 738.235227 # Average occupied blocks per context
system.cpu.icache.overall_accesses 39245397 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37208.490566 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context
system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 39244337 # number of overall hits
system.cpu.icache.overall_miss_latency 39441000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
system.cpu.icache.overall_misses 1060 # number of overall misses
system.cpu.icache.overall_mshr_hits 146 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 32279000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000023 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 914 # number of overall MSHR misses
system.cpu.icache.overall_hits 34651154 # number of overall hits
system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses
system.cpu.icache.overall_misses 1341 # number of overall misses
system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 37 # number of replacements
system.cpu.icache.sampled_refs 914 # Sample count of references to valid blocks.
system.cpu.icache.replacements 60 # number of replacements
system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 738.235227 # Cycle average of tags in use
system.cpu.icache.total_refs 39244337 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use
system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 114318 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 31118985 # Number of branches executed
system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 33755681 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.940576 # Inst execution rate
system.cpu.iew.EXEC:refs 137464023 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 32172568 # Number of stores executed
system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate
system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 33964004 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 361852587 # num instructions consuming a value
system.cpu.iew.WB:count 317781549 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.623035 # average fanout of values written-back
system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value
system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 225446782 # num instructions producing a value
system.cpu.iew.WB:rate 0.930924 # insts written-back per cycle
system.cpu.iew.WB:sent 318008427 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 5390321 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 197365 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 131280417 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 455 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 3671049 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 41039188 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 389592858 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 105291455 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 12266571 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 321076071 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2799 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 254272214 # num instructions producing a value
system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle
system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1704 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 19453848 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 10507 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 22405068 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 64376 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 5520980 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 2668 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 40501029 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 9599437 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 754340794 # number of integer regfile reads
system.cpu.int_regfile_writes 286169707 # number of integer regfile writes
system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 193455065 58.03% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 107162338 32.15% 90.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 32708524 9.81% 100.00% # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 577634708 # number of integer regfile reads
system.cpu.int_regfile_writes 302216415 # number of integer regfile writes
system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 57.98% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 333342642 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 98152 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000294 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 15 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 97651 99.49% 99.50% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 486 0.50% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 341246945 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.976837 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.032280 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.745109 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 143332703 42.00% 42.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 98734149 28.93% 70.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 68142120 19.97% 90.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 26890607 7.88% 98.78% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 3089152 0.91% 99.69% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 1054470 0.31% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 2951 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 576 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 217 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate
system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 109882124 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 237362106 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 106419 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34277.831445 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.336758 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 63976 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 1454854000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.398829 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 42443 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317827000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398829 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 42443 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1970665 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34310.495712 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31007.530164 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1936270 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1180109500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.017453 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34395 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1066504000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017453 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34395 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1440063 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1440063 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate
system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 42420 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.399714 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 42420 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 42.751383 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2077084 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34292.452953 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2000246 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2634963500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.036993 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 76838 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 2384331000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.036993 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 76838 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.192442 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.349126 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6305.950681 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11440.167306 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2077084 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34292.452953 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2000246 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2634963500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.036993 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 76838 # number of overall misses
system.cpu.l2cache.overall_hits 2002530 # number of overall hits
system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 76793 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 2384331000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.036993 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 76838 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 49392 # number of replacements
system.cpu.l2cache.sampled_refs 77392 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 49342 # number of replacements
system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 17746.117987 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3308615 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 29474 # number of writebacks
system.cpu.memDep0.conflictingLoads 22358679 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads
system.cpu.numCycles 341361263 # number of cpu cycles simulated
system.cpu.l2cache.writebacks 29450 # number of writebacks
system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads
system.cpu.numCycles 197244429 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking
system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 98511117 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 368076 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 1292599643 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 423407319 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 377348250 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 222275258 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 708961934 # The number of ROB reads
system.cpu.rob.rob_writes 799263493 # The number of ROB writes
system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 574492355 # The number of ROB reads
system.cpu.rob.rob_writes 837321831 # The number of ROB writes
system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:12
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

10
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 722489 # Simulator instruction rate (inst/s)
host_mem_usage 358012 # Number of bytes of host memory used
host_seconds 385.05 # Real time elapsed on the host
host_tick_rate 438776725 # Simulator tick rate (ticks/s)
host_inst_rate 1568972 # Simulator instruction rate (inst/s)
host_mem_usage 358500 # Number of bytes of host memory used
host_seconds 177.31 # Real time elapsed on the host
host_tick_rate 952856596 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.168950 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 278192520 # Number of instructions executed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs

6
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:12
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

10
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 424375 # Simulator instruction rate (inst/s)
host_mem_usage 365728 # Number of bytes of host memory used
host_seconds 655.54 # Real time elapsed on the host
host_tick_rate 564440982 # Simulator tick rate (ticks/s)
host_inst_rate 1018906 # Simulator instruction rate (inst/s)
host_mem_usage 366224 # Number of bytes of host memory used
host_seconds 273.03 # Real time elapsed on the host
host_tick_rate 1355197592 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192520 # Number of instructions simulated
sim_seconds 0.370011 # Number of seconds simulated
@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 278192520 # Number of instructions executed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_int_insts 278186228 # number of integer instructions
system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read
system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read
system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written
system.cpu.num_load_insts 90779388 # Number of load instructions
system.cpu.num_mem_refs 122219139 # number of memory refs

2
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
View file

@ -488,7 +488,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
egid=100
env=
errout=cerr

14
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -5,16 +5,16 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 12 2011 02:22:23
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *****************************info: Increasing stack size by one page.
********************
Reading the dictionary files: ***********************info: Increasing stack size by one page.
**************************
58924 words stored in 3784810 bytes
@ -74,4 +74,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 817002039000 because target called exit()
Exiting @ tick 610952992000 because target called exit()

774
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,475 +1,475 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 160923 # Simulator instruction rate (inst/s)
host_mem_usage 240360 # Number of bytes of host memory used
host_seconds 9501.35 # Real time elapsed on the host
host_tick_rate 85987979 # Simulator tick rate (ticks/s)
host_inst_rate 130186 # Simulator instruction rate (inst/s)
host_mem_usage 285488 # Number of bytes of host memory used
host_seconds 11733.03 # Real time elapsed on the host
host_tick_rate 52071207 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988756 # Number of instructions simulated
sim_seconds 0.817002 # Number of seconds simulated
sim_ticks 817002039000 # Number of ticks simulated
sim_insts 1527476062 # Number of instructions simulated
sim_seconds 0.610953 # Number of seconds simulated
sim_ticks 610952992000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 197674461 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 215147546 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 17901021 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 215739151 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 215739151 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 149758588 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 8186576 # number cycles where commit BW limit reached
system.cpu.commit.COM:branches 149616585 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 1552269342 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.985002 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.301395 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 694185983 44.72% 44.72% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 509617235 32.83% 77.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 176087126 11.34% 88.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 105147186 6.77% 95.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 31137095 2.01% 97.67% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 11224991 0.72% 98.40% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 11192282 0.72% 99.12% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 5490868 0.35% 99.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 8186576 0.53% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle
system.cpu.commit.COM:count 1528988756 # Number of instructions committed
system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle
system.cpu.commit.COM:count 1527476062 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.COM:loads 384102160 # Number of loads committed
system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions.
system.cpu.commit.COM:loads 383724495 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 533262345 # Number of memory references committed
system.cpu.commit.COM:refs 532790180 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 17902344 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 459109010 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 1.068683 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.068683 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 352008034 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14100.976079 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8499.435037 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 350035037 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 27821183500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.005605 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1972997 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 237485 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 14750871500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.004930 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1735512 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 15942.157352 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12645.445755 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 148213244 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 15096537500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.006349 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 946957 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 159966 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 9951852000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 786991 # number of WriteReq MSHR misses
system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1527476062 # Number of Instructions Simulated
system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated
system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 197.709284 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 501168235 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 14698.081203 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency
system.cpu.dcache.demand_hits 498248281 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 42917721000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.005826 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2919954 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 397451 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 24702723500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005033 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2522503 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses
system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.997749 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4086.780222 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 501168235 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 14698.081203 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 498248281 # number of overall hits
system.cpu.dcache.overall_miss_latency 42917721000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.005826 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2919954 # number of overall misses
system.cpu.dcache.overall_mshr_hits 397451 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 24702723500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005033 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2522503 # number of overall MSHR misses
system.cpu.dcache.overall_hits 464556927 # number of overall hits
system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses
system.cpu.dcache.overall_misses 4555120 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 2516044 # number of replacements
system.cpu.dcache.sampled_refs 2520140 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 2504740 # number of replacements
system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 4086.780222 # Cycle average of tags in use
system.cpu.dcache.total_refs 498255076 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3876881000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2224034 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 25470243 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 2119227193 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 403203369 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 1116867689 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 71636028 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 6728041 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 215739151 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 165973622 # Number of cache lines fetched
system.cpu.fetch.Cycles 1190006834 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 2725815 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1144873460 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 1839 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 29822694 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.132031 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 165973622 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 197674461 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.700655 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1623905370 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.336094 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.273592 # Number of instructions fetched each cycle (Total)
system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use
system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2229751 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched
system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 477535637 29.41% 29.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 564706157 34.77% 64.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 259330057 15.97% 80.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 261180842 16.08% 96.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 22809127 1.40% 97.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 31399021 1.93% 99.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 502829 0.03% 99.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 12 0.00% 99.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 6441688 0.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 10 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 165966882 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 153278500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 6740 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 540 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120110500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000037 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 6200 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 31 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 49795.025203 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 165973622 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 22741.617211 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency
system.cpu.icache.demand_hits 165966882 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 153278500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses
system.cpu.icache.demand_misses 6740 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 540 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120110500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 6200 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses
system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.436573 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 894.100654 # Average occupied blocks per context
system.cpu.icache.overall_accesses 165973622 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 22741.617211 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context
system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 165966882 # number of overall hits
system.cpu.icache.overall_miss_latency 153278500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses
system.cpu.icache.overall_misses 6740 # number of overall misses
system.cpu.icache.overall_mshr_hits 540 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120110500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 6200 # number of overall MSHR misses
system.cpu.icache.overall_hits 190192396 # number of overall hits
system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses
system.cpu.icache.overall_misses 269416 # number of overall misses
system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1750 # number of replacements
system.cpu.icache.sampled_refs 3333 # Sample count of references to valid blocks.
system.cpu.icache.replacements 9298 # number of replacements
system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 894.100654 # Cycle average of tags in use
system.cpu.icache.total_refs 165966819 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use
system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 10098709 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 158001976 # Number of branches executed
system.cpu.icache.writebacks 3 # number of writebacks
system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 175611349 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 1.044762 # Inst execution rate
system.cpu.iew.EXEC:refs 586795750 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 160862585 # Number of stores executed
system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate
system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 164362000 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 2114014731 # num instructions consuming a value
system.cpu.iew.WB:count 1694146367 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.583880 # average fanout of values written-back
system.cpu.iew.WB:consumers 2150205320 # num instructions consuming a value
system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 1234331323 # num instructions producing a value
system.cpu.iew.WB:rate 1.036807 # insts written-back per cycle
system.cpu.iew.WB:sent 1697627373 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 18573506 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 6103126 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 508224738 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 579 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 12080656 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 194089353 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 1988097398 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 425933165 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 26013466 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1707144682 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 381189 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 1432458045 # num instructions producing a value
system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle
system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6555 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 24902522 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 10588 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 71636028 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 847228 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 72909425 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 277837 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 11954619 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 832 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 124122578 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 44929168 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads
system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes
system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1131725915 65.30% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 435582288 25.13% 90.54% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 163921976 9.46% 100.00% # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads
system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes
system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 446588315 23.46% 91.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 1733158148 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 1029171 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000594 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 1903752721 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 182 0.02% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 466697 45.35% 45.36% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 562292 54.64% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 1623905370 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.067278 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.066518 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 608633589 37.48% 37.48% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 503635145 31.01% 68.49% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 353739534 21.78% 90.28% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 117719188 7.25% 97.53% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 32883027 2.02% 99.55% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 6737765 0.41% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 234496 0.01% 99.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 322546 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 80 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 147240855 12.30% 86.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 95168176 7.95% 94.45% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate
system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 452995728 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1010995901 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 789062 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34275.179377 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.682665 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 541538 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 8483929500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.313694 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 247524 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673660500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313694 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 247524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1734408 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.383782 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31001.108327 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1401925 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 11355419500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.191698 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 332483 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10307341500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191698 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 332483 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 2863 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.346581 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.148228 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 70 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 0.975550 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 2793 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86589000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975550 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 2793 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2224034 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2224034 # number of Writeback hits
system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate
system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 1913488178 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 5017400189 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 2368910398 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 1903752721 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6555 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 6002 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 1472792375 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 5.356881 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 2523470 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34205.361315 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1943463 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 19839349000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.229845 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 580007 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 17981002000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.229845 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 580007 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.233067 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.421257 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7637.149597 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13803.753842 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2523470 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34205.361315 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1943463 # number of overall hits
system.cpu.l2cache.overall_miss_latency 19839349000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.229845 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 580007 # number of overall misses
system.cpu.l2cache.overall_hits 1955854 # number of overall hits
system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 563673 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 17981002000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.229845 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 580007 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 569254 # number of replacements
system.cpu.l2cache.sampled_refs 588327 # Sample count of references to valid blocks.
system.cpu.l2cache.replacements 553099 # number of replacements
system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 21440.903439 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3151598 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 469235659000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 411363 # number of writebacks
system.cpu.memDep0.conflictingLoads 151128770 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads
system.cpu.numCycles 1634004079 # number of cpu cycles simulated
system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 404346 # number of writebacks
system.cpu.memDep0.conflictingLoads 432040536 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 167867809 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads
system.cpu.numCycles 1221905985 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 430755417 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 1988994 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 37 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 6064799926 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2072679155 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 1965930252 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 1095363349 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3532180532 # The number of ROB reads
system.cpu.rob.rob_writes 4048956705 # The number of ROB writes
system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 3418371032 # The number of ROB reads
system.cpu.rob.rob_writes 4851844016 # The number of ROB writes
system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------

2
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
View file

@ -61,7 +61,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
egid=100
env=
errout=cerr

8
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:12
M5 compiled Feb 11 2011 23:35:10
M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
M5 started Feb 11 2011 23:35:13
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 904614 # Simulator instruction rate (inst/s)
host_mem_usage 227300 # Number of bytes of host memory used
host_seconds 1690.21 # Real time elapsed on the host
host_tick_rate 523739013 # Simulator tick rate (ticks/s)
host_inst_rate 1866600 # Simulator instruction rate (inst/s)
host_mem_usage 231212 # Number of bytes of host memory used
host_seconds 819.13 # Real time elapsed on the host
host_tick_rate 1080693863 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated
sim_seconds 0.885229 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 1528988757 # Number of instructions executed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs

2
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
View file

@ -161,7 +161,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr

8
tests/long/20.parser/ref/x86/linux/simple-timing/simout
View file

@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:36:47
M5 compiled Feb 11 2011 23:35:10
M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip
M5 started Feb 11 2011 23:35:13
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 738382 # Simulator instruction rate (inst/s)
host_mem_usage 235020 # Number of bytes of host memory used
host_seconds 2070.73 # Real time elapsed on the host
host_tick_rate 801036637 # Simulator tick rate (ticks/s)
host_inst_rate 1188316 # Simulator instruction rate (inst/s)
host_mem_usage 238940 # Number of bytes of host memory used
host_seconds 1286.69 # Real time elapsed on the host
host_tick_rate 1289149200 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1528988757 # Number of instructions simulated
sim_seconds 1.658730 # Number of seconds simulated
@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 1528988757 # Number of instructions executed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.num_int_insts 1528317615 # number of integer instructions
system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read
system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read
system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written
system.cpu.num_load_insts 384102160 # Number of load instructions
system.cpu.num_mem_refs 533262345 # number of memory refs

6
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

10
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1421831 # Simulator instruction rate (inst/s)
host_mem_usage 223380 # Number of bytes of host memory used
host_seconds 3296.36 # Real time elapsed on the host
host_tick_rate 863379215 # Simulator tick rate (ticks/s)
host_inst_rate 2540540 # Simulator instruction rate (inst/s)
host_mem_usage 223860 # Number of bytes of host memory used
host_seconds 1844.83 # Real time elapsed on the host
host_tick_rate 1542694185 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4686862651 # Number of instructions simulated
sim_seconds 2.846007 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 4686862651 # Number of instructions executed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_mem_refs 1677713086 # number of memory refs

6
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:12
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

10
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 980837 # Simulator instruction rate (inst/s)
host_mem_usage 231100 # Number of bytes of host memory used
host_seconds 4778.43 # Real time elapsed on the host
host_tick_rate 1239642391 # Simulator tick rate (ticks/s)
host_inst_rate 1546064 # Simulator instruction rate (inst/s)
host_mem_usage 231584 # Number of bytes of host memory used
host_seconds 3031.48 # Real time elapsed on the host
host_tick_rate 1954011316 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4686862651 # Number of instructions simulated
sim_seconds 5.923548 # Number of seconds simulated
@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 4686862651 # Number of instructions executed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_int_insts 4686862580 # number of integer instructions
system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read
system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read
system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written
system.cpu.num_load_insts 1239184749 # Number of load instructions
system.cpu.num_mem_refs 1677713086 # number of memory refs

2
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
View file

@ -488,7 +488,7 @@ type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr

12
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -5,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:12
M5 compiled Feb 12 2011 02:22:23
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@ -29,4 +27,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 127560542500 because target called exit()
122 123 124 Exiting @ tick 108875474000 because target called exit()

719
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 87424 # Simulator instruction rate (inst/s)
host_mem_usage 240332 # Number of bytes of host memory used
host_seconds 2532.06 # Real time elapsed on the host
host_tick_rate 50378144 # Simulator tick rate (ticks/s)
host_inst_rate 92938 # Simulator instruction rate (inst/s)
host_mem_usage 245208 # Number of bytes of host memory used
host_seconds 2381.84 # Real time elapsed on the host
host_tick_rate 45710653 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363017 # Number of instructions simulated
sim_seconds 0.127561 # Number of seconds simulated
sim_ticks 127560542500 # Number of ticks simulated
sim_seconds 0.108875 # Number of seconds simulated
sim_ticks 108875474000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 16939138 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 19067543 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3582609 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 19223942 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 19223942 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 12326943 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 324452 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 243992167 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.907255 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.057266 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 97637775 40.02% 40.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 102801930 42.13% 82.15% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 24473335 10.03% 92.18% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 10688182 4.38% 96.56% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 6438517 2.64% 99.20% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 836047 0.34% 99.54% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 523551 0.21% 99.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 268378 0.11% 99.87% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 324452 0.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle
system.cpu.commit.COM:count 221363017 # Number of instructions committed
system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
@ -44,423 +44,424 @@ system.cpu.commit.COM:loads 56649590 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 77165306 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 3582617 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 70151117 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 1.152501 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.152501 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 51727133 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34247.563353 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34193.055556 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 51726620 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 17569000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 513 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 153 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 12309500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses
system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 26394.870828 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35294.285714 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20510427 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 139972000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000258 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 5303 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 3728 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55588500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1575 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 37331.807235 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 72242863 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 27087.517194 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency
system.cpu.dcache.demand_hits 72237047 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 157541000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000081 # miss rate for demand accesses
system.cpu.dcache.demand_misses 5816 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 3881 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 67898000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses
system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1935 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.336997 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1380.340507 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 72242863 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 27087.517194 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 72237047 # number of overall hits
system.cpu.dcache.overall_miss_latency 157541000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000081 # miss rate for overall accesses
system.cpu.dcache.overall_misses 5816 # number of overall misses
system.cpu.dcache.overall_mshr_hits 3881 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 67898000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_hits 71003033 # number of overall hits
system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000109 # miss rate for overall accesses
system.cpu.dcache.overall_misses 7734 # number of overall misses
system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 68562500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1935 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 46 # number of replacements
system.cpu.dcache.sampled_refs 1935 # Sample count of references to valid blocks.
system.cpu.dcache.replacements 48 # number of replacements
system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 1380.340507 # Cycle average of tags in use
system.cpu.dcache.total_refs 72237047 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use
system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 9 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 5656231 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 309852988 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 53029625 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 184220573 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 11003980 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 1085738 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 19223942 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 20440935 # Number of cache lines fetched
system.cpu.fetch.Cycles 196264127 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 182297 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 184675827 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 4455378 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.075352 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 20440935 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 16939138 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.723875 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 254996147 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.239017 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.348981 # Number of instructions fetched each cycle (Total)
system.cpu.dcache.writebacks 10 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched
system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 66307953 26.00% 26.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 121646972 47.71% 73.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 37731127 14.80% 88.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 20479784 8.03% 96.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1948325 0.76% 97.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1108960 0.43% 97.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1062530 0.42% 98.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1340 0.00% 98.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 4709156 1.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads
system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 20435488 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 139778500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000266 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 5447 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 440 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 112031000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000245 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 5007 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads
system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 4082.198961 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 20440935 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25661.556820 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency
system.cpu.icache.demand_hits 20435488 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 139778500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000266 # miss rate for demand accesses
system.cpu.icache.demand_misses 5447 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 440 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 112031000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000245 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 5007 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses
system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.746987 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1529.828433 # Average occupied blocks per context
system.cpu.icache.overall_accesses 20440935 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25661.556820 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context
system.cpu.icache.overall_accesses 27858568 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 20435488 # number of overall hits
system.cpu.icache.overall_miss_latency 139778500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000266 # miss rate for overall accesses
system.cpu.icache.overall_misses 5447 # number of overall misses
system.cpu.icache.overall_mshr_hits 440 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 112031000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000245 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 5007 # number of overall MSHR misses
system.cpu.icache.overall_hits 27852177 # number of overall hits
system.cpu.icache.overall_miss_latency 163077000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000229 # miss rate for overall accesses
system.cpu.icache.overall_misses 6391 # number of overall misses
system.cpu.icache.overall_mshr_hits 1005 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 3101 # number of replacements
system.cpu.icache.sampled_refs 5006 # Sample count of references to valid blocks.
system.cpu.icache.replacements 3428 # number of replacements
system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 1529.828433 # Cycle average of tags in use
system.cpu.icache.total_refs 20435488 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use
system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 124939 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 13366188 # Number of branches executed
system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 15799905 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.954963 # Inst execution rate
system.cpu.iew.EXEC:refs 84717237 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 21535662 # Number of stores executed
system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate
system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 22888685 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 389337537 # num instructions consuming a value
system.cpu.iew.WB:count 241459353 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.499412 # average fanout of values written-back
system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value
system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 194439848 # num instructions producing a value
system.cpu.iew.WB:rate 0.946450 # insts written-back per cycle
system.cpu.iew.WB:sent 242120517 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3656523 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 214895 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 75869162 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1275 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2489008 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 25600521 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 291514094 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 63181575 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 4005104 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 243631219 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 25200 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 223241922 # num instructions producing a value
system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle
system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 11003980 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 40028 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 11103688 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 71380 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 879354 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 44904 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 19219572 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 5084805 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 614135119 # number of integer regfile reads
system.cpu.int_regfile_writes 252115460 # number of integer regfile writes
system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 158353329 63.95% 64.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 64.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 64.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520272 0.61% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.04% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 64587764 26.08% 91.12% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 21994664 8.88% 100.00% # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 514946932 # number of integer regfile reads
system.cpu.int_regfile_writes 284476955 # number of integer regfile writes
system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1195391 0.42% 0.42% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 187555358 66.63% 67.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.05% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589850 0.56% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.61% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 67998663 24.16% 91.77% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 23168272 8.23% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 247636323 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 40899 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000165 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 37912 92.70% 92.70% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 2987 7.30% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 2334735 84.00% 86.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 386272 13.90% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 254996147 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.971138 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.960460 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 217661766 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 97493255 38.23% 38.23% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 86911390 34.08% 72.32% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 54912481 21.53% 93.85% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 12234045 4.80% 98.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 3109625 1.22% 99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 255105 0.10% 99.97% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 77911 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 2335 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 37681009 17.31% 82.72% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate
system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 69673728 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 1298 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 182988092 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34364.012739 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31058.917197 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 5 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 53951500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.996825 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48762500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996825 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5367 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34265.528407 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.178098 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1970 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 116400000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.632942 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3397 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 105426500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.632942 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3397 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 9 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 9 # number of Writeback hits
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate
system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2526643 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.579412 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 6942 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34296.657942 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1975 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 170351500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.715500 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4967 # number of demand (read+write) misses
system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 154189000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.715500 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 4967 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.068086 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 2231.049035 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.015700 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 6942 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34296.657942 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency
system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1975 # number of overall hits
system.cpu.l2cache.overall_miss_latency 170351500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.715500 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4967 # number of overall misses
system.cpu.l2cache.overall_hits 2116 # number of overall hits
system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 5220 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 154189000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.715500 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 4967 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 3400 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 2232.064735 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1970 # Total number of references to valid blocks.
system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 21807942 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads
system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.numCycles 255121086 # number of cpu cycles simulated
system.cpu.numCycles 217750949 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking
system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 57579297 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 975892 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 963293874 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 304077108 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 331962025 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 180705413 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 535181849 # The number of ROB reads
system.cpu.rob.rob_writes 594057529 # The number of ROB writes
system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 592991425 # The number of ROB reads
system.cpu.rob.rob_writes 827053987 # The number of ROB writes
system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------

8
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
View file

@ -5,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:36:47
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 777141 # Simulator instruction rate (inst/s)
host_mem_usage 230844 # Number of bytes of host memory used
host_seconds 284.84 # Real time elapsed on the host
host_tick_rate 461282227 # Simulator tick rate (ticks/s)
host_inst_rate 1396551 # Simulator instruction rate (inst/s)
host_mem_usage 231332 # Number of bytes of host memory used
host_seconds 158.51 # Real time elapsed on the host
host_tick_rate 828940820 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.131393 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 221363018 # Number of instructions executed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.num_int_insts 220339607 # number of integer instructions
system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_mem_refs 77165306 # number of memory refs

8
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
View file

@ -5,13 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:24
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...

10
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 446836 # Simulator instruction rate (inst/s)
host_mem_usage 238556 # Number of bytes of host memory used
host_seconds 495.40 # Real time elapsed on the host
host_tick_rate 506580174 # Simulator tick rate (ticks/s)
host_inst_rate 920852 # Simulator instruction rate (inst/s)
host_mem_usage 239052 # Number of bytes of host memory used
host_seconds 240.39 # Real time elapsed on the host
host_tick_rate 1043974445 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363018 # Number of instructions simulated
sim_seconds 0.250961 # Number of seconds simulated
@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 221363018 # Number of instructions executed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.num_int_insts 220339607 # number of integer instructions
system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read
system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read
system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written
system.cpu.num_load_insts 56649590 # Number of load instructions
system.cpu.num_mem_refs 77165306 # number of memory refs

11
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
View file

@ -5,12 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 12 2011 02:22:23
M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 13766000 because target called exit()
Exiting @ tick 11421500 because target called exit()

684
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 47133 # Simulator instruction rate (inst/s)
host_mem_usage 227692 # Number of bytes of host memory used
host_inst_rate 47598 # Simulator instruction rate (inst/s)
host_mem_usage 231896 # Number of bytes of host memory used
host_seconds 0.21 # Real time elapsed on the host
host_tick_rate 66053082 # Simulator tick rate (ticks/s)
host_tick_rate 55349277 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9809 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
sim_ticks 13766000 # Number of ticks simulated
sim_seconds 0.000011 # Number of seconds simulated
sim_ticks 11421500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 1920 # Number of BP lookups
system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted
system.cpu.BPredUnit.lookups 2777 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 1214 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle
system.cpu.commit.COM:count 9809 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
@ -44,415 +44,417 @@ system.cpu.commit.COM:loads 1056 # Nu
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1990 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted
system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit
system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses
system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks.
system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency
system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses
system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses
system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency
system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1789 # number of overall hits
system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses
system.cpu.dcache.overall_misses 389 # number of overall misses
system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses
system.cpu.dcache.overall_hits 2048 # number of overall hits
system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses
system.cpu.dcache.overall_misses 427 # number of overall misses
system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks.
system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use
system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks.
system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use
system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched
system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total)
system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked
system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking
system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched
system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses
system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks.
system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency
system.cpu.icache.demand_hits 970 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses
system.cpu.icache.demand_misses 285 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses
system.cpu.icache.demand_misses 365 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency
system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 970 # number of overall hits
system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses
system.cpu.icache.overall_misses 285 # number of overall misses
system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses
system.cpu.icache.overall_hits 1367 # number of overall hits
system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses
system.cpu.icache.overall_misses 365 # number of overall misses
system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks.
system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use
system.cpu.icache.total_refs 970 # Total number of references to valid blocks.
system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use
system.cpu.icache.total_refs 1367 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1318 # Number of branches executed
system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1551 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate
system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1060 # Number of stores executed
system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate
system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1306 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
system.cpu.iew.WB:consumers 10358 # num instructions consuming a value
system.cpu.iew.WB:count 11818 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back
system.cpu.iew.WB:consumers 14704 # num instructions consuming a value
system.cpu.iew.WB:count 15138 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 7281 # num instructions producing a value
system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle
system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.WB:producers 9995 # num instructions producing a value
system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle
system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 25083 # number of integer regfile reads
system.cpu.int_regfile_writes 11189 # number of integer regfile writes
system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued
system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
system.cpu.int_regfile_reads 23051 # number of integer regfile reads
system.cpu.int_regfile_writes 14062 # number of integer regfile writes
system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.26% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead 1786 11.05% 91.34% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate
system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses
system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes
system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency
system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses
system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency
system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 396 # number of overall misses
system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 437 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks.
system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use
system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 5334 # number of misc regfile reads
system.cpu.numCycles 27533 # number of cpu cycles simulated
system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 6857 # number of misc regfile reads
system.cpu.numCycles 22844 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking
system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 28728 # The number of ROB reads
system.cpu.rob.rob_writes 28005 # The number of ROB writes
system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
system.cpu.rob.rob_reads 30950 # The number of ROB reads
system.cpu.rob.rob_writes 39896 # The number of ROB writes
system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second

10
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 180423 # Simulator instruction rate (inst/s)
host_mem_usage 219128 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 103433649 # Simulator tick rate (ticks/s)
host_inst_rate 992012 # Simulator instruction rate (inst/s)
host_mem_usage 219616 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 556721453 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_int_insts 9715 # number of integer instructions
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_mem_refs 1990 # number of memory refs

18
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
View file

@ -34,7 +34,7 @@ periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Feb/07/2011 02:32:13
Real time: Feb/08/2011 00:58:34
Profiler Stats
--------------
@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.35
Virtual_time_in_minutes: 0.00583333
Virtual_time_in_hours: 9.72222e-05
Virtual_time_in_days: 4.05093e-06
Virtual_time_in_seconds: 0.26
Virtual_time_in_minutes: 0.00433333
Virtual_time_in_hours: 7.22222e-05
Virtual_time_in_days: 3.00926e-06
Ruby_current_time: 276484
Ruby_start_time: 0
Ruby_cycles: 276484
mbytes_resident: 38.6094
mbytes_total: 231.508
resident_ratio: 0.16679
mbytes_resident: 38.6797
mbytes_total: 231.98
resident_ratio: 0.166754
ruby_cycles_executed: [ 276485 ]
@ -125,7 +125,7 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 10950
page_reclaims: 11003
page_faults: 0
swaps: 0
block_inputs: 0

6
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:13
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second

10
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 32378 # Simulator instruction rate (inst/s)
host_mem_usage 237068 # Number of bytes of host memory used
host_seconds 0.30 # Real time elapsed on the host
host_tick_rate 911908 # Simulator tick rate (ticks/s)
host_inst_rate 81703 # Simulator instruction rate (inst/s)
host_mem_usage 237552 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
host_tick_rate 2292859 # Simulator tick rate (ticks/s)
sim_freq 1000000000 # Frequency of simulated ticks
sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000276 # Number of seconds simulated
@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_int_insts 9715 # number of integer instructions
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_mem_refs 1990 # number of memory refs

6
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled Feb 7 2011 02:32:07
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
M5 started Feb 7 2011 02:32:24
M5 compiled Feb 8 2011 00:58:32
M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
M5 started Feb 8 2011 00:58:34
M5 executing on burrito
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second

8
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
View file

@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 594010 # Simulator instruction rate (inst/s)
host_mem_usage 226844 # Number of bytes of host memory used
host_inst_rate 525864 # Simulator instruction rate (inst/s)
host_mem_usage 227336 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 1712507148 # Simulator tick rate (ticks/s)
host_tick_rate 1518719132 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9810 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
@ -208,7 +208,7 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_insts 9810 # Number of instructions executed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_int_insts 9715 # number of integer instructions
system.cpu.num_int_register_reads 26194 # number of times the integer registers were read
system.cpu.num_int_register_reads 21313 # number of times the integer registers were read
system.cpu.num_int_register_writes 9368 # number of times the integer registers were written
system.cpu.num_load_insts 1056 # Number of load instructions
system.cpu.num_mem_refs 1990 # number of memory refs

222
util/make_release.py
View file

@ -1,222 +0,0 @@
#!/usr/bin/env python
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
# Steve Reinhardt
# Nathan Binkert
import os
import re
import shutil
import sys
import time
from glob import glob
from os import system
from os.path import basename, dirname, exists, isdir, isfile, join as joinpath
def mkdir(*args):
path = joinpath(*args)
os.mkdir(path)
def touch(*args, **kwargs):
when = kwargs.get('when', None)
path = joinpath(*args)
os.utime(path, when)
def rmtree(*args):
path = joinpath(*args)
for match in glob(path):
if isdir(match):
shutil.rmtree(match)
else:
os.unlink(match)
def remove(*args):
path = joinpath(*args)
for match in glob(path):
if not isdir(match):
os.unlink(match)
def movedir(srcdir, destdir, dir):
src = joinpath(srcdir, dir)
dest = joinpath(destdir, dir)
if not isdir(src):
raise AttributeError
os.makedirs(dirname(dest))
shutil.move(src, dest)
if not isdir('.hg'):
sys.exit('Not in the top level of an m5 tree!')
usage = '%s <destdir> <release name>' % sys.argv[0]
if len(sys.argv) != 3:
sys.exit(usage)
destdir = sys.argv[1]
releasename = sys.argv[2]
release_dest = joinpath(destdir, 'release')
#encumbered_dest = joinpath(destdir, 'encumbered')
release_dir = joinpath(release_dest, releasename)
#encumbered_dir = joinpath(encumbered_dest, releasename)
if exists(destdir):
if not isdir(destdir):
raise AttributeError, '%s exists, but is not a directory' % destdir
else:
mkdir(destdir)
if exists(release_dest):
if not isdir(release_dest):
raise AttributeError, \
'%s exists, but is not a directory' % release_dest
rmtree(release_dest)
#if exists(encumbered_dest):
# if not isdir(encumbered_dest):
# raise AttributeError, \
# '%s exists, but is not a directory' % encumbered_dest
# rmtree(encumbered_dest)
mkdir(release_dest)
#mkdir(encumbered_dest)
mkdir(release_dir)
#mkdir(encumbered_dir)
system('hg update')
system('rsync -av --exclude ".hg*" --exclude build . %s' % release_dir)
# move the time forward on some files by a couple of minutes so we can
# avoid building things unnecessarily
when = int(time.time()) + 120
# make sure scons doesn't try to run flex unnecessarily
#touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when))
# get rid of non-shipping code
#rmtree(release_dir, 'src/encumbered/dev')
rmtree(release_dir, 'src/cpu/ozone')
#rmtree(release_dir, 'src/mem/cache/tags/split*.cc')
#rmtree(release_dir, 'src/mem/cache/tags/split*.hh')
#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc')
#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh')
#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc')
#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh')
rmtree(release_dir, 'configs/fullsys')
rmtree(release_dir, 'configs/test')
rmtree(release_dir, 'tests/long/*/ref')
rmtree(release_dir, 'tests/old')
rmtree(release_dir, 'tests/quick/00.hello/ref/x86')
rmtree(release_dir, 'tests/quick/02.insttest')
rmtree(release_dir, 'tests/test-progs/hello/bin/x86')
remove(release_dir, 'src/cpu/nativetrace.hh')
remove(release_dir, 'src/cpu/nativetrace.cc')
# get rid of some of private scripts
remove(release_dir, 'util/chgcopyright')
remove(release_dir, 'util/make_release.py')
def remove_sources(regex, subdir):
script = joinpath(release_dir, subdir, 'SConscript')
if isinstance(regex, str):
regex = re.compile(regex)
inscript = file(script, 'r').readlines()
outscript = file(script, 'w')
for line in inscript:
if regex.match(line):
continue
outscript.write(line)
outscript.close()
def remove_lines(s_regex, e_regex, f):
f = joinpath(release_dir, f)
if isinstance(s_regex, str):
s_regex = re.compile(s_regex)
if isinstance(e_regex, str):
e_regex = re.compile(e_regex)
inscript = file(f, 'r').readlines()
outscript = file(f, 'w')
skipping = False
for line in inscript:
if (not skipping and s_regex.match(line)) or \
(e_regex and skipping and not e_regex.match(line)):
if e_regex:
skipping = True
continue
skipping = False
outscript.write(line)
outscript.close()
def replace_line(s_regex, f, rl):
f = joinpath(release_dir, f)
if isinstance(s_regex, str):
s_regex = re.compile(s_regex)
inscript = file(f, 'r').readlines()
outscript = file(f, 'w')
for line in inscript:
if s_regex.match(line):
outscript.write(rl)
continue
outscript.write(line)
outscript.close()
# fix up the SConscript to deal with files we've removed
#remove_sources(r'.*split.*\.cc', 'src/mem/cache/tags')
#remove_sources(r'.*(ghb|stride)_prefetcher\.cc', 'src/mem/cache/prefetch')
remove_sources(r'.*nativetrace.*', 'src/cpu')
benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk',
'twolf', 'vortex' ]
for bench in benches:
rmtree(release_dir, 'tests', 'test-progs', bench)
#movedir(release_dir, encumbered_dir, 'src/encumbered')
rmtree(release_dir, 'tests/test-progs/anagram')
rmtree(release_dir, 'tests/quick/20.eio-short')
f = open('src/cpu/SConsopts', 'w+')
f.writelines(("Import('*')\n", "all_cpu_list.append('DummyCPUMakeSconsHappy')\n"))
f.close()
def taritup(directory, destdir, filename):
basedir = dirname(directory)
tarball = joinpath(destdir, filename)
tardir = basename(directory)
system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir))
taritup(release_dir, destdir, '%s.tar.bz2' % releasename)
#taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename)
print "release created in %s" % destdir
print "don't forget to tag the repository!"